Abstract: A counter apparatus for setting a dividing ratio given as a sum of a fixed value and a variable value, including an upper-digits-setting circuit for setting upper digits of a series of digits representing the dividing ratio to upper predetermined digits, the upper digits being fixed digits composing upper digits of a series of digits representing the fixed value; an adder for adding fixed digits composing middle digits of the series of digits representing the fixed value and variable digits composing upper digits of a series of digits representing the variable value and providing an output thereof as middle digits of the series of digits representing the dividing ratio which are variable digits; a middle-digits-setting circuit for setting the middle digits of the series of digits representing the dividing ratio to middle predetermined digits; and a lower-digits-setting circuit for setting lower digits of the series of digits representing the dividing ratio to lower predetermined digits, the lower digits being

Abstract: A digital counter allows the provision of start and stop values in order to allow it to be configurable to any length. The counter rolls over to zero at a maximum value and proceeds to count until it reaches an indicated stop count. At that point, it proceeds to the start count and continues counting. The counter counts half bytes of a cell of data for transmission to and from a multiport DRAM in accordance with communication protocols, such as asynchronous transfer mode (ATM.).

Abstract: A high speed divider circuit is provided for phase-locked loops (PLLs). The divider circuit in the feedback loop of the PLL has two divider circuits, a prescalar divide-by-4 circuit, which receives the high frequency signal from the voltage-controlled oscillator (VCO) of the PLL, and a programmable divide-by-N circuit, which resets itself after counting up to N. Responsive to the reset signal from the divide-by-N circuit, the prescalar divider circuit divides the VCO signal by 4+P, where P is a programmable value. This programmable periodic change in the divisor of the prescalar divide circuit allows the divisor in the classic PLL frequency synthesis equation to be set to nearly any number so that the synthesized output frequency of the PLL can be set with very fine resolution.

Abstract: A frequency converter is provided of which a frequency-dividing ratio is arbitrarily altered and retained after a power is turned off. The frequency converter has a programmable counter which outputs a signal having a desired frequency, a non-volatile memory for storing data for setting the frequency-dividing ratio and a control unit for controlling a writing operation of data stored into the non-volatile memory. The programmable counter, the non-volatile memory and the control unit are accommodated in a single package. The frequency converter may comprise a resonator and an oscillating circuit within the package so that the frequency converter can be treated as a single frequency generator such as a quartz-crystal oscillator.

Abstract: A timer apparatus which is provided with a control circuit 80, annexed to each of timers 1-1, 1-2 and 1-3 generating a control signal making the register 3 write data outputted from a CPU 50 when both a write signal 5 generated by the CPU 50 for writing data into the registers 3, and a timer single write signal 11 for specifying any of the timers, are generated, and furthermore is provided with a selection circuit 70 making each control circuit 80 generate a control signal when both the write signal 5 and a timer grouping signal 14 generated for specifying each of the plurality of timers 1-1, 1-2 and 1-3, are generated. When it is necessary that identical data be held in the respective registers 3 of the plurality of timers 1-1, 1-2 and 1-3, the identical data can be written into each of the registers 3 at the same time.

Abstract: A periodic signal is produced by counting pulses of a clock during a given period of time. The number of pulses counted is divided by a whole number. A count is then made of a batch of pulses of this clock, the number of pulses in this batch corresponds to the quotient of this division. At each time a batch is completed, a value of a periodic signal is produced.

Abstract: In a narrow-band filter for filtering an input signal having a predetermined frequency and comprising first through n-th low-pass filters (13-1 to 13-n) which are connected in parallel to one another, a switching circuit time divisionally connects the first through the n-th low-pass filters between input and output terminals (11, 12). The first through the n-th low-pass filters, thereby, time divisionally filters the input signal for first through n-th filtering durations, respectively. A control circuit (30) is supplied with a frequency designation signal designating the predetermined frequency and controls the switching circuit to change at least one of the first through the n-th filtering durations in accordance with the frequency designation signal.

Abstract: The invention discloses a method and an apparatus for implementing an L phase clock in conjuction with L counters, where L is an integer, to count at a frequency scalable by L.

Abstract: A programmable multiphase clock divider for selectively frequency dividing a multiphase input clock to provide a lower-frequency, self-aligned, multiphase output clock includes a counter, combinational logic circuitry, a multiphase signal generator and a multiplexor. With the counter serving as the sole frequency divider element, multiple phase-aligned clock phases are generated which are then programmably multiplexed to provide the desired frequency-divided, self-aligned clock phases. The counter, in response to a preset signal and an input clock phase, generates a multibit count signal, one bit of which forms the first output clock phase. The combinational logic circuitry receives a programming signal for decoding the multibit count signal to generate the counter preset signal and an output control signal.

Abstract: A frequency divider, constituted by N divide-by-two binaries, comprises logic circuits that enable the generation of a signal of the end of the frequency division by means of the change in state of the most significant bit generated by the Nth order divide-by-two binary. A binary code C representing a decimal integer value V is applied to the divider circuit. The frequency divider comprises circuits that enable the performance of a variable order division (V+1, V, . . . V-p, where p is a whole number greater than or equal to 1 and smaller than N-1) for one and the same binary code C.

Abstract: In a circuit for dividing the frequency of a received signal by an uneven number, initially another signal is derived through half-integer frequency division and thereafter divided by two. Preferably, a frequency division is performed alternately by an integer under the half-integer and by an integer above the half-integer, in order to achieve frequency division by a half-integer, whereby the toggling is performed dependent on the output signal.

Abstract: A data processing system (10) includes a programmable clock signal for an analog converter (28). A duty cycle of the programmable clock signal is programmed by an external user in a prescaler rate selection register (16). A counter subsequently counts for a first period of time corresponding to a phase in which the programmable clock signal is asserted. The counter then counts for a second period of time corresponding to a phase in which the programmable clock signal is negated. By allowing the user to program and modify the duty cycle of the programmable clock signal, the performance of the analog converter (28) may be optimized without constraining the requirements of an external system clock.

Abstract: A reload-timer/counter circuit provides a reload-timer function and a counter function commonly and selectively. The circuit is comprised of first, second, third, and fourth registers. The third and fourth registers act as a control status register and a mode register, respectively. The first and second registers act as, in the reload-timer mode a data register and a counter register, respectively, while in the counter mode, the first and second registers act as the counter registers.

Abstract: A programmable counter composed of D-type flipflops receives a clock pulse having a constant frequency and is configured to generate a count pulse when a count value reaches a programmed number. A ring counter composed of D-type flipflops receives the count pulse from the programmable counter. A coincidence detection and control circuit detects a predetermined count value of the ring counter, and modifies the programmed maximum count number of the programmable counter, so that the maximum count value of the programmable counter can be selected from either an ordinary maximum count number or the predetermined maximum count number.

Abstract: A programmable clock divider in which a system reference clock signal is divided by a programmed integer value. A storage register stores a value equal to the desired divisor minus two. A stored value of zero results in a divide by two. The stored value is loaded into a compare register and a counter is implemented to count reference clock signals. The compare register value and the counter value are compared by a comparator logic circuit. When the two values are equal, a flip-flop is toggled to switch the prescale clock value output, The flip-flop control logic includes circuitry for ensuring that odd divides exhibit an output clock frequency having a 50/50 duty cycle by controlling the flip-flop toggle to coincide with system clock edges. The flip-flop control logic also controls the timing for loading and resetting the compare and counter logic, respectively.

Abstract: A phase lock loop monitors a first digital signal and generates a second digital signal operating substantially at frequency and in-phase with the first digital signal. A programmable divider latches a program integer for providing a latch integer, compares the latch integer to a constant integer, and generates a flag signal having a first state when the latch integer mismatches the constant integer and a second state when the latch integer matches the constant integer. The latch integer is decremented when the flag signal has the first state. The flag signal is delayed in response to first and second clock signals for providing the second digital signal having a frequency determined by the program integer. The first and second digital signals are applied to a lock detection circuit for providing a lock detection signal.

Abstract: A method and apparatus for improving the speed of response and display accuracy of a periodic input signal, of the type having a widely variable frequency, on an analog gauge have a meter deflection representative of the frequency of the input signal. Frequency scaling means are provided for multiplying the frequency of the input signal by a first constant to generate an intermediate signal. Counting means are coupled to the frequency scaling means for counting the frequency of the intermediate signal for a time period which is directly proportional to the maximum sweep deflection arc of the gauge times a second constant, and is inversely proportional to the maximum expected frequency of the input signal. Meter driver means coupled to the counting means are provided for deflecting the meter proportional to the counted intermediate signal frequency.

Abstract: A programmable frequency divider circuit includes a prescaler which consists of p cascade-connected dividing cells, a cell of rank i in the cascade having a normal division factor 2 and also being programmable so as to divide by 3 the input frequency applied to the cell. Each cell of rank i supplies, as a signal enabling the programmed mode for the preceding cell of rank i-1, a signal which is referred to as a gating signal and which is calibrated as regards duration and position in time at the operating frequency of the cell i, the prescaler (PPSC) being associated with counting means (CNT) for producing a programmable division factor (R) which is equal to M.2.sup.p +N, where M is an integer number applied to the counting means (CNT), p is the number of cells of the prescaler (PPSC), and N is an integer number applied to the programming inputs of the prescaler (PPSC).

Abstract: A high speed, synchronous, programmable frequency divider is disclosed. The divider is composed of a cascade of conventional programmable counters, each of which receives some portion of an externally supplied integer N, such that the divider produces one output pulse for every N periods of a supplied clock signal. Although conventional frequency dividers are substantially slower than the speed of their individual counters, a divider according to this invention, however, will operate at very nearly the same speed. The improved performance is achieved through (a) individually choosing the timing of the clock signal applied to each circuit of the divider, and (b) introducing a delay circuit, typically a shift register, in a feedback path. A method for determining the values of the clock timing variations and for determining an optimum number of flip-flops in the shift register is given. A divider according to the invention may be optimized either for maximum speed or for best design margins at a given speed.

Abstract: A pulse counter has a programmable prescaler that divides the frequency of an input clock pulse signal by a factor designated by a code signal. A counter counts the prescaled clock pulse signal output by the programmable prescaler to generate a count output. A code generator encodes the count output to generate the code signal that controls the programmable prescaler.

Abstract: A dividing ratio is represented by a ratio (M/N) of two integers (M) and (N), and six data (N), (-N), (M), (M+N), (M-N) and (0) are generated, then one of the six data is selected on the basis of a condition that is predetermined by an input signal to be divided and a comparison result of the data (N), (-N) and data which is derived by addition or subtraction between the selected data from the six data and the previous calculation result of the addition or subtraction; and output or interception of an output signal is controlled on the basis the comparison result, and thereby the input signal is divided by the dividing ratio (M/N).

Abstract: A customer, automobile or other moving entity is monitored by sensing the presence of the entity to generate a signal. The signals are correlated with individual increments of time during an extended time period of days or months. Each signal may represent the count of a single individual or car, or the amount of time the individual or car is in the range of the sensor. The data is collected in a digital memory for the prolong periods of time and can be dumped to a personal computer in the form of a spreadsheet compatible file for future analysis. A unitary battery powered version of the invention includes a power saving circuit while another version of the invention, powered by a wall outlet, can be connected to multiple sensors for collecting data in a large environment such as a store.

Abstract: A fractional divider using a counter means to provide fractionality. A divider is used to divide the VCO output signal by N or N+1 as selected. A divider control circuit controls the divider to divide by the appropriate divisor to obtain the selected output frequency. The fractional divider circuit counts divider control signals which represent a first division period. The fractional divider circuit establishes a second period of multiple first periods and at the terminal count of each second period, provides a selected number of fractional control signals to the divider control to cause division by a different number, such as N+1. The fractional divider comprises a first counter programmed to count first periods and issue its terminal count upon receiving the programmed count of first periods. The fractional divider also comprises a second counter to provide the selected number of fractional control signals upon receipt of the terminal count of the first counter.

Abstract: A frequency division scheme which offsets for a phase lag produced on initial power-on is described. A division ratio of a programmable counter is initially set at a first division ratio at the time of releasing the programmable counter from its reset state. When the first division cycle is complete, the division ratio is reset to its steady state value. Thus, a delay equivalent to the phase lag is produced. A frequency synthesizer is also proposed where the division ratio is set, and a phase difference is detected. Reset signals are continually set while the phase difference is changed. This cycle is continued until the phase difference is reduced to one cycle of the input signals or less.

Abstract: A programmable frequency dividing network comprises a plurality of cascade-connected programmable frequency dividing stages each of which divides the frequency of a clock pulse by two and three based on a logic level of a preset input signal used to change a variable division ratio from one to another. In addition, there is provided a gating means for determining or detecting whether or not each of the outputs of programmable frequency dividing stages of the programmable frequency dividing network after a programmable frequency dividing stage as a second stage is brought to a predetermined pattern and an instruction signal for making a decision as to the division of the division ratio by (+1) is inputted, so as to generate the output of a logic level for causing a programmable frequency dividing stage equivalent to a first stage to divide the frequency of the clock pulse by three if it is determined to be positive in the above detection process.

Abstract: A digital oscillator is built around an accumulator which is incremented by a predetermined number N of unit values at every pulse of a sequence of pulses of a reference frequency and the carry output of the accumulator is used to produce the output frequency. In order to eliminate the jitter of that output, the carry signal is supplied to a delay chain, from the output of which a delay is selected in a manner dependent upon the content of the accumulator during the presence of the carry signal in question at the output of the accumulator. The carry pulse times a D register in which the contemporary content of the accumulator is stored until the next carry pulse while being supplied to a calculation circuit for selecting the appropriate delay derived from the D register content and the number of units of accumulator incrementation in use at the particular time.

Abstract: Two cascaded eight-bit maskable counters (62) and (64) provide a sixteen-bit output, for instance, to a digital-to-analog converter (10). Each of the counters (62) and (64) is a maskable counter that is operable to mask off a programmable number of the least significant bits therein. The next adjacent bit thereto comprises a virtual least significant bit. During the counting operation, the count is initiated at the virtual least significant bit such that the virtual least significant bit is clocked for each counting cycle. An initial value is first loaded into the counter (62) and (64) on a data bus (74). Thereafter, masked data is loaded into the counters (62) and (64) on the same data bus (74) to define the ones of the least significant bits that are masked off. In such a manner, the overall resolution of the counter can be varied without varying the clock rate to the counter.

Abstract: A programmable circuit for sampling an IR signal is responsive to a clock signal and a plurality of programmable factors which establish the characteristics of the sampling pattern. The circuit provides successive groups of samples whose resolution, phase and periodicity are established by the programmable factors such that IR signals characterized by different formats may be conveniently accommodated by the same hardware.

Abstract: In a phase locked loop having a variable divider, a dual modulus counter is used to provide the variable divider with selection signals. The variable divider is capable of providing an overall division ratio in increments of one over a contiguous range of values. The dual modulus counter includes a counter, a comparator and logic gates which generate selection signals that allow the variable divider to divide an input signal by at least division ratios R1 and R2. A phase locked loop utilizing the dual modulus counter is particularly well suited for use in a digital frequency synthesizer.

Abstract: A programmable frequency divider for dividing the frequency of a supplied high-frequency signal directly into a lower frequency includes a plurality of 2-scale-factor prescalers or programmable frequency divider units each capable of being switched between divide-by-2 and divide-by-3 modes. The 2-scale-factor prescalers are connected in cascade for producing an output signal which is frequency-divided at one of multiple division ratios at a time.

Abstract: A scaler comprising a plurality of flip-flops, varies its frequency division to correct phase by 0.5 clock cycle. Each flip-flop is continuously and synchronously responsive to either a rising or a falling edge of the clock pulses. Normally, the scaler's state transits along one of two loops, which generate output pulses having identical repetition rates. When a control signal is applied, the scaler's state transits from one loop to the other, generating at least one output at an alternative repetition rate. The alternative repetition rate is either lower or higher than the identical repetition rate by an integral number of half cycles of the input clock pulses. Where there are two control signals, a lower or higher alternative repetition rate can be selected. Since the flip-flops are responsive to either edge of the clock pulses without clock gating interruptions, there is no jitter and the scaler's robustness is improved. Also the clock frequency can be effectively halved.

Abstract: A multi-function high speed sequencer is provided in a high speed instruction processor. The high speed sequencer comprises a first input latch coupled to logic signals for producing a first sequence signal. A chain of alternately clocked even and odd principal latches are coupled to the output of the first input latch to produce even and odd principal sequence signals for accessing a high speed MSU. A plurality of staging latches are coupled between the odd and the even principal latches for producing even and odd secondary sequence signals for accessing a slower speed MSU.

Abstract: A local bit clock having the frequency of the signal to be received is generated at the receiving end by means of a clock generator (TG) and a counter (Z). A phase evaluation logic (PAL) evaluates the time position of the leading edge of a received pulse in comparison with a predetermined time position of the effective pulse edge of the local bit clock. In the synchronous case, the effective pulse edge is located at the center of the received pulse (center-of-bit sampling). Because of nonideal line properties, the duration of the received pulses may differ from the desired value. To be able to distinguish a momentary edge drift of a received pulse (pulse too short or too long) from an actual phase shift, the time positions of the leading and trailing edges of each pulse are determined.

Abstract: Disclosed herein is a counter circuit which includes a register for temporarily storing a count data signal, a data processing circuit coupled to the register and supplied with a control signal for producing a first count value from the count data signal in response to a first state of the control signal and for producing a second count value from the count data signal in response to a second state of the control signal, and a counter stage coupled to the data processing circuit and supplied with an input signal to be counted for producing a detection signal when the input signal to be counted is supplied thereto by a time number determined by the first or second count value.

Abstract: An asynchronous nonlogical counting device includes at least a first counter and a second counter connected in cascade. The first counter has a frequency dividing ratio of 2.sup.n where n is a natural number. A control unit produces a control signal based on the count value of the first counter. The second counter has a variable frequency dividing ratio which is based on the control signal. The counting device can be made programmable by substituting a comparator circuit for the control unit. The comparator compares the output of the first counter to an instruction signal from an external source.

Abstract: A digitally-operating electrical appliance or equipment which is adapted to automatically handle power-supply or line frequencies of 50 Hz or 60 Hz. A full wave of the power-supply frequency is utilized for the generating of a waveform having a pulse referenced thereto. A pulse sequence which is generated independently of the power-supply frequency and is of an essentially higher frequency than the former is counted into a counter, and the content of the counter is thereafter discriminated at a threshold value of about 55 Hz.

Abstract: A programmable counter or frequency divider includes the combination of a fixed modulus prescaler (110) and a programmable divider (120, 130, 140, 150, 160) in which the prescaler provides more than a single clock phase to the programmable divider and the programmable divider utilizes the multiple clock phases to allow operation in a true fractional-integer mode. The overall combination of the prescaler and programmable divider functions as a programmable divider for which the minimum increment in the overall divider modulus is less than the prescaler modulus, but the maximum clock frequency usable is the maximum clock frequency of the prescaler.

Abstract: An analog/digital voltage controlled oscillator includes a voltage to pulse converter which responds to a control voltage to generate appropriate control pulses to change the mode of operation of a divider to thereby vary the output frequency of the oscillator.

Abstract: A preset counter apparatus for copying machines and the like having respective keys corresponding to digit positions of units and tens and a display for displaying numerical value in the digit positions of units and tens. The preset counter apparatus is so controlled that a value "0" is automatically displayed in the units digit position when the key corresponding to the tens digit is initially activated and that a value previously set in the units digit position is maintained as it is regardless of the posterior activation of the key corresponding to the tens digit.

Abstract: A dividing mechanism for use in frequency synthesizers: comprising:a two modulus divider system having a first and second counter for providing respective programmable count totals A, M, and first counter being coupled to a dual modulus device providing moduli of n and n+1 whereby the two modulus divider system provides a division ratio of (Mn+A) for incoming signals:first and second input means for receiving first and second programming number signals N, Q, synchronization means for receiving a strobe signal from a further counter which provides a count total P, and logic interface means responsive to said first and second input means and said synchronization means to provide programming number signals A, M to said two modulus divider system, the logic interface means being such that in the absence of said strobe signal the two modulus divider system provides a count total C.sub.

Abstract: A frequency divider circuit for dividing an input signal with a predetermined integer or non-integer divisor. The frequency divider circuit comprises a polynomial counter, decode logic, and a clock edge selector. The polynomial counter, responsive to a clock signal at a predetermined frequency, cycles through a predetermined set of logic states which are logical combinations of the previous state, and generates a set of output signals which indicates the present logic state of the polynomial counter. The decode logic, responsive to the output signals of the polynomial counter, implements a predetermined logical mapping of said output signals into a decoded output signal. The clock edge selector, responsive to the decoded output signal of the decode logic, utilizes flip-flops and other logic to generate integer and non-integer multiples of the clock signal. The frequency divider circuit selects either integer or non-integer divisors depending on the informational content of a control signal.

Abstract: A synchronous programmable binary counter has a parallel section and a serial section, with the length (in bits) of the serial section being the same as the modulus of the parallel section. The parallel section counts on system clocks and produces two outputs. A parallel terminal count output is produced each time the parallel section count reaches a programmed value. A frame output is generated every time the parallel section reaches its maximum count and starts counting again. The serial counter section decrements its programmed value by one each time it receives a frame signal from the parallel section. This subtraction is accomplished by a half-adder and associated borrow flip-flop. The borrow flip-flop is set by each arrival of the frame signal. Between frame signals, the decremented programmed value is circulated in a shift register as the serial subtraction process is performed.

Abstract: A timeout circuit with internal calibration includes an oscillator (11) for generating an initial frequency for division by a modulo-n counter (20). The counter (20) receives the value of n from a calibration register (22) and divides the frequency of the oscillator by the value of n. A gate (26) prevents alteration of the contents of the register (22). The output of the counter (20) provides a calibrated frequency which is further divided by a day counter (32) for output to a countdown counter (34). The countdown counter (34) provides a predetermined countdown of the signal output by the day counter (32) and, at the end of the count, generates a Timeout signal. The predetermined countdown value is determined by a value stored in a register (36) which can be protected by a customer lock out circuit (42).

Abstract: An adjustable frequency signal generator is described which utilizes a stable fixed frequency oscillator in combination with an adjustable modulus frequency divider, to obtain a frequency divided output signal whose frequency may vary within a wide range, while maintaining spectral purity of a signal generated by the stable oscillator. In the preferred embodiment the modulus of the frequency divider is controlled by an up/down counter. The frequency of the frequency divided output signal is detected with respect to a reference signal frequency. When the detected output signal frequency is higher, the counter is incremented, thereby incrementing the modulus of the divider and decreasing the frequency of the output signal. Similarly, when the detected output signal frequency is lower than the reference signal frequency, the counter is decremented, whereby the modulus of the divider decreases and the output signal frequency increases.

Abstract: A method and arrangement for a fully synchronized, programmable frequency divider is disclosed that exhibits a near 50% duty cycle output signal independent of the divisor, whether even or odd, and that is suitable for use in a phase-locked loop (PLL) frequency synthesizer. As described in a first embodiment, the arrangement includes a data loader 31, a counter 32, a half-period detector 33, and a synchronizer 34. Next, a fast-locking, low-noise PLL frequency synthesizer is disclosed incorporating the fully synchronized, 50% duty cycle divider, and having a reference signal generator 71-72, a phase detector 73, a controlled oscillator 74-75, and the fully synchronized, programmable frequency divider 76. In a second embodiment, a fully synchronized programmable divider is described, including a data loader 31, a counter 32, a half-period detector 33', a synchronizer 34', and an additional block 82, a half-clock period detector.

Abstract: A timer which can be used to provide interrupt signals at predetermined but variable periods for multi-tasking microcomputers or serial data acquisition in pagers comprises a plurality of modulo counters. Each modulo counter has selectable clock inputs and has an output coupled via switches to a NOR gate and to the other modulo counters. Programmable configuring means control the switching means to configure the counters so as to produce desired outputs at the logic gate. The configuring means can also reset the modulus of the modulo counters to any desired value. Thus, the timer produces variable interrupt signals with little or no overhead processor time.

Abstract: Sampling pulses for determining a series of measurement periods are each synchronized, by a synchronizing circuit, with one of a plurality of input signal pulses to be measured. A first counter responds to the synchronized sampling pulse to start the counting of the input signal pulses. When the first counter has counted a predetermined number M of input signal pulses, a second counter starts counting the input signal pulses at the initial value M and stops the counting in response to the next synchronized sampling pulse. The count value of the second counter is applied to a display during the next counting of the input signal pulses by the first counter up to the predetermined number.

Abstract: The invention relates to a signal generator with programmable variable frequency and comprises a reference oscillator, a first frequency divider receiving the signal emitted by the reference oscillator and delivering an instantaneous frequency signal (FS). A control chain for said first frequency divider comprises a second frequency divider and a first programmable integrator system, which controls the first frequency divider. A control chain for the second frequency divider comprises a second integrator system receiving the output signal (FS).

Abstract: A phase locked loop including a programmable frequency divider with a variable modulus divider (VMD) having two modes of operation, n and n+1, a programmable counter for counting the number of times the VMD divides the input signal and a comparator for comparing the count in the counter to a predetermined number and switching the VMD from the first mode to the second mode when the instant count and predetermined number are equal. The programmable counter provides an output pulse each time the total count equals a selected number. The VMD is a GaAs semiconductor device.

Abstract: A method of and an apparatus for generating a control frequency in which two submultiples of a frequency standard are obtained which differ by unity in the respective frequency division and are mixed so that the contribution of a prior control frequency is reduced form period group to period group while the contribution of the new control frequency is increased from period group to period group. The system provides fine control of frequencies for, for example, driving synchronous motors without requiring excessively high frequency standard oscillators.