Charge-coupled Device Patents (Class 377/63)
  • Patent number: 9081442
    Abstract: A touch panel configured to compensate for negative pixel effect is disclosed. The panel can be configured to increase a capacitive sense signal, indicative of a touching or hovering object, in order to compensate for an increase in negative capacitance when the object is poorly grounded. To perform the compensation, the panel can be configured to have split sense lines so as to increase the number of electric fringe fields forming the sense signal, thereby providing a sense signal that is substantially stronger than the negative capacitance signal. Each sense line can be split into two or more strips.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: July 14, 2015
    Assignee: Apple Inc.
    Inventors: Marduke Yousefpor, Martin Paul Grunthaner
  • Patent number: 8385498
    Abstract: A charge transfer circuit, such as a charge coupled device or other bucket brigade device, which incorporates an amplifier to assist with charge transfer.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: February 26, 2013
    Assignee: Kenet, Inc.
    Inventor: Michael P. Anthony
  • Patent number: 8295429
    Abstract: A CCD color image sensor which prevents unnecessary charge from overflowing in a photoelectric conversion element. An image input apparatus having the CCD color image sensor comprises transferring unit which transfers effective charge accumulated in the photoelectric conversion element provided for each of the colors (R, G and B), extracted as an output signal, to a shift register by opening a shift gate; and discarding unit which discards unnecessary charge accumulated in the photoelectric conversion element by opening the shift gate at different timing from one color to another immediately before the photoelectric conversion element starts accumulating effective charge again. The discarding unit discards unnecessary charge immediately before effective charge accumulates, and discards unnecessary charge by opening the shift gate before unnecessary charge overflows in the photoelectric conversion element.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: October 23, 2012
    Assignee: Seiko Epson Corporation
    Inventor: Atsushi Sasaki
  • Patent number: 8044894
    Abstract: After a sampling transistor is turned ON at a first timing when a control signal has risen, during a sampling period from a second timing when a video signal has risen from a reference potential to a signal potential to a third timing when the control signal has fallen and is turned OFF, the sampling transistor samples and writes the signal potential in a holding capacitance, and negatively feeds back a current flowing into a drive transistor during the sampling period to the holding capacitance and applies mobility correction of the drive transistor on the written signal potential. A signal driver adjusts the second timing for the video signal supplied to respective signal lines to correct a backward shift of the third timing due to a transmission delay along a scanning line of the control signal output from the control scanner.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: October 25, 2011
    Assignee: Sony Corporation
    Inventors: Katsuhide Uchino, Tetsuro Yamamoto
  • Patent number: 7932767
    Abstract: A technique for increasing the charge storage capacity of a charge storage device without changing its inherent charge transfer function. The technique may be used to implement a charge domain signal processing circuits such as Analog to Digital Converters (ADCs) used in digital radio frequency signal receivers.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: April 26, 2011
    Assignee: Kenet, Inc.
    Inventors: Edward Kohler, Michael P. Anthony
  • Patent number: 7872521
    Abstract: Disclosed is a CCD device in which a charge transfer register of a CCD structure is connected to a charge detector via an output gate and has a reset gate between the charge detector and a reset drain, and an output gate pulse opposite in phase from a reset pulse applied to the reset gate is applied to the output gate. A dummy charge detector and an amplitude adjusting circuit are provided. On the basis of detection of the potential of a diffusion layer in the dummy charge detector, the amplitude adjusting circuit controls the amplitude of the output gate pulse applied to the output gate.
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: January 18, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Takao Tsuzuki
  • Patent number: 7643072
    Abstract: The present invention provides an image capturing apparatus which enables a desired image quality to be maintained regardless of transfer efficiency of a CCD image capturing element. R, G and B signals (CCD-RAW data) are acquired from the CCD image capturing element. In addition, various information, namely transfer efficiency of the CCD image capturing element, camera sensitivity upon photography, drive frequency of the CCD image capturing element, WB gains of the acquired R, G and B signals, pixel count, internal temperature of camera or temperature of the CCD image capturing element, and CCD color filter array of the CCD image capturing element are acquired. Signal processing on the acquired R, G and B signals is changed according to the acquired information in order to suppress image quality deterioration due to transfer efficiency degradation.
    Type: Grant
    Filed: July 19, 2006
    Date of Patent: January 5, 2010
    Assignee: Fujifilm Corporation
    Inventors: Tetsuro Ashida, Kousuke Irie, Hitoshi Yamashita, Tooru Ueda, Kenkichi Hayashi, Takeshi Miyashita
  • Patent number: 7336757
    Abstract: A CCD shift register capable of switching between two-phase driving and three-phase driving in which crosstalk among clock signal lines is reduced and a decrease in transfer efficiency is prevented. Transfer electrodes disposed at regular intervals along a channel region are supplied with clock signals through clock signal lines. Three pairs of clock signal lines that are supplied with an in-phase clock signal at three-phase driving are disposed next to each other. One pair of odd-numbered clock signal lines supplied with an in-phase clock signal at two-phase driving is disposed next to each other, and one pair of even-numbered clock signal lines supplied with an in-phase clock signal at two-phase driving is disposed next to each other.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: February 26, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Masataka Yoshimura, Masaaki Ohashi
  • Patent number: 7003068
    Abstract: A circuit for adding or subtracting an amount of charge from a charge sample, such as in a Charge Coupled Device (CCD), by portioning and pipelining the processing stages, to avoid introducing a memory effect. The operation, such as subtraction, is split into multiple stages, with each stage responsible for removing only a portion of the total amount of charge that is desired to be removed. The subtraction pipeline stages operate together to remove the total desired charge amount. In one embodiment each successive subtraction stage removes a corresponding lesser amount of charge. As a result, greater accuracy in the amount of charge removed is achieved as well operation at higher frequencies than previous charge subtraction approaches.
    Type: Grant
    Filed: June 21, 2004
    Date of Patent: February 21, 2006
    Assignee: Kenet, Inc.
    Inventors: Lawrence J. Kushner, Michael P. Anthony, Edward Kohler
  • Patent number: 6825879
    Abstract: In a solid-state image sensing device, photoelectric conversion elements are two-dimensionally arrayed in a matrix on a semiconductor substrate. A transfer gate portion is arranged adjacent to each photoelectric conversion element to read signal charges stored in the photoelectric conversion element. A vertical CCD is arranged adjacent to the transfer gate portion to transfer the signal charges read from the photoelectric conversion element in a vertical direction. A horizontal CCD transfers the signal charges transferred from the vertical CCD in a horizontal direction. A charge detection portion detects the signal charges transferred from the horizontal CCD and outputs them. Four vertical transfer electrodes are formed adjacent to each other on the vertical CCD in a vertical transfer direction of the signal charges. The vertical transfer electrodes include first and second transfer electrodes adjacent to each other in the vertical transfer direction.
    Type: Grant
    Filed: February 12, 1999
    Date of Patent: November 30, 2004
    Assignee: NEC Electronics Corporation
    Inventor: Masayuki Furumiya
  • Patent number: 6818878
    Abstract: A multi-resolution charge-coupled device (CCD) sensing device is provided. The multi-resolution CCD sensing device achieves the object of the invention by using more than two CCD shift registers. The purpose of the invention is to combine and store the charge signals from a longer CCD shift register to a shorter CCD shift register, and then to shift out the charge signals, so as to attain transmission functions with different resolutions. It can achieve the economy of smaller size and lower cost by using the multi-resolution CCD sensing device according to the invention, thereby increasing scanning speeds at lower resolutions.
    Type: Grant
    Filed: August 13, 2003
    Date of Patent: November 16, 2004
    Assignee: Avision Inc.
    Inventor: Yen-Cheng Chen
  • Patent number: 6784929
    Abstract: A programmable two-dimensional timing generator according to the invention employs a clock generator (102) and a user-defined two-stage waveform generator (106, 108). A single static random access memory (SRAM) (112) stores a user-defined waveform control word for both waveform generator control units. The SRAM data is entered via the host controller external data bus. A single waveform control word may be used to control both waveform generators.
    Type: Grant
    Filed: August 20, 1999
    Date of Patent: August 31, 2004
    Assignee: Infineon Technologies North America Corp.
    Inventor: Tai-Ming Chen
  • Patent number: 6728330
    Abstract: There is provided a register system of a microcomputer having a register that includes at least one register bit and having an additional storage arrangement allocated to the register and on which the data content of the register is able to be intermediately stored. To reduce the computing time for saving the data content of the register, while keeping the silicon surface required for the register system as small as possible, the additional storage arrangement includes at least one shift register having at least two shift register cells, the content of an arbitrary shift register cell being transferable into a register bit, and, conversely, the content of a register bit being transferable into an arbitrary shift register cell.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: April 27, 2004
    Assignee: Robert Bosch GmbH
    Inventor: Axel Aue
  • Patent number: 6683647
    Abstract: A method for driving a CCD solid-state image sensing device. The method is applied to driving the CCD in order to ensure a sufficiently large charge to be handled. In the method, the driving control is performed such that the length of a control interval, which starts from the point in time when a driving voltage is applied to an electrode terminal having the largest time constant (for example, the electrode having the longest wiring line as viewed from the input side of a driving clock, or the electrode laminated at the lowest layer) is more than the length of the other control intervals subsequent to the control interval. Thus, the influence of delay in the rise time of the driving voltage at the electrode which has the largest time constant is eliminated.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: January 27, 2004
    Assignee: Sony Corporation
    Inventor: Takashi Idouji
  • Patent number: 6639202
    Abstract: A multi-resolution charge-coupled device (CCD) sensing apparatus is provided. The multi-resolution CCD sensing apparatus includes a photo sensor set, a shift gate, and several CCD shift registers. The shift gate includes several switches for receiving the charge signal from the photo sensor set and the switches. The switches output the charge signals to the corresponding CCD components with respect to different resolutions for the acquisition of the scanning image with different resolutions. It can achieve the economy of size, low cost by using the multi-resolution CCD sensing apparatus according to the invention and therefore speeds up scanning at low resolution.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: October 28, 2003
    Assignee: Avision Inc.
    Inventor: Michael Chen
  • Patent number: 6618088
    Abstract: A charge transfer device is disclosed wherein three pixel rows are arranged adjacently to each other. First to third pixel rows are arranged adjacently to each other, and the charge transfer device includes a first charge transfer element for reading out and transferring signal charges generated in the first pixel row and a second charge transfer element for reading out and transferring signal charges generated in the second and third pixel rows. Second readout electrodes for reading out signal charges generated in the second pixel row into the second charge transfer element are provided with one electrode placed between adjacent pixels of the third pixel row.
    Type: Grant
    Filed: February 8, 1999
    Date of Patent: September 9, 2003
    Assignee: NEC Electronics Corporation
    Inventors: Shiro Tsunai, Kazuo Miwada
  • Patent number: 6586784
    Abstract: A method for reducing dark current within a charge coupled device includes the steps of providing three or more phases of gates separated by an insulating layer from a buried channel of the first conductivity type in a well or substrate of the second conductivity type, and a clock driver for causing the transfer of charge through the charge coupled device; providing a barrier for separating charge packets when in accumulation state; applying, at a first time period, voltages to all phases of gates sufficient to cause the surface of the first conductivity type to be accumulated by dark current reducing charge carriers; after the first time period, applying, at each gate phase n having a capacitance Cn to the layer of the second conductivity type, a voltage change on the gate phase n given by &Dgr;Vn such that the sum of products of the capacitances and voltage changes is substantially zero ∑ n ⁢   ⁢
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: July 1, 2003
    Assignee: Eastman Kodak Company
    Inventor: Christopher Parks
  • Patent number: 6583818
    Abstract: A solid state image pickup device having: a mode selector for selecting one of first and second modes; a plurality of photoelectric converters for converting received light into electric charges; transfer paths each having a plurality of packets for receiving the electric charges from the plurality of photoelectric converters and transferring the electric charges in each packet; a controller for reading the electric charges from each of the plurality of photoelectric converters and supplying the read electric charges to the transfer paths; and a driver for driving the transfer means in the selected first or second mode at the number of drive phases different from the number of drive phases of the non-selected mode.
    Type: Grant
    Filed: November 30, 1998
    Date of Patent: June 24, 2003
    Assignee: Fuji Photo Film Co., Ltd.
    Inventor: Tetsuo Toma
  • Publication number: 20010050714
    Abstract: The first present invention provides a circuit for processing charge detecting signal transferred to a floating diffusion amplifier from a charge coupled device. The circuit comprises: a first node connected to the floating diffusion amplifier; a first enhancement type field effect transistor being connected in series between a first fixed-voltage supply line for supplying a first fixed voltage and an output terminal, and the first enhancement type field effect transistor having a first gate connected to the first node; and a second enhancement type field effect transistor being connected in series between a second fixed-voltage supply line for supplying a second fixed voltage and the output terminal, wherein the second enhancement type field effect transistor has a second gate supplied with a third fixed voltage which is different in potential from the second fixed voltage.
    Type: Application
    Filed: January 25, 2001
    Publication date: December 13, 2001
    Applicant: NEC CORPORATION
    Inventor: Yoshizumi Haraguchi
  • Patent number: 6215840
    Abstract: Circuits for sequentially addressing memory locations in time with pulses received from a clock are disclosed. The circuits may provide a positive voltage output signal at successive output nodes associated with corresponding stages in the circuit responsive to the application of a clock signal to the circuit stages. The circuit may comprise at least first and second stages wherein said first stage comprises means for providing a positive voltage signal at a first output node in the first stage in response to application of a first positive clock pulse to the first stage, and wherein said second stage comprises means for providing a positive voltage signal at a second output node in the second stage in response to application of a second positive clock pulse to the second stage. Addressing of memory locations that contain pixel information for a video display is one particular application in which sequential addressing may be required.
    Type: Grant
    Filed: May 6, 1999
    Date of Patent: April 10, 2001
    Assignee: eMagin Corporation
    Inventors: Shashi D. Malaviya, Olivier Prache
  • Patent number: 5937025
    Abstract: A CCD shift register includes a continuous buried channel over a length of the shift register, a plurality of conductor segments, a plurality of narrow bus segments, and a plurality of wide busses. Each conductor segment includes a plurality of sets of conductors, and each set of conductors includes plurality of conductors, each conductor in a set corresponding to a respective clock signal of a plurality of clock signals. Each conductor of each set extends across the buried channel. A first narrow bus segment of the plurality of narrow bus segments includes a plurality of narrow busses that are disposed parallel to and offset from the buried channel, each narrow bus corresponding to a respective clock signal of the plurality of clock signals, and each narrow bus is coupled to a respective conductor of each set of a first conductor segment.
    Type: Grant
    Filed: August 26, 1997
    Date of Patent: August 10, 1999
    Assignee: Dalsa, Inc.
    Inventor: Charles Smith
  • Patent number: 5848305
    Abstract: When a voltage signal corresponding to charges circulating a circulating shift register including charge transfer channels, which are arranged in a ring pattern, are read out from the shift register as a signal value, since clocks for circulating the charges have a very high frequency, it is difficult to operate an A/D converter in synchronism with such clocks, and a very expensive A/D converter must be used. In view of this problem, when the signal is read out, the clock frequency is lowered, and the voltage signal corresponding to the charges is converted into a digital value using an A/D converter that operates at low speed. When a distance measuring device is configured using the circulating shift register, charges corresponding to an image are shifted by the circulating shift register. In this case, since the shift efficiency is less than 100%, the amount of charges immediately after a non-charge portion decreases as they are shifted, and such charges form a false image.
    Type: Grant
    Filed: January 30, 1997
    Date of Patent: December 8, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventor: Minoru Takasaki
  • Patent number: 5748035
    Abstract: Channel coupled feedback- technology for implementing many analog and digital signal processing functions in a single-polysilicon digital IC fabrication process is described. Field effect transistors are constructed having a common channel and the substrate regions of the field effect transistors in the channel are electronically connected. Thus, a fixed amount of charge can freely move within the channel in response to the application of the signal to be processed. By sensing the charge transferred within the channel when the input signal is applied, many signal processing functions are possible. Fixed-gain amplifiers, offset compensated amplifiers, integrators, differentiators, analog-to-digital converters, digital-to-analog converters, switchable gain amplifiers, automatic gain control systems, and linear transform computation circuits are constructed entirely with field effect transistors, eliminating the need for passive components for most signal processing functions.
    Type: Grant
    Filed: May 27, 1994
    Date of Patent: May 5, 1998
    Assignee: Arithmos, Inc.
    Inventor: Charles F. Neugebauer
  • Patent number: 5731833
    Abstract: In order to stabilize the reference level of an output signal from a solid-state image pick-up device, the solid-state image pick-up device includes an output circuit 12 for obtaining a picture signal Y1(t) from information charges outputted from a horizontal shift register 11, an impedance conversion circuit 13 for reducing the output impedance of the picture signal Y1(t) and a clamp circuit 14 for fixing the reference level in the picture signal Y1(t), all of which are integrated on the same semiconductor substrate.
    Type: Grant
    Filed: November 28, 1995
    Date of Patent: March 24, 1998
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Tohru Watanabe
  • Patent number: 5731722
    Abstract: A circuit for driving a capacitive load uses a plurality of driving signals with different phases including a quiescent time, and a driving time having a driving duration and an other time. An inductance element is connected across the driving terminals of the capacitive load, and a switch circuit is provided between a driving voltage source and the capacitive load. During the quiescent time, the switch circuit is closed to make the driving voltages the same potential, minimizing energy loss since no current flows during the quiescent time. During the driving time, the switch circuit is closed for a predetermined driving duration to clamp a sine wave around the peaks of the waveform, and the switch circuit is open during the other time when the sine wave is not at any of its peaks.
    Type: Grant
    Filed: July 28, 1995
    Date of Patent: March 24, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadashi Sugiki, Yukinori Ando
  • Patent number: 5675623
    Abstract: Signal processing involves accruing signal charge at photosensors, accumulating samples of the content of several adjacent photosensors in individual potential wells of a CCD according to a predetermined pattern, shifting them into individual stages of a first group of registers, and shifting the contents of the first group of registers into a second register to create a linear filtering operation. Accumulating the samples averages the content of adjacent pixels.
    Type: Grant
    Filed: December 4, 1995
    Date of Patent: October 7, 1997
    Assignee: Lucent Technologies Inc.
    Inventor: Kevin A. Shelby
  • Patent number: 5640028
    Abstract: A charge transfer device formed on a semiconductor substrate comprising: a charge transfer section formed on the semiconductor substrate for transferring charges, a floating gate having a floating gate diffusion layer formed on the semiconductor substrate for accumulating the charges transferred from the charge transfer section, an output gate section formed between the charge transfer section and the floating gate on the semiconductor substrate, and a charge detecting circuit electrically connected to the floating gate for outputting a voltage corresponding to the amount of the charges accumulated in the floating gate diffusion layer, the output gate section having a first output gate region adjacent to the charge transfer means and a second output gate region adjacent to the floating gate diffusion layer, the first output gate region having a first output gate electrode formed thereon with an insulating film therebetween, the second output gate region having a second output gate electrode formed thereon wit
    Type: Grant
    Filed: November 6, 1995
    Date of Patent: June 17, 1997
    Assignee: Sony Corporation
    Inventors: Seiichi Kawamoto, Yasuhito Maki, Tadakuni Narabu, Masahide Hirama
  • Patent number: 5634044
    Abstract: The control system controls the operation of a charge coupled device. The operation of the charge coupled device is responsive to a shift clock signal of a given frequency and a shift enable signal. The control system includes a timer for generating one of a number of shift clock signals. Each of the shift clock signals has a different frequency. A programmable register stores a plurality of control bits which may be programmed into the program memory of the control system. A multiplex switching is used for selecting one of the shift clock signals in response to the state of the control bits and directing the selected shift clock signal to the charge coupled device. An address decoder in response to addressing by the microprocessor, generates the shift enable signal which signal is directed to the charge coupled device concurrently with the presence of the selected shift clock signal.
    Type: Grant
    Filed: July 29, 1994
    Date of Patent: May 27, 1997
    Assignee: Pitney Bowes Inc.
    Inventors: Young W. Lee, Sungwon Moh, Arno Muller
  • Patent number: 5585652
    Abstract: The present invention is directed to methods and apparatus for accurately detecting light energy of a signal of interest (e.g., a laser pulse) even when the signal-to-noise ratio is relatively low. The present invention is further directed to accurate detection of a signal of interest even when either or both the signal of interest and background illumination vary across plural pixels of an imaging an array. For example, a signal of interest can be accurately detected even in the presence of pixel response non-uniformity and fixed pattern noise, or when the incident signal of interest is not confined laterally to a single pixel.
    Type: Grant
    Filed: October 25, 1994
    Date of Patent: December 17, 1996
    Assignees: Dalsa, Inc., Imra America, Inc.
    Inventors: Stacy R. Kamasz, Fred S. F. Ma, Michael G. Farrier, Mark P. Bendett
  • Patent number: 5539404
    Abstract: Analog memories such as CCD, which are advantageous in less power consumption and higher integration density, are used to configure a system for highly accurately executing digital/analog processing. A digital to analog converter according to the invention has at least one first analog memory having an input port for receiving input signal packets and a partial output drive port for driving the i-th output signal packet; at least one second analog memory having a function to integrate input signal packets applied thereto; and at least one signal packet routing mechanism for selectively routing output signal packets from the first analog memory according to an input digital signal bit. The extremely simple configuration of the present invention may be effectively utilized for realizing an ultra-parallel analog processor as well as applied to other fields such as video processing by combining a function of an input means for optical signals, which has been a main application of the CCD.
    Type: Grant
    Filed: February 7, 1994
    Date of Patent: July 23, 1996
    Assignees: Yasuo Nagazumi, G.D.S. Co., Ltd.
    Inventor: Yasuo Nagazumi
  • Patent number: 5524036
    Abstract: A charge transfer device having an improved signal stage is disclosed. This stage includes a floating region formed in a semiconductor layer and receiving signal charges from a charge transfer stage, a reset drain region formed in the semiconductor layer adjacently to the floating region, a reset gate for resetting the floating drain region in potential to the reset drain region, an absorption region formed in the semiconductor layer adjacently to the reset drain region, a barrier gate supplied with a constant voltage to form a channel region between reset drain region and the adsorption region, and a charge injection source connected to the reset drain region to inject charges thereinto.
    Type: Grant
    Filed: May 27, 1994
    Date of Patent: June 4, 1996
    Assignee: NEC Corporation
    Inventor: Kazuo Miwada
  • Patent number: 5508646
    Abstract: The invention concerns a charge-to-voltage converter including a read diode and a read transistor of no-load gain G.sub.o. The converter includes complementary circuits assuring a conversion gain greater than G.sub.o during read periods and a conversion gain substantially equal zero at other times.
    Type: Grant
    Filed: July 8, 1994
    Date of Patent: April 16, 1996
    Assignee: Thomson-CSF Semiconducteurs Specifiques
    Inventor: Jean-Alain Cortiula
  • Patent number: 5432364
    Abstract: An output circuit device for detecting and converting signal charge transferred thereto from a charge transfer section of a CCD into a signal voltage his constructed such that a gate oxide film of a driving side MOS transistor of a first stage source follower which receives signal charge is formed as a thinner film than gate oxide films of the other MOS transistors in the same circuit to reduce the 1/f noise.
    Type: Grant
    Filed: January 12, 1994
    Date of Patent: July 11, 1995
    Assignee: Sony Corporation
    Inventors: Hiroaki Ohki, Osamu Nishima, Hiroyuki Mori, Junya Suzuki
  • Patent number: 5393971
    Abstract: A charge transport apparatus for use in a signal information system (10) is disclosed. The apparatus includes a detector (18), having a number of radiation sensitive elements (24), for receiving a radiation signal (14) and generating electrical charge responsive to the received signal (14). The resulting charge is conveyed to a readout port area (32) by impressing a stepped potential gradient or a potential field with a varying sweep rate on the detector (18). The stepped potential gradient or variably swept potential field is communicated to the detector (18) via underlying tines (38).
    Type: Grant
    Filed: June 14, 1993
    Date of Patent: February 28, 1995
    Assignee: Ball Corporation
    Inventor: Wayne W. Frame
  • Patent number: 5386384
    Abstract: A fully parallel CCD memory chip of N address lines which detects in just one clock cycle, a perfect match between an input pattern and any of a plurality of stored patterns and also detects in less than (N+1)-comparison cycles and still just one XOR operation, the best matching in case a perfect one does not exist. The chip disclosed herein has a fully parallel architecture in which an input word is compared to all stored words at one time. A preferred embodiment of the invention uses a four phase CCD, wherein each stored word occupies one row of the CCD and each such bit of each such word occupies two cells. Where perfect matches exist, only one comparison clock cycle is needed to compare the input word with all stored words and where there is no perfect match, the best match will be detected on a subsequent comparison pulse. Charge packets represent binary words generated by external pulses that are applied to the chip through data input lines and then are compared to the data applied to the address lines.
    Type: Grant
    Filed: March 9, 1993
    Date of Patent: January 31, 1995
    Assignee: California Institute of Technology
    Inventors: Volnei A. Pedroni, Amnon Yariv, Aharon J. Agranat
  • Patent number: 5362978
    Abstract: A thinned backside illuminated charge-coupled imaging device has improved quantum efficiency by providing a sharp ion implant distribution profile (20) disposed at the rear surface (22) of the device. The sharp ion implant distribution profile (20) is formed using ion implantation at a beam energy potential of between 100-150 keV, which forms an electric field beneath the surface of the device. The ion distribution profile (20) is brought to the surface (22) of the device by removing silicon (18) from the rear surface (22), using a polishing technique wherein the device is lapped with colloidal silica abrasive to controllably remove silicon down to the level of the ion implantation profile (20).
    Type: Grant
    Filed: June 30, 1992
    Date of Patent: November 8, 1994
    Assignee: Hughes Aircraft Company
    Inventor: William America
  • Patent number: 5343060
    Abstract: The present invention is directed to a solid state imaging deice in which a light sensing region (3), a vertical register (4) and a channel stopper region (5) are formed within a well region (2) on an N-type silicon substrate (1). A positive electric charge storage region (6) is formed on the surface of the light sensing region (3) and a well region (7) is formed beneath the vertical register (4), respectively. Further, a transfer electrode (9) is selectively formed on the vertical register (4) through a gate insulating layer (8) and an Al light-intercepting layer (11) is formed on the transfer electrode (9) through an interlevel insulator (10). A surface protecting layer (12) is formed on the whole surface including the Al light-intercepting layer (11). In this solid state imaging device, a tapered portion (11a) is formed on the Al light-intercepting layer 11 corresponding to a peripheral edge portion of the light sensing region 3.
    Type: Grant
    Filed: January 21, 1993
    Date of Patent: August 30, 1994
    Assignee: Sony Corporation
    Inventor: Hideshi Abe
  • Patent number: 5294817
    Abstract: In an output circuit for a charge transfer device, a floating diffusion region is connected to a source side gate electrode of a double-gate read-out field effect transistor having its drain side gate electrode connected to the drain of the read-out transistor itself. Thus, the capacitance between the gate of the read-out transistor connected to the floating diffusion region and the drain of the read-out transistor can be made small, so that the total capacitance of the floating diffusion region is correspondingly reduced, with the result that a high detection sensitivity can be realized.
    Type: Grant
    Filed: April 2, 1993
    Date of Patent: March 15, 1994
    Assignee: NEC Corporation
    Inventor: Hiromasa Yamamoto
  • Patent number: 5291083
    Abstract: A bucket brigade analog delay line with voltage limiting feedback includes an input stage for receiving an input signal and a series of delay stages coupled to the input stage for propagating the input signal through the line. Each delay stage contains a storage capacitor for holding either a signal charge or a reference charge, a transfer device for transferring charge from one stage to another at regular clock intervals, and a tap circuit for allowing external sampling of the propagated input signal. Each delay stage also includes a negative feedback amplifier for maintaining the drain terminal of the transfer device at a constant potential during charge transfer, thereby eliminating errors caused by finite output impedance of the transfer device. The negative feedback amplifier also prevents overvoltage conditions which could result in failure of the charge transfer devices.
    Type: Grant
    Filed: January 12, 1993
    Date of Patent: March 1, 1994
    Assignee: Hewlett-Packard Company
    Inventors: Travis N. Blalock, Thomas Hornak
  • Patent number: 5287393
    Abstract: A charge coupled device transfers a charge packet to a floating diffusion region for producing voltage variation therein, and the voltage variation is relayed to an output terminal by means of a driving unit implemented by a plurality of source follower circuits coupled in cascade, wherein each of the second to final source follower circuits is implemented by a series combination of an enhancement type driving transistor and an enhancement type load transistor, and the enhancement type load transistor changes the channel conductance thereof complementary to the enhancement type driving transistor under the control of a control unit so as to improve the dynamic range of the output signal thereof without sacrifice of the sensitivity of the floating diffusion region.
    Type: Grant
    Filed: January 21, 1992
    Date of Patent: February 15, 1994
    Assignee: Nec Corporation
    Inventor: Kazuo Miwada
  • Patent number: 5276723
    Abstract: A floating diffusion type signal charge detection circuit for use in a charge transfer device includes a charge transfer region formed in a semiconductor layer, a plurality of transfer electrodes formed on the charge transfer region through an insulating layer, a floating diffusion formed in the semiconductor layer adjacent to a final stage of the charge transfer region, a reset drain formed in the semiconductor layer separate from the floating diffusion and connected to a reset drain voltage, and a reset gate formed through an insulating layer on a portion of the semiconductor layer between the floating diffusion and the reset drain. The floating diffusion, the reset drain and the reset gate forms a reset transistor. An amplifier is connected at its input to the floating diffusion so as to detect a voltage change appearing in the floating diffusion.
    Type: Grant
    Filed: May 14, 1991
    Date of Patent: January 4, 1994
    Assignee: NEC Corporation
    Inventor: Kazuo Miwada
  • Patent number: 5247554
    Abstract: A charge detection circuit includes a p-type semiconductor substrate, a reference voltage source for generating a reference voltage having a predetermined voltage difference with respect to the potential of the semiconductor substrate, a first n.sup.+ -type semiconductor region formed in the semiconductor substrate, for storing a carrier packet, a second n.sup.
    Type: Grant
    Filed: January 5, 1990
    Date of Patent: September 21, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tetsuo Yamada
  • Patent number: 5239565
    Abstract: In this invention, a plurality of clock buffers are provided to supply clock signals to a charge transfer apparatus. These clock buffers are driven by the same basic clock which is introduced through a plurality of clock logics. Accordingly, even if the charge transfer apparatus is comprised of a multi-stage charge coupled device having a large number of stages, those clock buffers still have enough ability to drive the charge transfer apparatus with high frequency. So, the driving circuit according to this invention can drive a multi-stage charge transfer apparatus with keeping the excellent frequency characteristics, even if the charge transfer apparatus is driven with high frequency.
    Type: Grant
    Filed: November 21, 1991
    Date of Patent: August 24, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shinihi Imai
  • Patent number: 5224134
    Abstract: A charge transfer device comprises a charge transfer section having a charge transfer region formed in a semiconductor substrate and transfer electrodes formed on the semiconductor substrate, and a reset transistor having a floating diffusion region formed in the semiconductor substrate for receiving an electric charge transferred from the charge transfer section, a reset drain applied with a reset voltage, and a reset gate formed above a channel between the floating diffusion region and the reset drain, the reset gate being applied with a reset pulse. A a peak hold circuit is connected to the reset gate of the reset transistor for hold a peak level of the reset voltage. A potential detection circuit includes a dummy transistor having a drain connected to a voltage V.sub.DD, a source grounded through a resistor which is considerably larger than an on-resistance of the dummy transistor itself, and a gate electrode connected to an output of the peak hold circuit.
    Type: Grant
    Filed: March 11, 1991
    Date of Patent: June 29, 1993
    Assignee: NEC Corporation
    Inventor: Kazuo Miwada
  • Patent number: 5220587
    Abstract: An amplification MOSFET in a source ground form receives at its gate an output signal of a source-follower circuit through a second capacitor. The source-follower circuit, on the otherhand, receives a voltage of a first capacitor which receives a signal charge. A predetermined bias voltage is supplied to the gate of the amplification MOSFET through a switch device while the signal charge of the first capacitor is reset. According to this structure, the second capacitor can transmit only the signal component and the voltage signal itself can be amplified by the source ground type amplification MOSFET. The amplification MOSFET can be biased to its optimum operation point by the switch device during the reset period of the first capacitor; hence, sensitivity can be substantially improved with a simple circuit structure.
    Type: Grant
    Filed: November 27, 1991
    Date of Patent: June 15, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Iwao Takemoto, Tatsuhisa Fujii, Atsushi Hasegawa
  • Patent number: 5210777
    Abstract: A charge coupled device is provided with a first signal input path for supplying an information signal for transfer through a delay line, which contain an inverting amplifier, and a second signal input path which has no inverting amplifier. The first and second signal input paths are arranged in parallel to each other. The charge coupled device also has a switching means associated with the first and second signal input paths so as to selectively establishing connection between one of the first and second signal input paths and the delay line so that non-inverted and inverted information signals can be selectively supplied to the delay line.
    Type: Grant
    Filed: April 16, 1990
    Date of Patent: May 11, 1993
    Assignee: Sony Corporation
    Inventors: Tadakuni Narabu, Tetsuya Kondo, Yasuhito Maki, Katsunori Noguchi
  • Patent number: 5204989
    Abstract: In a charge transfer device, a low impurity density region is provided in its portion forming a floating capacitor. It becomes possible thereby to reduce the capacitance of the floating capacitor and thus to ensure a larger output voltage relative to a signal charge.
    Type: Grant
    Filed: May 10, 1991
    Date of Patent: April 20, 1993
    Assignee: NEC Corporation
    Inventor: Junichi Yamamoto
  • Patent number: 5200983
    Abstract: A FISO analog signal acquisition system includes a plurality of CCD arrays (20a-20d), with each array containing a plurality of CCD serial registers (22). Each serial register (22) has a first cell (23) and a large number of additional cells (24) coupled in series with the first cell (24), with acquired samples being transferred along the string of additional cells (24) according to a clock signal having two or more phases, with each CCD array (20a-20d) operating in response to a set of clock signals having a different phase (P1,P2,/P1,/P2). A tapped delay line (10), or other similar hold signal generating means, produces a plurality of closely spaced-in-time sequential hold signals in response to a master hold signal. In response to each one of the hold signals, a CMOS transistor (Q.sub.x) briefly connects an associated first cell (23) to the signal to be sampled so that a series of closely spaced-in-time samples of the signal are acquired.
    Type: Grant
    Filed: April 17, 1992
    Date of Patent: April 6, 1993
    Assignee: Tektronix, Inc.
    Inventor: Grigory Kogan
  • Patent number: 5191599
    Abstract: A control device for a charge detection circuit comprising a CCD final gate electrode formed on a semiconductor substrate, an electric potential barrier forming gate electrode placed adjacent to the CCD final gate electrode, a diffusion region formed adjacent to the electric potential barrier forming gate electrode, a reset transistor connected to the diffusion region, a source follower circuit which uses as an input an electric potential in the diffusion region, a sample and hold circuit for receiving the output of the source follower circuit at a specified timing, a reference voltage source which has a value determined by the dynamic range of the source follower circuit, and an integrator which integrates a difference between the output of the sample and hold circuit and the output of the reference voltage source, and applies a value obtained by the integration to the electric potential barrier forming gate electrode.
    Type: Grant
    Filed: November 8, 1991
    Date of Patent: March 2, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Toshiki Seto
  • Patent number: 5189498
    Abstract: A charge coupled device includes a second conductivity type first horizontal channel in a first conductivity type semiconductor substrate, a second conductivity type second horizontal channel in the substrate at a predetermined distance from the first horizontal channel, and a second conductivity type transfer channel connecting the first horizontal channel with the second horizontal channel to enable transfer of charges from the first horizontal channel to the second horizontal channel. The pinning potential of the transfer channel is larger in absolute value than the pinning potential of the first and second horizontal channels, and the gate voltage pinning the transfer channel is smaller in absolute value than the gate voltage pinning the first and second horizontal channels.
    Type: Grant
    Filed: November 2, 1990
    Date of Patent: February 23, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kiyohiko Sakakibara