Abstract: A charge transfer device having a plurality of transfer gates to which phased clock pulses are provided to transfer charge serially from semiconductor regions underlying the transfer gates through an output region underlying an output gate to a charge detector region. The last transfer gate preceding the output gate is fed with a phased clock pulse via a signal line other than the signal lines feeding the remaining transfer gates. The former signal line has an RO time constant lower than that for the other signal lines and permits rapid charge transfer from the last stage to the charge detecting device.

Abstract: In a plural-level gate metallization CCD shift register the clocking voltages applied to the levels are automatically supplied differential offset biases to cause the potential wells to have uniform depth. The differential offset biases are developed responsive to the differences in the threshold voltages of insulated-gate field effect transistors integrated on the same semiconductor substrate as the CCD shift register so as to have their gate electrodes in the different levels of gate metallization.

Abstract: Pulse-duration-modulated signal is generated from samples of an analog signal voltage in a CCD device by fill-and-spill input of charge into the CCD device, scooping of fixed unit charge to generate a pulse train with pulses in a number proportional to the sample analog voltage, and box-car detection. The box-car detection uses a floating electrode, the resetting of which is selectively inhibited until just past the last pulse in the train that equals or exceeds the potential midway between the potentials defining logic ZERO and logic ONE.

Abstract: Charge subtraction for charge packets of two charge transfer device (CTD) delay lines is provided by alternately transferring them under a periodically clamped, normally floating sense gate, common to both delay lines. Adjacent the sense electrode, each delay line includes preceding and succeeding transfer gates, the gates of each line clocked by one of first and second oppositely phased clock signals for alternately transferring the charge packets under the sense gate. A reset switch clamps the sense gate to a reference voltage whenever its input voltage exceeds a first threshold level and unclamps the gate whenever its input voltage falls below the first threshold level.

Abstract: A pulse generator circuit for applying a pulse signal to the input source electrode of a charge coupled device (CCD) having a "fill and spill" input operation, includes a voltage reference circuit for generating the "fill" voltage level of the pulse signal and a capacitive element circuit for boosting the voltage level of the pulse signal to a "spill" voltage level which exceeds the operating potential applied to the pulse generating circuit. With this type of pulse generating circuit the operating potential applied to the CCD and its support circuitry (including the pulse generator circuit) can be reduced in order to lower system power consumption while ensuring proper "spill" operation.

Abstract: An accumulation-mode bulk channel CCD converts an electromagnetic radiation pattern into electrical signals. The device body may be of monocrystalline silicon and has a radiation-sensitive region which is of a first conductivity type determined by a dopant (e.g. sulphur, platinum, indium or thallium) having an energy level or levels sufficiently deep in the semiconductor band gap that substantially all of said dopant atoms are un-ionized at the device operating temperature. By this means the region is substantially free of majority charge carriers in the absence of radiation, and majority charge carriers trapped by the dopant atoms can be released upon excitation by the radiation. A first ohmic contact to the region supplies majority charge carriers to the dopant to replace charge carriers released by the incident radiation.

Abstract: In a device for current-reading of a quantity of electric charges, the control circuit for the first and second MOS transistors receives a constant potential and comprises:a third transistor, the drain and gate of which are connected to the constant potential and the source of which is connected to the drain and to the gate of the second transistor;a second capacitor connected through one of its terminals to the nodal point of the second and the third transistor.The device is employed for reading quantities of charges which arrive under the storage electrodes of charge-transfer filters.

Abstract: Trade-off between dynamic range and sampling rate in a charge coupled device is virtually eliminated in the serpentine charge coupled device of the present invention. In this device, for each charge packet transferred in a first direction, a plurality of n charge packets are transferred in a second transverse direction in the serpentine register. Accordingly, for a given charge transfer rate in the first direction, the charge coupled device clock frequency is increased by a factor of n. The serpentine register is formed on the semiconductive substrate having two parallel channel stops extending in a first direction and a plurality of parallel interlaced channel stop fingers extending in a second direction which are alternately connected to the two parallel channel stops.

Abstract: A charge domain parallel processing network. The network includes a floating gate CCD tapped delay line and an array of CCD signal processors each including a charge domain digital-analog multiplier. The delay line holds and shifts analog sampled data in the form of charge packets. At each stage of the delay line a floating gate sensing electrode is coupled to an analog input of an associated one of the CCD signal processors. The sampled data in the respective delay line stages are transferred and subsequently processed in parallel in the processors. Within each processor, the computation functions are performed in the charge domain. In some forms, local charge domain accumulating memories accumulate and store the processed signals, for example, providing a matrix-matrix product network or providing a triple-matrix product network.

Abstract: A charge domain digital-analog multiplier device. The device has one analog input, M-parallel digital inputs, and one analog output. An M-bit digital word signal is applied to the digital inputs and an analog signal is applied to the analog input. The output is a charge packet which is proportional to the product of the analog input signal and the digital word.

Abstract: A matrix operation device performs matrix multiplication of an input electrical signal by utilizing a plurality of charge-coupled devices having split electrodes. The multiplication is carried out by the split electrodes of the charge-coupled devices. A signal to be transformed is sampled by a delay circuit in the input of the operation device. The sampled signal is supplied to the operation device in the form of a time series or sequence consisting of the sample signals. Each sample is multiplied by a corresponding coefficient. The split electrodes of the charge-coupled devices have weighting coefficients corresponding to coefficients in the matrix. The samples multiplied by the coefficients are added in the output of the operation device and provided as an output signal, corresponding to the development of the matrix multiplication.

Abstract: In a charge transfer device wherein the charge transfer channel is bent through a predetermined angle of, for instance, 45.degree., 90.degree. or 180.degree., a unit of each bend includes at least two juxtaposed gate electrodes each of which has a portion bent by an angle equal to said predetermined angle relative to the axis of the preceding channel in such a way that the gate electrodes in the bend may be substantially equal in area to those in the straight charge transfer line sections and the channel length in the bend may be substantially equal to that in the straight charge transfer line section, whereby the decrease in transfer efficiency and S/N ratio due to the differences in gate area and channel length may be eliminated.

Abstract: A signal synthesizer apparatus having a parameter dependent multiplier which includes charge-coupled devices. The multiplier has a gating input to store a charge corresponding to an input signal applied thereto; a first set of transmission gates for selectively transferring portions of the stored input charge, the selectivity of the transmission gates being dependent on a prescribed parameter; a plurality of intermediate electrodes for storing the charges transferred by the transmission gates; a second set of transmission gates for transferring the charges stored by the intermediate electrodes; and an output electrode for combining all of the charges transferred from the intermediate electrodes by the second set of transmission gates. The signal output by the multiplier corresponds to the magnitude of the combined charges of the output electrode.

Abstract: CCD methods and devices for recording transient data signals, in which charge is transferred under the influence of transmission line fields at sampling sites disposed along a charge transfer channel.

Abstract: A solid state image-sensing device which includes photoelectric conversion regions for generating charges in amounts corresponding to those of light received by the photoelectric conversion regions, a charge-storing region for storing the charges produced in the photoelectric conversion regions, a charge transfer region, and a charge-shift control region for controlling the transfer of a charge stored in the charge-storing region to the charge transfer regions. The solid state image-sensing device further includes a charge shifting region which is formed between the charge-storing region and photoelectric conversion regions to successively shift the charges generated in the photoelectric conversion regions to the charge-storing region.

Abstract: A CCD comb filter is provided employing a basic block having a first, a second and a third delay line wherein particular mixing of the signals from the delay lines results in three outputs having a desired ratio. This basic block is utilized to construct a contour compensation circuit, a drop-out compensation circuit and a 3H delay line. The basic block is versatile and can be utilized for constructing other devices also.

Abstract: In a charge-coupled device, several bent electrodes and storage sites under the bent electrodes are disposed in a turning part for turning transfer direction of charge signal and they respectively have a first part having right angles to an initial direction and a second part having right angles to a direction to be changed, the first part decreases and the second part increases responding to a distance from an upstream part to a downstream part of the turning part.

Abstract: A charge coupled device is disclosed which includes a plurality of stages having increased charge storage capacity and decreased leakage current. Each stage is comprised of a semiconductor substrate of a first-type conductivity having a first surface. A charge transfer channel extends through the stage. An insulating layer of non-uniform thickness lies on the first surface. The insulating layer has at least two spaced apart relatively thick portions traversing the channel, and has relatively thin portions traversing the channel throughout the spaces between the spaced apart thick portions. Phase electrodes traverse the channel such that each phase electrode overlies one relatively thick portion and one adjacent relatively thin portion of the insulating layer. A shallow dopant layer of a second-type conductivity lies throughout the channel relatively near to the first surface.

Abstract: A signal compressor apparatus utilizing a charge coupled device having a charge storage well wherein the charge storage capacity is variable over the integration time of the device. During the minimum charge storage period, the input charge which exceeds an established limit is dumped, thereby providing compression of the input signal.

Abstract: This serial to parallel to serial (SPS) charge coupled device (CCD) shift register memory has a serial output shift register with stage gate electrode structures that are interdigitated with the gate electrode structures of each last stage of a plurality of parallel shift registers to transfer interlaced data bits from the parallel shift registers to the serial output register in a sequential order. This is done without employing a fixed voltage midway between the highest clock voltage and reference potential in the parallel registers in what is commonly called a midway store to regulate the transfer of data to the interdigitated gate electrode structures.

Abstract: Uniform background charge subtraction in a radiation sensing array is realized by removing the background charge from the array detectors several times during each array integration time. Radiation sensing arrays of the type to which the method of the invention can be applied include a radiation sensor with a charge storage reservoir to which there is coupled a CCD output register having a channel with multiple charge storage sites. Signal background and bias charge is accumulated in the charge storage reservoir and transferred to a CCD storage site by a transfer gate. Charge in the CCD storage site can be shifted to another storage site in the CCD channel or it can be dispersed to drain by means of a drain barrier gate. According to the method of the invention a number of times during each array integration period the charge accumulated in the charge storage reservoir is transferred to a CCD charge storage site and then returned in part to the reservoir leaving a metered amount in the charge storage site.