Abstract: As multiphase clocks to be supplied to a first gate driver that drives odd-numbered scanning lines in a liquid crystal display region and a second gate driver that drives even-numbered scanning lines, clocks, which are effective within an effective period of the image signal just before an image signal starts to be supplied to display elements for each scanning line of the liquid crystal display region, is generated and the first and second gate drivers drive switching elements in the effective period of the clock.

Abstract: A high voltage shift register stage which directly accepts low voltage clock signal inputs without using clock buffers. In particular, a shift register stage circuit is adapted to operate with a low voltage swing clock signal, with the stage circuit having a single state node, a, driven directly. This arrangement allows for reduced power consumption and higher operating speeds.

Abstract: Each stage of a shift register circuit has a first input (Rn?1) connected to the output of the preceding stage, a drive transistor (Tdrive)for coupling a first clocked power line voltage (Pn) to the output (Rn) of the stage, a compensation capacitor (C1) for compensating for the effects of a parasitic capacitance of the drive transistor, a first bootstrap capacitor (C2) connected between the gate of the drive transistor and the output (Rn) of the stage; and an input transistor (Tin1) for charging the first bootstrap capacitor (C2) and controlled by the first input (Rn?1). Each stage has an input section (10) coupled to the output (Rn?2) of the stage two stages before the stage having a second bootstrap capacitor (C3) connected between the gate of the input transistor (Tin1) and the first input (Rn?1). The use of two bootstrapping capacitors makes the circuit less sensitive to threshold voltage levels or variations, and enables implementation using amorphous silicon technology.

Abstract: A FIFO register unit is provided, comprising a first sub-register unit, an input multiplexer and an output multiplexer. The first sub-register unit comprises a first register, a second register and a third register. The first register comprises an input terminal to receive a first input data. The second register receives data from the first register. The third register receives the first input data from the input terminal, data from the first register or data from the second register and determines one of them to output as a first output data.

Abstract: A disable circuit for using in a dynamic shift register unit comprising: a first input, a second input, an output, a first reference line for receiving a first supply voltage, a second reference line for receiving a second supply voltage, and six transistors. The disable circuit is capable of being coupled with a dynamic shift register unit having an input for receiving an input pulse and an output for outputting a shifted pulse. The disable circuit generates an output signal during an input pulse period or an output pulse period for the dynamic shift register unit, wherein the input pulse period and the output pulse period are responsive to a first input pulsed signal from the first input and a second input pulsed signal from the second input, respectively.

Abstract: Each stage of a shift register circuit has a first input (Rn?1) connected to the output of a preceding stage, a drive transistor (Tdrive) for coupling a first clocked power line voltage (Pn) to the output (Rn) of the stage, a compensation capacitor (C1) for compensating for the effects of a parasitic capacitance of the drive transistor, a first bootstrap capacitor (C2) connected between the gate of the drive transistor and the output (Rn) of the stage; and an input transistor (Tin1) for charging the first bootstrap capacitor (C2) and controlled by the first input (Rn?1). Each stage has an input section (10) coupled to the output (Rn?2) of the stage two (or more) stages before the stage having a second bootstrap capacitor (C3) connected between the gate of the input transistor (Tin1) and the first input (Rn?1). The use of two bootstrapping capacitors makes the circuit less sensitive to threshold voltage levels or variations, and enables implementation using amorphous silicon technology.

Abstract: A circuit comprises a first circuit portion (52) controllable by first and second inputs, and a second circuit portion (54) for generating the second input. The first circuit portion (52) has first operating characteristics when the second input (invPn) is provided as control input, and second operating characteristics when the second input (invPn) is not provided as control input. The second circuit portion (54) is adapted to cease functioning through ageing before the end of the lifetime of the first circuit portion (52) thereby to switch the first circuit portion from the first to the second operating characteristics. This circuit uses the failure of a portion of the circuit which generates at least one input control signal, so as to change the overall circuit characteristics as the circuit ages.

Abstract: In one embodiment, an apparatus includes a system pulse latch to generate at least one system latch signal in response to a data input signal and a pulsed system clock signal; a shadow pulse latch to generate at least one shadow latch signal in response to the data input signal and the pulsed system clock signal; and an output joining circuit, coupled to the system pulse latch and the shadow pulse latch, to provide a data output signal in response to the at least one system latch signal and the at least one shadow latch signal.

Abstract: The shift register, which is an n-th shift register of a shift register chain, includes a first multiplexer, a second multiplexer, and a latch block, wherein n is a positive integer. The first multiplexer selects one of output data of the (n?1)-th shift register or output data of the (n+1)-th shift register and outputs the selected data to be used as a reset signal in the latch block. The second multiplexer selects one of the output data of the (n?1)-th shift register or the output data of the (n+1)-th shift register and outputs the selected data to be used as input data of the latch block. The latch block stores the output data of the second multiplexer in response to the clock control signal, the inverted clock control signal and the reset voltage, and outputs the stored data.

Abstract: In a shift register, which is for use in an image display apparatus of the TFT active matrix type in which a driver circuit is integrally provided on a display panel, and which is so arranged as to boost a start pulse SP to a start pulse SPO by using a level shifter, and to supply the start pulse SPO to a flip-flop F1 of a shift register section, the start pulse SP having an amplitude lower than a driving voltage and being supplied thereto, the shift register is provided with an operation control circuit for inactivating the level shifter when the first stage flip-flop F1 outputs an output signal S1 and activates the level shifter when a last stage flip-flop Fn outputs an output signal Sn. Therefore, it is possible to reduce power consumption of the level shifter during a period in which the start pulse SPO is transmitted from a flip-flop F2 to a flip-flop Fn?1.

Abstract: An apparatus and method is disclosed for automatically controlling multi-input-single-output (MISO) systems or processes. The control output signal of a single-input-single-output (SISO) automatic controller is converted by a reverse, sequential or combined split-range setter into a plurality of ranges of signals so that the SISO controller is converted to a single-input-multi-output (SIMO) automatic controller based on certain criteria; and the resulting controller output signals are able to manipulate a plurality of actuators to control one continuous process variable in different operating conditions. Without the need of building process mathematical models, this inventive apparatus and method is useful for automatically controlling unevenly paired multivariable systems or processes where there are more system inputs than outputs including but not limited to pH processes, chemical reactors, and air handling units.

Abstract: An improved technique of interfacing a computer lighting device to a control computer is disclosed, wherein a hardware device is interposed between the control computer and the lighting device. The hardware device handles certain functions in hardware, thereby permitting the microprocessor at the lighting device to incur substantially less processing load.

Abstract: A bi-directional shift-register circuit for outputting data in different turns according to a switching signal. Each shift-register unit includes a first input terminal, a second input terminal, an output terminal and a clock input terminal for receiving the clock signal.

Abstract: Each of stages RS(1), RS(2), . . . of a shift register is constituted by six TFTs. A ratio of a channel width and a channel length (W/L) of each of these TFTs 1 to 6 is set in accordance with a transistor characteristic of each TFT in such a manner that the shift register normally operates for a long time even at a high temperature.

Abstract: An apparatus and method is disclosed for providing a phase locked loop clock divider circuit utilizing a high speed linear feedback shift register with a two stage pipeline in its feedback path. A plurality of “pre-load” flip flop (PLFF) circuits and multiplexers are coupled to a plurality of linear feedback shift register (LFSR) flip flop circuits and multiplexers. The PLFF circuits hold pre-calculated initial LFSR sequence values to be loaded into the LFSR flip flop circuits. The load enable signal to the PLFF multiplexers and to the LFSR multiplexers is low for three successive input clock cycles. The present invention is capable of operating at high frequencies due to a shortened timing critical feedback path.

Abstract: A shift register that is suitable for reducing the required number of clock signals as well as simplifying the configuration of an external control circuit uses a plurality of stages connected, in series, to a start pulse input line. In each stage, an output circuit responds to a first control signal to apply any one of first and second clock signals to a row line of a liquid crystal cell array and thus to charge the low line of the liquid crystal cell array, and responds to a second control signal to discharge a voltage at the row line. An output circuit responds to a clock signal different from any one of the start pulse and an output signal of the previous stage to generate the first control signal, and responds to a clock signal different from the first control signal to generate the second control signal.

Abstract: The present invention comprises a multi-function shifter that uses N-nary logic and includes an operation selection and various 1-of-N multiplexers to support a variety of shift modes. The shift modes include rotates, logical shifts in which 0 is shifted into any vacated bit positions, and arithmetic shifts in which the value of the original most significant bit is shifted into any vacated bit positions. The present invention includes a general 32-bit shifter that can shift an arbitrary number of places in a single cycle, using any of the modes described above.

Abstract: A high speed barrel shifter in which fill input data is especially added.

Abstract: A remote control transmission circuit for generating a multicarrier under control of a single microcomputer. This transmission circuit is arranged so as to allow reduction of the number of the program commands and making it easy to perform a different process during the output of the multicarrier. The number of the shift circuits of the shift circuits 2a to 2f which are connected is set by a switching circuit 4. A change-over switch 6 performs the change-over operation as to whether a new shift circuit 5 is coupled. The change-over switch 6 is controlled by an overflow signal of a counter 7 whose count source is an inversion signal of the carrier (multicarrier) output 1. The control of the change-over switch 6 automatically controls the period for the correction of the carrier output 1 without the control due to the microcomputer.

Abstract: A shifting circuit operates on a plurality of input sub-words, that collectively constitute an input data word, to generate a plurality of result sub-words that collectively represent the input data word, shifted. The shifting circuit receives, during each cycle, a separate one of the plurality of input sub-words. A combiner/selector performs a shift on each sub-word provided on the I-bus, taking carry-in bits from a carry-in register. Before a shifting operation is executed, the carry-in register is initialized to zero. (Alternately, the carry-in register may be reset to zero after a shifting operation is executed.) The carry-in register is also connected to receive the sub-words provided by the data source circuit onto the I-bus.

Abstract: A data shift control circuit for a shift register in response to a logic operation command code is disclosed. The shift register includes a first register and a second register and the logic operation command code includes a first portion and a second portion. The circuit includes a first decoder for decoding the first portion to transmit a move signal; a second decoder for decoding the second portion to transmit a control signal; a control signal channel, electrically connected to the first register and the second register, for allowing the first register and the second register to receive the control signal and for allowing the shift register to execute a first action; and a move signal channel, electrically connected to all registers of the shift register for allowing the all registers to receive the move signal and for allowing the move register to execute a second action.

Abstract: A barrel shifter for shifting a plurality of bits in a single clock cycle has a bypass circuit through which unshifted results from an arithmetic logic unit (ALU) are bypassed around a shift circuit and provided directly to an output of the barrel shifter. An isolation circuit having tristate inverters isolates the shift circuit of the barrel shifter from the ALU results when the results are not to be shifted so that internal signal nodes of the shift circuit with high capacitance will not be switched. When the results are to be shifted, the tristate inverters of the isolation circuit are enabled to pass the results to the shift circuit where they are shifted and then provided to the barrel shifter output. By providing the results to the shift circuit only when a shift is to be performed, and otherwise isolating the shift circuit, power consumption is reduced.

Abstract: A data input/output circuit includes a 32-bit reversible shift register (1) which includes four 8-bit reversible shift registers (2-5). Input gate circuits (6, 7) selectively apply data being inputted in a bit-serial fashion from an external to the 8-bit reversible shift registers (3, 4), and output gate circuits (8-12) selectively output data being stored in arbitrary stages of the 32-bit reversible shift register (1) in a bit-serial fashion. Input latches (13-15) and output latches (16-18) each of which is an 8-bit latch are connected to the respective 8-bit reversible shift registers (2-4) and a data bus (19). The input latches (13-15) hold the data being stored in the 8-bit reversible shift registers (2-4) and send the same onto the data bus (19) in a bit-parallel fashion, and the output latches (16-18) hold the data being sent from the data bus (19) and preset the same into the 8-bit reversible shift registers (2-4) in a bit-parallel fashion.

Abstract: A emitter coupled logic circuit is reduced in circuit scale, while maintaining the speed of shift registers and compatibility with analog circuits. When data held in the first self-holding circuit section 41 or the second self-holding section 42 is deleted, the threshold voltage VTH applied to the base electrodes of the first and third transistors Q41 and Q43 is set outside the logical amplitude. When data is transferred, also, the threshold voltage VTH is set at a value intermediate to the logical amplitude. Because of this the data held in the first and second self-holding circuit sections can be reliably deleted without an increase in the number of elements.

Abstract: A serial bit input controller uses clock and data input lines for communicating command information, as well as the clock and data information, to an integrated circuit chip. The circuit functions by employing a multi-stage shift register as a command storage register. The outputs of the shift register are connected to the inputs of coincidence logic gates, the outputs of which in turn supply signals to command state latch circuits. The selection of any one of the command state latch circuits depends upon the data stored in the multi-stage shift register. The shift register, in turn, is enabled by signals on the clock line by holding the clock line high and toggling it with data pulses. When the desired count is reached, the clock signal is allowed to resume, and is applied to the latch circuits to store the command state in the selected latch circuit. To clear the system, a two-stage binary clear latch is employed.

Abstract: A successive-approximation register (SAR) has a single shift register for processing, that is presetting and selectively resetting, a number of bits. The single shift register is arranged to provide bit selection for processing the bits and also to provide desired result accumulation in the processed bits. Further, the single shift register comprises an array of stages, the stages including a first stage, a last stage and a number of active stages equal to the number of bits of digital output. Conveniently, the SAR adopts a "One-bits to Right" test implemented by a Manchester Carry Chain in the opposite direction to the shift direction.

Abstract: A bi-directional shift register capable of transferring bit data in either a forward or reverse direction. The shift register includes multiple transfer elements (e.g., flip-flop circuits) cascaded together which provide synchronous transfer of the bit data from one stage to an adjacent stage in either direction. The shift register further includes two switching circuits for electrically connecting an input terminal of one transfer element to an output terminal of the adjacent transfer element. The first switching circuit is enabled to cause the transfer of the bit data in the forward direction, and the second switching circuit is enabled to cause the transfer of the bit data in the reverse direction.

Abstract: A scannable flip-flop circuit allows data at its data input or its scan input to be stored in the flip-flop at its data output or shifted out of the flip-flop at its scan output. The flip-flop provides control circuitry for selecting the source of the input data and scan data. Data stored at the flip-flop data output may also be shifted out at the scan output. During scan operations, additional control circuitry allows data stored at the data outputs to be preserved.

Abstract: A shift count confirmation shift register capable of receiving and storing logic values and sequentially providing representations thereof at the storage register output, as well as providing a shift complete signal at a confirmation signal output upon the completion of the shifting of these logic states stored therein.

Abstract: An improved shift register assembly having an integrated multi-phased dynamic shift register with a corresponding multi-phased driving buffer for addressing elements of an array. The shift register and buffer combination is used to select segments on the array having a common select line thus reducing the number of input lines needed to address such an array. Furthermore, the multi-phased operation of the shift register allows for faster operation than tyhat of a traditional shift register setup.

Abstract: A phase lock loop monitors the frequency of redundant input clock signals and switches back and forth therebetween should one or the other become invalid. Thus, the PLL may continue normal operation even with a failure of one input clock signal. If both the input clock signals fail, an internal reference signal maintains the PLL at a nominal operating frequency until one of the input clock signals is restored whereby the loop can quickly re-establish phase lock. To determined validity, the input clock signals are sampled and stored by the reference signal in a predetermined manner. The input clock signal is valid if the samples of the input clock signal each have the same logic state after the sampling period; otherwise, the input clock signal is invalid if the samples of the input clock signal have at least one different logic state after the sampling period.

Abstract: A scan-register having first and second data input ports (SYS.sub.-- DATA, SCAN.sub.-- IN), a data output port, and inputs for at least first, second, third, and fourth control signals (SYS.sub.-- CLK, M.sub.-- LOAD, CLK.sub.-- B, CLK.sub.-- A).

Abstract: A variable length shift register is formed of a plurality of flip-flops arranged to form separate shift registers of different lengths. The shift registers are interconnected by multiplexers which connect either the input or the output of each shift register to the input of an adjacent shift register. Control signals are provided to the multiplexers to controllably select the length of the variable shift register by selectively inserting shift registers into the variable shift register and bypassing others.

Abstract: An optical serial-to-parallel converter constructed from at least two optical shift registers connected in cascade, each optical shift register having a 1.times.2 optical switch connected to its output. Each optical shift register in the sequence is optically coupled to the next sequential optical shift register through one output of said 1.times.2 optical switch to the input port of the next sequential optical shift register. The input port of the first optical shift register serves as the input to the optical serial-to-parallel converter, receiving a series of optical pulses. The output ports of each of said third optical switches serve as the output ports of the optical serial-to-parallel converter. The optical shift registers are controlled by two clocks, operating at the same rate, but each out of phase with the other.

Abstract: A hybrid superconducting-semiconducting field effect transistor-like circuit element comprised of a superconducting field effect transistor and a closely associated cryogenic semiconductor inverter for providing signal gain is described. The hybrid circuit functions as a nearly ideal pass gate in cryogenic applications.

Abstract: A universal shift register (200) utilizes a matrix (236-251) of high speed transmission gates to effect the various modes of register data manipulation in place of conventional operating mode selection logic gate elements. The shift register additionally includes apparatus allowing for the cascading of the register with units of similar design.

Abstract: A data processing circuit having a bit reverse function and including a bit reverse circuit which reverses a bit string of data and a shifting circuit which shifts the data with the reversed bit string such that a part of the bit string or arbitrary bits of the data may be selectively reversed according to an information representing bits to be reversed.

Abstract: Through the step number control transfer gate activated by the step number control signal, the input data is sent into a specific transfer step of the shift register, and the data transferred from the specific transfer step is delivered from the output step. By selecting an arbitrary step number control transfer gate, the input transfer step is varied without changing the output step to change to an arbitrary data delay length. Therefore, only by increasing the driving capacity of the driver of the input data, a shift register short in delay time, small in increase of integration area, and low in power consumption will be obtained.

Abstract: A FIFO memory device facilitates transfer of data between a host CPU and a peripheral device in one of a number of modes. In one mode, the FIFO memory device functions as two FIFO memories, one for passing data from the host CPU to the peripheral device, and one for passing data to the host CPU from the peripheral device. In another mode, the FIFO memory device functions as a single FIFO which facilitates passing data from the host CPU to the peripheral device or from to peripheral device to the host CPU. The FIFO includes two RAMs addressed by a set of address counters. Of importance, the host CPU can bypass the address counters to directly address each RAM, thereby reading data from or writing data into either RAM regardless of the state of the address counters.

Abstract: There is disclosed a barrel shifter for providing efficient wiring therein and a compact composition as compared with conventional ones, in which a low-level-input resistor and a high-level-input resistor are arranged in parallel to each other, and low-level-input-bit lines and high-level-input-bit lines are alternately arranged corresponding to both resistors respectively, the width of both the input and output sides of a barrel-shifter main unit are so arranged as to be substantially the same as the width of the respective resistors substantially defined by wiring width of the respective input-bit lines, and a wiring area from the high-level-input resistor is incorporated in the barrel-shifter main unit as well as a wiring area from the low-level-input resistor.

Abstract: An optical shift register constructed from at least two optical memory cells connected in cascade, each memory cell having an optical combiner, a 1.times.2 optical switch, a clock, and an optical amplifier, all connected by optical fibers. Each memory cell in the sequence is connected to the next sequential cell by an optical fiber from its output port to the input port of the next sequential cell. The input port of the first optical memory cell serves as the input to the shift register. The output port of the last sequential optical memory cell serves as the output port of the shift register. Each cell is controlled by a clock, all clocks operating at the same rate, but each out of phase with the clock in the next sequential cell. Control signals are provided by said clocks to shift optical pulses from one cell to the next for the enter-shift-exit cycle of the shift register.

Abstract: A logic integrated circuit of the scan path system comprises a combination circuit and a shift register associated to the combination circuit and including a plurality of cascaded flipflops. The shift register has a scan input, a clock input, a scan control input, and a scan output. A scan input terminal is connected to the scan input of the shift register, and a clock terminal is connected to the clock input of the shift register. A scan output terminal is connected to the scan output of the shift register. Further, there is provided a counter having an input connected to the clock terminal and an output connected to the scan control input of the shift register. This counter has a frequency division ratio equivalent to the stage number of the flipflops in the shift register, so that the shift register is switched between a shift register mode and a normal mode by the frequency division signal from the counter.

Abstract: In the present invention, a reprogrammable control circuit is disclosed. The reprogrammable control circuit comprises a single-bit register for serially receiving an input bit signal and providing a control signal. The control signal represents the state of the bit stored in the register. A transmission gate means receives the control signal from the single-bit shift register and an input signal and provides an output signal therefrom. The control signal of the bit shift register is used to control the transmission of the input signal to the output signal. A plurality of reprogrammable control circuit which comprises a plurality of bit shift registers, each having a transmission gate means associated therewith is also disclosed. The reprogrammable control circuit can be used in an improved PLA, improved RAM, improved RCIM, improved ALU, improved counter, improved CAM, PCN to improve the reliability of routing signals and power, and to preserve the states of flip-flops.

Abstract: A register circuit comprises a plurality of registers commonly receiving a data signal and selection signals respectively, each of the registers including a first input terminal for receiving the data signal; a second input terminal for receiving a corresponding one of the selection signals; an output terminal for outputting a stored data signal; a storing unit, connected to the output terminal, for storing the data signal; and a control unit, connected to the storing unit, the first input terminal, the second input terminal, and the output terminal, for transferring the data signal to the storing unit when the selection signal is effective and resetting the storing unit when the data signal is already stored in the storing unit and the selection signal is not effective.

Abstract: In a digital control system wherein control voltages are analog voltages, a method and control system for generating a variable output bit resolution from an N bit analog to digital converter utilizing a control circuit to control the input spread of the voltage references to the A/D converter. Depending on the binary value of the MSD position, the input reference voltage spread is controlled. If the binary value is zero, the input reference voltage spread is one-half the normal value and the resolution is N+1 bits and if the binary value is zero for both the MSD and MSD-1 positions, the input reference voltage spread is one-fourth the normal value and the resolution is N+2 bits and so on until the first binary one value is found after consecutive preceding binary zero values.

Abstract: Apparatus is disclosed for establishing scan-ring testing circuitry and control logic therefor on CMOS integrated circuit chips which can then be tested thereby during fabrication, after wire bonding and packaging, and while assembled and connected with other components on a printed circuit board. Tri-state buffers fabricated on the IC chip within the scan-ring control circuitry facilitate the operation of the scan-ring testing circuitry in several distinct operating modes which enable the functional circuitry of the integrated circuit to be electrically isolated from the associated signal pads for testing of the functional circuitry independently of circuitry connected to the signal pads, and for testing circuitry connected to the signal pads independently of the function circuitry of the chip.

Abstract: A serial-to-parallel converter has a number of memory cells connected in series for successively shifting input data in synchronism with a shift clock. The content of each memory cell is transferred by a latch circuit. The memory cells are provided with input terminals so that they can be set to "1" or "0" simultaneously before the entry of input data. This resetting, or presetting, reduces the number of reversals of the output polarity of the memory cells and hence the power consumed by the circuit can be diminished.

Abstract: A programmable logic device includes an AND plane and an OR plane associated with the AND plane. At least one of the AND and OR planes includes an array of programmable memory elements which can be selectively programmed to define a desired logic function. In one form, a function cell designed for providing one of a predetermined functions, such as a counter or shift register function, selectively is provided. In another form, a driver circuit connected to a pair of input lines has a first state in which one of the paired input lines serves as an inverting input line and the other as a non-inverting input line and a second state in which both of the paired input lines are set at low level. In a further form, two pairs of input lines of the AND plane are connected to an input or input/output terminal of the device.

Abstract: A combined digital-to-analog converter and latch memory circuit (10) includes an R-2R resistive ladder network (12) and a current-controlled latch memory 18. The R-2R resistive ladder network has plural input nodes (100 and 102) and an analog signal output (104). Each of the input nodes corresponds to a different bit of a digital word that is to be converted to an analog signal. The current-controlled latch memory includes plural subcircuits (14 and 16). Each of the latch subcircuits uses an amount of current to store the logic state of the bit of the digital word and to derive directly the node of the R-2R resistive ladder network. This configuration promotes the efficient use of space, power, and circuit elements.

Abstract: A digital integrated circuit incorporates a plurality of multi-port flip-flop circuits which are interconnected by a plurality of gate circuits. A separate source of clock pulses is provided for each of the ports of the multi-port flip-flop circuits, and each clock pulse source is selectively effective to cause the multi-port flip-flop circuits to perform independent functions. During operation under one source of clock pulses, the flip-flops perform their ordinary function as D type flip-flops. During operation under another source of clock pulses, the flip-flops function as one or more shift registers in order to set the flip-flops to a predefined initial state in accordance with serial input data, and/or to provide serial output data in response to the state of the flip-flops following a preceding operation.