Abstract: In at least one embodiment, under a non-load condition of a first supply line for a first clock signal and a second supply line for a second clock signal, a fall time of a clock pulse of the first clock signal, which is supplied to the first supply line, is longer than that of the second clock signal, which is supplied to the second supply line.

Abstract: An exemplary shift register includes a plurality of transistors. The transistors are subjected to the control of a start pulse signal, a first clock signal and a second clock signal to generate a gate driving signal. The first clock signal and the second clock signal are phase-inverted with respect to each other. A logic low level of the first clock signal and another logic low level of the second clock signal are different from each other. Moreover, the transistors are negative threshold voltage transistors. A potential at the gate of the each of the transistors is lower than another potential at the source/drain of the transistor at the situation of the transistor being switched-off state.

Abstract: A dual-gate transistor formed of two transistors connected in series between a first power terminal and a first node is used as a charging circuit for charging a gate node (first node) of a transistor intended to pull up an output terminal of a unit shift register. The dual-gate transistor is configured such that the connection node (second node) between the two transistors constituting the dual-gate transistor is pulled down to the L level by the capacitive coupling between the gate and second node in accordance with the change of the gate from the H level to the L level.

Abstract: Provided are a bi-directional scanning type gate line driving circuit that does not require a dummy unit shift register and a method of driving the same. In a gate line driving circuit including a multi-stage shift register capable of bi-directional shifting, a start pulse is input to a unit shift register at a first stage and a unit shift register at the last stage of the multi-stage shift register. In forward shifting, a clock signal supplied to the unit shift register at the last stage is kept at a deactivation level during a period from a time at which an activation period of an output signal of the unit shift register at the last stage ends to a time at which the start pulse is activated during a subsequent frame period.

Abstract: A shift register includes plural shift register stages for providing plural gate signals to plural gate lines. Each shift register stage includes a pull-up unit, an input unit, an energy-store unit, a discharging unit and a pull-down unit. The pull-up unit pulls up a first gate signal according to a driving control voltage and a first clock. The input unit is utilized for inputting a second gate signal generated by a preceding shift register stage to become a driving control voltage which is stored in the energy-store unit. The discharging unit is utilized for performing an alternate pull-down operation on the driving control voltage according to a second clock and a third clock. The pull-down unit is utilized for performing an alternate pull-down operation on the first gate signal according to the second and third clocks.

Abstract: A shift register is disclosed, which can prevent malfunctioning of device by decreasing the load on a discharging voltage source line, and can decrease a size of stage. The shift register comprises a plurality of stages to sequentially output scan pulses through respective output terminals, wherein each of the stages comprises a pull-up switching unit controlled based on a signal state of node, and connected between the output terminal and any one among a plurality of clock transmission lines to transmit the clock pulses provided with sequential phase differences; and a node controller to control the signal state of node, and to discharge the node by using the clock pulse from any one among the plurality of clock transmission line.

Abstract: A shift register includes a first flip-flop group composed of a plurality of cascaded first flip-flops, each first flip-flop having a first master latch and a first slave latch and having first and second transmission paths for transmitting a master clock and a slave clock, a second flip-flop group composed of a plurality of cascaded second flip-flops, each second flip-flop having a second master latch and a second slave latch which are each composed of a transistor with a relatively small transistor size and having a third transmission path connected to the first transmission path and a fourth transmission path connected to the second transmission path, and a transfer portion configured to transfer pieces of data held in the second flip-flops to one of the first master latches and the first slave latches of the first flip-flops.

Abstract: There is provided a display device capable of preventing a malfunction and a display defect due to an off-leak from occurring even when a circuit in a shift register is configured utilizing thin film transistors of relatively large off-leaks. In at least one embodiment, each of bistable circuits that constitute the shift register includes: a thin film transistor for increasing a potential of an output terminal based on a first clock; a thin film transistor for decreasing the potential of the output terminal; a thin film transistor for increasing a potential of a range netA connected to a gate terminal of the thin film transistor based on a start signal; thin film transistors for decreasing the potential of the range netA; a capacitor for increasing the potential of a range netB connected to a gate terminal of the thin film transistor; and a thin film transistor for decreasing the potential of the range netB.

Abstract: An exemplary shift register (20) includes shift register units (S1˜Sn). The shift register units receive a clock signal and an inverse clock signal and output a plurality of shift register signals in sequence. An output of previous adjacent one of the shift register units is an input of the shift register unit.

Abstract: An exemplary shift register (20) includes a plurality of shift register units (200). The shift register units receive a clock signal and an inverse clock signal and output a plurality of shift register signals in sequence. The outputs waveforms of pre-stage shift register unit and the rear-stage shift register unit have no overlapping signals.

Abstract: A shift register includes a plurality of shift register units each including an input circuit, a pull-up circuit and a pull-down circuit. The shift register unit receives an input voltage at an input end and provides an output voltage at an output end. The input circuit controls the signal transmission path between a first clock signal and a first node according to the input voltage. The pull-up circuit controls the signal transmission path between a second clock signal and the output end according to the level of the first node. The pull-down circuit includes a pull-down unit and a control unit. The pull-down unit maintains the level of the first node or the output end according to the level of the second node. The control unit maintains the level of the second node according to the first clock signal, the second clock signal and the level of the first node.

Abstract: A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer.

Abstract: A shift register includes first and second shift register units. Two adjacent first shift register units respectively receive a first and second clock signal. Two adjacent second shift register units respectively receive a third and a fourth clock signal. Each first and second shift register unit includes a cascade data input terminal, a cascade data output terminal, an output terminal used to output a shift signal, a feedback terminal, and a reset terminal. The shift signals of the Mth second and Nth first shift register unit are respectively fed back to the feedback terminal of the (N+1)th first and Mth second shift register unit. The reset terminal and the cascade data output terminal of the Nth first and Mth second shift register unit are respectively connected to the output terminal and the cascade data input terminal of (N+1)th first and (M+1)th second shift register unit.

Abstract: An electronic system including a shift register is disclosed. The shift register includes a first transistor, a first trigger circuit, a second transistor, and a second trigger circuit. The first transistor receives a first input signal. The first trigger circuit is serially connected to the first transistor between a first level and a second level and is connected with the first transistor in a first node. The second transistor receives a second input signal inverted to the first input signal. The second trigger circuit receives the level of the first node, is serially connected to the second transistor between a third level and the second level, and is connected with the second transistor in a second node.

Abstract: A shift register includes a plurality of register units cascade-connected with each other. Each register unit includes a pull-up circuit, a pull-up driving circuit, a pull-down circuit, and a pull-down driving circuit. The pull-up circuit coupled to a first clock signal is used for providing an output signal. The pull-up driving circuit turns on in response to a driving pulse from a previous register unit and a second clock signal, and turns off in response to a third clock signal. The pull-down driving circuit which is coupled to an input node of the pull-down circuit, turns on in response to a first clock signal, and turns off in response to a the first clock signal or output of the pull-up driving circuit.

Abstract: A shift register unit includes a plurality of register units electrically coupled in cascade. Each register unit outputs an output pulse according to a first clock signal, a second clock signal and an output pulse of a previous register unit. Each register unit includes a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, and a driving unit. The first switch unit is used for conducting the input pulse to a first node when the first switch is turned on. The second switch unit is used for conducting the output pulse of the register unit according to the first clock signal to an output end when the second switch unit is turned on in response to the input pulse. The third switch unit electrically coupled to a supply end is used for conducting a supply voltage to the output end when the second switch unit is turned off.

Abstract: A shift register includes a plurality of shift register stages for providing gate signals. Each shift register stage has a pull-up unit, a carry unit, a carry control unit, an input unit and a pull-down unit. The pull-up unit is employed to pull up a gate signal according to a driving control voltage and a first clock. The carry unit generates a preliminary start pulse signal based on the driving control voltage and the first clock. The carry control unit outputs the preliminary start pulse signal to become a forward or backward start pulse signal according to first and second bias voltages. The input unit is utilized for inputting a start pulse signal generated by a preceding or succeeding shift register stage to become the driving control voltage. The pull-down unit pulls down the gate signal, the preliminary start pulse signal and the driving control voltage according to multiple clocks.

Abstract: The power consumption of a shift register or a display device including the shift register is reduced. A clock signal is supplied to a shift register by a plurality of wirings, not by one wiring. Any one of the plurality of wirings supplies a clock signal in only part of the operation period of the shift register, not during the whole operation period of the shift register. Therefore, the capacity load caused with the supply of clock signals can be reduced, leading to reduction in power consumption of the shift register.

Abstract: A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer.

Abstract: A shift register applied on a double-frame-rate LCD is provided. The LCD includes an upper display area with c gate lines, a lower display area with d gate lines, and a gate driving circuit. The gate driving circuit includes a first shift register coupled to the corresponding x gate lines of the upper display area, a second shift register coupled to the corresponding y lines of the lower display area, and a third shift register coupled to the corresponding (c-x) gate lines of the upper display area and the corresponding (d-y) gate lines of the lower display area.

Abstract: Systems for displaying images are provided. An embodiment of such a system has a dynamic shift register. The dynamic shift register includes a sampling unit, a holding unit, and a first logic circuit. The sampling unit, which is coupled to an incoming signal and a first input terminal of the dynamic shift register, samples the incoming signal according to a first input signal received by the first input terminal to generate a sampled value. The holding unit, which is coupled to the sampling unit, is utilized to hold the sampled value. The first logic circuit, which is coupled to the holding unit and an output terminal of the dynamic shift register, generates an output signal according to the sampled value and a second input signal inputted into the first logic circuit.

Abstract: A shift register includes a plurality of stages cascade-connected with each other. Each stage includes a pull-up circuit, a pull-up driving circuit, and a pull-down circuit. The pull-up circuit coupled to a first clock signal is used for providing an output signal. The pull-up driving circuit includes a control circuit and a first transistor. The control circuit has a gate coupled to a previous stage, and a drain coupled to a second clock signal. The first transistor includes a gate coupled to the source of the control circuit, a drain coupled to a driving end of the previous stage, and a source coupled to a first input end. The pull-down circuit pulls down voltage on the first input end.

Abstract: A gate driving circuit includes several driving circuit units and several switch units. Each driving circuit unit outputs several driving signals to several scan lines sequentially. One of the switch units is respectively disposed between two adjacent driving circuit units and conducts or blocks a first and a second clock signal transmitted to driving circuit units.

Abstract: A shift register includes a plurality of shift register stages for providing gate signals. Each shift register stage has a pull-up unit, a carry unit, a carry control unit, an input unit and a pull-down unit. The pull-up unit is employed to pull up a gate signal according to a driving control voltage and a first clock. The carry unit generates a preliminary start pulse signal based on the driving control voltage and the first clock. The carry control unit outputs the preliminary start pulse signal to become a forward or backward start pulse signal according to first and second bias voltages. The input unit is utilized for inputting a start pulse signal generated by a preceding or succeeding shift register stage to become the driving control voltage. The pull-down unit pulls down the gate signal, the preliminary start pulse signal and the driving control voltage according to multiple clocks.

Abstract: A shift register of an LCD device operates based on two clock signals and maintains the gate voltage of an output transistor switch using two pull-down transistor switches. The gate voltages of the pull-down transistor switches are switched periodically between the high and low level of the clock signals. During the output period, the transistor switches have negative gate-source voltages so as to reduce leakage.

Abstract: Various embodiments of the present invention provide systems and methods for event alignment control. For example, an event alignment control circuit is disclosed that includes a delay table, a flag write controller circuit, and a signal reconstruction circuit. The delay table includes at least a first register and a last register, and is operable to transfer data from the first register to the last register. The flag write controller circuit is operable to receive an indication of assertion of an event flag and to write information relevant to the event flag to the first register of the delay table. The signal reconstruction circuit is electrically coupled to the last register, and reconstructs the event flag based at least in part on the information relevant to the event flag obtained from the last register.

Abstract: A shift register including a plurality of multi-stage shift register circuits is provided. The mth stage shift register circuit includes a node, a shift register unit and a control circuit. A first control signal, enabled in an mth period, is defined on the node. The shift register unit is controlled by an (m?1)th stage output signal provided by an (m?1)th stage shift register circuit and a clock signal for providing the enabled mth stage output signal in the mth period, and controlled by an (m+1)th stage second control signal provided by an (m+1)th stage shift register circuit for providing a disenabled mth stage output signal in the (m+1)th period. The control circuit, controlled by the clock signal, provides and outputs an mth stage second control signal to the (m?1)th stage shift register circuit according to the mth stage first control signal, wherein m is a natural number greater than 1.

Abstract: The present invention provides a display device which includes a drive circuit having a CMOS shift register circuit constituted of a simple CMOS circuit. A drive circuit includes a shift register circuit, and the shift register circuit includes n(n?2) pieces of basic circuits which are connected vertically in multiple stages.

Abstract: A semiconductor integrated circuit includes logic circuits connected in a plurality of stages, a voltage-level inverting unit that is inserted in a signal transmission path of the logic circuits and inverts a voltage level input to the logic circuits, and an inversion-timing control unit that controls inversion timing for the voltage level inverted by the voltage-level inverting unit.

Abstract: A shift register is used for outputting an output pulse at output end in response to a delay of an input pulse received at an input end. The shift register includes a controller, a pre-charging switch, a level shifting switch, and an output generator. The controller is used for generating a level switching signal. The pre-charging switch is used for conducting a first supply voltage to a level shifting node in response to the input pulse. The level shifting switch turns on in response to the level switching signal. The output generator is used for generating the output pulse at the output end, when the level shifting switch turns on.

Abstract: Disclosed is a shift register including a plurality of flip-flops configured in series to shift input data in response to an applied clock, and a drive operation controller.

Abstract: At least one embodiment the present invention a plurality of unit circuits connected in multiple stages, to normal operation when the unit circuits are simultaneously turned on to output high-level output signals. When a shift register malfunctions, so that output signals provided by previous- and subsequent-stage unit circuits are simultaneously set to high level, malfunction restoration circuits and included in a unit circuit detect the malfunction in at least one embodiment. The malfunction restoration circuit provides a high voltage to a node, thereby forcibly pulling down an output signal. Also, the malfunction restoration circuit forcibly discharges another node, so that a charge accumulated in a capacitance is released. As a result, the shift register in malfunction can be instantaneously restored to normal operation. At least one embodiment of the present invention is suitable for driver circuits or suchlike of display devices and imaging devices.

Abstract: The present invention provides a shift register having simple circuit scheme capable of increasing lifetime of whole circuit and a related Liquid Crystal Display (LCD). The shift register includes a plurality of shift register units connected in cascade, wherein at least one of the plurality of shift register units includes: an output terminal, a first switch element, a second switch element, a third switch element, a fourth switch element, a fifth switch element, and a sixth switch element. In addition, The LCD includes a plurality of gate output signal lines and the shift register mentioned above. The plurality of shift register units connected in cascade are coupled to the plurality of gate output signal lines, respectively.

Abstract: A shift register which is capable of simultaneously driving gate lines is disclosed. The shift register includes a plurality of stages for simultaneously supplying all-drive signals to gate lines for an all-drive period and sequentially supplying scan pulses to the gate lines for a scan period.

Abstract: A pull-up driving part maintains a signal of a first node at a high level by receiving a turn-on voltage in response to one of a previous stage or a vertical start signal. A pull-up part outputs a clock signal through an output terminal in response to the signal of the first node. A first holding part maintains a signal of a second node at a high level or a low level when the signal of the first node is respectively low or high. A second holding part maintains the signal of the first node and a signal of the output terminal at a ground voltage in response to the signal of the second node or a delayed and inverted clock signal.

Abstract: A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer.

Abstract: In one embodiment of the present invention, a shift register includes a plurality of stages which are activated in sequence. Each stage includes a logic circuit controlling first and second output circuits. The first output circuit includes a first switch in the form of a transistor, which connects an output of the stage to receive a pulse width control signal when the stage is active. A second switch in the form of a transistor connects the stage output to receive an inactive signal level when the stage is inactive. The second output circuit comprises a third switch in the form of a transistor, which connects a further output to receive an active signal level when the stage is active. A fourth switch in the form of a transistor connects the further output to receive an inactive signal level when the stage is inactive. The further output of each stage is connected to the logic circuit of at least one adjacent stage, such as a reset input of a preceding stage and/or a set input of a succeeding stage.

Abstract: A low power consumption shift register which inputs a CK signal with a low voltage with almost no effect of variation in characteristics of transistors. In the invention, an input portion of an inverter is set at a threshold voltage thereof and a CK signal is inputted to the input portion of the inverter through a capacitor means. In this manner, the CK signal is amplified, which is sent to the shift register. That is, by obtaining the threshold potential of the inverter, the shift register which operates with almost no effect of variation in characteristics of transistors can be provided. A level shifter of the CK signal is generated from an output pulse of the shift register, therefore, the low power consumption shift register having the level shifter which flows a shoot-through current for a short period can be provided.

Abstract: A shift register includes a plurality of stages cascade-connected with each other. Each stage includes a pull-up circuit, a pull-up driving circuit, and a pull-down circuit. The pull-up circuit coupled to a first clock signal is used for providing an output signal. The pull-up driving circuit includes a control circuit and a first transistor. The control circuit has a gate coupled to a previous stage, and a drain coupled to a second clock signal. The first transistor includes a gate coupled to the source of the control circuit, a drain coupled to a driving end of the previous stage, and a source coupled to a first input end. The pull-down circuit pulls down voltage on the first input end.

Abstract: A flip-flop is provided. The flip-flop is used in a shift register in a source driver. The flip-flop is used to receive a first clock signal, an input signal and output an output signal. The output signal is fed back to the flip-flop. The flip-flop includes a flop core for receiving the input signal and output the output signal. When the input signal and the output signal are all disabled, the flop core is disabled to function. When the input signal or the output signal is enabled, the flop core is enabled to function to output the output signal.

Abstract: Systems for driving displays are provided. In this regard, an representative system for driving a display comprises a signal driving circuit having a first shift register and a second shift register coupled in series to the first shift register. The signal driving circuit is operative to drive a display according to inputs provided by only two clock signals.

Abstract: A liquid crystal display panel includes liquid crystal cells forming a matrix in a display area of the liquid crystal display panel; odd and even gate driving circuits provided at an outer area of the display area, the display area being positioned between the odd and even gate driving circuits, the odd driving circuit including a plurality of odd stages, the even driving circuit including a plurality of even stages; a plurality of gate lines, including even gate lines and odd gate lines in the liquid crystal cell matrix, the odd gate lines being driven by the odd driving circuit, and the even gate lines being driven by the even driving circuit, wherein a length of each of the odd stages and the even stages corresponds to size larger than a length of the liquid crystal cell.

Abstract: In one embodiment of the present invention, a source driver includes a shift register including latch stages each including a level shifter that level-shifts clock signals so that the signals are fed into a set-reset flip-flop as inverted set input signals. Outputs from the set-reset flip-flop are delayed by a hazard preventing circuit and then fed into a level shifter in the next latch stage as enable signals. A delay trimming circuit causes a NAND circuit to perform a NAND operation with respect to outputs obtained by a delay of the outputs by a delay circuit and outputs from the level shifter in the next latch stage, so that a sampling pulse is derived. This allows for provision of a pulse output circuit capable of further trimming delay in output pulses and of securing a sufficient interval between the output pulses.

Abstract: A shift register and a shift register unit for diminishing clock coupling effect are introduced herein. Each stage shift register unit includes at least one pull-up driving module, a pull-up module, at least one pull-down module and a pull-down driving module. Before a waveform of either a first clock signal or a second clock signal employed by the pull-up module transits into a rising edge, the pull-down driving module employs a first periodic signal to turn on the pull-down module in advance for a specific period, and/or before the waveform of the first or second clock signal employed by the pull-up module transits into a falling edge, the pull-down driving module employs a second periodic signal to turn off the pull-down module in advance for a specific period. Accordingly, the pull-down module can gain a sufficient capability against the clock coupling effect so as to optimize the waveform outputted from the shift register unit.

Abstract: A shift register includes a plurality of register units cascade-connected with each other. Each register unit includes a pull-up circuit, a pull-up driving circuit, a pull-down circuit, and a pull-down driving circuit. The pull-up circuit coupled to a first clock signal is used for providing an output signal. The pull-up driving circuit turns on in response to a driving pulse from a previous register unit and a second clock signal, and turns off in response to a third clock signal. The pull-down driving circuit which is coupled to an input node of the pull-down circuit, turns on in response to a first clock signal, and turns off in response to a the first clock signal or output of the pull-up driving circuit.

Abstract: A shift register having individual driving nodes is disclosed. The shift register includes a first clock pull-down module, a second clock pull-down module, a key pull-down module, a self feedback module, and a driving output unit. The first clock pull-down module is used to pull-down the potential of a gate line to a low voltage when the first clock signal is in a high voltage level. The second clock signal pull-down module pulls down the potential of the gate line to the low voltage when the second clock signal is in a high voltage level. The key pull-down module rapidly pulls down the potential of the gate line to the low voltage level after the gate line outputs an output signal. The self feedback module is used to output a driving signal to the key pull-down module. The driving signal output unit outputs a next stage driving signal which is irrelative to the operation of the previous stage shift register.

Abstract: Disclosed is a shift register which includes first transistor connected between a first clock signal terminal and an output terminal, a second transistor with a gate connected to an input terminal and a source connected to a gate of the first transistor, a third transistor with a gate connected to a second clock signal terminal, an inverter with an input connected to the input terminal, a fourth transistor cascode connected to the third transistor with a gate connected to an output of the inverter, a fifth transistor connected between the gate of the first transistor and a power supply terminal, a sixth transistor connected between the fourth transistor and the power supply terminal with a gate connected to the input terminal, and a seventh transistor connected between the output terminal and the power supply terminal, the fifth and seventh transistors having gates connected in common to a connection node of the fourth and the sixth transistors.

Abstract: A shift register includes a shift circuit configured to shift an input signal in synchronization with a shift clock to output an output signal of the shift register, and a clock control circuit configured to enable the shift clock in response to the input signal and disable the shift clock in response to the output signal of the shift register.

Abstract: A shift register including shift register units controlled by first and second clock signals for generating an output signal. For each unit, in an active period, the first driving device drives the first switch device to activate the output signal, and the second driving device provides a voltage signal according to the first clock signal to drive the first switch device to de-activate the output signal. When the first switch device de-activates the output signal, the second switch device provides the voltage signal to serve as the output signal according to the second clock signal. In the active period, the voltage signal has a low level, and the first and second clock signals are set as alternating-current signals and are opposite to each other. In a blanking period, the voltage signal has a high level, and each of the first and second clock signals is set as a direct-current signal.

Abstract: A shift register circuit can be manufactured in a simple manner. A shift register circuit is composed of a plurality of cascade-connected latch circuits that latch an input signal in synchronization with a clock signal and output a resultant signal. Two input signals IN and /IN having phases inverted relative to each other are input to each latch circuit, which latches the input signals IN and /IN in synchronization with a clock signal CLK input to a control input, and outputs latched inverted and non-inverted signals /OUT and OUT.