Abstract: The present invention provides a shift register having simple circuit scheme capable of increasing lifetime of whole circuit and a related Liquid Crystal Display (LCD). The shift register includes a plurality of shift register units connected in cascade, wherein at least one of the plurality of shift register units includes: an output terminal, a first switch element, a second switch element, a third switch element, a fourth switch element, a fifth switch element, and a sixth switch element. In addition, The LCD includes a plurality of gate output signal lines and the shift register mentioned above. The plurality of shift register units connected in cascade are coupled to the plurality of gate output signal lines, respectively.

Abstract: Disclosed is a shift circuit capable of reducing current consumption and circuit area and increasing the operation speed. The shift circuit includes a transfer unit for transferring input data to a first node in response to a clock signal, and a latch unit for latching the data on the first node in response to a clock signal.

Abstract: In a semiconductor device including an N-line M-stage shift register circuit operated at high speed of, for example, several hundreds MHz. Input circuits input a common test pattern to each of pairs of shift registers in, for example, two lines out of the N lines. A plurality of outputs of the pairs of shift registers in the two lines are compared in comparators, and the comparison results are output. The N-line M-stage shift register circuit and the comparators are operated in synchronization with a clock signal at several hundreds MHz. Hence, even when the circuit scale (area) of the N-line M-stage shift register circuit is increased to involve apparent wiring delay, a defect in the shift register circuit can be detected at an actual speed.

Abstract: To reduce a circuit area of a data line driving circuit. The data line driving circuit includes a plurality of circuit blocks. A circuit block has shift register unit circuits, logical operation unit circuits and a control unit circuit. The control unit circuit specifies the operation period of the corresponding circuit block on the basis of the input and output signals of the shift register unit circuits and supplies a clock signal and an inverted clock signal to the shift register unit circuit.

Abstract: A shift register having individual driving nodes is disclosed. The shift register includes a first clock pull-down module, a second clock pull-down module, a key pull-down module, a self feedback module, and a driving output unit. The first clock pull-down module is used to pull-down the potential of a gate line to a low voltage when the first clock signal is in a high voltage level. The second clock signal pull-down module pulls down the potential of the gate line to the low voltage when the second clock signal is in a high voltage level. The key pull-down module rapidly pulls down the potential of the gate line to the low voltage level after the gate line outputs an output signal. The self feedback module is used to output a driving signal to the key pull-down module. The driving signal output unit outputs a next stage driving signal which is irrelative to the operation of the previous stage shift register.

Abstract: A shift register is provided for use in a data driver. The shift register includes a shift registering unit. The shift registering unit selectively receives a clock signal. The shift registering unit includes a flip-flop; and a first selection circuit. The first selection circuit selectively sends the clock signal to the flip-flop according to a first selection signal, wherein before the flip-flop receives a data signal that is enabled, the first selection circuit sends the clock signal to the flip-flop according to the first selection signal so that the flip-flop correctly outputs the enabled data signal according to the clock signal.

Abstract: A method, an apparatus, and a computer program are provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances and resistances are typically minimized, while adding large decoupling capacitances between the supply voltage and ground. However, situations may arise where reduction of series inductances and resistances cannot be accomplished. Therefore, to assist in controlling the transient current swings, reduction of clocking frequencies are performed in a controlled manner.

Abstract: An exemplary shift register (20) includes a plurality of shift register units (200) connected one by one. Each of the shift register units includes a first switch unit (201), a second switch unit (202), a third switch unit (203), a fourth switch unit (204), and a fifth switch unit (205). A signal input terminal of each shift register unit is coupled to an output terminal of a rear-stage shift register unit. A first clock input terminal receives a first clock signal to turn on/off the first and second switch units. The third switch unit receives a second clock signal. The fourth switch unit pulls up the output voltage of the output terminal according to a controlling signal from the first switch unit. The fifth switch unit pulls down the output voltage of the output terminal according to controlling signals from the second and third switch units.

Abstract: Disclosed is a semiconductor circuit in which a floating node is set to any voltage by utilizing a control signal which is applied to a refresh terminal and has a period shorter than that of a clock signal. The semiconductor circuit includes first and second transistors connected between a first clock terminal and a first power supply terminal, third and fourth transistors connected between the refresh terminal and the first power supply terminal, and fifth and sixth transistors connected between a second power supply terminal and the first power supply. Gates of the fourth and fifth transistors are connected in common to an input terminal, a gate of the third transistor is connected to a second clock terminal, a gate of the first transistor is connected to a connection node between the fifth and sixth transistors, the gate of the second transistor is connected to the gate of the sixth transistor, and a connection node between the first and second transistors is connected to an output terminal.

Abstract: A high-speed shift register circuit is provided. The shift register circuit includes a first transistor supplying a clock signal to a first output terminal, a second transistor discharging the first output terminal, a third transistor supplying the above clock signal to a second output terminal, and a fourth transistor discharging the second output terminal. The gates of the first and third transistors are both connected to a first node, and the gates of the second and fourth transistors are both connected to a second node. The first node is charged by a fifth transistor which is connected between the first node and a first input terminal and which has a gate connected to a second input end.

Abstract: A programmable clock deskewer generates an output clock with minimal clock skew. This is accomplished by means of a single series path coupling the input clock to the output clock. The programmable clock deskewer includes: an output clock generator, responsive to the input clock and control information, to generate the deskewed output clock; and a controller, responsive to the input clock, to generate the control information for controlling the frequency of the deskewed output clock. The programmable clock deskewer may be used to implement a clock tree with various clock outputs for a system on chip integrated circuit.

Abstract: A shift register has an output stage formed by a first transistor connected between an output terminal and a first clock terminal and a second transistor connected between the output terminal and a ground. Third and fourth transistors are connected in series between the gate of the first transistor (first node) and the ground. A second node between the third and fourth transistors is connected to a power source via a fifth transistor. The fifth transistor has its gate connected to the first node. Accordingly, when the third and fourth transistors are turned off to raise the first node in level, the fifth transistor is turned on, whereby a predetermined voltage is applied to the second node.

Abstract: A low-speed DLL facilitates a deskewed interface between a high-speed RX data demultiplexer circuit directly to an Application Specific Integrated Circuit (ASIC) with which it is integrated by locking a 156 MHz ASIC clock to a 156 MHz reference derived from a high speed 2.5 GHz clock. The DLL employs a digital interpolator to generate 32 phases of the 156 MHz clock. The digital interpolator supplies the phases using a double clocked shift register with recirculating feedback. The shift register is double clocked using the 2.5 GHz clock. The register outputs are tapped and fed to a 32:1 multiplexer having a phase select input that is controlled by the phase difference signal generated by the DLL. The phase difference control signal is converted to a digital representation of its magnitude by which the requisite number of phase shift increments may be selected.

Abstract: A shift register circuit includes a plurality of latch circuits connected in series to sequentially transfer a pulse signal ST from one to another, a clock signal line transmitting a clock signal CLK, and a plurality of switching circuits performing electrical connection and disconnection between the clock signal line and the plurality of latch circuits. Upon turning on the shift register, at least one of the switching circuits electrically disconnects at least one of the latch circuits from the clock signal line. During an initialization period immediately after power has been turned on, the frequency of the clock signal CLK is lower than in a normal operation period and gradually increases toward the frequency used in the normal operation period.

Abstract: The invention relates to a shift register cell for safely providing a configuration bit having a master latch which can be connected to a serial data input on the shift register cell for the purpose of buffer storing a data bit; a first slave latch which can be connected to the master latch for the purpose of buffer storing the data bit; at least one second slave latch which can be connected to the master latch for the purpose of buffer storing the data bit, and having an evaluation logic unit which outputs the configuration bit on the basis of the data bits which are buffer stored in the master latch and in the slave latches. In addition, the invention provides a shift register for safely providing configuration bits which has a plurality of inventive shift register cells which are connected in series to form a shift register chain.

Abstract: A driver circuit of a display device, which includes TFTs of a single conductivity type and outputs an output signal with normal amplitude. A pulse is inputted to TFTs 101 and 104 to turn ON the TFTs and a potential of a node ? is raised. When the potential of the node ? reaches (VDD?VthN), the node ? becomes in a floating state. Accordingly, a TFT 105 is turned ON and a potential of an output node is raised as a clock signal becomes High level. On the other hand, a potential of a gate electrode of the TFT 105 is further raised due to an operation of a capacitance means 107 as the potential of the output node is raised, so that the potential of the gate electrode of the TFT 105 becomes higher than (VDD+VthN). Thus, the potential of the output node is raised to VDD without causing a voltage drop due to a threshold voltage of the TFT 105.

Abstract: A low power consumption shift register which inputs a CK signal with a low voltage with almost no effect of variation in characteristics of transistors. In the invention, an input portion of an inverter is set at a threshold voltage thereof and a CK signal is inputted to the input portion of the inverter through a capacitor means. In this manner, the CK signal is amplified, which is sent to the shift register. That is, by obtaining the threshold potential of the inverter, the shift register which operates with almost no effect of variation in characteristics of transistors can be provided. A level shifter of the CK signal is generated from an output pulse of the shift register, therefore, the low power consumption shift register having the level shifter which flows a shoot-through current for a short period can be provided.

Abstract: An apparatus is provided, which includes a memory interface circuit, a clock signal generating circuit, and a plurality of memory circuits. The memory circuits are operatively coupled and arranged in an order on a plurality of memory modules, such that the memory module positioned at the beginning of the order is coupled to an output of the clock signal generating circuit and the memory interface circuit. The memory module that is positioned at the end of the order is unique in that it includes a clock signal terminating circuit connected to the last memory integrated circuit. With this configuration, a clock loop is formed by directly routing the clock signal from the output of the clock signal generating circuit through each of the memory modules in the order (without connecting to any of the intervening memory integrated circuits) to the memory integrated circuit positioned at the end of the order.

Abstract: A method and mechanism for generating a clock signal with a relatively linear increase or decrease in clock frequency. A first clock signal is generated with a first frequency which is then used to generate a second clock signal with a second frequency. The second frequency is generated by dropping selected pulses of the first clock signal. Particular patterns of bits are stored in a storage element. Bits are then selected and conveyed from the storage element at a frequency determined by the first clock signal. The conveyed bits are used to construct the second clock signal. By selecting the particular pattern of bits selected and conveyed, the frequency of the second clock signal may be determined. Further, by changing the patterns of bits within the registers at selected times, the frequency of the second clock signal may be made to change in a relatively linear manner.

Abstract: A shift register includes bidirectional register units, a direction switching section, a register unit selecting section, and a shift clock supply section. The bidirectional register units are cascaded through first input/output terminals for data shifting and perform data shifting operation. The bidirectional register units have second input/output terminals which separately and directly input/output data. The direction switching section switches the shifting directions of the bidirectional register units. The register unit selecting section selects one of the bidirectional register units and inputs/outputs data through the second input/output terminal. The shift clock supply section supplies shift clocks to the bidirectional register units ranging from the bidirectional register unit selected by the register unit selecting section to the last-stage bidirectional register unit.

Abstract: A shift register device includes transistor pass gates and latches connected in series and disposed along a data bit line, each latch connected to a corresponding transistor pass gate. Each transistor pass gate is controlled by a separate control signal input line that a provides a signal to the transistor pass gate connected to it. The signals are provided in a staggered time pattern beginning with a latch disposed last in succession, shifting data from one position to the next succeeding position. Each latch is capable of storing one bit of data. The shift register utilizes less silicon space while reducing the amount of power consumed during operation.

Abstract: A shift-register circuit. The PMOS transistor includes a first gate coupled to an inverse output signal output from a previous-stage shift-register unit, a first drain, and a first source coupled to an output signal output from the previous-stage shift-register unit. The first NMOS transistor includes a second gate coupled to the first drain, a second drain coupled to the clock signal, and a second source. The capacitor is coupled between the second gate and the second source. The second NMOS transistor includes a third gate coupled to the first drain, a third drain coupled to the inverse clock signal, and a third source. The third NMOS transistor includes a fourth gate coupled to the first gate, a fourth drain coupled to the second gate, and a fourth source. The fourth NMOS transistor includes a fifth gate coupled to the first source, a fifth drain coupled to the second source, and a fifth source coupled to the ground voltage level.

Abstract: A shift register circuit includes a plurality of latch circuits connected in series to sequentially transfer a pulse signal ST from one to another, a clock signal line transmitting a clock signal CLK, and a plurality of switching circuits performing electrical connection and disconnection between the clock signal line and the plurality of latch circuits. Upon turning on the shift register, at least one of the switching circuits electrically disconnects at least one of the latch circuits from the clock signal line. During an initialization period immediately after power has been turned on, the frequency of the clock signal CLK is lower than in a normal operation period and gradually increases toward the frequency used in the normal operation period.

Abstract: A low power consumption shift register which inputs a CK signal with a low voltage with almost no effect of variation in characteristics of transistors. In the invention, an input portion of an inverter is set at a threshold voltage thereof and a CK signal is inputted to the input portion of the inverter through a capacitor means. In this manner, the CK signal is amplified, which is sent to the shift register. That is, by obtaining the threshold potential of the inverter, the shift register which operates with almost no effect of variation in characteristics of transistors can be provided. A level shifter of the CK signal is generated from an output pulse of the shift register, therefore, the low power consumption shift register having the level shifter which flows a shoot-through current for a short period can be provided.

Abstract: In a shift register and LCD device having the shift register that may be employed in the liquid crystal display device having a large screen size and a large resolution, the shift register includes stages cascade-connected with each other and each of the stages have a carry buffer for generating a carry signal. The pull-down transistor of each of the stages of the shift register is divided into a first pull-down transistor and a second pull-down transistor. A power voltage Vona larger than the power voltage Von applied to a clock generator is applied to the shift register. A signal delay due to the RC delay of the gate lines may be minimized, the shift register is independent of the variation of the threshold voltage of the TFTs, and image display quality may not be deteriorated.

Abstract: A shift-register circuit. The input circuit receives the input pulse and outputs a high-voltage level input signal when the input pulse is at high voltage level.

Abstract: A shift-register unit. The first transistor includes a first source/drain coupled to a first terminal, a second source/drain, and a first gate coupled to a reset signal to stop the shift-register unit outputting a pulse signal. The second transistor includes a third source/drain coupled to the second source/drain, a fourth source/drain coupled to a second terminal, and a second gate coupled to a setting signal to initial the shift-register unit. The third transistor includes a fifth source/drain coupled to an output terminal, a third gate coupled to the second source/drain and a sixth source/drain coupled to a clock signal to start outputting the pulse signal. The fourth transistor includes a seventh source/drain coupled to the first terminal, an eighth source/drain coupled to the output terminal and a fourth gate coupled to a refresh signal to set a voltage level of the shift-register unit in a standby mode.

Abstract: A driver circuit of a display device, which includes TFTs of a single conductivity type and outputs an output signal with normal amplitude. A pulse is inputted to TFTs 101 and 104 to turn ON the TFTs and a potential of a node &agr; is raised. When the potential of the node &agr; reaches (VDD−VthN), the node &agr; becomes in a floating state. Accordingly, a TFT 105 is turned ON and a potential of an output node is raised as a clock signal becomes High level. On the other hand, a potential of a gate electrode of the TFT 105 is further raised due to an operation of a capacitance means 107 as the potential of the output node is raised, so that the potential of the gate electrode of the TFT 105 becomes higher than (VDD+VthN). Thus, the potential of the output node is raised to VDD without causing a voltage drop due to a threshold voltage of the TFT 105.

Abstract: A shift register with low power consumption has memory circuits 151-15N connected in series, gate circuits in memory circuits 152n−1 in the odd-numbered locations become conductive when clock signal CK is high, and gate circuits in memory circuits 152n in the even-numbered locations become conductive when clock signal CK is low, wherein data signals S input are latched for output when the gate circuits are shut off. The circuit configuration is simplified. The Shift register operates every one half of the cycle of clock signal CK, allowing the frequency of clock signal to be reduced by half, resulting in reduced power consumption.

Abstract: A shift register has m stages which store one of two states, where m is an integer more than 1, each stage including clock input terminals at which n-phase clock signals are input, where n is an integer more than 1, and an input terminal, and an output terminal. The input terminal of one stage receives the signal delivered from an input terminal of the shift register or from the output terminal of the previous stage. The signal output at the output terminal of one stage is passed to the input terminal of the subsequent stage or to an output terminal of the shift register. Each stage receives an initial state level from one of the clock input terminals. The initial state level is used to initialize the state of each stage.

Abstract: A command buffer for use in packetized DRAM includes a four stage shift register for shifting for sequentially storing four 10-bit command words. The shift register combines the four 10-bit command words into a single 40-bit command word and transfer the 40-bit command word to a storage register for processing by the DRAM. The shift register may then continue to receive and store subsequent 10-bit command words. The command buffer also includes circuitry for determining whether a command packet is intended for the memory device containing the command buffer or whether it is intended for another memory device. Specifically, a portion of the 40-bit command word from the storage register is compared to identifying data stored in an identifying latch. In the event of a match, a chip select signal is generated to cause the memory device to perform the function corresponding to other portions of the 40-bit command word.

Abstract: An on-chip parallel/load, serial-shift shift register stores information bits for one or more chip parameters. The bits are represented by fuses that are connected to respective input terminals of the shift register. When the chip is not in test mode (TM), the fuses are electrically connected to respective cells of the shift register, and the output of the shift register is electrically isolated from an output buffer. When the chip is put into test mode, the electrical connections between the fuses and the shift register bits are broken, leaving the fuse information isolated in the shift register. The test mode also connects the output of the shift register to the output buffer and the output of the first shift register bit is seen on the output pin. The rest of the shift register information bits are serially shifted out of the shift register by toggling the CEB pin.

Abstract: A multi-shifting shift register is adapted for outputting a selected address signal to a memory unit, and includes a control circuit for outputting a number (i) of shift signals and a timing pulse signal. One of the shift signals is at an enabled state and the other ones of the shift signals are at a disabled state during each cycle of the timing pulse signal. A multi-shifting circuit includes a number (N), which is larger than the number (i), of cascaded register units, each of which has a flip-flop that has an input end, and an output end for generating an address signal, and a selector that has the number (i) of select inputs for receiving the number (i) of the shift signals respectively from the control circuit, the number (i) of address signal inputs, and an output. The output end of the flip-flop is connected to a first one of the address signal inputs of the selector.

Abstract: A low power linear feedback shift register includes an ordered set of register steps including memory devices. Enabling devices enable a single current memory device at every shift operation. Each register step includes a lower power memory device consuming a minimum amount of power when disabled, and a feedback device, an output terminal thereof being connected to an input terminal of the memory device, the feedback device having first and second input terminals connected to an output terminal of the memory device and an output terminal of a second subsequent memory device, respectively, in the set. The output terminal of each memory device is connected to a selection device, selecting at every shift operation the output terminal of a first subsequent memory device following the current memory device being enabled at the current shift operation.

Abstract: A low power, low area shift register permits control over delay by dividing the shift register cells into a plurality of segments that are serially connected. A first selector provides data from a shift register input selectively to an input of one of the segments. A second selector provides data from an input or output of a selected cell of one segment of shift register cells to a shift register output.

Abstract: An active matrix drive type liquid crystal device is equipped with a data line driving circuit (101) composed of a bidirectional shift register which has an odd number of output stages and a scanning line driving circuit (104). composed of a bidirectional shift register which has an odd number of output stages so as to make it possible to horizontally and vertically invert the horizontal scanning direction and the vertical scanning direction easily by using a relatively simple constitution.

Abstract: An apparatus for synchronizing a clock signal to a data signal. The apparatus comprises a detector and a control circuit. The detector may be configured to produce a value representing a position of an edge of said data signal based upon a state of said clock signal. The control circuit may be configured to adjust the clock signal based upon the value.

Abstract: CMOS semiconductor latch and register (500) circuitry is disclosed, comprising a first tunneling structure latch circuit (502); data input circuitry (506), coupled and adapted to pass data to (504) said first tunneling structure latch circuit (502), a second tunneling structure latch circuit (514), data transmission circuitry (516), coupled between said first and second tunneling structure latch circuits, and adapted to transfer data from said first tunneling structure latch circuit to said second tunneling structure latch circuit, and data output circuitry (518), coupled to (512) said second tunneling structure latch circuit (514).

Abstract: A system for quantizing an analog signal comprises an input terminal for receiving an analog input signal, a clock terminal for receiving a clock signal, and an inverted clock terminal for receiving an inverted clock signal. A first negative-resistance device has a first terminal coupled to the clock terminal and a second terminal coupled to the input terminal. A second negative-resistance device has a first terminal coupled to the input terminal and a second terminal coupled to the inverted clock terminal. An output terminal coupled to the first negative-resistance device and the second negative-resistance device to provide a quantized output signal.

Abstract: A balanced dual-edge triggered bit shifting circuit includes a clock circuit to generate low skew, or edge-aligned, complementary clock signals, and a shift register that shifts a data bit in response to the complementary clock signals. The clock circuit is formed from two clock generators, each of which generates the edge-aligned complementary clock signals by alternatively coupling the input terminals of two buffer circuits to a voltage supply terminal and a ground terminal. Transfer gates coordinate the coupling of the input terminals of the buffer circuits so that the resulting output clock signals generated by each clock generator have clock transitions that are substantially simultaneous. The shift register is formed from at least one shift register stage that receives the edge-aligned complementary clock signals. The shift register stage includes two latching stages, each latching stage having an inverter with an output coupled to a latch circuit.

Abstract: A shift register unit has stages. In each stage, a clamping transistor and the control electrode of an output transistor are connected to the output electrode of an input transistor to which an output one stage behind is input. A pull-down resistor is connected to the output electrode of the output transistor. A capacitor is inserted between the control electrode and output electrode of the output transistor. A clock signal is input to the output transistor, and a signal obtained by inverting a clock signal two stages forward is input to the clamping transistor.

Abstract: A shift register matrix including a matrix of cells having a plurality of rows and a plurality of columns, each cell storing one bit of data. A plurality of pulse generators is included to generate pulses to the cells which cause new data to be shifted into the cells. One pulse generator is included for each column of the matrix. The pulse generator for each column is coupled to all the cells in the column. Each pulse generator supplies a pulse to each of the cells in its respective column to cause new data to be shifted into the cells of that column. The pulses are sent to the respective columns in sequential order, one column at a time, until all the data in the matrix has been shifted by one bit.

Abstract: A balanced switching circuit comprises a plurality of transfer gates, each transfer gate having an input terminal, an output terminal, and at least one control terminal adapted to receive a control signal. Each transfer gate, which may be comprised of pass transistors such as n- and p-channel metal oxide semiconductor (MOS) transistors, is operable to couple the input terminal to the output terminal in response to the control signal. The plurality of transfer gates are arranged in N rows and N columns with the input and output terminals of the N transfer gates in each row connected in series between a first signal terminal and a second signal terminal. Each transfer gate has its control terminal connected to one of N clock terminals adapted to receive respective clock signals. Each clock terminal is coupled to the control terminal of only one transfer gate in each row and only one transfer gate in each column.

Abstract: A shift register having several cascaded stages, each stage containing an output at a first node connected to a next stage, a first input connected to an output of a preceding stage, a second input connected to an output of the next stage and a first terminal connected to a first clock signal and a second terminal connected to a second clock signal, the stage containing a first semiconductor device switching the output of the stage between high and low values of the first clock signal, the first semiconductor device being controlled by the potential of a second node, itself connected to the output of the preceding stage across a second semiconductor device controlled by the output of the preceding stage; to a negative potential across a third semiconductor device controlled by the output of the next stage; and to the second terminal connected to the second clock signal across a first capacitance, wherein a second capacitance is mounted between the second node and the output of the next stage.

Abstract: A race-free shift register device having a plurality of series-connected flip-flop circuits and latch circuits. By a delay circuit, the timing of a clock signal input to each individual flip-flop circuit is delayed with respect to the clock signal input to the associated latch circuit, so that the operating timing of the latch circuit is not delayed with respect to the operating timing of the flip-flop circuit, even if a skew happens to occur in the clock signal. The latch circuit therefore surely holds bit data output by the flip-flop circuit, so the bit data to be input to a preceding flip-flop circuit is prevented from being prematurely provided to a succeeding flip-flop circuit, thereby ensuring prevention of a race condition.

Abstract: The subject of the present invention is a shift register for an LCD, the stages of which use the Boostrap [sic] effect and can contain just three M.I.S. transistors, as well as enhancements to this circuit with four or seven MIS transistors.The advantages are the low number of components used, the increase in the lifetime of the shift register and the possibility of working with control signals having an amplitude of 5 or 10 v below that of the output signals.

Abstract: A high speed digital static shift register includes a series-connected pair of resonant tunneling diodes (RTDs) 22, 24 to achieve a bistable operating state. A clocked switch 20 provides the means of setting the binary state of this bistable pair. In order for one bistable pair to drive a following pair, a method of providing isolation and gain using a buffer amplifier 26 between the two pairs of RTDs is also provided. In one embodiment, the buffer amplifier comprises enhancement FET 30 and depletion load FET 28.

Abstract: This invention relates to the structure of multiple registers used in image signal processing, and aims to simplify the register structure and to reduce the power consumption of the registers and the time required for testing an image signal processing LSI with the registers. A semiconductor integrated circuit according to the invention has a clock generation circuit and a clock buffer circuit for generating a plurality of clock signals, a register group including a plurality of registers connected in series and operable in synchronism with the clock signals, at least one combinational circuit connected to the register group, and means for selecting one of a normal operation mode and a scan test mode for the register group. The clock generation circuit receives a system clock CP.sub.IN, a scan test mode selection signal S.sub.MODEN, and clock CPS.sub.IN, and outputs a clock .phi. and a clock (.phi..sub.1 bar) controlled by the signal S.sub.

Abstract: An XY-address solid-state image pickup apparatus comprises a pixel array made up a plurality of pixels two-dimensionally arranged and horizontal and vertical scanning circuits for reading the signal from the pixel array. Each scanning circuit comprises a plurality of unit stages cascaded, each unit stage comprising a plurality of first shift register units cascaded and a single second shift register unit which is associated with the plurality of first shift register units and which is driven by a clock different from the clock that drives the plurality of first shift register units. Each unit stage further comprises a first switch and a second switch. The input to the first unit of the first shift register units is also fed to the second shift register unit via the first switch. The output of the second shift register unit is fed to each of the plurality of first register units within the unit stage via the second switch.

Abstract: Apparatus and method to logically process signals representative of multiple bits of multiple-bit numbers include successively delaying applications of the bit-representative signals to logical processing stages from associated input registers by a delay interval between input registers that is substantially equal to the processing delay interval per bit-level processing stage. In this way, successively more significant bits of each of plural numbers being logically processed are validly available for processing at each bit-level logic stage after a delay that is substantially equal to the processing delay interval of a preceding bit-level logic stage.