Inspecting Printed Circuit Boards Patents (Class 382/147)
  • Publication number: 20040234121
    Abstract: Disclosed is a method for inspection a circuit wiring on a circuit board, which comprises the steps of supplying an inspection signal to the circuit wiring (S141), detecting potential variation which is generated in the circuit wiring in response to the supplied inspection signal, by use of a plurality of sensor elements (S142), and creating image data representing the shape of the circuit if the detected potential variation at the specific position is out of a given range (S143-N), while omitting the generation of the image data if the detected potential variation at the specific position falls within the given range (S143-Y).
    Type: Application
    Filed: February 27, 2004
    Publication date: November 25, 2004
    Inventors: Tatsuhisa Fujii, Kazuhiro Monden, Mikiya Kasai, Shogo Ishioka, Shuji Yamaoka
  • Publication number: 20040228516
    Abstract: A method for inspecting a repeating pattern of a sample for defects. The repeating pattern has a translation vector, which defines a separation of substantially identical sections of the repeating pattern. The repeating pattern has a first section and a second section which are separated substantially by the translation vector. The method includes comparing the first section and the second section to identify a discrepancy indicative of a possible defect. The method also includes analyzing a reference data source in order to identify if the defect exists, and when the defect exists, in which one of the first section and the second section the defect exists. The reference data source is derived from a source exogenous to the sample.
    Type: Application
    Filed: May 12, 2003
    Publication date: November 18, 2004
    Applicant: Tokyo Seimitsu Co (50%) and Accretech (Israel) Ltd (50%)
    Inventors: Gilad Golan, Oma Bregman-Amitai
  • Publication number: 20040213451
    Abstract: A method for obtaining confidence measure of a ball grid array (BGA) model having a plurality of balls in semiconductor surface mounted devices is provided. The method comprises the steps of extracting BGA images from a real surface mounted device, generating a BGA ball model and a BGA body model, generating a first confidence measure of the BGA ball model wherein the first confidence measure includes a first standard deviation of the BGA ball model and a first local image contrast of each BGA ball, and generating a second confidence measure of the BGA body model wherein the second confidence measure includes a second standard deviation of the BGA body model and a second local image contrast of the BGA body.
    Type: Application
    Filed: April 22, 2003
    Publication date: October 28, 2004
    Inventors: Tong Fang, Ming Fang
  • Patent number: 6810139
    Abstract: A method is provided for the detection of defects on a semiconductor wafer by checking individual pixels on the wafer, collecting the signature of each pixel, defined by the way in which it responds to the light of a scanning beam, and determining whether the signature is that of a faultless pixel or of a pixel that is defective or suspect to be defective. An apparatus is also provided for the determination of such defects, which comprises a stage for supporting a wafer, a laser source generating a beam that is directed onto the wafer, collecting optics and photoelectric sensors for collecting the laser light scattered by the wafer in a number of directions and generating corresponding analog signals, an A/D converter deriving from said signals digital components defining pixel signatures, and selection systems for identifying the signatures of suspect pixels and verifying whether the suspect pixels are indeed defective.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: October 26, 2004
    Assignee: Applied Materials, Inc.
    Inventors: Zeev Smilansky, Sagie Tsadka, Zvi Lapidot, Rivi Sherman
  • Patent number: 6801652
    Abstract: A method for checking the fitting at automatic onserting units for the onserting of substrates with components, comprising the steps of: taking a picture of the surface of a component to be onserted positioned in a delivery means with a camera; comparing the picture in an image evaluation unit following the camera to a stored pattern of the component to be onserted; given agreement in the comparison, onserting the component onto the substrate; and given disagreement in the comparison, outputting an error message.
    Type: Grant
    Filed: May 3, 1999
    Date of Patent: October 5, 2004
    Assignee: Siemens Aktiengesellschaft
    Inventors: Harald Stanzl, Jochen Prittmann
  • Patent number: 6795573
    Abstract: A statistical processing unit compares the gray levels at identical positions in raw and reference images using a raw image having three or more gray levels obtained by sensing an object by an image pick-up unit. As the reference image, a predetermined designed image or at least one shift image obtained by shifting the raw image by an integer multiple of the repetition period in the repetition direction of a specific pattern is used. The statistical processing unit statistically analyzes the occurrence state of the difference between the raw and reference images, thus accurately obtaining the formation state of repetitive patterns on the object.
    Type: Grant
    Filed: January 26, 2001
    Date of Patent: September 21, 2004
    Assignee: Nikon Corporation
    Inventor: Kouji Yoshida
  • Patent number: 6788806
    Abstract: A method of inspecting whether a printed board is appropriately supported by a supporting device, when a holding device holding an electric component mounts the electric component on the printed board supported by the supporting device, the method including the steps of taking, with an image taking device, an image of at least one prescribed detection portion of the printed board supported by the supporting device, and judging, based on image data representing the taken image of the detection portion, whether the printed board is appropriately supported by the supporting device.
    Type: Grant
    Filed: December 26, 2000
    Date of Patent: September 7, 2004
    Assignee: Fuji Machine Manufacturing Company
    Inventors: Sumio Kadomatsu, Takayoshi Kawai
  • Publication number: 20040165764
    Abstract: The invention takes into account the fact that the size of the SAWs varies greatly depending on the stepper and the die size (design). In general, it cannot be assumed that one SAW can be imaged with one camera image. A SAW is preferably broken down into regular logical parts (segments) of identical size. A SAW index is allocated to each logical SAW segment. One image field of the camera can image only a certain number of these SAW segments. An index, hereinafter called an image field segment index, is allocated to each segment of an image field, hereinafter called an image field segment.
    Type: Application
    Filed: February 5, 2004
    Publication date: August 26, 2004
    Applicant: Leica Microsystems Semiconductor GmbH
    Inventor: Detlef Michelsson
  • Patent number: 6779386
    Abstract: An apparatus and method for detecting characteristics of a microelectronic substrate. The microelectronic substrate can have a first surface with first topographical features, such as roughness elements, and a second surface facing opposite from the first surface and having second topographical features, such as protruding conductive structures. In one embodiment, the apparatus can include a support member configured to carry the microelectronic substrate with a first portion of the first surface exposed and a second portion of the second surface exposed. The apparatus can further include a topographical feature detector positioned proximate to support member and aligned with the first portion of the first surface of the microelectronic substrate to detect characteristics, such as a roughness, of the first surface while the microelectronic substrate is carried by the support member.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: August 24, 2004
    Assignee: Micron Technology Inc.
    Inventors: Chee Peng Neo, Cher Khng Victor Tan, Kian Seng Ho, Hock Chuan Tan
  • Patent number: 6775899
    Abstract: A test printing portion with a pattern dimension smaller than a minimum printing pattern dimension is formed on a substrate, and a printing state of this test printing portion is inspected after printing. Based on inspection results of the test printing portion, acceptability of the printing state of the entire substrate is judged. The test printing portion is created on a periphery of the substrate outside the printing pattern area or an unprinted space inside the printing pattern area. A detection device detects the test printing portion, and inspects its printing state. Based on the inspection results, the acceptability of the printing state of the entire substrate is judged. This enables the printing state to be easily inspected at low cost while securing a necessary decree of accuracy.
    Type: Grant
    Filed: May 23, 2000
    Date of Patent: August 17, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Michinori Tomomatsu, Masayuki Mantani, Takaaki Sakaue
  • Publication number: 20040149021
    Abstract: A method for enhancing information derived from acoustically inspected samples comprises deriving an acoustic image of a sample, and generating a visual superposition of one or more additional images. The additional images are selected from the group consisting of an optical image, a second acoustic image in a different sized field of view form said acoustic image, an infrared image, an X-ray image, and an electron beam image.
    Type: Application
    Filed: August 22, 2001
    Publication date: August 5, 2004
    Inventors: Lawrence W. Kessler, Thomas E. Adams, Michael G. Oravecz
  • Patent number: 6771805
    Abstract: Perspective viewing inspection system comprises a stage for holding a printed circuit board (PCB) mounted with electronic parts, teaching means for teaching position data and pose data of the PCB during inspection and also part electrode's addresses on the PCB, means for making an inspection program including layout of inspection areas, means for imaging the inspection areas of the PCB, means for evaluating part-mounting and soldering quality or means for displaying images captured therewith, and means for coordinating the whole system operations. The means for imaging involves an active vision system consisting of an active mirror, an active objective, an ocular, a zoom leans, and an imaging device enabling gaze at solder joints and capture of bird's eye perspective view images thereof. The stage is equipped with a PCB pose controller to orient the PCB at directions wherewith the means for imaging obtains the solder joint's angular perspective view images.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: August 3, 2004
    Assignee: Keiso Research Laboratories, Inc.
    Inventor: Shigeki Kobayashi
  • Patent number: 6771807
    Abstract: A method and a system for detecting surface defects on electronic circuits, such as Printed Circuit Boards (PCB), are described herein. The method first comprises identifying contours on a digital image of the PCB. Then anomalies are detected on the PCB image by comparing the identified contours to contours on a vectorial model of the PCB. Each detected anomaly is compared to manufacturing data to verify if it corresponds to a defect.
    Type: Grant
    Filed: January 18, 2001
    Date of Patent: August 3, 2004
    Assignee: Solvision Inc.
    Inventors: Alain Coulombe, Michel Cantin, Louis Bérard, Jonathan Gauthier
  • Patent number: 6760471
    Abstract: A system and method for compensating pixel values in an inspection machine for inspecting printed circuit boards includes an image acquisition system for providing pixel values from a digitized image to a compensation circuit. The compensation circuit applies one or more compensation values to the digitized pixel values to provide compensated digitized pixel values for storage in a memory. The compensated digitized pixel values are then available for use by an image processor which implements inspection techniques during a printed circuit board manufacturing process. With this technique, the system corrects the errors on a pixel by pixel basis as the pixel values representing an image of a printed circuit board are transferred from the image acquisition system to the memory.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: July 6, 2004
    Assignee: Teradyne, Inc.
    Inventor: Douglas W. Raymond
  • Patent number: 6750899
    Abstract: A novel inspection system for inspecting an article of manufacture, such as a printed circuit board, is disclosed, where the system includes a strobed illuminator adapted to project light through a reticle so as to project a pattern of light onto an area of the printed circuit board. A board transport responsively positions the board to at least two distinct positions, where each position corresponding to a different phase of the projected light. Also included is a detector adapted to acquire at least two images of the area, each image corresponding to one of the at least two different phases. An encoder monitors the movement of the board and outputs a position output, and a processor connected to the encoder, the board transport, the illuminator and the detector controlledly energizes the illuminator to expose the area as a function of the position output, the processor co-siting the at least two images and constructing a height map image with the co-sited images.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: June 15, 2004
    Assignee: CyberOptics Corporation
    Inventors: David Fishbaine, Timothy A. Skunes, Eric P. Rudd, David M. Kranz, Carl E. Haugan
  • Patent number: 6748104
    Abstract: A method for rapid determination of the position and/or orientation of a semiconductor device, electronic component or other object includes performing multiple times an operation of matching a pattern against an image. The matching operation finds the location, if any, of a respective pattern in the image and determines the degree of match. The position and orientation of the object is determined from the results of one of the matching operations, for example, from the operation that revealed the highest degree of match.
    Type: Grant
    Filed: March 24, 2000
    Date of Patent: June 8, 2004
    Assignee: Cognex Corporation
    Inventors: Ivan Bachelder, Aaron Wallack
  • Patent number: 6748103
    Abstract: A reusable circuit design for use with electronic design automation EDA tools in designing integrated circuits is disclosed, as well as reticle inspection and fabrication methods that are based on such reusable circuit design. The reusable circuit design is stored on a computer readable medium and contains an electronic representation of a layout pattern for at least one layer of the circuit design on an integrated circuit. The layout pattern includes a flagged critical region which corresponds to a critical region on a reticle or integrated circuit that is susceptible to special inspection or fabrication procedures. In one aspect of the reusable circuit design, the special analysis is performed during one from a group consisting of reticle inspection, reticle production, integrated circuit fabrication, and fabricated integrated circuit inspection.
    Type: Grant
    Filed: February 4, 2003
    Date of Patent: June 8, 2004
    Assignee: KLA-Tencor
    Inventors: Lance A. Glasser, Jun Ye, Shauh-Teh Juang, David S. Alles, James N. Wiley
  • Patent number: 6738506
    Abstract: An image processing system for use in semiconductor wafer inspection comprises a multiplicity of self-contained image processors for independently performing image cross-correlation and defect detection. The system may also comprise an image normalization engine for performing image brightness and contrast normalization. The self-contained image processors and image normalization engine access image data from a memory array; the array is fed data from a multiplicity of imaging modules operating in parallel. The memory array is configured to allow simultaneous access for data input, normalization, and cross-correlation and defect detection. Multiple image processing systems can be configured in parallel as a single image processing computer, all sending defect data to a common display module.
    Type: Grant
    Filed: April 17, 2002
    Date of Patent: May 18, 2004
    Assignee: Multibeam Systems, Inc.
    Inventors: S. Daniel Miller, N. William Parker, Steven B. Hobmann
  • Patent number: 6738504
    Abstract: An inspection apparatus for semiconductor devices, comprising: a light irradiation means for irradiating light to a surface of a semiconductor device, the surface having external connection terminals formed thereon; an image pickup means for picking up a plane image of the surface of the semiconductor device by using an optical system to provide an image data; an inspection means for inspecting misalignment of tips of the external connection terminals based on the image data; the external connection terminals standing on, and being bonded to, electrode pads of the semiconductor device and being bent to crank shapes having respective middle portions laterally extending out of positions of the electrode pads; and the irradiation means irradiating light from a side opposite to the laterally extending middle portions of the external connection terminals with respect to the electrode pads.
    Type: Grant
    Filed: August 24, 2000
    Date of Patent: May 18, 2004
    Assignee: Shinko Electric Industries Co., Ltd
    Inventors: Mitsutoshi Higashi, Kei Murayama
  • Patent number: 6724929
    Abstract: To provide a wafer inspecting apparatus for classifying by kind defects appearing on a patterned wafer, a wafer is inspected by a wafer defect inspecting apparatus unit and coordinate value data representing positions and sizes of defects on the sample is output thereby. The coordinate value data is supplied to an image data forming unit and graphic images representing defects on the wafer are formed for respective chips on the wafer, and image data is produced. The image data is output to a pattern overlap evaluating unit which analyzes a state of overlap of a first image corresponding to the image data and a second image representing the circuit pattern based on the wiring information and outputting overlap analysis data. A defect kind automatic classifying unit receives the overlap analysis data and classifies defects by kind of defect based on the overlap analysis data.
    Type: Grant
    Filed: March 29, 2000
    Date of Patent: April 20, 2004
    Assignee: Seiko Instruments Inc.
    Inventor: Ryoichi Matsuoka
  • Publication number: 20040071336
    Abstract: In an exposure method of drawing and exposing a second pattern with a scanner so as to match a first pattern formed on a sample upon exposure with a reduction projection exposure apparatus, a matrix is set on the sample. A distortion correction map representing an offset of a point corresponding to each matrix point on the first pattern from an ideal position is formed. The block of the matrix small for a large offset and large for a small offset are set when drawing the second pattern while correcting drawing information of the second pattern on the basis of offset information represented by the correction map. The block size of the distortion correction map is not uniformly reduced. A small block size is set for a large distortion, and a large block size is set for a small distortion, thereby reducing the data amount.
    Type: Application
    Filed: October 6, 1998
    Publication date: April 15, 2004
    Inventor: YOSHIKIYO YUI
  • Patent number: 6714671
    Abstract: An input subject pattern is compared with a good product pattern that is registered beforehand, and a different portion of these is detected as a defect pattern. The detected defect pattern is classified in accordance with the features of the contour of the defect pattern.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: March 30, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koichi Wakitani, Noriaki Yukawa
  • Patent number: 6707936
    Abstract: Device design information (18) for a semiconductor device is used to generate theoretical probability of failure information (21), which represents the probability that a manufacturing defect will cause an electrical failure in an actual device fabricated according to the design information. An actual wafer (23), which contains a plurality of devices (22) manufactured according to the design information, is inspected for actual defects (25). The probability of failure information is then used to determine for each of several detected defects a corresponding probability value. Then, the individual probability values for the respective defects are combined in order to obtain a composite failure probability, which serves as a basis for evaluating the expected yield of operational devices from the particular wafer.
    Type: Grant
    Filed: March 9, 2000
    Date of Patent: March 16, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas W. Winter, Thomas K. Powell, Jr., Steven M. James
  • Patent number: 6701003
    Abstract: A method and system for component identification system for electronic board tester to identify the actual defective components in a failed board is disclosed. It uses image captures of the front side and backside of the tested board to extract an outline diagram that is compared to a database of outline diagrams of known boards until a match is found. Each outline diagram in the database is associated with a connection list between the standard connector of the board and the individual components. Test results with errors relating to connections of the standard connector are linked via the associated connection list of the match's outline diagram to the individual components. The outline diagram is displayed and printed with the defective components highlighted. Use of the identification system to select the best test algorithm and test parameter setup is disclosed. Connection to and operation with automatic handler systems is also disclosed.
    Type: Grant
    Filed: April 10, 2000
    Date of Patent: March 2, 2004
    Assignee: Innoventions, Inc.
    Inventor: David Y. Feinstein
  • Patent number: 6693278
    Abstract: In the production of semiconductors it is necessary to inspect circuit patterns on wafers. In circuits having very small details (for example, 40 nm), inspection can be carried out by means of electron beam columns, a plurality of wafers then being inspected at the same time and the signals being compared on-line. In an inspection apparatus in accordance with the invention more beam columns 1 to 7 are provided for every wafer A, B, C in order to obtain a high feed-through rate. The inspection is carried out by way of an x-y scan and the wafers are fed through according to a rectilinear movement, thus providing the possibility of scanning only the Care Area Fraction of the wafers, resulting in a high feed-through rate for the wafers in the inspection apparatus.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: February 17, 2004
    Assignee: FEI Company
    Inventors: Diederik Jan Maas, Jan Martijn Krans
  • Patent number: 6690819
    Abstract: A method and apparatus for accurately recognizing most of components available in the market with moderate illuminating condition in high speed image processing are disclosed. After imaging a component having a predetermined electrode pattern, a core electrode 32 is extracted with the image being swept from a corner 33a (S1) through a small window. A H0V0 coordinate system is implemented with the core electrode set as its origin to observe its neighbor electrodes (S2). At this state, electrodes are sequentially extracted through a small window placed in an area predicted from previously extracted electrodes. Thereafter, an extracted electrode pattern is produced, and coordinates of its electrodes are obtained. Then, the extracted electrode pattern is collated with the predetermined electrode pattern by overlaying with each other for positioning (S3).
    Type: Grant
    Filed: February 9, 2000
    Date of Patent: February 10, 2004
    Assignee: Juki Corporation
    Inventor: Takashi Teraji
  • Patent number: 6681038
    Abstract: An apparatus for automatically assessing the quality of a printed circuit board assembly (6) using digitized video image analysis. The apparatus integrates with existing relatively low precision automated surface mount technology (“SMT”) manufacturing systems as an inspection station (56a) insertable at various steps in the assembly process or as a separate manually loaded station. The inspection station includes a high resolution video imaging system and a video image analyzer comprising an onboard master computer (26a) that generates control signals to reposition the camera mounted within a screen (45) on a movable carriage (22a) and/or reposition the circuit board, and adjust the lighting; and generates individual board status data to be archived, graphically displayed on monitors (40a, 41a) or otherwise utilized by a rework station.
    Type: Grant
    Filed: February 23, 2000
    Date of Patent: January 20, 2004
    Assignee: Vectron, Inc.
    Inventor: Joseph L. Vilella
  • Patent number: 6674889
    Abstract: The present invention provides a pattern inspection apparatus whereby, even if a large number of defects are detected during inspection it is possible to continue inspection without interruption of the inspecting operation and the apparatus comprising optical means 4 and 5 for generating pattern image data from a pattern under test 9 held by the moving holding means 3, an image comparison sections 71 that compare the pattern under inspection with reference pattern image information so as to make a judgment as to whether or not a defect exists in the partial patterns under inspection, the image comparison sections 71 having a comparison pattern image information storage means 712, which stores comparison pattern image data for a partial pattern under inspection, reference pattern image information storage means 711 and/or 713 which store reference pattern image data corresponding to the partial patterns under inspection and an image processing means 715 that perform a comparison between the comparison pattern
    Type: Grant
    Filed: June 19, 2000
    Date of Patent: January 6, 2004
    Assignee: NEC Corporation
    Inventor: Naohisa Takayama
  • Patent number: 6675120
    Abstract: A color optical inspection system extracts only such luma and chroma spatial features as are necessary for detection of defects related to the physical characteristics of devices populating the surface of a board. During the training phase, the features of each device present on each of a number of golden boards is extracted and compared against a set of established criteria, thereby to select one or more spatial features to be extracted for the associated devices during the inspection phase. A match region whose boundaries are defined by the selected features of the devices on the golden boards is established during the training phase. During the inspection phase, the selected features of each associated device are extracted to determine whether they fall inside the match region. If the extracted features falls outside the corresponding match region, then a defect is reported.
    Type: Grant
    Filed: June 25, 2001
    Date of Patent: January 6, 2004
    Assignee: Photon Dynamics, Inc.
    Inventors: William K. Pratt, Owen Y. Sit
  • Patent number: 6665433
    Abstract: An improved circuit board inspection system incorporates self learning techniques for accurate determination of Z-axis elevations of electrical connections. A Delta Z, referenced to a laser range finder generated surface map of the circuit board, is automatically determined from a series of cross sectional images of the electrical connections for each electrical connection on the circuit board. The Delta Z values for each electrical connection are stored in a data base from which customized Delta Z values for specifically defined board views may be calculated.
    Type: Grant
    Filed: October 16, 2002
    Date of Patent: December 16, 2003
    Assignee: Agilent Technologies, Inc.
    Inventor: Paul A. Roder
  • Patent number: 6633663
    Abstract: A method and system for determining component dimensional information in a component placement system. The component information is derived from the pick and place equipment which is used to place the components on the substrate. The component is grasped at substantially the centroid position and moved over the aperture of a camera. The edges of the component are located, and from the edges an accurate location of the centroid may be obtained. The centroid, as well as the length, width and thickness of the component is stored in a database for use during placing of the component. Other features derived include orientation indicia obtained from component features which are viewed by the camera. During placement, all features associated with the component necessary to accurately locate the component on a substrate are obtained from the database.
    Type: Grant
    Filed: May 5, 1998
    Date of Patent: October 14, 2003
    Assignee: International Business Machines Corporation
    Inventor: Kris A. Slesinger
  • Publication number: 20030185431
    Abstract: A method and system are disclosed for extracting a golden template image of a unit. An image associated with the unit is obtained. A region within the image is selected. A first region growing algorithm extracts an object region using the selected region. A boundary tracing algorithm extracts an outer boundary of the object region using the extracted object region. A second region growing algorithm extracts a golden template image of the unit using the extracted object region.
    Type: Application
    Filed: February 20, 2003
    Publication date: October 2, 2003
    Inventors: DeZhong Hong, Chiat Pin Tay
  • Patent number: 6617602
    Abstract: A method of detecting an edge of an object, including the steps of lighting, in each one of a plurality of different directions, at least a portion of the object, taking an image of the portion of the object and a vicinity of the portion which are lighted in the each one of the different directions, synthesizing the respective images of the portion of the object taken by lighting the portion in the different directions, and detecting, based on the synthesized images, an edge of the portion of the object.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: September 9, 2003
    Assignee: Fuji Machine Mfg. Co., Ltd.
    Inventors: Seigo Kodama, Yasushi Okada
  • Patent number: 6614925
    Abstract: A system and method for performing basic training in a dynamic image recognition system, including collecting raw image data on a blank object, segmenting out a region of interest on the object, performing spatial image transforms to generate a set of derived spaces for the region of interest, generating a set of presence/absence features for the object by creating a set of presence/absence features, representing each significant presence/absence feature as one or more presence/absence boxes, building a blank object presence/absence score set, building an assembled board presence/absence score set, building a presence/absence knowledge base using the blank object presence/absence score set and the assembled object presence absence score set, and pruning each presence/absence box. The system and method further includes generating a set of polarity features from a first assembled object.
    Type: Grant
    Filed: April 22, 2002
    Date of Patent: September 2, 2003
    Assignee: Intelligent Reasoning Systems, Inc.
    Inventors: Mark R. DeYong, Jeff E. Newberry, John W. Grace, Thomas C. Eskridge
  • Patent number: 6608922
    Abstract: In a method of recognizing a connection of a reconstructing pattern in a printed wiring board when a circuit modification process after a printed board wiring is performed by a physical cutting, a jumper, or the like, a physical connection table is prepared which has a forward connecting direction address (KP address) indicating a forward connection order of connecting elements (a land, a via, a manual land, an external land, a line, and a jumper) with a predetermined connecting element (the land) being made a starting point and a backward connecting direction address (NKP address) indicating a backward connection order to the forward connection order, based on a pattern input information table. Also, a large area pattern is regarded as one of a peripheral line, a punching line, an imaginary line, and a cutting line of the above-mentioned lines, whereby the connecting elements are made to include the large area pattern.
    Type: Grant
    Filed: October 27, 1999
    Date of Patent: August 19, 2003
    Assignee: Fujitsu Limited
    Inventor: Hideharu Matsushita
  • Patent number: 6597381
    Abstract: A user interface method and system are disclosed that allow for user selection on a display device of one or more functions performed via a computer in an automated optical inspection system. The user interface provides a real-time information display that makes apparent critical board inspection information and potential undesirable operating conditions so that corrective action can be rapidly initiated. The user interface includes one or more button icons respectively associated with the user selectable functions and at least one view area window for displaying information items. The information items displayed in a view window can be dynamically linked to provide interactivity between windows and simultaneous updating of related information items in all windows. A filter area window is used for selecting which information items to discriminate and display in the view windows.
    Type: Grant
    Filed: July 24, 1999
    Date of Patent: July 22, 2003
    Assignee: Intelligent Reasoning Systems, Inc.
    Inventors: Thomas C. Eskridge, Jeff E. Newberry, Mark R. DeYong, Scott A. Dunn, Wesley K. Huffstutter, John W. Grace, Marc A. Lumeyer, Michael A. Ellison, John R. Zoch
  • Patent number: 6584420
    Abstract: A defect examination apparatus detects defect locations for a plurality of to-be-inspected objects vertically and horizontally arranged according to a prescribed rule. A blob analysis section finds location coordinates for the plurality of to-be-inspected objects. Based on location coordinates found by this blob analysis section, a rotation angle calculation section finds a rotation angle for a horizontal series of the to-be-inspected objects against a horizontal line. The rotation angle calculation section also finds a rotation angle for a vertical series of the to-be-inspected objects against a vertical line. A pitch size calculation section finds vertical and horizontal pitch sizes for the plurality of to-be-inspected objects. A matrix number analysis section finds a matrix number for each to-be-inspected object based on a rotation angle found by the rotation angle calculation section and a pitch size found by the pitch size calculation section.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: June 24, 2003
    Assignee: Olympus Optical Co., Ltd.
    Inventor: Takeshi Minami
  • Publication number: 20030113009
    Abstract: An improved circuit board inspection system incorporates a technique that confirms observed electrical connection defects. The improved circuit board inspection system applies a localized investigative routine upon portions of a printed circuit board having one or more identified defects. The technique accounts for the slope of a portion under test of the printed circuit board and provides results that are more accurate from inspection systems that report electrical connection defects.
    Type: Application
    Filed: December 14, 2001
    Publication date: June 19, 2003
    Inventors: Horst Mueller, Sunit Bhalla, Kris Kanack, Stig Oresjo
  • Patent number: 6574358
    Abstract: A method of training a system to identify inspection sites on a circuit board is described. The method uses a priori information, which includes a region of interest, approximate sizes and approximate spacings of a plurality of nominal pad locations, and a pad count or an aperture count. A region is created which is associated with each one of the nominal pad locations within an image of a printed circuit board. A search tool is run to find pad candidates within each one of the regions. The pad candidates are filtered. The best pad candidates are selected from among each of the found pad candidates. The best pad candidates are averaged to provide an average, and are modified based on the average.
    Type: Grant
    Filed: November 8, 1999
    Date of Patent: June 3, 2003
    Assignee: Cognex Technology and Investment Corporation
    Inventors: Juha Koljonen, Leonid Taycher
  • Patent number: 6571006
    Abstract: Methods are disclosed that measure the extent of a group of objects within a digital image by comparing signature, representative of the relationship of the objects to one another, against instances of a measured signature at varying positions within the image. The position(s) where the signature(s) vary by a predetermined comparison criterion indicates the extent of the group of objects. It is disclosed that the comparison to a reference signature allows proper identification of measured signatures despite noise in the digital image. A preferred embodiment uses the CALIPER TOOL to generate signatures of edges, where the window of the CALIPER TOOL has a projection axis substantially parallel to the extent being measured. A preferred application is desired wherein the method measure the length of leads in a lead set.
    Type: Grant
    Filed: November 30, 1998
    Date of Patent: May 27, 2003
    Assignee: Cognex Corporation
    Inventors: Albert A. Montillo, Ivan A. Bachelder, Cyril C. Marrion, Jr.
  • Patent number: 6571007
    Abstract: A ball-arranging substrate comprising a substrate with a main surface, a plurality of ball-arranging holes formed on the main surface for sucking and holding minute electroconductive balls at the locations corresponding to those of electrodes formed on a semiconductor device or a printed circuit board, wherein when light illuminates the ball-arranging surface to allow optical recognition of the arrangement of the minute electroconductive balls by means of the light reflected by the minute electroconductive balls and by the main surface, the wave length of the light of the light source is set in the range of 300 to 900 nm, and the reflectivity is made not more than 50% based on the light source. A reflective mirror should be provided on the rear surface of the substrate opposite to the light source, in the case when the substrate is transparent to the irradiated light.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: May 27, 2003
    Assignee: Nippon Steel Corporation
    Inventors: Kenji Shimokawa, Eiji Hashino, Kohei Tatsumi
  • Patent number: 6571183
    Abstract: A method of, an and apparatus for, creating an image of currents flowing through current paths in a microelectronic circuit such that the image of the currents has improved spatial resolution using filters. The filters increase the spatial resolution and eliminate noise and edge artifacts in magnetic field and electric field images of electronic circuits. In accordance with the method, a magnetic field image is created with a scanning SQUID microscope. A magnetic inversion technique is then used to convert the magnetic field image into a current density image. The current density image is filtered based upon known restrictions on the wiring geometry of the microelectronic circuit being imaged. The technique can also be applied to convert electric fields of a circuit from a scanning single electron transistor microscope into images of the voltage levels on the wires in the circuit.
    Type: Grant
    Filed: October 18, 2000
    Date of Patent: May 27, 2003
    Assignee: University of Maryland
    Inventors: Frederick Charles Wellstood, Sojiphong Chatraphorn, Erin Franklin Fleet
  • Patent number: 6567542
    Abstract: A method involves training a system to identify inspection sites on a printed circuit board. The method uses a priori information, which includes a sample pad description. A training region of interest is created within an image of the printed circuit board. A search tool is run to find pad candidates within the training region. The pad candidates are filtered and false pad candidates are eliminated. The filtered pad candidates are averaged to provide an average, and are modified based on the average.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: May 20, 2003
    Assignee: Cognex Technology and Investment Corporation
    Inventors: Juha Koljonen, Leonid Taycher
  • Patent number: 6560729
    Abstract: A computer system automatically determines and displays the physical location of a failed memory cell of an array of memory cells on magnified images of a memory IC (integrated circuit) die from label information of the failed memory cell generated by a test station. The label information includes any combination of a sector label, an I/O label, a column label, and a row label. The memory IC die is comprised of a plurality of sectors, and the sector label corresponds to the sector having the failed memory cell located therein. A sector is comprised of a plurality of I/O regions, and the I/O label specifies the I/O region having the failed memory cell located therein, within the sector having the sector label. An I/O region is comprised of a plurality of horizontal conductive structures and vertical conductive structures.
    Type: Grant
    Filed: July 3, 2000
    Date of Patent: May 6, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Suntra Anuntapong, Surasit Phurikhup, Wannee Soiluck
  • Patent number: 6549649
    Abstract: A testing system operable to accurately position a plurality of contact electrodes relative to a plurality of electrical contacts is disclosed. For one embodiment, the testing system comprises a first imaging system coupled to a wafer chuck. The wafer chuck is used to place the electrical contacts of a wafer in contact with the plurality of electrodes. To facilitate accurate positioning between the wafer electrical contacts and the contact electrodes, the first imaging system is configured to locate the plurality of contact electrodes. The testing system also comprises a second imaging system configured to locate the wafer electrical contacts. An image generator coupled to the first imaging system generate an alignment image on a focal point of the first imaging system. The testing system calibrates the first imaging system to the second imaging system using the alignment image.
    Type: Grant
    Filed: March 4, 1999
    Date of Patent: April 15, 2003
    Assignee: Electroglas, Inc.
    Inventor: John A. Penkethman
  • Patent number: 6549647
    Abstract: Methods and an apparatus are disclosed for providing enhanced vibration immunity in a solder paste inspection system, although they are usable in any number of industries that require rapid acquisition of several images. The method includes capturing at least three images on a frame transfer CCD array before any data is sequentially read from the array. The present method is extendable to a larger number of images. Additionally, the masked memory area can be larger than the image area of the frame transfer CCD array.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: April 15, 2003
    Assignee: CyberOptics Corporation
    Inventors: Timothy A. Skunes, David Fishbaine
  • Patent number: 6546126
    Abstract: A method for automatically setting illumination intensity of light sources used within either positional recognition devices or quality control devices that, in turn, are used in devices that automatically equip components on a printed circuit board or ceramic substrates. The individual light sources are successively varied and an image of a component to be placed on a printed circuit board or substrate is registered by a camera. The resulting picture elements are registered as grayscale values and stored in an image evaluation unit. The grayscale values are either represented as useful structures of the component or unwanted structures of the component dependent on the illumination intensity of the individual light sources. The stored grayscale values for all of the light sources are summed according to respective useful and unwanted structures of the component and then compared to one another.
    Type: Grant
    Filed: December 21, 1999
    Date of Patent: April 8, 2003
    Assignee: Siemiens Aktiengesellschaft
    Inventors: Günther Wittmann, Matthias Hedrich
  • Patent number: 6542630
    Abstract: A method and apparatus for inspecting the placement of a device-under-inspection (DUI), for example a surface-mount component, on a circuit board includes scanning the circuit board to acquire stored images of the circuit board. From the stored images, a pad-bounding rectangle is constructed that circumscribes the outer edges of the pads for the DUI. An error-bounding rectangle is then constructed from the pad-bounding rectangle. The error-bounding rectangle has a length equal to the length of the pad-bounding rectangle plus a lengthwise error deemed allowable for placing the pins of the DUI over its pads. Similarly, the error-bounding rectangle has a width equal to the width of the pad-bounding rectangle plus an allowable widthwise error. A pin-bounding rectangle is constructed that circumscribes the outer edges of the pins of the DUI. The invention then determines whether the DUI is properly placed by examining whether any portion of the pin-bounding rectangle lies outside of the error-bounding rectangle.
    Type: Grant
    Filed: September 14, 1999
    Date of Patent: April 1, 2003
    Assignee: Teradyne, Inc.
    Inventor: Lyle L. E. Sherwood
  • Publication number: 20030052968
    Abstract: To provide an inspecting apparatus of a printed state or the like in a flexible printed circuit board which requires no skill, generates no error by oversight and further improves an operation efficiency, a substrate feeding out unit (2), a substrate inverting unit (4), a camera inspecting unit (5), a substrate inverting unit (9) and a defect point marking unit (10) for a printed state or the like are sequentially placed on working tables (1, 1) along a moving direction of a flexible printed circuit board, in this order, the substrate inverting units (4, 9) respectively invert the flexible printed circuit board, the camera inspecting unit (5) detects a print defect point by means of a camera (8), and the defect point marking unit (10) applies a marking to the print defect point by a laser marker (13) on the basis of a signal output from the camera inspecting unit (5).
    Type: Application
    Filed: August 28, 2002
    Publication date: March 20, 2003
    Inventor: Takehiko Murakami
  • Patent number: 6529624
    Abstract: In an apparatus for inspecting cream solder on a PCB, a camera captures an image of cream solder coated on the upper surface of the PCB. A first illuminator illuminates the cream solder such that the light reflected from an edge of the-cream solder, forming an angle with respect to the upper surface of the PCB, proceeds toward the camera. A second illuminator illuminates the cream solder such that the light reflected from the upper surface of the cream solder, parallel to the upper surface of the PCB, proceeds toward the camera. A controller controls the camera, the first and the second illuminators, and for processing the image captured by the camera into a binary image.
    Type: Grant
    Filed: June 23, 1999
    Date of Patent: March 4, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chang-hyo Kim