Inspection Of Semiconductor Device Or Printed Circuit Board Patents (Class 382/145)
  • Patent number: 12229943
    Abstract: Provided is a method for acquiring images. The method includes: acquiring a first image embodying a display panel; determining repair indication information of a plurality of defects in the display panel in the first image, wherein the repair indication information indicates a degree of a repair demand for the defects; selecting a target defect from the plurality of defects based on the repair indication information of the plurality of defects; and acquiring a repair reference image embodying the target defect by photographing the target defect in the display panel.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: February 18, 2025
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventor: Guolin Zhang
  • Patent number: 12223687
    Abstract: An image processing device that processes a color image in which each pixel has gradation values of three primary colors of RGB includes an image acquiring section to acquire an image; a difference image generating section to use a first primary color image extracted from the color image and a second primary color image in which a gradation value of a second primary color except the first primary color is extracted from the color image, to generate a difference image; a recognition image generating section configured to generate a recognition image having a gradation value obtained by subtracting a gradation value of the difference image from a gradation value of an image in which any one of the three primary colors of RGB is extracted from the color image; and a recognition processing section configured to perform recognition processing of the recognition target using the recognition image.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: February 11, 2025
    Assignee: FUJI CORPORATION
    Inventors: Keiichi Ono, Kazuya Kotani, Tomoya Fujimoto
  • Patent number: 12222385
    Abstract: A testing method includes: a wafer under test is detected based on a pre-set test region to obtain detection results of a plurality of chips in the wafer under test; a discrete point distribution diagram of the detection results of the plurality of chips are obtained, a discrete point in the discrete point distribution diagram being used for representing a position of an abnormal chip in the wafer under test; the discrete point distribution diagram is divided into a plurality of test regions based on graphic distribution characteristics in the pre-set test region, and a test result distribution diagram for representing graphic characteristics of the discrete point distribution diagram is obtained; a correlation between the test result distribution diagram and the graphic distribution characteristics in the pre-set test region is obtained; and a test result of the wafer under test is obtained based on the correlation.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: February 11, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yu-Ting Cheng
  • Patent number: 12217988
    Abstract: A method and a device for detecting a placement of wafers in a wafer cassette are provided. The wafer cassette includes a plurality of receiving grooves. The receiving grooves hold and store the wafers. Light is emitted through the wafer cassette. The light passes through the gaps and is imaged, and the image is captured. Characteristic information is extracted from the image. The extracted characteristic information is compared with standard characteristic information of a preset image, and whether a placement of all the wafers in the wafer cassette is qualified and satisfactory is determined according to a compared result.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: February 4, 2025
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: Yu-Ting Chou
  • Patent number: 12204842
    Abstract: According to some embodiments, the present disclosure provides a method for determining wafer inspection parameters. The method includes identifying an area of interest in an IC design layout, performing an inspection simulation on the area of interest by generating a plurality of simulated optical images from the area of interest using a plurality of optical modes, and selecting, based on the simulated optical images, at least one of the optical modes to use for inspecting an area of a wafer that is fabricated based on the area of interest in the IC design layout.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Bing-Siang Chao
  • Patent number: 12190498
    Abstract: Systems and methods for detecting defects on a reticle are provided. One system is configured for generating different stacked difference images for multiple instances of first patterned areas in different rows on a wafer based on images generated for the first patterned areas in the different rows. The system is also configured for performing double detection based on the different stacked difference images. The system then identifies defects on the reticle based on the defects detected by the double detection. As described further herein, the systems and methods detect defects from multiple reticle rows printed on a wafer, which can reduce noise and enable detection of substantially small repeater defects. The embodiments are particularly useful for high sensitivity repeater defect detection for extreme ultraviolet (EUV) reticles and multi-die reticles (MDR).
    Type: Grant
    Filed: November 30, 2022
    Date of Patent: January 7, 2025
    Assignee: KLA Corp.
    Inventors: Nurmohammed Patwary, James A. Smith, Heonju Shin, Jusang Maeng, Kenong Wu, Xiaochun Li, Hucheng Lee
  • Patent number: 12190519
    Abstract: The acquisition unit 41B acquires a target image indicating a target object of inspection. The detection unit 42B detects, on the basis of a group of images each of which indicates the target object in a normal state, the target image that indicates the target object that is not in the normal state among the target images that the acquisition unit 41B acquires.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: January 7, 2025
    Assignee: NEC CORPORATION
    Inventors: Tomoharu Kiyuna, Ikuma Takahashi, Maki Sano, Kenichi Kamijo, Kimiyasu Takoh, Yoshikazu Kitamura
  • Patent number: 12183066
    Abstract: A computerized system and method of training a deep neural network (DNN) is provided. The DNN is trained in a first training cycle using a first training set including first training samples. Each first training sample includes at least one first training image synthetically generated based on design data. Upon receiving a user feedback with respect to the DNN trained using the first training set, a second training cycle is adjusted based on the user feedback by obtaining a second training set including augmented training samples. The DNN is re-trained using the second training set. The augmented training samples are obtained by augmenting at least part of the first training samples using defect-related synthetic data. The trained DNN is usable for examination of a semiconductor specimen.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: December 31, 2024
    Assignee: Applied Materials Israel Ltd.
    Inventors: Leonid Karlinsky, Boaz Cohen, Idan Kaizerman, Efrat Rosenman, Amit Batikoff, Daniel Ravid, Moshe Rosenweig
  • Patent number: 12175656
    Abstract: A method for gray level ratio inspection comprising: obtaining an electron image that comprises region of interest (ROI) pixels of a ROI of the sample and reference pixels of a reference region of the sample, where the ROI pixels are obtained by illuminating the ROI with the electron beam and the reference pixels are obtained without illuminating the reference region with an electron beam; calculating a reference dark level value based on values of at least some of the reference pixels; calculating, responsive to the reference dark level value, a gray level ratio between a first gray level value related to a first sub-set of the ROI pixels and a second gray level value related to a second sub-set of the ROI pixels; determining whether the gray level ratio is indicative of a defect; and generating defect information following a determination that the gray level ratio is indicative of the defect.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: December 24, 2024
    Assignee: Applied Materials Israel Ltd.
    Inventors: Effi Siman tov, Udi Abrahamov
  • Patent number: 12141959
    Abstract: Embodiments of the invention provide automatic detection of same-type objects on an inspection line and automatically capture and/or display an image of the object once it is detected. Additionally, embodiments of the invention automatically provide the outline of an object to a user, enabling the user to either confirm or easily correct the outline. The confirmed or corrected outline is then automatically applied to all images of inspected items of the same-type, allowing optimization of inspection tasks such as defect detection, for all inspected items, based on a short, possibly a one-time, input, from the user.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: November 12, 2024
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Yonatan Hyatt, Alexander Spivak, Katherina Shefer
  • Patent number: 12124176
    Abstract: An inspection apparatus for inspecting an object such as a pellicle for use in an EUV lithographic apparatus, the inspection apparatus including: a vacuum chamber; a load lock forming an interface between the vacuum chamber and an ambient environment; and a stage apparatus configured to receive the object from the load lock and displace the object inside the vacuum chamber, wherein the vacuum chamber comprises a first parking position and a second parking position for temporarily storing the object.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: October 22, 2024
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Pawel Safinowski, Derk Servatius Gertruda Brouns
  • Patent number: 12124950
    Abstract: An optimization method comprises determining jump ratios of embedding layer parameters of a trained quantization model in a predetermined time range. The quantization model comprises a neural network model obtained after quantization processing on the embedding layer parameters. The method also comprises determining a jump curve in the predetermined time range according to the jump ratios, and fitting the jump curve to obtain a corresponding time scaling parameter. The method also comprises optimizing an initial algorithm of the quantization model based on the time scaling parameter to obtain an optimized target optimization algorithm, and training the quantization model based on the target optimization algorithm.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: October 22, 2024
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Yi Yuan, Zhicheng Mao, Yongzhuang Wang, Yuhui Xu
  • Patent number: 12119070
    Abstract: A system, method and apparatus of memory failure prediction through image analyses using an artificial neural network. A sequence of images indicative of progress of memory failures in a region of an integrated circuit die can be generated according to a physical layout of memory cells in the region. The artificial neural network can be trained to recognize graphical features in early images in the sequence and to predict, based on the recognized graphical features, memory failures shown in subsequent images in the sequence. A computing apparatus can use the artificial neural network to analyze an input image shown current memory failures in the region and to identify one or more memory cells in the region that are likely to have subsequent memory failures.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: October 15, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Abhishek Chaurasia
  • Patent number: 12111579
    Abstract: The present invention relates to a method and an apparatus for determining at least one unknown effect of defects of an element of a photolithography process. The method comprises the steps of: (a) providing a model of machine learning for a relationship between an image, design data associated with the image and at least one effect of the defects of the element of the photolithography process arising from the image; (b) training the model of machine learning using a multiplicity of images used for training purposes, design data associated with the images used for training purposes and corresponding effects of the defects; and (c) determining the at least one unknown effect of the defects by applying the trained model to a measured image and the design data associated with the measured image.
    Type: Grant
    Filed: September 1, 2023
    Date of Patent: October 8, 2024
    Assignee: Carl Zeiss SMT GmbH
    Inventors: Alexander Freytag, Christoph Husemann, Dirk Seidel, Carsten Schmidt
  • Patent number: 12107052
    Abstract: An overlay mark forming a Moire pattern, an overlay measurement method using the overlay mark, an overlay measurement apparatus using the overlay mark, and a manufacturing method of a semiconductor device using the overlay mark are provided. The overlay mark for measuring an overlay based on an image is configured to determine a relative misalignment between at least two pattern layers. The overlay mark includes a first overlay mark including a pair of first grating patterns which has a first pitch along a first direction and which is rotationally symmetrical by 180 degrees, and includes a second overlay mark including a pair of second grating patterns and a pair of third grating patterns. The second grating patterns partially overlap the first grating patterns and are rotationally symmetrical by 180 degrees, and the third grating patterns partially overlap the first grating patterns and are rotationally symmetrical by 180 degrees.
    Type: Grant
    Filed: May 4, 2023
    Date of Patent: October 1, 2024
    Assignee: AUROS TECHNOLOGY, INC.
    Inventors: Hyun Chul Lee, Hyun Jin Chang
  • Patent number: 12105414
    Abstract: A method for semiconductor metrology includes depositing first and second overlying film layers on a semiconductor substrate and patterning the layers to define an overlay target. The target includes a first grating pattern in the first layer, including at least a first linear grating oriented in a first direction and at least a second linear grating oriented in a second direction perpendicular to the first direction, and a second grating pattern in the second layer, including at least a third linear grating identical to the first linear grating and a fourth linear grating identical to the second linear grating. The second grating pattern has a nominal offset relative to the first grating pattern by first and second displacements in the first and second directions, respectively. A scatterometric image of the substrate is captured and processed to estimate an overlay error between the patterning of the first and second layers.
    Type: Grant
    Filed: October 6, 2022
    Date of Patent: October 1, 2024
    Assignee: KLA Corporation
    Inventors: Itay Gdor, Yuval Lubashevsky, Daria Negri, Eitan Hajaj, Vladimir Levinski
  • Patent number: 12080042
    Abstract: Methods for retrieving images from a database are provided. A query image is obtained. A plurality of patches are extracted from the query image. A set of weightings is obtained according to a plurality of bases of a sparsity-based dictionary. The set of weightings includes a plurality of non-zero weightings. The patches are encoded with the set of weightings to obtain an encoding matrix. The database is searched based on the encoding matrix to retrieve the images corresponding to the query image. The database and the dictionary are dynamically updated to adapt to the query image encountered.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: September 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Katherine Chiang
  • Patent number: 12073556
    Abstract: A defect inspection system may include an information-obtaining module and a defect inspection module. The information obtaining module may be arranged over a transferring apparatus to continuously photograph a surface of a substrate transferred by the transferring apparatus. The defect inspection module may generate an image signal based on information of the substrate provided from the information-obtaining module. The defect inspection module may compare the image signal with a reference to detect a defect of the substrate.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: August 27, 2024
    Assignee: SK hynix Inc.
    Inventor: Jeong Ok Park
  • Patent number: 12061152
    Abstract: Provided are a repair diagram generation device, a repair diagram generation method, and a program which accurately and efficiently generate a repair diagram showing a repair region to be repaired and a repair method from a captured image of a structure. A repair diagram generation device includes an image acquisition unit that acquires a captured image of a structure, a damage detection unit that detects damage from the captured image by image processing and specifies a degree of the damage, a method specifying unit that specifies a repair method of the damage based on the damage and the degree of the damage, and a repair diagram generation unit that generates a repair diagram showing a repair region and the repair method for repairing the damage based on the damage and the repair method.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: August 13, 2024
    Assignee: FUJIFILM Corporation
    Inventor: Shuhei Horita
  • Patent number: 12039716
    Abstract: The purpose of the present invention is to provide a defect inspection device with which it is possible to determine a defect candidate position more accurately than before, even when design data cannot be obtained or are difficult to be utilized sufficiently. The present invention solves the problem by: setting an appropriate reference die or reference chip over a wafer to be inspected; setting, with respect to each of swath channel die images obtained by dividing a reference die swath image into a plurality of portions and detecting the portions, one or more reference patterns; correcting a position error of a swath image obtained from another die to be inspected, using the reference pattern for each swath channel image; and performing defect detection using the corrected swath channel image.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: July 16, 2024
    Assignee: Hitachi High-Tech Corporation
    Inventors: Takashi Hiroi, Takahiro Urano, Nobuaki Hirose
  • Patent number: 12025557
    Abstract: Provided herein are devices, systems, and methods for characterizing a biological sample in vivo or ex vivo in real-time using time-resolved spectroscopy. A light source generates a light pulse or continuous light wave and excites the biological sample, inducing a responsive fluorescent signal. A demultiplexer splits the signal into spectral bands and a time delay is applied to the spectral bands so as to capture data with a detector from multiple spectral bands from a single excitation pulse. The biological sample is characterized by analyzing the fluorescence intensity magnitude and/or decay of the spectral bands. The sample may comprise one or more exogenous or endogenous fluorophore. The device may be a two-piece probe with a detachable, disposable distal end. The systems may combine fluorescence spectroscopy with other optical spectroscopy or imaging modalities. The light pulse may be focused at a single focal point or scanned or patterned across an area.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: July 2, 2024
    Assignees: Black Light Surgical, Inc., Cedars-Sinai Medical Center
    Inventors: Pramod Butte, Keith Black, Jack Kavanaugh, Bartosz Bortnik, Zhaojun Nie
  • Patent number: 12007340
    Abstract: The present invention provides an X-ray CT apparatus capable of obtaining a high-quality X-ray CT image by suppressing occurrence of an artifact. The X-ray CT apparatus including an X-ray imaging system including an X-ray irradiation unit and an X-ray detector, a rotating stage disposed between the X-ray irradiation unit and the X-ray detector, a rotation mechanism configured to relatively rotate the X-ray imaging system and the rotating stage about a rotation axis orthogonal to an optical axis of an X-ray that runs from the X-ray irradiation unit to the X-ray detector, and a load mechanism which is set on the stage and applies test force to a test piece includes an angle changing mechanism that tilts a bending tester to change the direction of the test force applied to the test piece by the bending tester from a direction orthogonal to the optical axis of the X-ray.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: June 11, 2024
    Assignee: SHIMADZU Techno-Research, Inc.
    Inventors: Takashi Nakayama, Atsuhiro Hayashi
  • Patent number: 11996267
    Abstract: A particle beam apparatus includes an object table configured to hold a semiconductor substrate; a particle beam source configured to generate a particle beam; a detector configured to detect a response of the substrate caused by interaction of the particle beam with the substrate and to output a detector signal representative of the response; and a processing unit configured to: receive or determine a location of one or more defect target areas on the substrate; control the particle beam source to inspect the one or more defect target areas; identify one or more defects within the one or more defect target areas, based on the detector signal obtained during the inspection of the one or more defect target areas; control the particle beam source to repair the one or more defects.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: May 28, 2024
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Ruben Cornelis Maas, Alexey Olegovich Polyakov, Teis Johan Coenen
  • Patent number: 11995543
    Abstract: A wafer processing method and apparatus, a storage medium and an electronic device are disclosed, relating to the field of integrated circuit (IC) manufacturing and wafer stacking. The wafer processing method includes: partitioning a target wafer into one or more pre-divided areas each having one or more dies; determining area ratings for each pre-divided area based on test data of the dies in each pre-divided area; and feeding the area ratings of the pre-divided areas to a trained classification model to determine a classification category of the target wafer; identifying a second wafer having a same classification category as the target wafer; and stacking the target wafer with the second wafer. This method improves the production yield of stacked ICs.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: May 28, 2024
    Assignee: Changxin Memory Technologies, Inc.
    Inventor: Xiaodong Pan
  • Patent number: 11982684
    Abstract: Systems, methods and programs are provided for automated science experiments which use a model with learnt model parameters to define points for physical-characteristic measurements once the model is trained. The systems, methods and programs use active learning which enables describing a relationship between local features of sample-surface structure shown in image patches and determined representations of physical-characteristic measurements.
    Type: Grant
    Filed: May 26, 2023
    Date of Patent: May 14, 2024
    Assignee: UT-Battelle, LLC
    Inventors: Maxim A. Ziatdinov, Kevin Roccapriore, Yongtao Liu, Kyle P. Kelley, Rama K. Vasudevan, Jacob D. Hinkle, Sergei V. Kalinin
  • Patent number: 11982623
    Abstract: A method of analysis of defects of a type from among a plurality of types of defects between two samples based on an image of each sample characteristic of a type of defect from among the plurality of types of defects includes: for each sample, creating a minimap including bins and representative of a type of defect whose resolution is less than the image of the sample, each bin of the minimap being associated with pixels of the image of the sample and having a score dependent on the pixels and representative of the quantity of a type of defects; determining the distance between each minimap representing the same type or types of defects, the distance between two minimaps being defined as the minimum distance between two minimaps by considering the following transformations: a rotation and/or a symmetry so that each distance between two minimaps is associated with a transformation.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: May 14, 2024
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Patrick-Jeremy Dahan, Renaud Varache, Wilfried Favre
  • Patent number: 11971331
    Abstract: Provided are a three-dimensional display device, a three-dimensional display method, and a program capable of notifying a user of an event having a causal relationship with a damage. The three-dimensional display device (10) includes a memory (16) that stores a three-dimensional model of a structure, a damage displayed in the three-dimensional model, and an event that has a causal relationship with the damage; a display unit (26); and a processor (20). In the three-dimensional display device (10), the processor (20) causes the display unit (26) to display the three-dimensional model, superimpose the damage on the three-dimensional model and display the damage, and display the event having the causal relationship with the damage.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: April 30, 2024
    Assignee: FUJIFILM Corporation
    Inventor: Kazuma Matsumoto
  • Patent number: 11956396
    Abstract: An information processing apparatus includes a processor configured to evaluate a performance of each of a plural combinations of processes, each combination including a series of processes, the plural combinations being included in plural processes, the series of processes being configured to be performed on an image, the performance being evaluated on a basis of a result of performing the series of processes on a test image for each combination, and output an evaluation result for at least two combinations.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: April 9, 2024
    Assignee: FUJIFILM Business Innovation Corp.
    Inventors: Shusaku Kubo, Junichi Shimizu, Kosuke Tomokuni, Mamiko Sato
  • Patent number: 11949826
    Abstract: An image reading device includes a sensor and circuitry. The sensor reads an image on a recording medium. The circuitry inspects the image and outputs an inspection result. The circuitry excludes an area of the recording medium as a first area from an area to be inspected, based on a type of the recording medium or a position of the recording medium with respect to a reading position at which the sensor reads the image, to determine a second area to be inspected. The circuitry outputs the inspection result based on the second area.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: April 2, 2024
    Assignee: Ricoh Company, Ltd.
    Inventors: Rie Suzuki, Tatsuya Ishii
  • Patent number: 11933717
    Abstract: A metrology system may include a metrology tool to selectively perform metrology measurements in a static mode in which one or more metrology targets on a sample are stationary during a measurement or a scanning mode in which one or more metrology targets are in motion during a measurement, and a controller communicatively coupled to the translation stage and at least one of the one or more detectors. The controller may receive locations of metrology targets on the sample to be inspected, designate the metrology targets for inspection with the static mode or the scanning mode, direct the metrology tool to perform metrology measurements on the metrology targets in the static mode or the scanning mode based on the designation, and generate metrology data for the sample based on the metrology measurements on the metrology targets.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: March 19, 2024
    Assignee: KLA Corporation
    Inventors: Andrew V. Hill, Amnon Manassen, Yoram Uziel, Yossi Simon, Gilad Laredo
  • Patent number: 11922307
    Abstract: With respect to an inference method performed by at least one processor, the method includes inputting, by the at least one processor, into a learned model, non-processed object image data of a second object and data related to a second process for the second object, and inferring, by the at least one processor using the learned model, processed object image data of the second object on which the second process has been performed. The learned model has been trained so that an output obtained in response to non-processed object image data of a first object and data related to a first process for the first object being input approaches processed object image data of the first object on which the first process has been performed.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: March 5, 2024
    Assignees: Preferred Networks, Inc., Tokyo Electron Limited
    Inventors: Kosuke Nakago, Daisuke Motoki, Masaki Watanabe, Tomoki Komatsu, Hironori Moki, Masanobu Honda, Takahiko Kato, Tomohiko Niizeki
  • Patent number: 11923441
    Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-? layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-? layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: March 5, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Steven C. H. Hung, Benjamin Colombeau, Andy Lo, Byeong Chan Lee, Johanes F. Swenberg, Theresa Kramer Guarini, Malcolm J. Bevan
  • Patent number: 11906578
    Abstract: A multispectral inspection (MSI) device for analyzing an electronic item having a printed circuit board (PCB). An electronic power supply powers the electronic item in accordance with one or more test vectors. An optical imaging scanner, terahertz (THz) imaging scanner, and a functional imaging scanner are each operative to scan the electronic item. An electronic processor is programmed to scan the various scanners and control the power supply to acquire optical, THz, and functional images of the electronic item. The images are combined to form a standard three-dimensional (3D) signature and artificial intelligence (AI) classifiers are applied to the 3D signature to perform non-destructive analyses of the electronic item.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: February 20, 2024
    Assignee: BATTELLE MEMORIAL INSTITUTE
    Inventors: Thomas F. Kent, Jeremiah P. Schley, Anthony F. George, Richard J. Higgins, Katie T. Liszewski, David Maung
  • Patent number: 11861286
    Abstract: For each defect in a set of defects, the defect may be associated with a defect attribute constructed from a set of computer-aided design (CAD) identifiers associated with polygons in an integrated circuit (IC) design that overlap with a defect area of the defect. Next, the set of defects may be segregated into defect groups based on the associated defect attributes. The defect groups may be used to perform additional processing on the set of defects.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: January 2, 2024
    Assignee: Synopsys, Inc.
    Inventors: Ankush B. Oberai, Kiran U. Agashe
  • Patent number: 11815470
    Abstract: Disclosed herein is a method for detecting defects on a sample. The method includes obtaining scan data of a region of a sample in a multiplicity of perspectives, and performing an integrated analysis of the obtained scan data. The integrated analysis includes computing, based on the obtained scan data, and/or estimating cross-perspective covariances, and determining presence of defects in the region, taking into account the cross-perspective covariances.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: November 14, 2023
    Assignee: Applied Materials Israel, Ltd.
    Inventors: Haim Feldman, Eyal Neistein, Harel Ilan, Shahar Arad, Ido Almog, Ori Golani
  • Patent number: 11816827
    Abstract: A system for visual inspection, which includes a processor that receives a sensitivity level relating to an image of an item on an inspection line, the image being displayed on the user interface device, and calculates a minimal defect size visible in the image at the received sensitivity level. The calculated minimal defect size is then displayed on a user interface. This visual demonstration of minimal detectable size, which changes as the user changes sensitivity level, enables the user to easily obtain a desired minimal detectable defect size.
    Type: Grant
    Filed: February 14, 2021
    Date of Patent: November 14, 2023
    Assignee: INSPEKTO A.M.V. LTD.
    Inventors: Alexander Spivak, Yonatan Hyatt, Sivan Mottes
  • Patent number: 11789069
    Abstract: Embodiments of the invention include a computer-implemented method that includes controlling, using a processor, a high-resolution optical inspection tool (HROIT) to identify a reference die tamper circuit on a reference die of a wafer; and controlling, using the processor, a low-resolution optical inspection tool (LROIT) to use the reference die tamper circuit to determine that the reference die tamper circuit is on a second die of the wafer.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: October 17, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 11762303
    Abstract: The present application provides a method for improving overlay metrology accuracy of self-aligned multiple patterning, overlay metrology pattern comprising a front layer pattern and a current layer pattern, the front layer pattern comprising a plurality of first grating structures overlaid on the periphery of the current layer pattern, the first grating structure being composed of a plurality of repeatedly arranged strip elements; segmenting the strip element in the first grating structure, so that each of the strip elements forms a sub-grating structure comprising a plurality of repeatedly arranged strip structures; forming a plurality of repeatedly arranged core structures corresponding to the plurality of repeatedly arranged strip structures; form a gate structure comprising a plurality of repeatedly arranged fin structures; removing two outermost fin structures of the gate structure; the gate structure and the current layer pattern structure together forming an overlay metrology structure.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: September 19, 2023
    Assignee: Shanghai Huali Integrated Circuit Corporation
    Inventors: Yuyang Bian, Cong Zhang
  • Patent number: 11763059
    Abstract: A defect map may be created by merging defects at locations on multiple dies that include copies of an integrated circuit (IC). Layout shapes or nets may be determined that overlap with the defects in the defect map. Next, connectivity between the layout shapes or nets may be determined. The defects may then be grouped into defect groups based on the connectivity between the layout shapes or nets, where each defect group comprises defects that overlap with layout shapes or nets that are electrically connected to each other.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: September 19, 2023
    Assignee: Synopsys, Inc.
    Inventors: Ankush Bharati Oberai, Rajesh Ramesh Sahani
  • Patent number: 11756188
    Abstract: Input data may be received. The input data may include an image of a pattern and location data that identifies a modified portion of the pattern. A processing device may determine a first parameter of a first dimension within the pattern and a second parameter of a second dimension outside of the pattern. A combined set may be generated based on the first parameter and the second parameter. A defect associated with the modified portion may be classified based on the combined set.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: September 12, 2023
    Assignee: Applied Materials Israel Ltd.
    Inventors: Vadim Vereschagin, Roman Kris, Ishai Schwarzband, Boaz Cohen, Evgeny Bal, Ariel Shkalim
  • Patent number: 11741596
    Abstract: A semiconductor wafer fault analysis system includes: a database to store a first reference map, which is classified as a first fault type, and a second reference map, which is classified as a second fault type; a first auto-encoder/decoder to remove a noise corresponding to the first fault type from the first reference map to generate a first pre-processed reference map; a second auto-encoder/decoder to remove a noise corresponding to the second fault type from the second reference map to generate a second pre-processed reference map; and a fault type analyzer. The database is updated based on the first and second pre-processed reference maps, and the fault type analyzer is to classify a fault type of a target map based on the updated database. The target map is generated by measuring a target wafer.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: August 29, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Chul Park, Ami Ma, Jisu Ryu, Changwook Jeong
  • Patent number: 11726438
    Abstract: This method includes a step of imaging, by an imaging apparatus in a substrate treatment system, a reference substrate which is a reference for condition setting and acquiring a captured image of the reference substrate; and a step of imaging, by the imaging apparatus, a treated substrate on which the predetermined treatment has been performed under a current treatment condition and acquiring a captured image of the treated substrate. A deviation amount in color information between the captured image of the treated substrate and the captured image of the reference substrate is calculated. A correction amount of the treatment condition is calculated based on a correlation model acquired in advance and on the deviation amount in the color information. Also included is a step of setting the treatment condition based on the correction amount and performing the treatment on a target substrate based on the set treatment condition.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: August 15, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Takuya Mori, Tadashi Nishiyama, Akiko Kiyotomi, Hiroshi Tomita
  • Patent number: 11727557
    Abstract: A defect inspecting apparatus includes a reference image generator configured to generate a first reference image and a second reference image from design layout data. An image inspector is configured to obtain a first inspection image of a first inspection region of a photomask and a second inspection image of a second inspection region of the photomask. An operation processor is configured to extract a first coordinate offset by comparing the first inspection image with the first reference image and to extract a second coordinate offset by comparing the second inspection image with the second reference image.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: August 15, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kang Won Lee, Cheol Ki Min, Jong Ju Park, Hyon Seok Song
  • Patent number: 11719533
    Abstract: A method for imaging overlay targets on a wafer includes (1) using a sensor to acquire images of overlay targets on a wafer while the wafer is in motion and (2) accelerating and decelerating the wafer to move the overlay targets into alignment with the sensor between acquiring images of the overlay targets. Accelerating/decelerating the wafer may include: (1) accelerating the wafer at a maximum acceleration and then decelerating the wafer at a maximum deceleration, (2) accelerating/decelerating the wafer in a triangular waveform pattern, (3) accelerating/decelerating the wafer in a sinusoidal pattern, or (4) accelerating/decelerating the wafer in a near-sinusoidal pattern (created by combining a pure sinusoidal profile with one or more harmonic profiles). A system is also provided for implementing the above method(s).
    Type: Grant
    Filed: March 28, 2021
    Date of Patent: August 8, 2023
    Assignee: KLA Corporation
    Inventors: David L. Brown, Andrew V. Hill, Amnon Manassen
  • Patent number: 11695880
    Abstract: An information processing method including: acquiring a superimposed image in which electronic information corresponding to an image of an object captured by an image capturing unit of an information processing apparatus is superimposed on the image; storing the superimposed image in a storage; and displaying the superimposed image stored in the storage on a display of the information processing apparatus, and even in a case where the object is not included in an image capturing range of the image capturing unit, the superimposed image stored in the storage is displayed on the display.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: July 4, 2023
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yuka Katahira
  • Patent number: 11657534
    Abstract: To provide a novel and improved information processing device that can make more efficient an inspection performed by a flying body capable of performing imaging. Provided is an information processing device including an imaging position information acquisition unit configured to acquire imaging position information at a time when a structure is imaged which is acquired by an imaging device configured to fly over a periphery of die structure to image the structure on the basis of certain flight information, and a damage data generating unit configured to use a captured image of the structure imaged by the imaging device and the imaging position information and to generate data related to damage of the structure including position information of damage of the structure included in the captured image.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: May 23, 2023
    Assignee: SONY GROUP CORPORATION
    Inventors: Kayoko Tanaka, Kohtaro Sabe, Tsutomu Sawada, Satoru Shimizu, Kousuke Suzuki, Peter Duerr, Miki Shibuya, Hironari Mizumura
  • Patent number: 11651482
    Abstract: Method for obtaining at least one significant feature in a series of components of the same type on the basis of data sets by non-destructive testing. The method includes examining a classified random sample of components which have a known production sequence, by a non-destructive testing. A three-dimensional data set for each component is obtained, and components of the sample are divided by good and rejected parts. Defect-free component regions from all of the components of the random sample are extracted. At least one feature which is characteristic of the type of component and production process which, over a predetermined time of component production, exhibits considerable characteristic differences between the good and rejected parts is determined. The determination can be accomplished using neural networks, machine learning approaches, or statistics from the field of data analytics. The at least one feature and its characteristic is defined as a trained classifier.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: May 16, 2023
    Assignee: YXLON INTERNATIONAL GMBH
    Inventors: Thomas Wenzel, Jeremy Simon
  • Patent number: 11645774
    Abstract: An image processing apparatus comprises: an obtaining unit configured to obtain an image and distance information concerning a distance from an in-focus plane, which corresponds to each pixel included in the image; a setting unit configured to set an image processing condition according to the distance information based on an output characteristic of an output apparatus concerning a sharpness; and a processing unit configured to perform image processing for the image using the distance information obtained by the obtaining unit and the image processing condition set by the setting unit, wherein the processing unit changes, in accordance with the distance information, a band of a spatial frequency of the image to which the image processing is applied.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: May 9, 2023
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shinichi Miyazaki, Maya Yazawa, Hidetsugu Kagawa
  • Patent number: 11636579
    Abstract: An information processing method includes obtaining information on a deformation factor of a surface of a target substrate; obtaining a surface image of the target substrate; calculating a correction coefficient for correcting an image change due to deformation of the surface, based on the information on the deformation factor of the surface; and generating a corrected image of the target substrate by correcting the surface image of the target substrate using the correction coefficient.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: April 25, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Toyohisa Tsuruda, Masato Hosaka
  • Patent number: 11631245
    Abstract: Apparatus and methods for a smart glasses device are provided. The smart glasses device may execute a prediction model on video data captured by the smart glasses device to retrain the prediction model. The prediction model may be retrained in response to a data synchronization between an output of the prediction model and a gesture captured by the smart glasses device.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: April 18, 2023
    Assignee: Bank of America Corporation
    Inventors: Sandeep Verma, Shailendra Singh, Divya Sharma, Nandini Rathaur