Applying Superposed Diverse Coatings Or Coating A Coated Base Patents (Class 427/103)
  • Publication number: 20140375417
    Abstract: A tunable resistance system includes a layer of a first functional material deposited on a component of the system. The first functional material undergoes a phase transition at a first critical voltage. An insulating layer is deposited upon the layer of first functional material. A layer of a second functional material deposited on the insulating layer. The second functional material undergoes a phase transition at a second critical voltage. The insulating layer is configured to induce a stress on the layer so as to change the first critical voltage. In this way, the resistance of the system is tunable, allowing the system to undergo multi-stage electrical switching of resistive states.
    Type: Application
    Filed: February 6, 2013
    Publication date: December 25, 2014
    Applicant: PRESIDENT AND FELLOWS OF HARVARD COLLEGE
    Inventors: You Zhou, Zheng Yang, Shriram Ramanathan
  • Publication number: 20140361864
    Abstract: To provide a resistance change device that can be protected from an excess current without enlarging a device size. A resistance change device 1 according to the present embodiment includes a lower electrode layer 3, an upper electrode layer 6, a first metal oxide layer 51, a second metal oxide layer 52, and a current limiting layer 4. The first metal oxide layer 51 is disposed between the lower electrode layer 3 and the upper electrode layer 6, and has a first resistivity. The second metal oxide layer 52 is disposed between the first metal oxide layer 51 and the upper electrode layer 6, and has a second resistivity higher than the first resistivity. The current limiting layer 4 is disposed between the lower electrode layer 3 and the first metal oxide layer 51, and has a third resistivity higher than the first resistivity and lower than the second resistivity.
    Type: Application
    Filed: August 27, 2013
    Publication date: December 11, 2014
    Inventors: Natsuki Fukuda, Kazunori Fukuju, Yutaka Nishioka, Koukou Suu
  • Patent number: 8815332
    Abstract: An apparatus, comprising two conductive surfaces or layers and a nanostructure assembly bonded to the two conductive surfaces or layers to create electrical or thermal connections between the two conductive surfaces or layers, and a method of making same.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: August 26, 2014
    Assignee: Smoltek AB
    Inventors: Mohammad Shafiqul Kabir, Andrzej Brud
  • Publication number: 20130335191
    Abstract: A chip resistor includes an insulating substrate, top terminal electrodes formed on top surface of the substrate using silver-based cermet, bottom electrodes, resistive element that is situated between the top terminal electrodes and overlaps them partially, an optional internal protective coating that covers resistive element completely or partially, an external protective coating that covers completely the internal protection coating and partially covers top terminal electrodes, a plated layer of nickel that covers face sides of the substrate, top and bottom electrodes, and overlaps partially external protective coating, finishing plated layer that covers nickel layer. The overlap of nickel layer and external protective layer possesses a sealing property because of metallization of the edges of external protective layer prior to the nickel plating process.
    Type: Application
    Filed: August 19, 2013
    Publication date: December 19, 2013
    Applicant: Vishay Intertechnology, Inc.
    Inventors: Michael Belman, Leonid Akhtman
  • Publication number: 20130280546
    Abstract: A method and article of manufacture of intermixed tunable resistance composite materials containing at least one of W:Al2O3, Mo:Al2O3 or M:Al2O3 where M is a conducting compound containing either W or Mo. A conducting material and an insulating material are deposited by such methods as ALD or CVD to construct composites with intermixed materials which do not have structure or properties like their bulk counterparts.
    Type: Application
    Filed: March 14, 2013
    Publication date: October 24, 2013
    Inventors: Jeffrey W. Elam, Anil U. Mane
  • Publication number: 20130210679
    Abstract: The present invention relates to method for preparing a metal nanoparticle organic composite film, preferably a metal nanoparticle organic composite film of a chemical sensing device, to a metal nanoparticle organic composite film obtained by said method, and to a chemical sensing device comprising a metal nanoparticle organic composite film or an array of different metal nanoparticle organic composite films obtained by said method.
    Type: Application
    Filed: August 16, 2012
    Publication date: August 15, 2013
    Applicant: Sony Corporation
    Inventors: Yvonne JOSEPH, Isabelle Raible, Nadejda Krasteva, Gabriele Nelles
  • Publication number: 20130127588
    Abstract: An ultra wideband frequency compensated resistor and related methodologies for frequency compensation are disclosed. In exemplary configuration, a resistive layer is provided over a substrate, and a frequency compensating structure is provided over at least a portion of the resistive layer and separated therefrom by an insulative layer. In certain embodiments, the insulating layer may be an adhesive that may also be effective to secure a protective cover over the resistive material and supporting substrate. In selected embodiments, the frequency compensating structure corresponds to a plurality of conductive layers, one or more of which may be directly electrically connected to terminations for the resistive material while one or more of the conductive layers are not so connected.
    Type: Application
    Filed: October 4, 2012
    Publication date: May 23, 2013
    Applicant: AVX Corporation
    Inventor: AVX Corporation
  • Publication number: 20130127587
    Abstract: A co-fired multi-layer stack chip resistor is provided. The co-fired multi-layer stack chip resistor includes a ceramic substrate and a multi-layer stack resistance structure monomer. The ceramic substrate is formed by stacking multiple layers of the ceramic membranes, wherein the ceramic membranes is formed of a bearing membrane and a porcelain slurry with the solvent, the binder and the dispersant. The multi-layer stack resistance structure monomer is stacked on the ceramic substrate, and includes multiple bearing membranes and multiple resistive layers, wherein each resistive layer is formed on the surface of the corresponding bearing membrane, the resistive layers are parallel to each other, and the contiguous resistive layers are stacked with the interval of the predetermined distance along the vertical direction.
    Type: Application
    Filed: June 21, 2012
    Publication date: May 23, 2013
    Applicant: PROSPERITY DIELECTRICS CO., LTD.
    Inventors: YUNG CHENG TSAI, CHING JEN TSAI, TUNG YI CHOU, HUNG CHUN WU
  • Publication number: 20130089675
    Abstract: Plasma nitridation, in place of plasma oxidation, is used for the formation of a CCP layer. Al, Mg, Hf, etc. all form insulating nitrides under these conditions. Maintaining the structure at a temperature of at least 150° C. during plasma nitridation and/or performing post annealing at a temperature of 220° C. or higher, ensures that no copper nitride can form.
    Type: Application
    Filed: December 1, 2012
    Publication date: April 11, 2013
    Applicant: HEADWAY TECHNOLOGIES, INC.
    Inventor: HEADWAY TECHNOLOGIES, INC.
  • Publication number: 20120126934
    Abstract: A chip resistor includes an insulating substrate 11, top terminal electrodes 12 formed on top surface of the substrate using silver-based cermet, bottom electrodes 13, resistive element 14 that is situated between the top terminal electrodes 12 and overlaps them partially, an optional internal protective coating 15 that covers resistive element 14 completely or partially, an external protective coating 16 that covers completely the internal protection coating 15 and partially covers top terminal electrodes 12, a plated layer of nickel 17 that covers face sides of the substrate, top 12 and bottom 13 electrodes, and overlaps partially external protective coating 16, finishing plated layer 18 that covers nickel layer 17. The overlap of nickel layer 17 and external protective layer 16 possesses a sealing property because of metallization of the edges of external protective layer 16 prior to the nickel plating process.
    Type: Application
    Filed: July 18, 2011
    Publication date: May 24, 2012
    Applicant: VISHAY INTERTECHNOLOGY, INC.
    Inventors: Michael Belman, Leonid Akhtman
  • Publication number: 20120129007
    Abstract: The free layer of a CPP-TMR sensor is biased by laterally disposed hard bias (HB) layers that include a seedlayer structure, a magnetic layer structure of high coercivity material and a capping layer structure. The magnetic layer structure is a layer of FePt-containing material, such as FePtCu, while the seedlayers and capping layers include layers of Cr, CrTi, Fe, FeCo or FeCoMo. These combinations enable the promotion of the L10 phase of the FePt-containing material which provides a high coercivity magnetic layer structure at much lower annealing temperatures than in the prior art.
    Type: Application
    Filed: November 22, 2010
    Publication date: May 24, 2012
    Inventors: Min Zheng, Kunliang Zhang, Min Li
  • Publication number: 20120112873
    Abstract: A process is described for integrating two closely spaced thin films without deposition of the films through deep vias. The films may be integrated on a wafer and patterned to form a microscale heat-trimmable resistor. A thin-film heating element may be formed proximal to a thin-film resistive element, and heat generated by the thin-film heater can be used to permanently trim a resistance value of the thin-film resistive element. Deposition of the thin films over steep or abrupt topography is minimized by using a process in which the thin films are deposited in a sequence that falls between depositions of thick metal contacts to the thin films.
    Type: Application
    Filed: December 29, 2011
    Publication date: May 10, 2012
    Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics Pte Ltd., STMicroelectronics S.r.I.
    Inventors: Olivier Le Neel, Stefania Maria Serena Privitera, Pascale Dumont-Girard, Maurizio Gabriele Castorina, Calvin Leung
  • Publication number: 20110274831
    Abstract: A manufacturing method of an electronic part (varistor 2) whose device 4 is covered by an outer cover material 6, including the steps of: forming a first outer cover film 8 by coating and fixing a first outer cover film liquid material 30 that includes an organic solvent, on the device 4; and forming a second outer cover film 10 by coating and fixing a second outer cover film liquid material 34, on the first outer cover film 8. The first outer cover film includes a silicone resin or a silicone elastomer, and one or more kind (s) of aluminum hydroxide, magnesium hydrate, or calcium hydrate at a weight ratio ranging from 45/55 to 5/95.
    Type: Application
    Filed: February 15, 2010
    Publication date: November 10, 2011
    Applicant: NIPPON CHEMI-CON CORPORATION
    Inventors: Kazuhiro Saegusa, Sinya Satou, Shogo Aizawa
  • Patent number: 8029860
    Abstract: A manufacturing method for a nozzle plate including a plurality of nozzle holes may include the step of forming a plurality of through-holes extending through a plate member in a thickness direction of the plate member. The manufacturing method may also include the step of forming a water repellant film in a region of one surface of the plate member where apertures of the through-holes are not positioned. The manufacturing method may further include the step of pressing individual regions on the one surface of the plate member, the individual regions respectively including the apertures of the through holes, to separate at least portions of the water repellant film formed in the individual regions from the water repellant film formed on the one surface.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: October 4, 2011
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Yasunori Kobayashi
  • Publication number: 20110032645
    Abstract: The present invention is directed to align crystal c-axes in magnetic layers near two opposed junction wall faces of a magnetoresistive element so as to be almost perpendicular to the junction wall faces. A magnetic sensor stack body has, on a substrate, a magnetoresistive element whose electric resistance fluctuates when a bias magnetic field is applied and, on sides of opposed junction wall faces of the magnetoresistive element, field regions including magnetic layers for applying the bias magnetic field to the element. The magnetoresistive element has at least a ferromagnetic stack on a part of an antiferromagnetic layer, and width of an uppermost face of the ferromagnetic stack along a direction in which the junction wall faces are opposed to each other is smaller than width of an uppermost face of the antiferromagnetic layer in the same direction.
    Type: Application
    Filed: August 4, 2010
    Publication date: February 10, 2011
    Applicant: Canon Anelva Corporation
    Inventors: Abarra Einstein NOEL, Masahiro Suenaga, Yoshinori Ota, Tetsuya Endo
  • Patent number: 7632537
    Abstract: A process is disclosed for manufacturing a thick-film circuit such as a hybrid circuit on a titanium or titanium-alloy substrate. The process includes firing a glassy dielectric layer upon at least one surface of the substrate. A thick-film circuit including a titanium or titanium-alloy substrate is also disclosed.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: December 15, 2009
    Assignee: Hybird Electronics Australia Pty Ltd.
    Inventor: Walter Henry Berryman
  • Publication number: 20090206982
    Abstract: A thin-film resistor with a layer structure with a Ti layer and a TiN layer is described, wherein a layer thickness of the Ti layer and a layer thickness of the TiN layer are selected such that a resulting temperature coefficient of resistance (TCR) is smaller than 1000 ppm/° C.
    Type: Application
    Filed: December 9, 2005
    Publication date: August 20, 2009
    Applicant: UNIVERSITAET DUISBURG-ESSEN
    Inventors: Heinz Deiters, Susanne Linnenberg, Dirk Nachrodt, Uwe Paschen, Holger Vogt
  • Patent number: 7528350
    Abstract: The present invention provides a novel method for electrical connection between a polymer PTC device and a metal lead element to thereby prevent the problems of the connection by caulking or soldering. For this purpose, the present invention provides a process for producing a connection structure by laser welding, said connection structure having (A) a PTC device (10) including (i) a laminar polymer PTC element (12) and (ii) a metal foil electrode (14) disposed on a main surface of the laminar polymer PTC element (12), and (B) a metal lead element (20) electrically connected to the metal foil electrode. The metal foil electrode (14) has at least two metal layers, one of which, the X-th layer, has laser beam absorption a % that is the lowest among the metal layers of the metal foil electrode (14). The X-th layer is present between a first metal layer (18) of the metal foil electrode and the laminar polymer PTC element (12).
    Type: Grant
    Filed: September 3, 2003
    Date of Patent: May 5, 2009
    Assignee: Tyco Electronics Raychem KK
    Inventors: Atsushi Nakagawa, Arata Tanaka, Mikio Iimura
  • Patent number: 7326889
    Abstract: A method of manufacturing a PTC element comprising a pair of lead terminals bonded together by thermocompression with a matrix held therebetween comprises a matrix preparing step of preparing a matrix constructed by dispersing a conductive filler into a crystalline polymer; a terminal preparing step of preparing a pair of lead terminals holding the matrix therebetween, a surface of each lead terminal facing the matrix being formed with a plurality of anchor protrusions separated from each other; a flattening step of flattening the anchor protrusions formed in respective nonoverlapping areas in the pair of lead terminals kept from overlapping the matrix; and a thermocompression bonding step of holding the matrix between respective overlapping areas in the pair of lead terminals overlapping the matrix, and securing the pair of lead terminals and the matrix together by thermocompression bonding.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: February 5, 2008
    Assignee: TDK Corporation
    Inventors: Hisanao Tosaka, Tokuhiko Handa, Hirokazu Satoh, Tsutomu Hatakeyama
  • Patent number: 7214295
    Abstract: The present invention discloses a method of manufacturing a thin film resistor with a moisture barrier by depositing a metal film layer on a substrate and depositing a layer of tantalum pentoxide film overlaying the metal film layer. The present invention also includes a thin film resistor having a substrate; a metal film layer attached to the substrate; and a tantalum pentoxide layer overlaying the metal film layer, the tantalum pentoxide layer providing a barrier to moisture, the tantalum pentoxide layer not overlaid by an oxidation process.
    Type: Grant
    Filed: April 9, 2001
    Date of Patent: May 8, 2007
    Assignee: Vishay Dale Electronics, Inc.
    Inventor: Stephen C. Vincent
  • Patent number: 7008565
    Abstract: A method of preparing an electroconductive foam, and the foam so prepared. An electroconductive polymer such as polyaniline is dispersed in a liquid medium that includes an aromatic solvent such as xylene and an organic dopant/dispersant such as an aromatic sulfonic acid. The electroconductive polymer together with the organic dopant/dispersant constitute between 10% and 25% of the resulting dispersion. The dispersion is introduced to the pores of an electrically insulating foam matrix such as polyurethane. Excess dispersion is expelled and the foam is dried actively, to line the pores with an electroconductive lining.
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: March 7, 2006
    Assignee: More Energy Ltd.
    Inventors: Alexander Osherov, Leonid Sklyarski, Ilya Glants, Yuri Katsman
  • Patent number: 6995984
    Abstract: The invention relates to an electronic assembly, in particular for low power consumption electric switching devices such as low power contactors, time relays or the like. In order to provide protection against input current pulses, an ohmic resistor (6) is provided in the form of a resistive layer that is applied by pressing.
    Type: Grant
    Filed: June 30, 2001
    Date of Patent: February 7, 2006
    Assignee: Moeller GmbH
    Inventor: Gerd Schmitz
  • Patent number: 6935023
    Abstract: A method of forming an electrical connection for a fluid ejection device including a fluid channel communicating with a first side and a second side of the fluid ejection device and an array of drop ejecting elements formed on the first side of the fluid ejection device includes forming a trench in the second side of the fluid ejection device, depositing a conductive material in the trench, forming a first opening in the fluid ejection device between the first side of the fluid ejection device and the conductive material in the trench, depositing a conductive material in the first opening, and forming a conductive path between the conductive material in the first opening and a wiring line of one of the drop ejecting elements.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: August 30, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Timothy E. Beerling, Timothy L. Weber, Melissa D. Boyd
  • Patent number: 6882509
    Abstract: Disclosed is a method of making a SVGMR sensor element. In the first embodiment a buffer layer is formed between a seed layer and a ferromagnetic (FM) free layer, the buffer layer being composed of alpha-Fe2O3 having a crystal lattice constant that is close to the FM free layer's crystal constant and has the same crystal structure. The metal oxide buffer layer enhances the specular scattering. In the second embodiment, a high conductivity layer (HCL) is formed over the buffer layer to create a spin filter-SVGMR. The HCL layer enhances the GMR ratio of the spin filter SVGMR. The third embodiment include a pinned FM layer comprising a three layer structure of a lower AP layer, a space layer (e.g., Ru) and an upper AP layer.
    Type: Grant
    Filed: March 2, 2004
    Date of Patent: April 19, 2005
    Assignee: Headway Technologies, Inc.
    Inventors: Jei-Wei Chang, Bernard Dieny, Mao-Min Chen, Cheng T. Horng, Kochan Ju, Simon Liao
  • Patent number: 6824814
    Abstract: A method of forming a perovskite thin film includes preparing a perovskite precursor solution; preparing a silicon substrate for deposition of a perovskite thin film, including forming a bottom electrode on the substrate; securing the substrate in a spin-coating apparatus and spinning the substrate at a predetermined spin rate; injecting a perovskite precursor solution into the spin-coating apparatus thereby coating the substrate with the perovskite precursor solution to form a coated substrate; baking the coated substrate at temperatures which increase incrementally from about 90° C. to 300° C.; and annealing the coated substrate at a temperature of between about 500° C. to 800° C. for between five minutes to fifteen minutes.
    Type: Grant
    Filed: May 21, 2002
    Date of Patent: November 30, 2004
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Wei-Wei Zhuang, Sheng Teng Hsu, Wei Pan, Masayuki Tajiri
  • Patent number: 6808740
    Abstract: A magnetoresistance effect film includes a substrate, a plurality of ferromagnetic particles disposed on the substrate, a nonmagnetic film deposited on the substrate and covering the plurality of ferromagnetic particles, and a pair of electrodes arranged on the nonmagnetic film, in which the resistance across the pair of electrodes is changed by applying a magnetic field. The magnetoresistance effect film is manufactured by vapor-depositing ferromagnetic particle starting material on a substrate at a temperature not exceeding 300° C., the starting material being vapor-deposited in an amount enough to cover the substrate surface to a thickness ranging from 0.5 to 15 nm, and, after formation of ferromagnetic particles on the substrate, vapor-depositing at a temperature not exceeding room temperature a nonmagnetic film over the ferromagnetic particles, the nonmagnetic film having a thickness ranging from 1 to 100 nm, and providing a pair of electrodes each at a predetermined position on the nonmagnetic film.
    Type: Grant
    Filed: June 17, 2003
    Date of Patent: October 26, 2004
    Assignees: National Institute of Advanced Industrial Science and Technology, Hiroyuki Akinaga
    Inventors: Hiroyuki Akinaga, Masaharu Oshima, Masaki Mizuguchi
  • Patent number: 6711807
    Abstract: The present invention provides a method of manufacturing a composite array structure that comprises a plurality of elements of an electrically conductive composite material interconnected by at least one region of an electrically insulating material. The method comprises forming regions of the electrically insulating material around regions of the electrically conductive material such that at least a surface of the regions of the electrically insulating material is below a surface of the regions of the electrically conductive material.
    Type: Grant
    Filed: November 5, 2002
    Date of Patent: March 30, 2004
    Assignee: General Electric Company
    Inventors: Anil Raj Duggal, Minyoung Lee, Lionel Monty Levinson
  • Patent number: 6699521
    Abstract: A method of fabricating an uncooled ferroelectric/pyroelectric infrared detector having a semi-transparent electrode material includes using a lattice matched substrate material and a crystallographically oriented bottom electrode material as a template for the growth of a crystallographically oriented ferroelectric/pyroelectric film. In a second preferred embodiment, the method includes fabricating a detector assembly, inverting the assembly, and attaching the inverted assembly to a circuit. This embodiment avoids temperature processing constraints associated with the circuit, and thus facilitates the use of higher growth temperatures. Advantages associated with the embodiments of the present invention include the ability to fabricate a crystallographically oriented bottom electrode material as a template for the growth of a crystallographically oriented ferroelectric/pyroelectric film. Furthermore, once the fabrication is complete, the substrate upon which the electrode is deposited can be easily removed.
    Type: Grant
    Filed: April 17, 2000
    Date of Patent: March 2, 2004
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Steven Tidrow, Meimei Tidrow
  • Patent number: 6663793
    Abstract: The present invention relates to a method for producing a low temperature 0-3 composite material, comprising the steps of providing a mixture, wherein the mixture comprises a liquid phase and a particulate phase and wherein the liquid phase comprises a reactive metal alkoxide; depositing the mixture on to a plastic substrate; and consolidating the mixture to provide a 0-3 composite material, wherein the 0-3 composite material is suitable for use as an electronic component.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: December 16, 2003
    Assignee: Sciperio, Inc.
    Inventors: Robert L. Parkhill, Steven M. Coleman, Edward T. Knobbe
  • Patent number: 6568265
    Abstract: A humidity sensor includes a pair of interdigital electrodes disposed on an insulating substrate and defining a gap therebetween, an undercoat layer of silane compound lying on the gap-defining electrodes and substrate, and a humidity sensitive thin film lying thereon. The humidity sensitive thin film is formed of a crosslinked product of a conductive polymer having ethylenically unsaturated groups, and physically bound to the undercoat layer through an interpenetrating polymer network. The sensor is fully resistant to water so that it ensures stable operation over a long time even in a dew condensing atmosphere. The sensor is free of hysteresis and able to measure humidity over a very wide range.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: May 27, 2003
    Assignee: TDK Corporation
    Inventors: Akira Shibue, Kenryo Namba
  • Publication number: 20020058104
    Abstract: A pointing stick includes a substrate, an input pillar set vertically on the substrate, and at least one strain gauge for sensing pressure and producing pointing signals corresponding to the pressure. A portion of the strain gauge is set between the input pillar and the substrate. The strain gauge includes a first pressure resistor set on an upper surface of the substrate. A first electrode and a second electrode are electrically connected to the first pressure resistor. The first electrode and the second electrode form a loop to let current pass through the first pressure resistor. The first electrode and the second electrode are separated by a gap with a predetermined distance in a pressing direction, which is perpendicular to the surface of the substrate.
    Type: Application
    Filed: April 25, 2001
    Publication date: May 16, 2002
    Inventor: Wei-Ting Chen
  • Patent number: 6317023
    Abstract: The invention is directed to a method of embedding thick film passive components on an organic substrate wherein a flexible metallic substrate has a conductive paste underprint applied thereon. The method comprises the following steps: applying a conductor paste underprint onto a flexible metallic substrate; firing the preceding article; applying at least one passive component paste onto the underprint; firing the preceding article; and applying the passive component side of the metallic substrate onto at least one side of an organic layer which is at least partially coated with an adhesive layer wherein the passive component side of the article is embedded into the adhesive layer.
    Type: Grant
    Filed: October 15, 1999
    Date of Patent: November 13, 2001
    Assignee: E. I. du Pont de Nemours and Company
    Inventor: John James Felten
  • Patent number: 6315853
    Abstract: A method for manufacturing an ink jet recording head by combining each of the processes to fabricate a heater board comprises (I) the first step of patterning a resistive layer on a substrate, (II) the second step of laminating a first protection layer and patterning the protection layer to form a groove by removing an area for wiring electrode layers to be formed later, (III) the third step of laminating a layer formed by material for use of the wiring electrode layers, (IV) the forth step of continuously giving heat treatment to the surface of the substrate, while the surface is not allowed to be exposed to the air outside, to enable the layer formed by the material of the wiring electrode layers to flow into only the groove on the first protection layer provided in the first step, and making the surface flat, as a result of which, a pair of electrode layers are formed to enable the resistive layer between them to be constituted as the heat generating unit and (V) the fifth step of forming a second protecti
    Type: Grant
    Filed: October 15, 1996
    Date of Patent: November 13, 2001
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masahiko Kubota, Masami Kasamoto, Toshihiro Mori, Teruo Ozaki
  • Patent number: 6309695
    Abstract: This invention particularly relates to a thick film resistor and a process for the preparation of said thick firm resistor useful for making strain gauge with enhanced gauge factor upto 1000. The thick film resistor of the present invention is obtained by inducing the strain sensitivity in thick film resistor after its fabrication on substrate by coating it with a formulation capable of gauge factor enhancement and subjecting it to high temperature in furnace. The usage of thick film resistor have industrial applications such as hybrid circuit and thermistors etc.
    Type: Grant
    Filed: April 26, 1999
    Date of Patent: October 30, 2001
    Assignee: Council of Scientific & Industrial Research of Rafi Marg
    Inventor: Awatar Singh
  • Patent number: 6303192
    Abstract: A method for making a multi-layered integrated circuit structure, includes depositing a methyl compound spin on glass layer over a substrate. The spin on glass layer is treated by plasma-deposition to form a SiO2 skin on the methyl compound spin on glass layer and then treated again by plasma-deposition to form a cap layer which adheres to the SiO2 skin.
    Type: Grant
    Filed: July 22, 1998
    Date of Patent: October 16, 2001
    Assignee: Philips Semiconductor Inc.
    Inventors: Rao V. Annapragada, Tekle M. Tafari, Subhas Bothra
  • Patent number: 6272736
    Abstract: A method for forming a thin-film resistor includes forming two insulators on the thin-film resistor, forming contact holes by performing wet etching processes, and forming interconnect and contact plugs at the same time. The invention also provides another method for forming a thin-film resistor that forms a thin-film resistor over the passivation layer instead. That is, forming a thin-film resistor on the top of the device, so that the resistance can be re-modified according to the actual needs.
    Type: Grant
    Filed: November 13, 1998
    Date of Patent: August 14, 2001
    Assignee: United Microelectronics Corp.
    Inventor: Jia-Sheng Lee
  • Patent number: 6269534
    Abstract: A method for producing an electric resistor, in particular a resistance strain gauge, in which an insulating layer and a resistive layer are sequentially applied to a carrier element. The insulating layer or the resistive layer is applied to a backing sheet, the side of the backing sheet carrying the insulating or resistive layer being covered with a flexible film layer whose adhesion to the insulating layer or resistive layer is stronger than the adhesion of the backing sheet to the insulating layer or resistive layer. The film layer with the insulating or resistive layer is peeled off of the adhesive backing sheet and applied to a carrier element, which is heated to burn off the film layer and sinter on the insulating or resistive layer.
    Type: Grant
    Filed: December 3, 1998
    Date of Patent: August 7, 2001
    Assignee: Mannesmann VDO AG
    Inventors: Erich Mattmann, Klaus Weber
  • Publication number: 20010010832
    Abstract: A method for forming a resistor on a roughened surface for use in process fluids employed in the semiconductor-processing industry as part of a clean, particle-free, nonreactive, non-trapping, ultra-pure, thermally tolerant, sealed system. In one arrangement, the method for forming the resistor includes the steps of selecting a coating for the roughened surface from among the group of resistive materials, roughening a surface to promote mechanical adherence of the coating to the selection of a coating comprising resistive material, roughening a surface for promoting mechanical adherence of the resistive material thereto, and electroplating the resistive material onto the roughened surface to provide a uniformly controllable resistance in the coating.
    Type: Application
    Filed: January 30, 2001
    Publication date: August 2, 2001
    Inventor: Steven A. Black
  • Patent number: 6238741
    Abstract: A process of forming a multi-layer feature on a ceramic or organic article in which first and second layers of paste are sequentially screened through a screening mask wherein the screening mask has not been moved between screening steps. A structure produced by this process is also disclosed.
    Type: Grant
    Filed: December 7, 1998
    Date of Patent: May 29, 2001
    Assignee: International Business Machines Corporation
    Inventors: James M. Blazick, Michael E. Cropp, James N. Humenik, Gerald H. Leino, Jawahar P. Nayak, Frank V. Ranalli, Deborah A. Sylvester, John A. Trumpetto, James C. Utter, Rao V. Vallabhaneni, Renee L. Weisman
  • Patent number: 6232144
    Abstract: A method of providing nickel barrier end terminations for a zinc oxide semiconductor device with exposed body surfaces and end terminal regions, in which the device is controllably reacted with a nickel plating solution only on an exposed end terminal region and thereafter provided with a final tin or tin-lead termination.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: May 15, 2001
    Assignee: Littelfuse, Inc.
    Inventor: Neil McLoughlin
  • Patent number: 6187372
    Abstract: A method for creating large area, thick film resistors with improved predictability and uniformity. “Tent poles” are employed during the printing of the large area resistors to prop up the screen mesh to ensure the resultant resistor does not have a scooped out center portion. The tent poles can be made from gold pads, resistor spots or emulsion spots.
    Type: Grant
    Filed: April 29, 1999
    Date of Patent: February 13, 2001
    Assignee: Agilent Technologies, Inc.
    Inventors: Rosemary O Johnson, John F Casey, Lewis R Dove
  • Patent number: 6180164
    Abstract: A method for forming a ruthenium-based thick-film resistor having copper terminations, in which the thick-film resistor is fired in a non-oxidizing atmosphere so as not to oxidize the copper terminations yet without reducing the thick-film resistor to metallic ruthenium. A ruthenium-based thick-film resistor ink having a matrix material and an organic vehicle is deposited on a copper layer that will form the terminations for the thick-film resistor formed by firing the ink. The organic vehicle of the ink is then burned out at a temperature of less than 350° C. in an oxidizing atmosphere, such as air. Thereafter, the ink is fired in a non-oxidizing atmosphere (e.g., nitrogen) at a temperature sufficient to sinter the matrix material and yield a ruthenium-based thick-film resistor with copper terminations formed by the copper layer.
    Type: Grant
    Filed: October 26, 1998
    Date of Patent: January 30, 2001
    Assignee: Delco Electronics Corporation
    Inventors: Marion Edmond Ellis, Philip Harbaugh Bowles, Washington Morris Mobley
  • Patent number: 6174606
    Abstract: A conductive composite is described containing silver particles and a polymer which covers each silver particle and wherein a heterocyclic organic compound containing nitrogen such as benzotriazole (BTA) is present to reduce Ag dissolution and ion mobility by forming a water insoluble complex with the Ag ion. The invention overcomes the problem of silver dissolution or corrosion a conductive composite as a result of normal high Ag ion mobility in the presence of moisture and an electric field.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: January 16, 2001
    Assignee: International Business Machine Corporation
    Inventors: Vlasta Agnes Brusic, Judith Marie Roldan, Ravi F. Saraf
  • Patent number: 6171644
    Abstract: The present invention aims to present an electronic component which is free from the fear of sneaking-in of water etc. from the edge of electrode, by covering the electrode edge with resin. For the purpose, external electrodes (3) are formed at both ends of varistor (1) comprised of ceramic sheet (1a) and internal electrode (2) laminated alternately, and then, a within-the-surface insulation layer (30) is formed by covering the porous surface inside the varistor (1), or filling the Porosity, with silicone resin, and an outside-the-surface insulation layer (31) is formed covering the surface of varistor (1) and the edge of external electrode (3).
    Type: Grant
    Filed: April 22, 1999
    Date of Patent: January 9, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Riho Jinno, Kazuyuki Nakamura
  • Patent number: 6153256
    Abstract: A chip resistor includes a spaced pair of main top electrodes on an insulating substrate, a resistor layer formed on the insulating substrate to bridge between the main top electrodes, an overcoat layer formed over the resistor layer, and a pair of auxiliary top electrodes formed on the main top electrodes in contact with the overcoat layer. Each of the auxiliary top electrodes contains a glass material in addition to a metal material for integration with the overcoat layer.
    Type: Grant
    Filed: August 13, 1999
    Date of Patent: November 28, 2000
    Assignee: Rohm Co., Ltd.
    Inventors: Shigeru Kambara, Kaoru Sakai
  • Patent number: 6127040
    Abstract: Electroceramic component having a component body (10), connection metallization coatings (2, 3) and also a protective encapsulation (15 to 18) made of two different materials on in each case two mutually opposite areas of the component body (10) which are free from the connection metallization coatings (2, 3).
    Type: Grant
    Filed: February 22, 1999
    Date of Patent: October 3, 2000
    Assignee: Siemens Matsushita Components GmbH & Co. KG
    Inventors: Peter Grobbauer, Gunter Ott, Heinrich Zodl
  • Patent number: 6090435
    Abstract: The electronic component of the present invention includes: an element having an internal electrode therein; an external electrode formed on an end portion of the element where an end face of the internal electrode is exposed; and a protection layer formed on the entire surface of the element except for the end portion of the element, wherein the protection layer is made of a metal oxide.
    Type: Grant
    Filed: September 15, 1998
    Date of Patent: July 18, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd
    Inventors: Iwao Ueno, Yasuo Wakahata
  • Patent number: 6047463
    Abstract: A resistor may be embedded into a substrate. A portion of the resistor may be exposed, by segmenting the substrate, for instance, so that the resistor may be trimmed to a desired resistance level. Alternatively, a portion of a resistor may be embedded into a substrate, with another portion of the resistor being disposed on the outer surface of the substrate. The portion of the resistor on the outer surface may be trimmed to adjust the resistance of the resistor to a desired level.
    Type: Grant
    Filed: June 12, 1998
    Date of Patent: April 11, 2000
    Assignee: Intermedics Inc.
    Inventor: Kenneth R. Ulmer
  • Patent number: 5935642
    Abstract: Resistor material such as polysilicon is deposited on the insulating surface of a substrate and patterned to form resistor layers disposed generally parallel. Another resistor material such as polysilicon is deposited filling each space between adjacent resistor layers, with an insulating film being interposed between the upper and lower resistor materials, and etched back to form other resistor layers at respective spaces. After an insulating film is formed covering the resistor layers, contact holes are formed in the insulating film. A conductive layer is deposited and patterned to serially connect the resistor layers.
    Type: Grant
    Filed: November 20, 1996
    Date of Patent: August 10, 1999
    Assignee: Yamaha Corporation
    Inventor: Shigeru Suga
  • Patent number: 5884391
    Abstract: An electrical device comprising a resistive element having a first electrode in electrical contact with the top surface of the resistive element and a second electrode in electrical contact with the bottom surface of the resistive element. An insulating layer is formed on the first and second electrodes. A portion of the insulating layer is removed from the first and second electrodes to form first and second contact points. A conductive layer is formed on the insulating layer and makes electrical contact with the first and second electrodes at the contact points. The conductive layer has portions removed to form first and second end terminations separated by electrically non-conductive gaps. The wrap-around configuration of the device allows for an electrical connection to be made to both electrodes from the same side of the electrical device.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: March 23, 1999
    Assignee: Littelfuse, Inc.
    Inventors: Katherine M. McGuire, Honorio Luciano