Nonuniform Coating Patents (Class 427/63)
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Patent number: 11894162Abstract: Described is a method comprising directing an ultra-low voltage electron beam to a surface of a first insulating layer. The first insulating layer is disposed on a second insulating layer. The method includes modifying, by the application of the ultra-low voltage electron beam, the surface of the first insulating layer to selectively switch an interface between a first state having a first electronic property and a second state having a second electronic property.Type: GrantFiled: February 11, 2021Date of Patent: February 6, 2024Assignee: University of Pittsburgh—Of the Commonwealth System, of Higher EducationInventor: Jeremy Levy
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Patent number: 11895932Abstract: Techniques regarding selectively tuning the operating frequency of superconducting Josephson junction resonators are provided. For example, one or more embodiments described herein can comprise a method that can include chemically altering a Josephson junction of a Josephson junction resonator via a plasma treatment. The method can also comprise selectively tuning an operating frequency of the Josephson junction resonator based on a property of the plasma treatment.Type: GrantFiled: June 25, 2020Date of Patent: February 6, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eric Peter Lewandowski, Jeng-Bang Yau, Eric Zhang, Bucknell C Webb
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Patent number: 11621100Abstract: The present invention relates to a screen-printing paste composition for producing an electrical conductor arrangement, which screen-printing paste composition comprises particulate noble metal, comprising platinum and palladium, metal oxides, and organic binders and/or solvents, the proportion of the metal oxides in the screen-printing paste composition being 5 to 15 wt. %, based on the total amount of platinum and metal oxides. Suitable screen-printing paste compositions can be processed to form composite products by means of application to a substrate, subsequent drying and baking, which composite products can be used, for example, in particle sensors or heating devices. The particle sensors and heating devices thus produced are characterized by improved adhesion to the substrate at high temperatures and by conductivity, and demonstrated very good reproducibility of the electrical resistance in different production batches.Type: GrantFiled: October 29, 2019Date of Patent: April 4, 2023Assignee: Heraeus Nexensos GmbHInventors: Tim Asmus, Stefan Dietmann, Christoph Nick
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Patent number: 11469485Abstract: Techniques regarding an embedded microstrip transmission line implemented in one more superconducting microwave electronic devices are provided. For example, one or more embodiments described herein can comprise an apparatus, which can include a superconducting material layer positioned on a raised portion of a dielectric substrate. The raised portion can extend from a surface of the dielectric substrate. The apparatus can also comprise a dielectric film that covers at least a portion of the superconducting material layer and the raised portion of the dielectric substrate.Type: GrantFiled: October 21, 2020Date of Patent: October 11, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Isaac Lauer, William Francis Landers, Srikanth Srinivasan, Neereja Sundaresan
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Patent number: 11398329Abstract: A partially insulating layer for use in an HTS magnet coil. The partially insulating layer comprises an insulating body 401 having within it a set of linking tracks and a set of pickup tracks. Each linking track is electrically conductive and is electrically connected to first and second surfaces of the partially insulating layer, in order to provide an electrical path between said first and second surfaces. Each pickup track is electrically conductive and is inductively coupled to a respective linking track, and electrically isolated from the first and second surfaces. Each of the pickup tracks is configured for connection to a current measuring device in order to measure a current induced in the pickup track by a change in current flowing in the respective linking track.Type: GrantFiled: March 31, 2020Date of Patent: July 26, 2022Assignee: Tokamak Energy Ltd.Inventors: Rod Bateman, Robert Slade, Bas Van Nugteren
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Patent number: 10919656Abstract: A system and method for storing perishable items under controlled atmospheric conditions is provided. Total atmospheric pressure within a vacuum chamber containing the perishable items is reduced to below a predetermined total pressure limit. Oxygen partial pressure within the chamber is monitored. When the Oxygen partial pressure falls below a predetermined lower Oxygen partial pressure limit, an Oxygen-containing gas is admitted to the vacuum chamber to raise the Oxygen partial pressure above the lower Oxygen partial pressure limit. Total atmospheric pressure within the chamber is also monitored. When the total atmospheric pressure reaches or exceed the predetermined total pressure limit, total pressure within the vacuum chamber is once again reduced below the predetermined total pressure limit.Type: GrantFiled: March 16, 2018Date of Patent: February 16, 2021Assignee: Ripelocker LLCInventors: George Frank Lobisser, G. Kyle Lobisser, Todd Hansen, Eric Levi, Justin Chase Bothell
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Publication number: 20150148236Abstract: A method of forming a superconductor includes exposing a layer disposed on a substrate to an oxygen ambient, and selectively annealing a portion of the layer to form a superconducting region within the layer.Type: ApplicationFiled: November 27, 2013Publication date: May 28, 2015Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Connie P. Wang, Paul Murphy, Paul Sullivan, Sukti Chatterjee
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Publication number: 20140364319Abstract: In some implementations of the invention, existing extremely low resistance materials (“ELR materials”) may be modified and/or new ELR materials may be created by enhancing (in the case of existing ELR materials) and/or creating (in the case of new ELR materials) an aperture within the ELR material such that the aperture is maintained at increased temperatures so as not to impede propagation of electrical charge there through. In some implementations of the invention, as long as the propagation of electrical charge through the aperture remains unimpeded, the material should remain in an ELR state; otherwise, as the propagation of electrical charge through the aperture becomes impeded, the ELR material begins to transition into a non-ELR state.Type: ApplicationFiled: February 28, 2014Publication date: December 11, 2014Applicant: Ambature, Inc.Inventor: Douglas J. Gilbert
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Patent number: 8809236Abstract: A method for manufacturing a high temperature superconductor (=HTS) coated tape (20), with the following steps: preparation of a substrate tape (1), deposition of at least one buffer layer (2), deposition of an HTS film (3), deposition of a metallic protection layer (35) on the HTS film (3) and deposition of a metallic shunt layer (36) is characterized in that, prior to deposition of the metallic shunt layer (36), the partially prepared coated tape (10) undergoes a laser beam cutting in order to provide a desired tape form, wherein the laser beam cutting is applied together with a gas flow and/or a liquid flow (23). The method reduces the loss of critical current and reduces or avoids a deterioration of the critical temperature in a HTS coated tape due to tape cutting.Type: GrantFiled: February 15, 2012Date of Patent: August 19, 2014Assignees: Oswald Elektromotoren GmbH, Bruker HTS GmbHInventors: Johannes Oswald, Bernhard Oswald, Thomas Reis, Alexander Rutt, Alexander Usoskin
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Publication number: 20140194294Abstract: The present invention relates to a method for producing superconducting coils (1) having the steps of providing a substrate (2) and applying a superconducting material in the form of at least one coil onto the substrate. The application of the superconducting material is performed by at least one coating method directly on the substrate. Winding coated flat wires can be dispensed with. Furthermore, the present invention comprises a superconducting apparatus comprising a superconducting coil (1) produced in accordance with the method.Type: ApplicationFiled: August 6, 2012Publication date: July 10, 2014Applicant: Siemens AktiengesellschaftInventor: Dierk Schröder
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Patent number: 8716189Abstract: A method of producing a superconductive material involves the step (1) of applying a solution of an organic compound of metals, oxides of the metals forming a superconductive material, onto a support body to be subsequently dried, a provisional baking step (2) of causing organic components of the organic compound of the metals to undergo thermal decomposition, and a main baking process step (3) of causing transformation of the oxides of the metals into the superconductive material, thereby producing an epitaxially-grown superconductive coating material, wherein at the time of irradiation of a surface of the support body coated with the solution of the organic compound of the metals for forming the superconductive material, and/or of a surface of the support body, opposite to the surface coated with the solution of the organic compound of the metals, with the laser light, during a period between the steps (1) and (2).Type: GrantFiled: February 5, 2008Date of Patent: May 6, 2014Assignees: National Institute of Advanced Industrial Science and Technology, The Japan Steel Works, Ltd.Inventors: Mitsugu Sohma, Tetsuo Tsuchiya, Toshiya Kumagai, Kenichi Tsukada, Kunihiko Koyanagi, Takashi Ebisawa, Hidehiko Ohtu
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Patent number: 8658571Abstract: The invention relates to a method for the wet chemical production of an HTSL on a carrier, wherein an HTSL precursor solution comprising no trifluoroacetate may be utilized if the same is heated to a temperature Ts during the heat treatment of the HTSL precursor, wherein the remaining substances of the HTSL precursor solution form at least a partial melt, which is below the temperature at which RE2BaCuOx is formed, and which is deposited from the liquid phase while forming a peritectic.Type: GrantFiled: March 18, 2010Date of Patent: February 25, 2014Assignee: BASF SEInventors: Isabel van Driessche, Pieter Vermeir, Serge Hoste, Michael Baecker
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Patent number: 8649834Abstract: A layered superconductor device includes multiple layers of a single crystal superconducting material having intermittent layers of superconducting material dispersed in a pattern with a second material such that each layer of the multiple layers a single crystal superconducting material are interconnected via superconducting material, allowing for a continuous current path, and a thickness of the superconducting material never exceeds a first predetermined thickness.Type: GrantFiled: September 13, 2012Date of Patent: February 11, 2014Assignee: The United States of America as represented by the Secretary of the NavyInventor: Thomas O. Jones
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Patent number: 8506826Abstract: A method for manufacturing a micro electro-mechanical system (MEMS) switch system (600, 700) includes etching each of a plurality of base circuit layers (425) and a plurality of passive component substrate layers (412, 418, 42, 426). The method continues with laser milling of a first dielectric film (406) to create a spacer layer (405). A metal cladding (402, 403) formed on a flexible dielectric film layer 404 is etched so as to form a plurality of switch component features. Further laser milling is performed with respect to the flexible dielectric film layer to form at least one switch structure (448, 450). Thereafter, a stack (400) is assembled which is comprised of the spacer layer disposed between the flexible dielectric film layer and the plurality of base circuit layers. Additional layers can also be included in the stack. When the stack is completed, heat and pressure are applied to join the various layers forming the stack.Type: GrantFiled: August 2, 2011Date of Patent: August 13, 2013Assignee: Harris CorporationInventor: John E. Rogers
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Publication number: 20130137579Abstract: A method for producing a superconductive conductor includes: a base material preparation process of preparing a base material having a groove formed on at least one face thereof; a superconducting layer formation process of forming a superconducting layer on a surface of the base material at a side at which the groove is formed; and a cutting process of cutting completely through the base material along the groove.Type: ApplicationFiled: August 2, 2012Publication date: May 30, 2013Applicant: FURUKAWA ELECTRIC CO., LTD.Inventors: Yoshinori Nagasu, Hisaki Sakamoto, Masaru Higuchi
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Patent number: 8315678Abstract: Superconducting connections are provided to internal layers of a multi-layer circuit board structure, for example by superconducting vias.Type: GrantFiled: October 8, 2008Date of Patent: November 20, 2012Assignee: D-Wave Systems Inc.Inventor: Sergey V. Uchaykin
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Publication number: 20120077680Abstract: Systems, articles, and methods are provided related to nanowire-based detectors, which can be used for light detection in, for example, single-photon detectors. In one aspect, a variety of detectors are provided, for example one including an electrically superconductive nanowire or nanowires constructed and arranged to interact with photons to produce a detectable signal. In another aspect, fabrication methods are provided, including techniques to precisely reproduce patterns in subsequently formed layers of material using a relatively small number of fabrication steps. By precisely reproducing patterns in multiple material layers, one can form electrically insulating materials and electrically conductive materials in shapes such that incoming photons are redirected toward a nearby electrically superconductive materials (e.g., electrically superconductive nanowire(s)). For example, one or more resonance structures (e.g.Type: ApplicationFiled: May 27, 2011Publication date: March 29, 2012Applicant: Massachusetts Institute of TechnologyInventors: Karl K. Berggren, Xiaolong Hu, Daniele Masciarelli
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Publication number: 20120065072Abstract: A superconducting metallic glass transition-edge sensor (MGTES) and a method for fabricating the MGTES are provided. A single-layer superconducting amorphous metal alloy is deposited on a substrate. The single-layer superconducting amorphous metal alloy is an absorber for the MGTES and is electrically connected to a circuit configured for readout and biasing to sense electromagnetic radiation.Type: ApplicationFiled: September 12, 2011Publication date: March 15, 2012Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGYInventor: Charles C. Hays
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Publication number: 20120015818Abstract: A method for producing a high temperature superconductor (=HTS) coated conductor (12), wherein a buffer layer (2; 22) and an HTS layer (4; 24; 65) are deposited on a substrate (1; 21), with the following steps: a) after depositing the buffer layer (2; 22), the surface (2a) is locally roughened, resulting in a roughened surface (13), b) a non-superconducting, closed intermediate layer (3; 23) is deposited on top of the roughened surface (13), c) and the HTS layer (4; 24; 65) is deposited on top of the intermediate layer (3; 23). A simple method for producing a HTS coated conductor with reduced losses, and with improved critical current and critical magnetic field is thereby provided.Type: ApplicationFiled: July 18, 2011Publication date: January 19, 2012Applicant: Bruker HTS GmbHInventors: Klaus Schlenga, Alexander Usoskin
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Publication number: 20120015817Abstract: A coated conductor is provided with improved electrical connection between the conductive layers such as the high temperature superconductor layer and a metal protection layer applied onto the high temperature superconductor layer and the substrate. A method includes obtaining such electrical connection, in particular, creating a coated conductor wherein the substrate is a core covered with the layers all around its periphery.Type: ApplicationFiled: July 15, 2010Publication date: January 19, 2012Inventors: Arnaud Allais, Mark O. Rikel, Jürgen Ehrenberg
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Publication number: 20110281734Abstract: Disclosed is a three layer process for making contact points to a high transition temperature superconductor (HTSC), particularly to (Bi,Pb)2 Sr2 Ca2 CU3019+x with and without silver in the superconductor. The contact structure is a three layer configuration with a perforated silver foil (3) sandwiched between two metal spray gun deposited silver layers (2,5) and subsequent heat treatment in air. The contact has been made on tubes and rods (1). The silver contacts are capable of carrying a continuous current of 200 Amps without adding any substantial heat load to the cryogen used to cool the HTSC. The contact resistance at 4.2K is in the range of 1.5×10(hoch?8) to 8.5? 10(hoch?8)OHM in zero applied filed.Type: ApplicationFiled: July 23, 2010Publication date: November 17, 2011Inventors: Shrikant EKBOTE, Gursharan Kaur PADAM, Narendra Kumar ARORA, Mukul SHARMA, Ramesh SETHI, Mrinal Kanti BANERJEE
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Publication number: 20110177952Abstract: A method is disclosed for making a template for a superconducting coil on a former (25) from a sheet (23) of flexible biaxially-textured material having at least two joining edges, the surface texture of the sheet being defined by a plurality of grains, and the former having a substantially curved surface. The method comprises the steps of shaping the sheet so that each joining edge lies adjacent to another joining edge on application of the sheet to the former, each joining edge and its adjacent edge being a pair of edges, and so that the sheet is dimensioned to cover a part of the surface of the former and substantially to fit that part of the former; positioning the sheet on the former so that regions of the sheet either side of the pair of edges have substantially aligned grains; and forming a join between the pair of edges, the template thereby having a substantially continuous textured surface across the join.Type: ApplicationFiled: November 23, 2006Publication date: July 21, 2011Applicant: COATED CONDUCTOR CYLINDERS LTDInventor: Eamonn Maher
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Patent number: 7902119Abstract: Porous ceramic superconductors having a film thickness over 0.5 microns are provided. The superconducting material is applied to a vicinal substrate and optionally nanoparticles are inserted to release local strain. The resultant superconductors exhibit improved Jc values compared to nonvicinal (flat) counterparts and those having no nanoparticles.Type: GrantFiled: July 21, 2006Date of Patent: March 8, 2011Inventors: Judy Wu, Rose Emergo, Timothy Haugan, Paul Barnes
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Publication number: 20110033674Abstract: A simple and controlled method to fabricate a 3D, epitaxial, biaxially textured nanofence comprised of single crystalline MgO nanobelt segments or links that grew both vertically and horizontally along <100> directions of the (100) STO substrate was developed. Continuous supply of Ni catalyst during the co-laser ablation of MgO and Ni metal led to the growth of nanobelts with such a unique morphology. Individual single crystalline MgO nanobelts had a square cross-section with high aspect ratios. X-ray diffraction results obtained from an entire MgO nanofence layer confirmed that MgO nanofence had epitaxial relation with STO substrate of [100]MgO?[100]STO. Such oxide nanofences can be used as a 3D biaxially-textured nanotemplate for epitaxial growth of wide-ranging, 3D, electronic, magnetic and electromagnetic nanodevices.Type: ApplicationFiled: February 24, 2010Publication date: February 10, 2011Applicant: UT-BATTELLE, LLCInventors: Amit Goyal, Sung-Hun Wee
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Publication number: 20110034336Abstract: A superconducting article includes a substrate having a biaxially textured surface, and an epitaxial biaxially textured superconducting film supported by the substrate. The epitaxial superconducting film includes particles of Ba2RENbO6 and is characterized by a critical current density higher than 1 MA/cm2 at 77K, self-field. In one embodiment the particles are assembled into columns. The particles and nanocolumns of Ba2RENbO6 defects enhance flux pinning which results in improved critical current densities of the superconducting films. Methods of making superconducting films with Ba2RENbO6 defects are also disclosed.Type: ApplicationFiled: August 4, 2010Publication date: February 10, 2011Inventors: Amit Goyal, Sung-Hun Wee, Eliot Specht, Claudia Cantoni
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Publication number: 20100323899Abstract: A superconductive element is described, comprising a rigid support made of a non-superconductive material, said support comprising at least one superconductive track formed by a groove containing a superconductive material having a density equal to at least 85% of the value of its theoretical density, and the process for producing said element. The present invention also relates to the possible uses of the superconductive elements, and also to superconductive devices comprising said superconductive elements.Type: ApplicationFiled: June 14, 2010Publication date: December 23, 2010Applicant: EDISON S.p.A.Inventor: Giovanni Giunchi
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Publication number: 20100216646Abstract: A process for preparing a superconductor article includes depositing a precursor solution onto a substrate to form a precursor film, the precursor solution comprising precursor components to a rare earth-alkaline earth metal-transition metal oxide in one or more solvents, decomposing the precursor film to form an intermediate film comprising the rare earth metal, the alkaline earth metal, and the transition metal of the first precursor solution, selectively removing portions of the intermediate film, wherein a patterned intermediate film is obtained, and treating the patterned intermediate film to form a rare earth-alkaline earth metal-transition metal oxide superconductor.Type: ApplicationFiled: February 26, 2010Publication date: August 26, 2010Applicant: American Superconductor CorporationInventors: Thomas Kodenkandath, Wei Zhang
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Patent number: 7756557Abstract: An AC-tolerant high temperature superconductor tape with transposed filaments having two layers of high temperature superconducting material with striations and corresponding filaments and an insulating layer positioned therebetween.Type: GrantFiled: November 30, 2006Date of Patent: July 13, 2010Assignee: The United States of America as represented by the Secretary of the Air ForceInventors: Paul N. Barnes, Milan Polak, Chakrapani Varanasi
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Patent number: 7749556Abstract: A method for manufacturing a field emission substrate is disclosed. The method includes the following steps: providing a substrate having a conductive layer; forming a hydrophobic layer on the conduction layer; patterning the hydrophobic layer; and removing the hydrophobic layer from the surface of the conductive layer so that the formed layer of electron-emitting materials can contact the surface of the conductive layer. The patterned hydrophobic layer can include plural bumps, and the pitches between the neighboring bumps are in a range of 1 ?m to 500 ?m. By way of the steps illustrated above, the emitting layer on the substrate can be made easily and arranged accurately. Hence, the electrons can be emitted homogeneously.Type: GrantFiled: June 30, 2006Date of Patent: July 6, 2010Assignees: Tatung Company, Industrial Technology Research InstituteInventors: Hung-Yung Li, Tsuey-May Yin, Tsai-Ling Ho
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Publication number: 20100143660Abstract: A process for preparing a shaped substrate suitable in the production of coated conductors which process allows the deformation of a textured substrate onto which a textured buffer layer has been already grown.Type: ApplicationFiled: June 3, 2009Publication date: June 10, 2010Inventors: Jurgen Ehrenberg, Mark Rikel
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Patent number: 7723152Abstract: In the condition where a nozzle for applying a coating liquid is disposed on the lower side of a substrate and a substrate surface controlled in wettability is faced down, the nozzle and the substrate are moved relative to each other, whereby the coating liquid is applied to a desired region of the substrate, and then the coating liquid is dried, to obtain a pattern included a dried coating layer.Type: GrantFiled: March 21, 2006Date of Patent: May 25, 2010Assignee: Sony CorporationInventor: Akihiro Nomoto
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Patent number: 7695756Abstract: A tool for manufacturing molecular electronic devices having a coating unit contained in a controlled ambient environment. The coating unit is coupled to a source of active device molecules in solution. The coating unit is configured to apply a selected quantity of the solution to a surface of a substrate and the process tool processes the coated substrate in conditions that cause the active device molecules to attach to active areas of the substrate.Type: GrantFiled: April 29, 2004Date of Patent: April 13, 2010Assignee: ZettaCore, Inc.Inventors: Antonio R. Gallo, Werner G. Kuhr
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Publication number: 20090233800Abstract: Under one aspect, a method of making a superconductor wire includes providing an oxide superconductor layer overlaying a substrate; forming a substantially continuous barrier layer over the oxide superconductor layer, the barrier layer including metal; depositing a layer of metal particles over the barrier layer, said depositing including applying a liquid including metal particles over the barrier layer; and sintering the layer of metal particles to form a substantially continuous metal layer over the barrier layer. In one or more embodiments, the oxide superconductor layer is oxygen-deficient, and the method may include oxidizing the oxygen-deficient oxide superconductor layer. At least a portion of the sintering and the oxidizing may occur simultaneously, for example by performing them at an oxygen partial pressure and a temperature sufficient to both sinter the metal particles and to oxidize the oxygen-deficient oxide superconductor layer.Type: ApplicationFiled: March 23, 2007Publication date: September 17, 2009Applicant: American Superconductor CorporationInventors: Yibing Huang, Thomas Kodenkandath, Joseph Lynch, Martin W. Rupich, Wei Zhang
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Publication number: 20090099025Abstract: Superconducting connections are provided to internal layers of a multi-layer circuit board structure, for example by superconducting vias.Type: ApplicationFiled: October 8, 2008Publication date: April 16, 2009Inventor: Sergey V. Uchaykin
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High temperature superconducting (HTS) tape coil with enhanced protection and method for making same
Patent number: 7517834Abstract: The invention provides an improved method of manufacturing an HTS tape coil for an MRI device with enhanced protection, the method comprising attaching high-Q capacitors at each end of an HTS wire, removing substantially all electrically conductive sheathing material on an inner side of the HTS wire, while retaining substantially all electrically conductive sheathing material on an outer side of the HTS wire. The invention also provides an HTS wire made in accordance with the foregoing method.Type: GrantFiled: January 23, 2007Date of Patent: April 14, 2009Assignee: The University of Hong KongInventors: Yum Wing Wong, Edward S. Yang -
Publication number: 20090048113Abstract: A superconducting thin film is disclosed having columnar pinning centers utilizing nano dots, and comprising nano dots (3) which are formed insularly on a substrate (2) and three-dimensionally in shape and composed of a material other than a superconducting material and also other than a material of which the substrate is formed, columnar defects (4) composed of the superconducting material and grown on the nano dots (3), respectively, a lattice defect (6) formed on a said columnar defect (4), and a thin film of the superconducting material (5) formed in those areas on the substrate which are other than those where said columnar defects are formed.Type: ApplicationFiled: October 9, 2008Publication date: February 19, 2009Applicants: JAPAN SCIENCE AND TECHNOLOGY AGENCY, NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGYInventors: Ioan Adrian Crisan, Hideo Ihara, Yoshiko Ihara, Hideyo Ihara, Hidetaka Ihara, Gen-ei Ihara, Chiaki Ihara
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Patent number: 7014727Abstract: A method of forming high resolution electronic circuits (10) on a substrate (12) is provided. The method includes the steps of laminating a dielectric layer (14) on a substrate (12), laser drilling channels (16 and 18) in the dielectric film (14) and the substrate (12), and filling channels (16 and 18) with a filler material (20). Further, a release layer (22) is applied to dielectric film layer (14) and filler material (20), the release layer (22) having an adhesive thereon. Release layer (22) is peeled or otherwise removed from substrate (12), leaving filler material (20) formed and shaped on substrate (12), thus producing a high resolution electronic circuit on substrate (12).Type: GrantFiled: July 7, 2003Date of Patent: March 21, 2006Assignees: Potomac Photonics, Inc., Parelec, Inc.Inventors: Christopher Wargo, Paul Kydd, Scott Mathews, Susan Gordon, legal representative, Chengping Zhang, Todd A. Kegresse, Michael Duignan, deceased
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Patent number: 6882293Abstract: A Josephson junction has a Si substrate, a two layer film comprising an amorphous MgO layer and a high orientation MgO layer on the Si substrate, and a NbN film or the NbCN film laminated on the two layer film.Type: GrantFiled: August 21, 2003Date of Patent: April 19, 2005Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Akira Shoji, Hirotaka Yamamori
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Patent number: 6830776Abstract: A method of manufacturing a high temperature superconductor is disclosed. The method includes depositing, by pulsed laser deposition, alternating layers of YBa2Cu3O7-x (Y123) and Y2BaCuO5-y (Y211). The Y211 layers are characterized by a multiplicity of nanosized globular inclusions, effectively enhancing flux pinning and thus increasing current transport.Type: GrantFiled: January 31, 2003Date of Patent: December 14, 2004Assignee: The United States of America as represented by the Secretary of the Air ForceInventors: Paul N. Barnes, Timothy J. Haugan
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Patent number: 6638568Abstract: A method of curing cracks in a ceramic shaped body made from ceramic magnet materials or ceramic superconductor materials, in which a filling material which melts at a lower temperature than the material of the shaped body or is flowable at a lower temperature than the material of the shaped body is applied to the surface of the shaped body at least in the area of a crack and/or is introduced into at least one crack, in which the shaped body with the filling material is heated to and maintained at a temperature at which the material of the shaped body does not yet melt or is not yet flowable, but at which the filling material is in at least partially molten and flowable state at least until the fused filling material can penetrate at least partially into the crack, in which the filling material consists of non-metallic or essentially of non-metallic compounds and is at least partially crystallized, and in which the shaped body with the filling material is cooled, wherein the thermal crystallization conditionsType: GrantFiled: July 31, 2001Date of Patent: October 28, 2003Assignee: Nexans Superconductors GmbHInventors: Michael Baecker, Joachim Bock, Herbert C. Freyhardt, Andreas Leenders, Heribert Walter, Martin Ullrich
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Publication number: 20030148066Abstract: Ion texturing methods and articles are disclosed.Type: ApplicationFiled: July 30, 2001Publication date: August 7, 2003Inventors: Ronald P. Reade, Paul H. Berdahl, Richard E. Russo, Leslie G. Fritzemeier
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Patent number: 6352741Abstract: High temperature superconductive (HTS) integrated circuits can be fabricated in three ways according to the invention. First, a planar multiple layer HTS integrated circuit is fabricated using multiple HTS layers. The layers include altered regions which have been bombarded using ion implantation to destroy superconductivity of the altered regions without interrupting the lattice structure of the altered regions. Second, a planar multiple-layer HTS integrated circuit includes upper and lower HTS layers, each including central and opposing regions. A first implant energy is used to destroy superconducting properties of the opposing regions of the lower HTS layer without interrupting the lattice structure. A second implant energy is used to destroy superconducting properties of a top portion of the central region to define a contact. Third, a HTS integrated circuit is formed from a single HTS layer using three ion implantation steps and ions having first, second and third energies and range.Type: GrantFiled: April 17, 1995Date of Patent: March 5, 2002Assignee: TRW Inc.Inventors: Hugo W. K. Chan, Arnold H. Silver
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Publication number: 20010003118Abstract: The present invention relates to a SQUID made of an oxide superconducting thin film is formed on a sapphire substrate. CeO2 film, RBa2Cu3O7−x film (“R” indicates a rare earth element chosen among a group formed Yb, Er, Ho, Y, Dy, Gd, Eu, Sm and Nd) and SrTiO3 film are deposited the substrate top of sapphire successively. Furthermore, an oxide superconducting thin film to be a SQUID is deposited on the SrTiO3 film.Type: ApplicationFiled: March 23, 1999Publication date: June 7, 2001Inventor: TATSUOKI NAGAISHI
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Patent number: 6235685Abstract: A rod 1 made of superconducting oxide is soaked in a molten normal conductor 2 to join the rod 1 and the normal conductor 2, whereby a superconducting oxide current lead is prepared. As a result, a contact resistance at the interface between the superconducting oxide and the normal conductor can be reduced. Consequently, Joule's heat at a current lead having a small cross sectional area can be suppressed low, which in turn realizes the reduction of the load on a freezer and the amount of evaporated cooling solvent, with respect to a superconducting coil.Type: GrantFiled: November 15, 1999Date of Patent: May 22, 2001Assignee: International Superconductivity Technology CenterInventors: Junya Maeda, Teruo Izumi, Yuichi Imagawa, Satoshi Matsuoka, Yuh Shiohara, Shoji Tanaka, Hiroshi Okamoto
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Patent number: 6147032Abstract: An implant patterned superconductive device and a method for indirect implant-patterning of oxide superconducting materials is provided. The method forms a device having an oxide superconducting layer on a substrate, deposits a passivation layer atop the oxide superconducting layer, and implants chemical impurities in a selected portion of the superconducting layer through the passivation layer. This modifies the conductivity of the selected portion of the oxide superconducting layer and electrically isolates the selected portion from the non-selected portion of the oxide superconducting layer. The passivation layer is made of a material less susceptible to implant damage than the oxide superconducting layer to allow inhibition of the oxide superconducting layer while protecting the crystalline structure of the top surface of the oxide superconducting layer and keeping it planarized.Type: GrantFiled: May 19, 1999Date of Patent: November 14, 2000Assignee: TRW Inc.Inventors: John R. LaGraff, Claire L. Pettiette-Hall, James M. Murduck, Hugo W-K. Chan
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Patent number: 6110392Abstract: The invention is a process for reducing roughness of a surface of a superconductor material (23) having an undesirable surface roughness (30 and 32) and a trilayer superconductor integrated circuit (100). The process for reducing roughness of a surface of superconductor material having an undesirable surface roughness includes coating the surface with an oxide layer (40) to fill the undesirable surface roughness and to produce an exposed oxide surface (42) with a roughness less than the surface roughness; and etching the exposed oxide surface to remove a thickness of the oxide layer followed by removing at least a portion of the oxide layer filling the undesirable surface roughness and a portion of the surface of the superconductor material to produce an exposed etched surface (44) comprised of at least the superconductor material which has a surface roughness less than the undesirable surface roughness.Type: GrantFiled: September 18, 1998Date of Patent: August 29, 2000Assignee: TRW Inc.Inventors: George L. Kerber, Michael Leung
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Patent number: 6066600Abstract: A high temperature superconductor junction and a method of forming the junction are disclosed. The junction 40 comprises a first high-T.sub.c superconductive layer (first base electrode layer) 46 on a substrate 42 and a dielectric layer 48 on the first high-T.sub.c superconductive layer. The dielectric layer and the first high-T.sub.c superconductive layer define a ramp edge 50. A trilayer SNS structure 52 is disposed on the ramp edge to form an SSNS junction. The SNS structure comprises a second high-T.sub.c superconductive layer (second base electrode layer) 54 directly on the first high-T.sub.c superconductive layer, a normal barrier layer 56 on the second high-T.sub.c superconductive layer, and a third high-T.sub.c superconductive layer 58 (counterelectrode) on the barrier layer. The ramp edge is typically formed by photoresist masking and ion-milling. A plasma etch step can be performed in-situ to remove the photoresist layer 62 following formation of the ramp edge.Type: GrantFiled: January 22, 1998Date of Patent: May 23, 2000Assignee: TRW Inc.Inventor: Hugo W. Chan
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Patent number: 5981443Abstract: A bicrystal substrate is formed by joining end faces of a first single crystal substrate and a second single crystal substrate, the end faces having different crystal orientations. A high critical temperature superconducting thin film is then epitaxially formed on the bicrystal substrate. The superconducting thin film is etched so as to form a first superconducting electrode on the first single crystal substrate, a second superconducting electrode on the second single crystal substrate, and a superconducting bridge across a joint between the first and second single crystal substrates and connecting the first electrode and the second electrode. A conductive film is formed on the superconducting bridge by vapor deposition, and is then etched so as to form a weak link on a part of the superconducting bridge over the joint.Type: GrantFiled: August 26, 1998Date of Patent: November 9, 1999Assignee: Oki Electric Industry Co., Ltd.Inventor: Zhongmin Wen
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Patent number: 5942376Abstract: Solution films of a photosensitive metal arylketone alcoholate are micro-patterned by exposure to ultraviolet radiation under a mask. The resultant patterns are developed in an apolar solvent and annealed to provide thin film metal oxides for use in integrated circuits.Type: GrantFiled: August 14, 1997Date of Patent: August 24, 1999Assignees: Symetrix Corporation, Mitsubishi Materials CorporationInventors: Hiroto Uchida, Nobuyuki Soyama, Kensuke Kageyama, Katsumi Ogi, Michael C. Scott, Larry D. McMillan, Carlos A. Paz de Araujo
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Patent number: 5916848Abstract: An edge junction 10 with reduced parasitic inductance. The edge junction 10 has a laminar structure 22 including: a substrate 14; a first superconductive layer 12 deposited on a substrate 14; a first dielectric layer 16 deposited on the first superconductive layer 12; a second superconductive layer 18 deposited on the first dielectric layer 16; and a second dielectric layer 20 deposited on the second superconductive layer 18. The first and second superconductive layers 12 and 18 and the first and second dielectric layers 16 and 20 form a first laminar structure 22 having a planar segment 24 and a self-aligned ramp segment 26, the ramp segment 26 having a constantly-decreasing thickness and being connected to the planar segment 24 at an angle .theta. thereto.Type: GrantFiled: October 8, 1997Date of Patent: June 29, 1999Assignee: TRW Inc.Inventor: Dale J. Durand