Nonuniform Coating Patents (Class 427/63)
  • Publication number: 20150148236
    Abstract: A method of forming a superconductor includes exposing a layer disposed on a substrate to an oxygen ambient, and selectively annealing a portion of the layer to form a superconducting region within the layer.
    Type: Application
    Filed: November 27, 2013
    Publication date: May 28, 2015
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Connie P. Wang, Paul Murphy, Paul Sullivan, Sukti Chatterjee
  • Publication number: 20140364319
    Abstract: In some implementations of the invention, existing extremely low resistance materials (“ELR materials”) may be modified and/or new ELR materials may be created by enhancing (in the case of existing ELR materials) and/or creating (in the case of new ELR materials) an aperture within the ELR material such that the aperture is maintained at increased temperatures so as not to impede propagation of electrical charge there through. In some implementations of the invention, as long as the propagation of electrical charge through the aperture remains unimpeded, the material should remain in an ELR state; otherwise, as the propagation of electrical charge through the aperture becomes impeded, the ELR material begins to transition into a non-ELR state.
    Type: Application
    Filed: February 28, 2014
    Publication date: December 11, 2014
    Applicant: Ambature, Inc.
    Inventor: Douglas J. Gilbert
  • Patent number: 8809236
    Abstract: A method for manufacturing a high temperature superconductor (=HTS) coated tape (20), with the following steps: preparation of a substrate tape (1), deposition of at least one buffer layer (2), deposition of an HTS film (3), deposition of a metallic protection layer (35) on the HTS film (3) and deposition of a metallic shunt layer (36) is characterized in that, prior to deposition of the metallic shunt layer (36), the partially prepared coated tape (10) undergoes a laser beam cutting in order to provide a desired tape form, wherein the laser beam cutting is applied together with a gas flow and/or a liquid flow (23). The method reduces the loss of critical current and reduces or avoids a deterioration of the critical temperature in a HTS coated tape due to tape cutting.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: August 19, 2014
    Assignees: Oswald Elektromotoren GmbH, Bruker HTS GmbH
    Inventors: Johannes Oswald, Bernhard Oswald, Thomas Reis, Alexander Rutt, Alexander Usoskin
  • Publication number: 20140194294
    Abstract: The present invention relates to a method for producing superconducting coils (1) having the steps of providing a substrate (2) and applying a superconducting material in the form of at least one coil onto the substrate. The application of the superconducting material is performed by at least one coating method directly on the substrate. Winding coated flat wires can be dispensed with. Furthermore, the present invention comprises a superconducting apparatus comprising a superconducting coil (1) produced in accordance with the method.
    Type: Application
    Filed: August 6, 2012
    Publication date: July 10, 2014
    Applicant: Siemens Aktiengesellschaft
    Inventor: Dierk Schröder
  • Patent number: 8716189
    Abstract: A method of producing a superconductive material involves the step (1) of applying a solution of an organic compound of metals, oxides of the metals forming a superconductive material, onto a support body to be subsequently dried, a provisional baking step (2) of causing organic components of the organic compound of the metals to undergo thermal decomposition, and a main baking process step (3) of causing transformation of the oxides of the metals into the superconductive material, thereby producing an epitaxially-grown superconductive coating material, wherein at the time of irradiation of a surface of the support body coated with the solution of the organic compound of the metals for forming the superconductive material, and/or of a surface of the support body, opposite to the surface coated with the solution of the organic compound of the metals, with the laser light, during a period between the steps (1) and (2).
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: May 6, 2014
    Assignees: National Institute of Advanced Industrial Science and Technology, The Japan Steel Works, Ltd.
    Inventors: Mitsugu Sohma, Tetsuo Tsuchiya, Toshiya Kumagai, Kenichi Tsukada, Kunihiko Koyanagi, Takashi Ebisawa, Hidehiko Ohtu
  • Patent number: 8658571
    Abstract: The invention relates to a method for the wet chemical production of an HTSL on a carrier, wherein an HTSL precursor solution comprising no trifluoroacetate may be utilized if the same is heated to a temperature Ts during the heat treatment of the HTSL precursor, wherein the remaining substances of the HTSL precursor solution form at least a partial melt, which is below the temperature at which RE2BaCuOx is formed, and which is deposited from the liquid phase while forming a peritectic.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: February 25, 2014
    Assignee: BASF SE
    Inventors: Isabel van Driessche, Pieter Vermeir, Serge Hoste, Michael Baecker
  • Patent number: 8649834
    Abstract: A layered superconductor device includes multiple layers of a single crystal superconducting material having intermittent layers of superconducting material dispersed in a pattern with a second material such that each layer of the multiple layers a single crystal superconducting material are interconnected via superconducting material, allowing for a continuous current path, and a thickness of the superconducting material never exceeds a first predetermined thickness.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: February 11, 2014
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Thomas O. Jones
  • Patent number: 8506826
    Abstract: A method for manufacturing a micro electro-mechanical system (MEMS) switch system (600, 700) includes etching each of a plurality of base circuit layers (425) and a plurality of passive component substrate layers (412, 418, 42, 426). The method continues with laser milling of a first dielectric film (406) to create a spacer layer (405). A metal cladding (402, 403) formed on a flexible dielectric film layer 404 is etched so as to form a plurality of switch component features. Further laser milling is performed with respect to the flexible dielectric film layer to form at least one switch structure (448, 450). Thereafter, a stack (400) is assembled which is comprised of the spacer layer disposed between the flexible dielectric film layer and the plurality of base circuit layers. Additional layers can also be included in the stack. When the stack is completed, heat and pressure are applied to join the various layers forming the stack.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: August 13, 2013
    Assignee: Harris Corporation
    Inventor: John E. Rogers
  • Publication number: 20130137579
    Abstract: A method for producing a superconductive conductor includes: a base material preparation process of preparing a base material having a groove formed on at least one face thereof; a superconducting layer formation process of forming a superconducting layer on a surface of the base material at a side at which the groove is formed; and a cutting process of cutting completely through the base material along the groove.
    Type: Application
    Filed: August 2, 2012
    Publication date: May 30, 2013
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Yoshinori Nagasu, Hisaki Sakamoto, Masaru Higuchi
  • Patent number: 8315678
    Abstract: Superconducting connections are provided to internal layers of a multi-layer circuit board structure, for example by superconducting vias.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: November 20, 2012
    Assignee: D-Wave Systems Inc.
    Inventor: Sergey V. Uchaykin
  • Publication number: 20120077680
    Abstract: Systems, articles, and methods are provided related to nanowire-based detectors, which can be used for light detection in, for example, single-photon detectors. In one aspect, a variety of detectors are provided, for example one including an electrically superconductive nanowire or nanowires constructed and arranged to interact with photons to produce a detectable signal. In another aspect, fabrication methods are provided, including techniques to precisely reproduce patterns in subsequently formed layers of material using a relatively small number of fabrication steps. By precisely reproducing patterns in multiple material layers, one can form electrically insulating materials and electrically conductive materials in shapes such that incoming photons are redirected toward a nearby electrically superconductive materials (e.g., electrically superconductive nanowire(s)). For example, one or more resonance structures (e.g.
    Type: Application
    Filed: May 27, 2011
    Publication date: March 29, 2012
    Applicant: Massachusetts Institute of Technology
    Inventors: Karl K. Berggren, Xiaolong Hu, Daniele Masciarelli
  • Publication number: 20120065072
    Abstract: A superconducting metallic glass transition-edge sensor (MGTES) and a method for fabricating the MGTES are provided. A single-layer superconducting amorphous metal alloy is deposited on a substrate. The single-layer superconducting amorphous metal alloy is an absorber for the MGTES and is electrically connected to a circuit configured for readout and biasing to sense electromagnetic radiation.
    Type: Application
    Filed: September 12, 2011
    Publication date: March 15, 2012
    Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventor: Charles C. Hays
  • Publication number: 20120015818
    Abstract: A method for producing a high temperature superconductor (=HTS) coated conductor (12), wherein a buffer layer (2; 22) and an HTS layer (4; 24; 65) are deposited on a substrate (1; 21), with the following steps: a) after depositing the buffer layer (2; 22), the surface (2a) is locally roughened, resulting in a roughened surface (13), b) a non-superconducting, closed intermediate layer (3; 23) is deposited on top of the roughened surface (13), c) and the HTS layer (4; 24; 65) is deposited on top of the intermediate layer (3; 23). A simple method for producing a HTS coated conductor with reduced losses, and with improved critical current and critical magnetic field is thereby provided.
    Type: Application
    Filed: July 18, 2011
    Publication date: January 19, 2012
    Applicant: Bruker HTS GmbH
    Inventors: Klaus Schlenga, Alexander Usoskin
  • Publication number: 20120015817
    Abstract: A coated conductor is provided with improved electrical connection between the conductive layers such as the high temperature superconductor layer and a metal protection layer applied onto the high temperature superconductor layer and the substrate. A method includes obtaining such electrical connection, in particular, creating a coated conductor wherein the substrate is a core covered with the layers all around its periphery.
    Type: Application
    Filed: July 15, 2010
    Publication date: January 19, 2012
    Inventors: Arnaud Allais, Mark O. Rikel, Jürgen Ehrenberg
  • Publication number: 20110281734
    Abstract: Disclosed is a three layer process for making contact points to a high transition temperature superconductor (HTSC), particularly to (Bi,Pb)2 Sr2 Ca2 CU3019+x with and without silver in the superconductor. The contact structure is a three layer configuration with a perforated silver foil (3) sandwiched between two metal spray gun deposited silver layers (2,5) and subsequent heat treatment in air. The contact has been made on tubes and rods (1). The silver contacts are capable of carrying a continuous current of 200 Amps without adding any substantial heat load to the cryogen used to cool the HTSC. The contact resistance at 4.2K is in the range of 1.5×10(hoch?8) to 8.5? 10(hoch?8)OHM in zero applied filed.
    Type: Application
    Filed: July 23, 2010
    Publication date: November 17, 2011
    Inventors: Shrikant EKBOTE, Gursharan Kaur PADAM, Narendra Kumar ARORA, Mukul SHARMA, Ramesh SETHI, Mrinal Kanti BANERJEE
  • Publication number: 20110177952
    Abstract: A method is disclosed for making a template for a superconducting coil on a former (25) from a sheet (23) of flexible biaxially-textured material having at least two joining edges, the surface texture of the sheet being defined by a plurality of grains, and the former having a substantially curved surface. The method comprises the steps of shaping the sheet so that each joining edge lies adjacent to another joining edge on application of the sheet to the former, each joining edge and its adjacent edge being a pair of edges, and so that the sheet is dimensioned to cover a part of the surface of the former and substantially to fit that part of the former; positioning the sheet on the former so that regions of the sheet either side of the pair of edges have substantially aligned grains; and forming a join between the pair of edges, the template thereby having a substantially continuous textured surface across the join.
    Type: Application
    Filed: November 23, 2006
    Publication date: July 21, 2011
    Applicant: COATED CONDUCTOR CYLINDERS LTD
    Inventor: Eamonn Maher
  • Patent number: 7902119
    Abstract: Porous ceramic superconductors having a film thickness over 0.5 microns are provided. The superconducting material is applied to a vicinal substrate and optionally nanoparticles are inserted to release local strain. The resultant superconductors exhibit improved Jc values compared to nonvicinal (flat) counterparts and those having no nanoparticles.
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: March 8, 2011
    Inventors: Judy Wu, Rose Emergo, Timothy Haugan, Paul Barnes
  • Publication number: 20110034336
    Abstract: A superconducting article includes a substrate having a biaxially textured surface, and an epitaxial biaxially textured superconducting film supported by the substrate. The epitaxial superconducting film includes particles of Ba2RENbO6 and is characterized by a critical current density higher than 1 MA/cm2 at 77K, self-field. In one embodiment the particles are assembled into columns. The particles and nanocolumns of Ba2RENbO6 defects enhance flux pinning which results in improved critical current densities of the superconducting films. Methods of making superconducting films with Ba2RENbO6 defects are also disclosed.
    Type: Application
    Filed: August 4, 2010
    Publication date: February 10, 2011
    Inventors: Amit Goyal, Sung-Hun Wee, Eliot Specht, Claudia Cantoni
  • Publication number: 20110033674
    Abstract: A simple and controlled method to fabricate a 3D, epitaxial, biaxially textured nanofence comprised of single crystalline MgO nanobelt segments or links that grew both vertically and horizontally along <100> directions of the (100) STO substrate was developed. Continuous supply of Ni catalyst during the co-laser ablation of MgO and Ni metal led to the growth of nanobelts with such a unique morphology. Individual single crystalline MgO nanobelts had a square cross-section with high aspect ratios. X-ray diffraction results obtained from an entire MgO nanofence layer confirmed that MgO nanofence had epitaxial relation with STO substrate of [100]MgO?[100]STO. Such oxide nanofences can be used as a 3D biaxially-textured nanotemplate for epitaxial growth of wide-ranging, 3D, electronic, magnetic and electromagnetic nanodevices.
    Type: Application
    Filed: February 24, 2010
    Publication date: February 10, 2011
    Applicant: UT-BATTELLE, LLC
    Inventors: Amit Goyal, Sung-Hun Wee
  • Publication number: 20100323899
    Abstract: A superconductive element is described, comprising a rigid support made of a non-superconductive material, said support comprising at least one superconductive track formed by a groove containing a superconductive material having a density equal to at least 85% of the value of its theoretical density, and the process for producing said element. The present invention also relates to the possible uses of the superconductive elements, and also to superconductive devices comprising said superconductive elements.
    Type: Application
    Filed: June 14, 2010
    Publication date: December 23, 2010
    Applicant: EDISON S.p.A.
    Inventor: Giovanni Giunchi
  • Publication number: 20100216646
    Abstract: A process for preparing a superconductor article includes depositing a precursor solution onto a substrate to form a precursor film, the precursor solution comprising precursor components to a rare earth-alkaline earth metal-transition metal oxide in one or more solvents, decomposing the precursor film to form an intermediate film comprising the rare earth metal, the alkaline earth metal, and the transition metal of the first precursor solution, selectively removing portions of the intermediate film, wherein a patterned intermediate film is obtained, and treating the patterned intermediate film to form a rare earth-alkaline earth metal-transition metal oxide superconductor.
    Type: Application
    Filed: February 26, 2010
    Publication date: August 26, 2010
    Applicant: American Superconductor Corporation
    Inventors: Thomas Kodenkandath, Wei Zhang
  • Patent number: 7756557
    Abstract: An AC-tolerant high temperature superconductor tape with transposed filaments having two layers of high temperature superconducting material with striations and corresponding filaments and an insulating layer positioned therebetween.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: July 13, 2010
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Paul N. Barnes, Milan Polak, Chakrapani Varanasi
  • Patent number: 7749556
    Abstract: A method for manufacturing a field emission substrate is disclosed. The method includes the following steps: providing a substrate having a conductive layer; forming a hydrophobic layer on the conduction layer; patterning the hydrophobic layer; and removing the hydrophobic layer from the surface of the conductive layer so that the formed layer of electron-emitting materials can contact the surface of the conductive layer. The patterned hydrophobic layer can include plural bumps, and the pitches between the neighboring bumps are in a range of 1 ?m to 500 ?m. By way of the steps illustrated above, the emitting layer on the substrate can be made easily and arranged accurately. Hence, the electrons can be emitted homogeneously.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: July 6, 2010
    Assignees: Tatung Company, Industrial Technology Research Institute
    Inventors: Hung-Yung Li, Tsuey-May Yin, Tsai-Ling Ho
  • Publication number: 20100143660
    Abstract: A process for preparing a shaped substrate suitable in the production of coated conductors which process allows the deformation of a textured substrate onto which a textured buffer layer has been already grown.
    Type: Application
    Filed: June 3, 2009
    Publication date: June 10, 2010
    Inventors: Jurgen Ehrenberg, Mark Rikel
  • Patent number: 7723152
    Abstract: In the condition where a nozzle for applying a coating liquid is disposed on the lower side of a substrate and a substrate surface controlled in wettability is faced down, the nozzle and the substrate are moved relative to each other, whereby the coating liquid is applied to a desired region of the substrate, and then the coating liquid is dried, to obtain a pattern included a dried coating layer.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: May 25, 2010
    Assignee: Sony Corporation
    Inventor: Akihiro Nomoto
  • Patent number: 7695756
    Abstract: A tool for manufacturing molecular electronic devices having a coating unit contained in a controlled ambient environment. The coating unit is coupled to a source of active device molecules in solution. The coating unit is configured to apply a selected quantity of the solution to a surface of a substrate and the process tool processes the coated substrate in conditions that cause the active device molecules to attach to active areas of the substrate.
    Type: Grant
    Filed: April 29, 2004
    Date of Patent: April 13, 2010
    Assignee: ZettaCore, Inc.
    Inventors: Antonio R. Gallo, Werner G. Kuhr
  • Publication number: 20090233800
    Abstract: Under one aspect, a method of making a superconductor wire includes providing an oxide superconductor layer overlaying a substrate; forming a substantially continuous barrier layer over the oxide superconductor layer, the barrier layer including metal; depositing a layer of metal particles over the barrier layer, said depositing including applying a liquid including metal particles over the barrier layer; and sintering the layer of metal particles to form a substantially continuous metal layer over the barrier layer. In one or more embodiments, the oxide superconductor layer is oxygen-deficient, and the method may include oxidizing the oxygen-deficient oxide superconductor layer. At least a portion of the sintering and the oxidizing may occur simultaneously, for example by performing them at an oxygen partial pressure and a temperature sufficient to both sinter the metal particles and to oxidize the oxygen-deficient oxide superconductor layer.
    Type: Application
    Filed: March 23, 2007
    Publication date: September 17, 2009
    Applicant: American Superconductor Corporation
    Inventors: Yibing Huang, Thomas Kodenkandath, Joseph Lynch, Martin W. Rupich, Wei Zhang
  • Publication number: 20090099025
    Abstract: Superconducting connections are provided to internal layers of a multi-layer circuit board structure, for example by superconducting vias.
    Type: Application
    Filed: October 8, 2008
    Publication date: April 16, 2009
    Inventor: Sergey V. Uchaykin
  • Patent number: 7517834
    Abstract: The invention provides an improved method of manufacturing an HTS tape coil for an MRI device with enhanced protection, the method comprising attaching high-Q capacitors at each end of an HTS wire, removing substantially all electrically conductive sheathing material on an inner side of the HTS wire, while retaining substantially all electrically conductive sheathing material on an outer side of the HTS wire. The invention also provides an HTS wire made in accordance with the foregoing method.
    Type: Grant
    Filed: January 23, 2007
    Date of Patent: April 14, 2009
    Assignee: The University of Hong Kong
    Inventors: Yum Wing Wong, Edward S. Yang
  • Publication number: 20090048113
    Abstract: A superconducting thin film is disclosed having columnar pinning centers utilizing nano dots, and comprising nano dots (3) which are formed insularly on a substrate (2) and three-dimensionally in shape and composed of a material other than a superconducting material and also other than a material of which the substrate is formed, columnar defects (4) composed of the superconducting material and grown on the nano dots (3), respectively, a lattice defect (6) formed on a said columnar defect (4), and a thin film of the superconducting material (5) formed in those areas on the substrate which are other than those where said columnar defects are formed.
    Type: Application
    Filed: October 9, 2008
    Publication date: February 19, 2009
    Applicants: JAPAN SCIENCE AND TECHNOLOGY AGENCY, NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Ioan Adrian Crisan, Hideo Ihara, Yoshiko Ihara, Hideyo Ihara, Hidetaka Ihara, Gen-ei Ihara, Chiaki Ihara
  • Patent number: 7014727
    Abstract: A method of forming high resolution electronic circuits (10) on a substrate (12) is provided. The method includes the steps of laminating a dielectric layer (14) on a substrate (12), laser drilling channels (16 and 18) in the dielectric film (14) and the substrate (12), and filling channels (16 and 18) with a filler material (20). Further, a release layer (22) is applied to dielectric film layer (14) and filler material (20), the release layer (22) having an adhesive thereon. Release layer (22) is peeled or otherwise removed from substrate (12), leaving filler material (20) formed and shaped on substrate (12), thus producing a high resolution electronic circuit on substrate (12).
    Type: Grant
    Filed: July 7, 2003
    Date of Patent: March 21, 2006
    Assignees: Potomac Photonics, Inc., Parelec, Inc.
    Inventors: Christopher Wargo, Paul Kydd, Scott Mathews, Susan Gordon, legal representative, Chengping Zhang, Todd A. Kegresse, Michael Duignan, deceased
  • Patent number: 6882293
    Abstract: A Josephson junction has a Si substrate, a two layer film comprising an amorphous MgO layer and a high orientation MgO layer on the Si substrate, and a NbN film or the NbCN film laminated on the two layer film.
    Type: Grant
    Filed: August 21, 2003
    Date of Patent: April 19, 2005
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Akira Shoji, Hirotaka Yamamori
  • Patent number: 6830776
    Abstract: A method of manufacturing a high temperature superconductor is disclosed. The method includes depositing, by pulsed laser deposition, alternating layers of YBa2Cu3O7-x (Y123) and Y2BaCuO5-y (Y211). The Y211 layers are characterized by a multiplicity of nanosized globular inclusions, effectively enhancing flux pinning and thus increasing current transport.
    Type: Grant
    Filed: January 31, 2003
    Date of Patent: December 14, 2004
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Paul N. Barnes, Timothy J. Haugan
  • Patent number: 6638568
    Abstract: A method of curing cracks in a ceramic shaped body made from ceramic magnet materials or ceramic superconductor materials, in which a filling material which melts at a lower temperature than the material of the shaped body or is flowable at a lower temperature than the material of the shaped body is applied to the surface of the shaped body at least in the area of a crack and/or is introduced into at least one crack, in which the shaped body with the filling material is heated to and maintained at a temperature at which the material of the shaped body does not yet melt or is not yet flowable, but at which the filling material is in at least partially molten and flowable state at least until the fused filling material can penetrate at least partially into the crack, in which the filling material consists of non-metallic or essentially of non-metallic compounds and is at least partially crystallized, and in which the shaped body with the filling material is cooled, wherein the thermal crystallization conditions
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: October 28, 2003
    Assignee: Nexans Superconductors GmbH
    Inventors: Michael Baecker, Joachim Bock, Herbert C. Freyhardt, Andreas Leenders, Heribert Walter, Martin Ullrich
  • Publication number: 20030148066
    Abstract: Ion texturing methods and articles are disclosed.
    Type: Application
    Filed: July 30, 2001
    Publication date: August 7, 2003
    Inventors: Ronald P. Reade, Paul H. Berdahl, Richard E. Russo, Leslie G. Fritzemeier
  • Patent number: 6352741
    Abstract: High temperature superconductive (HTS) integrated circuits can be fabricated in three ways according to the invention. First, a planar multiple layer HTS integrated circuit is fabricated using multiple HTS layers. The layers include altered regions which have been bombarded using ion implantation to destroy superconductivity of the altered regions without interrupting the lattice structure of the altered regions. Second, a planar multiple-layer HTS integrated circuit includes upper and lower HTS layers, each including central and opposing regions. A first implant energy is used to destroy superconducting properties of the opposing regions of the lower HTS layer without interrupting the lattice structure. A second implant energy is used to destroy superconducting properties of a top portion of the central region to define a contact. Third, a HTS integrated circuit is formed from a single HTS layer using three ion implantation steps and ions having first, second and third energies and range.
    Type: Grant
    Filed: April 17, 1995
    Date of Patent: March 5, 2002
    Assignee: TRW Inc.
    Inventors: Hugo W. K. Chan, Arnold H. Silver
  • Publication number: 20010003118
    Abstract: The present invention relates to a SQUID made of an oxide superconducting thin film is formed on a sapphire substrate. CeO2 film, RBa2Cu3O7−x film (“R” indicates a rare earth element chosen among a group formed Yb, Er, Ho, Y, Dy, Gd, Eu, Sm and Nd) and SrTiO3 film are deposited the substrate top of sapphire successively. Furthermore, an oxide superconducting thin film to be a SQUID is deposited on the SrTiO3 film.
    Type: Application
    Filed: March 23, 1999
    Publication date: June 7, 2001
    Inventor: TATSUOKI NAGAISHI
  • Patent number: 6235685
    Abstract: A rod 1 made of superconducting oxide is soaked in a molten normal conductor 2 to join the rod 1 and the normal conductor 2, whereby a superconducting oxide current lead is prepared. As a result, a contact resistance at the interface between the superconducting oxide and the normal conductor can be reduced. Consequently, Joule's heat at a current lead having a small cross sectional area can be suppressed low, which in turn realizes the reduction of the load on a freezer and the amount of evaporated cooling solvent, with respect to a superconducting coil.
    Type: Grant
    Filed: November 15, 1999
    Date of Patent: May 22, 2001
    Assignee: International Superconductivity Technology Center
    Inventors: Junya Maeda, Teruo Izumi, Yuichi Imagawa, Satoshi Matsuoka, Yuh Shiohara, Shoji Tanaka, Hiroshi Okamoto
  • Patent number: 6147032
    Abstract: An implant patterned superconductive device and a method for indirect implant-patterning of oxide superconducting materials is provided. The method forms a device having an oxide superconducting layer on a substrate, deposits a passivation layer atop the oxide superconducting layer, and implants chemical impurities in a selected portion of the superconducting layer through the passivation layer. This modifies the conductivity of the selected portion of the oxide superconducting layer and electrically isolates the selected portion from the non-selected portion of the oxide superconducting layer. The passivation layer is made of a material less susceptible to implant damage than the oxide superconducting layer to allow inhibition of the oxide superconducting layer while protecting the crystalline structure of the top surface of the oxide superconducting layer and keeping it planarized.
    Type: Grant
    Filed: May 19, 1999
    Date of Patent: November 14, 2000
    Assignee: TRW Inc.
    Inventors: John R. LaGraff, Claire L. Pettiette-Hall, James M. Murduck, Hugo W-K. Chan
  • Patent number: 6110392
    Abstract: The invention is a process for reducing roughness of a surface of a superconductor material (23) having an undesirable surface roughness (30 and 32) and a trilayer superconductor integrated circuit (100). The process for reducing roughness of a surface of superconductor material having an undesirable surface roughness includes coating the surface with an oxide layer (40) to fill the undesirable surface roughness and to produce an exposed oxide surface (42) with a roughness less than the surface roughness; and etching the exposed oxide surface to remove a thickness of the oxide layer followed by removing at least a portion of the oxide layer filling the undesirable surface roughness and a portion of the surface of the superconductor material to produce an exposed etched surface (44) comprised of at least the superconductor material which has a surface roughness less than the undesirable surface roughness.
    Type: Grant
    Filed: September 18, 1998
    Date of Patent: August 29, 2000
    Assignee: TRW Inc.
    Inventors: George L. Kerber, Michael Leung
  • Patent number: 6066600
    Abstract: A high temperature superconductor junction and a method of forming the junction are disclosed. The junction 40 comprises a first high-T.sub.c superconductive layer (first base electrode layer) 46 on a substrate 42 and a dielectric layer 48 on the first high-T.sub.c superconductive layer. The dielectric layer and the first high-T.sub.c superconductive layer define a ramp edge 50. A trilayer SNS structure 52 is disposed on the ramp edge to form an SSNS junction. The SNS structure comprises a second high-T.sub.c superconductive layer (second base electrode layer) 54 directly on the first high-T.sub.c superconductive layer, a normal barrier layer 56 on the second high-T.sub.c superconductive layer, and a third high-T.sub.c superconductive layer 58 (counterelectrode) on the barrier layer. The ramp edge is typically formed by photoresist masking and ion-milling. A plasma etch step can be performed in-situ to remove the photoresist layer 62 following formation of the ramp edge.
    Type: Grant
    Filed: January 22, 1998
    Date of Patent: May 23, 2000
    Assignee: TRW Inc.
    Inventor: Hugo W. Chan
  • Patent number: 5981443
    Abstract: A bicrystal substrate is formed by joining end faces of a first single crystal substrate and a second single crystal substrate, the end faces having different crystal orientations. A high critical temperature superconducting thin film is then epitaxially formed on the bicrystal substrate. The superconducting thin film is etched so as to form a first superconducting electrode on the first single crystal substrate, a second superconducting electrode on the second single crystal substrate, and a superconducting bridge across a joint between the first and second single crystal substrates and connecting the first electrode and the second electrode. A conductive film is formed on the superconducting bridge by vapor deposition, and is then etched so as to form a weak link on a part of the superconducting bridge over the joint.
    Type: Grant
    Filed: August 26, 1998
    Date of Patent: November 9, 1999
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Zhongmin Wen
  • Patent number: 5942376
    Abstract: Solution films of a photosensitive metal arylketone alcoholate are micro-patterned by exposure to ultraviolet radiation under a mask. The resultant patterns are developed in an apolar solvent and annealed to provide thin film metal oxides for use in integrated circuits.
    Type: Grant
    Filed: August 14, 1997
    Date of Patent: August 24, 1999
    Assignees: Symetrix Corporation, Mitsubishi Materials Corporation
    Inventors: Hiroto Uchida, Nobuyuki Soyama, Kensuke Kageyama, Katsumi Ogi, Michael C. Scott, Larry D. McMillan, Carlos A. Paz de Araujo
  • Patent number: 5916848
    Abstract: An edge junction 10 with reduced parasitic inductance. The edge junction 10 has a laminar structure 22 including: a substrate 14; a first superconductive layer 12 deposited on a substrate 14; a first dielectric layer 16 deposited on the first superconductive layer 12; a second superconductive layer 18 deposited on the first dielectric layer 16; and a second dielectric layer 20 deposited on the second superconductive layer 18. The first and second superconductive layers 12 and 18 and the first and second dielectric layers 16 and 20 form a first laminar structure 22 having a planar segment 24 and a self-aligned ramp segment 26, the ramp segment 26 having a constantly-decreasing thickness and being connected to the planar segment 24 at an angle .theta. thereto.
    Type: Grant
    Filed: October 8, 1997
    Date of Patent: June 29, 1999
    Assignee: TRW Inc.
    Inventor: Dale J. Durand
  • Patent number: 5880069
    Abstract: A desired pattern is formed on a non-superconducting oxide film after the non-superconducting oxide film has been formed on a magnesia substrate. A superconducting oxide film is formed over the exposed parts of the substrate and the non-superconducting oxide film. The epitaxial orientation of the superconducting oxide film section on the non-superconducting oxide film is different from that of the superconducting oxide film section on the substrate. A tilt-boundary junction is produced at a boundary between the superconducting film sections which are different in epitaxial orientation from each other. Thus, a Josephson junction having a desired pattern can be obtained.
    Type: Grant
    Filed: February 1, 1994
    Date of Patent: March 9, 1999
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Masao Nakao, Hiroaki Furukawa, Ryohkan Yuasa, Shuji Fujiwara
  • Patent number: 5789346
    Abstract: Method for manufacturing a superconducting device including forming on a surface of a substrate a non-superconducting oxide layer, a first oxide superconductor thin film, etching the first oxide superconductor thin film so as to form a concave portion, implanting ions to the first oxide superconductor thin film at the bottom of the concave portion so as to form an insulating region such that the first oxide superconductor thin film is divided into two superconducting regions by the insulating region, and forming a second oxide superconductor thin film on the insulating region and the two superconducting regions, which is continuous to the two superconducting regions.
    Type: Grant
    Filed: May 20, 1996
    Date of Patent: August 4, 1998
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5786306
    Abstract: A method is provided for fabrication of superconducting oxides and superconducting oxide composites and for joining superconductors to other materials. A coating of a molten alloy containing the metallic elements of the oxide is applied to a substrate surface and oxidized to form the superconducting oxide. A material can be contacted to the molten alloy which is subsequently oxidized joining the material to the resulting superconducting oxide coating. Substrates of varied composition and shape can be coated or joined by this method.
    Type: Grant
    Filed: May 1, 1991
    Date of Patent: July 28, 1998
    Assignee: Massachusetts Institute of Technology
    Inventors: Wei Gao, John B. Vander Sande
  • Patent number: 5750474
    Abstract: A superconductor-insulator-superconductor Josephson tunnel junction, comprising: a single crystalline substrate having a perovskite crystal structure; a template layer formed of a b-axis oriented PBCO thin film on the substrate; and a trilayer structure consisting of a lower electrode, a barrier layer and an upper electrode, which serve as a superconductor, an insulator and a superconductor, respectively, the lower electrode and the upper electrode each being formed of an a-axis oriented YBCO superconducting thin film and having an oblique junction edge at an angle of 30.degree. to 70.degree., the barrier layer being formed of an insulating thin film between the two superconducting electrodes, can be operated at a low power with an exceptional speed in calculation and data processing.
    Type: Grant
    Filed: September 5, 1996
    Date of Patent: May 12, 1998
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Gun-Yong Sung, Jeong-Dae Suh
  • Patent number: 5739084
    Abstract: A method for fabricating a superconducting device with a substrate, a first oxide superconductor thin film, a barrier layer, a diffusion layer, and a second oxide superconductor thin film. The first oxide superconductor thin film with a very thin thickness is formed on the principal surface of the substrate. The barrier layer and the diffusion source layer are formed on a portion of the first oxide superconductor thin film. The second oxide superconductor thin film is grown on an exposed surface of the first oxide superconductor thin film until the barrier and diffusion source layers are embedded in the second oxide superconductor thin film, so that a material of the diffusion source layer is diffused into the second oxide superconductor thin film.
    Type: Grant
    Filed: January 2, 1997
    Date of Patent: April 14, 1998
    Assignee: Sumitomo Electric Industries Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
  • Patent number: 5683968
    Abstract: A superconducting device or a super-FET has a pair of superconducting electrode regions (20b, 20c) consisting of a thin film (20) oxide superconductor being deposited on a substrate (5) and a weak/ink region (20a), the superconducting electrode regions (20b, 20c) being positioned at opposite sides of the weak link region (20a), these superconducting electrode regions (20b, 20c) and the weak link region (20a) being formed on a common plane surface of the substrate (5). The weak link region (20a) is produced by local diffusion of constituent element(s) of the substrate (5) and/or a gate electrode insulating layer (16) into the thin film (20) of the oxide superconductor in such a manner that a substantial wall thickness of the thin film (20) of the oxide superconductor is reduced at the weak link region (20a) so as to leave a weak link or superconducting channel (10) in the thin film (20) of oxide superconductor over a non-superconducting region (50) which is produced by the diffusion.
    Type: Grant
    Filed: August 31, 1995
    Date of Patent: November 4, 1997
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama