Nonuniform Coating Patents (Class 427/63)
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Patent number: 6235685Abstract: A rod 1 made of superconducting oxide is soaked in a molten normal conductor 2 to join the rod 1 and the normal conductor 2, whereby a superconducting oxide current lead is prepared. As a result, a contact resistance at the interface between the superconducting oxide and the normal conductor can be reduced. Consequently, Joule's heat at a current lead having a small cross sectional area can be suppressed low, which in turn realizes the reduction of the load on a freezer and the amount of evaporated cooling solvent, with respect to a superconducting coil.Type: GrantFiled: November 15, 1999Date of Patent: May 22, 2001Assignee: International Superconductivity Technology CenterInventors: Junya Maeda, Teruo Izumi, Yuichi Imagawa, Satoshi Matsuoka, Yuh Shiohara, Shoji Tanaka, Hiroshi Okamoto
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Patent number: 6147032Abstract: An implant patterned superconductive device and a method for indirect implant-patterning of oxide superconducting materials is provided. The method forms a device having an oxide superconducting layer on a substrate, deposits a passivation layer atop the oxide superconducting layer, and implants chemical impurities in a selected portion of the superconducting layer through the passivation layer. This modifies the conductivity of the selected portion of the oxide superconducting layer and electrically isolates the selected portion from the non-selected portion of the oxide superconducting layer. The passivation layer is made of a material less susceptible to implant damage than the oxide superconducting layer to allow inhibition of the oxide superconducting layer while protecting the crystalline structure of the top surface of the oxide superconducting layer and keeping it planarized.Type: GrantFiled: May 19, 1999Date of Patent: November 14, 2000Assignee: TRW Inc.Inventors: John R. LaGraff, Claire L. Pettiette-Hall, James M. Murduck, Hugo W-K. Chan
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Patent number: 6110392Abstract: The invention is a process for reducing roughness of a surface of a superconductor material (23) having an undesirable surface roughness (30 and 32) and a trilayer superconductor integrated circuit (100). The process for reducing roughness of a surface of superconductor material having an undesirable surface roughness includes coating the surface with an oxide layer (40) to fill the undesirable surface roughness and to produce an exposed oxide surface (42) with a roughness less than the surface roughness; and etching the exposed oxide surface to remove a thickness of the oxide layer followed by removing at least a portion of the oxide layer filling the undesirable surface roughness and a portion of the surface of the superconductor material to produce an exposed etched surface (44) comprised of at least the superconductor material which has a surface roughness less than the undesirable surface roughness.Type: GrantFiled: September 18, 1998Date of Patent: August 29, 2000Assignee: TRW Inc.Inventors: George L. Kerber, Michael Leung
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Patent number: 6066600Abstract: A high temperature superconductor junction and a method of forming the junction are disclosed. The junction 40 comprises a first high-T.sub.c superconductive layer (first base electrode layer) 46 on a substrate 42 and a dielectric layer 48 on the first high-T.sub.c superconductive layer. The dielectric layer and the first high-T.sub.c superconductive layer define a ramp edge 50. A trilayer SNS structure 52 is disposed on the ramp edge to form an SSNS junction. The SNS structure comprises a second high-T.sub.c superconductive layer (second base electrode layer) 54 directly on the first high-T.sub.c superconductive layer, a normal barrier layer 56 on the second high-T.sub.c superconductive layer, and a third high-T.sub.c superconductive layer 58 (counterelectrode) on the barrier layer. The ramp edge is typically formed by photoresist masking and ion-milling. A plasma etch step can be performed in-situ to remove the photoresist layer 62 following formation of the ramp edge.Type: GrantFiled: January 22, 1998Date of Patent: May 23, 2000Assignee: TRW Inc.Inventor: Hugo W. Chan
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Patent number: 5981443Abstract: A bicrystal substrate is formed by joining end faces of a first single crystal substrate and a second single crystal substrate, the end faces having different crystal orientations. A high critical temperature superconducting thin film is then epitaxially formed on the bicrystal substrate. The superconducting thin film is etched so as to form a first superconducting electrode on the first single crystal substrate, a second superconducting electrode on the second single crystal substrate, and a superconducting bridge across a joint between the first and second single crystal substrates and connecting the first electrode and the second electrode. A conductive film is formed on the superconducting bridge by vapor deposition, and is then etched so as to form a weak link on a part of the superconducting bridge over the joint.Type: GrantFiled: August 26, 1998Date of Patent: November 9, 1999Assignee: Oki Electric Industry Co., Ltd.Inventor: Zhongmin Wen
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Patent number: 5942376Abstract: Solution films of a photosensitive metal arylketone alcoholate are micro-patterned by exposure to ultraviolet radiation under a mask. The resultant patterns are developed in an apolar solvent and annealed to provide thin film metal oxides for use in integrated circuits.Type: GrantFiled: August 14, 1997Date of Patent: August 24, 1999Assignees: Symetrix Corporation, Mitsubishi Materials CorporationInventors: Hiroto Uchida, Nobuyuki Soyama, Kensuke Kageyama, Katsumi Ogi, Michael C. Scott, Larry D. McMillan, Carlos A. Paz de Araujo
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Patent number: 5916848Abstract: An edge junction 10 with reduced parasitic inductance. The edge junction 10 has a laminar structure 22 including: a substrate 14; a first superconductive layer 12 deposited on a substrate 14; a first dielectric layer 16 deposited on the first superconductive layer 12; a second superconductive layer 18 deposited on the first dielectric layer 16; and a second dielectric layer 20 deposited on the second superconductive layer 18. The first and second superconductive layers 12 and 18 and the first and second dielectric layers 16 and 20 form a first laminar structure 22 having a planar segment 24 and a self-aligned ramp segment 26, the ramp segment 26 having a constantly-decreasing thickness and being connected to the planar segment 24 at an angle .theta. thereto.Type: GrantFiled: October 8, 1997Date of Patent: June 29, 1999Assignee: TRW Inc.Inventor: Dale J. Durand
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Patent number: 5880069Abstract: A desired pattern is formed on a non-superconducting oxide film after the non-superconducting oxide film has been formed on a magnesia substrate. A superconducting oxide film is formed over the exposed parts of the substrate and the non-superconducting oxide film. The epitaxial orientation of the superconducting oxide film section on the non-superconducting oxide film is different from that of the superconducting oxide film section on the substrate. A tilt-boundary junction is produced at a boundary between the superconducting film sections which are different in epitaxial orientation from each other. Thus, a Josephson junction having a desired pattern can be obtained.Type: GrantFiled: February 1, 1994Date of Patent: March 9, 1999Assignee: Sanyo Electric Co., Ltd.Inventors: Masao Nakao, Hiroaki Furukawa, Ryohkan Yuasa, Shuji Fujiwara
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Patent number: 5789346Abstract: Method for manufacturing a superconducting device including forming on a surface of a substrate a non-superconducting oxide layer, a first oxide superconductor thin film, etching the first oxide superconductor thin film so as to form a concave portion, implanting ions to the first oxide superconductor thin film at the bottom of the concave portion so as to form an insulating region such that the first oxide superconductor thin film is divided into two superconducting regions by the insulating region, and forming a second oxide superconductor thin film on the insulating region and the two superconducting regions, which is continuous to the two superconducting regions.Type: GrantFiled: May 20, 1996Date of Patent: August 4, 1998Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
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Patent number: 5786306Abstract: A method is provided for fabrication of superconducting oxides and superconducting oxide composites and for joining superconductors to other materials. A coating of a molten alloy containing the metallic elements of the oxide is applied to a substrate surface and oxidized to form the superconducting oxide. A material can be contacted to the molten alloy which is subsequently oxidized joining the material to the resulting superconducting oxide coating. Substrates of varied composition and shape can be coated or joined by this method.Type: GrantFiled: May 1, 1991Date of Patent: July 28, 1998Assignee: Massachusetts Institute of TechnologyInventors: Wei Gao, John B. Vander Sande
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Patent number: 5750474Abstract: A superconductor-insulator-superconductor Josephson tunnel junction, comprising: a single crystalline substrate having a perovskite crystal structure; a template layer formed of a b-axis oriented PBCO thin film on the substrate; and a trilayer structure consisting of a lower electrode, a barrier layer and an upper electrode, which serve as a superconductor, an insulator and a superconductor, respectively, the lower electrode and the upper electrode each being formed of an a-axis oriented YBCO superconducting thin film and having an oblique junction edge at an angle of 30.degree. to 70.degree., the barrier layer being formed of an insulating thin film between the two superconducting electrodes, can be operated at a low power with an exceptional speed in calculation and data processing.Type: GrantFiled: September 5, 1996Date of Patent: May 12, 1998Assignee: Electronics and Telecommunications Research InstituteInventors: Gun-Yong Sung, Jeong-Dae Suh
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Patent number: 5739084Abstract: A method for fabricating a superconducting device with a substrate, a first oxide superconductor thin film, a barrier layer, a diffusion layer, and a second oxide superconductor thin film. The first oxide superconductor thin film with a very thin thickness is formed on the principal surface of the substrate. The barrier layer and the diffusion source layer are formed on a portion of the first oxide superconductor thin film. The second oxide superconductor thin film is grown on an exposed surface of the first oxide superconductor thin film until the barrier and diffusion source layers are embedded in the second oxide superconductor thin film, so that a material of the diffusion source layer is diffused into the second oxide superconductor thin film.Type: GrantFiled: January 2, 1997Date of Patent: April 14, 1998Assignee: Sumitomo Electric Industries Ltd.Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
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Patent number: 5683968Abstract: A superconducting device or a super-FET has a pair of superconducting electrode regions (20b, 20c) consisting of a thin film (20) oxide superconductor being deposited on a substrate (5) and a weak/ink region (20a), the superconducting electrode regions (20b, 20c) being positioned at opposite sides of the weak link region (20a), these superconducting electrode regions (20b, 20c) and the weak link region (20a) being formed on a common plane surface of the substrate (5). The weak link region (20a) is produced by local diffusion of constituent element(s) of the substrate (5) and/or a gate electrode insulating layer (16) into the thin film (20) of the oxide superconductor in such a manner that a substantial wall thickness of the thin film (20) of the oxide superconductor is reduced at the weak link region (20a) so as to leave a weak link or superconducting channel (10) in the thin film (20) of oxide superconductor over a non-superconducting region (50) which is produced by the diffusion.Type: GrantFiled: August 31, 1995Date of Patent: November 4, 1997Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
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Patent number: 5672569Abstract: A superconducting circuit having patterned superconducting wiring lines. Each wiring line consists of at least one portion (2') of the thin film (2) of an oxide superconductor deposited on a substrate (1). The portion (2') has a predetermined crystal orientation and the remaining portions (2") have a different crystal orientation or changed to non-superconductor. The superconducting circuit has a planar surface.In variations, two different wiring lines (21, 22) each having a different crystal orientation are produced at different portions of a thin film of oxide superconductor, so that superconducting current flow separately through two different portions in a common thin film.Type: GrantFiled: March 8, 1995Date of Patent: September 30, 1997Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
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Patent number: 5670204Abstract: Nb--Sn precursor articles are described that include a Nb alloy article that is at least partially coated with a layer of a Sn alloy, such as a Sn--Cu alloy. The precursor articles described herein have a controlled concentration of the impurity elements As and S in the Sn alloy layer. The concentration of these elements in the Sn alloy layer is less than or equal to 50 ppm by weight. This invention also describes a method for making Nb--Sn precursor articles having a controlled concentration of As and S impurities.Type: GrantFiled: June 26, 1995Date of Patent: September 23, 1997Assignee: General Electric CompanyInventors: Melissa Lea Murray, Bruce Alan Knudsen, Christopher Gus King, Mark Gilbert Benz, Robert John Zabala, Anthony Mantone
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Patent number: 5650377Abstract: Fine epitaxial patterns of yttrium barium copper oxide on a strontium titanate substrate are provided by using a silicon nitride mask to define the pattern to be formed. A thin film of yttrium barium copper oxide is placed on the silicon nitride mask and exposed portions of strontium titanate substrate. Where the yttrium barium copper oxide is in contact with the silicon nitride mask, it is nonepitaxial in crystal structure. Where the yttrium barium copper oxide contacts the strontium titanate substrate in the openings, it is epitaxial in structure forming fine patterns that become superconducting below the critical transition temperature. A channel can be formed in the strontium titanate substrate. The epitaxial yttrium barium copper oxide pattern is formed in this channel to minimize possible exposure to the silicon nitride mask.Type: GrantFiled: October 5, 1993Date of Patent: July 22, 1997Assignee: International Business Machines CorporationInventors: Dieter Paul Kern, Robert Benjamin Laibowitz, Kim Yang Lee, Mark I. Lutwyche
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Patent number: 5648320Abstract: Circuit board devices are provided based on use of high temperature superconducting ceramic polymers comprising high temperature superconducting ceramic powders distributed in electrically insulative organic polymers which are thermosetting by reaction of a two-part liquid mixture or by catalytic or photoinitiation of a one-part liquid. The ceramic domains transmit their superconductivity across the insulating barriers of organic polymers enabling formation of superconductive lines and superconducting bonds to electronic devices to be adhered to circuit boards, and providing superconducting circuitry.Type: GrantFiled: April 14, 1995Date of Patent: July 15, 1997Inventor: Richard L. Jacobs
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Patent number: 5646096Abstract: Patterned superconducting wiring lines each consisting of a portion of a thin film of an oxide superconductor deposited on a flat substrate, the portion having a predetermined crystal orientation (a-axis or c-axis orientation) with respect to a flat surface of the substrate, remaining portions of the thin film of the oxide superconductor having a different crystal orientation (c-axis or a-axis orientation) from the portion and/or consisting of an insulation zones. Both of the portion and the remaining portions have a substantially identical thickness so that the thin film has a substantially flat planar surface.Type: GrantFiled: June 7, 1995Date of Patent: July 8, 1997Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hiroshi Inada, Takao Nakamura, Mitchimoto Iiyama
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Patent number: 5637555Abstract: A method for manufacturing a three-terminal superconducting device is disclosed. A superconducting channel constituted in an oxide superconductor thin film is deposited on a deposition surface of a substrate. A gate electrode for the device is formed through a gate insulator layer on the superconducting channel of the device. The steps of forming the gate electrode include forming a thin film that stands upright with respect to the insulator layer for the gate.Type: GrantFiled: August 23, 1995Date of Patent: June 10, 1997Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
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Patent number: 5612291Abstract: A superconductive device for helping shield magnetic field comprises at least two members; a layer containing superconductive oxide over each of said members; means for connecting said members to form a substrate; and means for connecting said layers containing superconductive oxide along a joint in which said members are connected.Type: GrantFiled: April 20, 1994Date of Patent: March 18, 1997Assignee: NGK Insulators, Ltd.Inventors: Shoji Seike, Hideki Shimizu, Makoto Tani
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Patent number: 5595959Abstract: A method of forming a high-Tc microbridge superconductor device is disclosed, which comprises the steps of forming an inclined step on the surface of a substrate, the inclined step having an angle of inclination of from about 20 to about 80 degrees; depositing a layer of c-axis oriented superconductor material overlying the substrate such that there is a break in the layer of superconductor material at the inclined step; and depositing a layer of normal material overlying the layer of c-axis oriented superconductor material.Type: GrantFiled: November 22, 1994Date of Patent: January 21, 1997Assignee: Biomagnetic Technologies, Inc.Inventors: Mark S. DiIorio, Shozo Yoshizumi, Kai-Yuen Yang
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Patent number: 5594257Abstract: A superconducting device comprises a substrate having a principal surface, a non-superconducting oxide layer having a similar crystal structure to that of an oxide superconductor formed on the principal surface, which can compensates the lattice mismatch between the substrate and the oxide superconductor, a superconducting source region and a superconducting drain region formed of c-axis oriented oxide superconductor thin films on the non-superconducting oxide layer, and an insulating region formed of a doped oxide superconductor on the non-superconducting oxide layer separating the superconducting source region and the superconducting drain region between them. On the insulating region an extremely thin superconducting channel formed of a c-axis oriented oxide superconductor thin film is arranged.Type: GrantFiled: June 24, 1993Date of Patent: January 14, 1997Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Michitomo Iiyama
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Patent number: 5582877Abstract: A process for fabricating the Josephson junction includes the steps of preparing a substrate, forming a first superconducting layer, forming a second superconducting layer transversely on the first layer with an insulating layer interposed therebetween wherein the insulating layer is an oxide or nitride of the superconducting material, and injecting ion beams into the insulating layer so as to form low oxygen- or nitrogen-concentrated area linking the first and second layers.Type: GrantFiled: February 24, 1995Date of Patent: December 10, 1996Assignee: Shimadzu CorporationInventors: Shinji Nagamachi, Masahiro Ueda, Kei Shinada, Mitsuyoshi Yoshii
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Patent number: 5567674Abstract: A thin film of oxide superconductor consisting of more than two portions (1, 11, 12) each possessing a predetermined crystal orientation and deposited on a common surface of a substrate (2). At least one selected portion (10) of thin film of oxide superconductor is deposited on a thin under-layer (4, 100) which facilitates crystal growth of selected portions and which is deposited previously on the substrate. The selected portions (10) may consist of a-axis oriented thin film portions while non-selected portions (11, 12) may consists of c-axis oriented thin film portions. The thin under-layer can be a buffer layer (4) or a very thin film (100) of oxide superconductor.Type: GrantFiled: June 7, 1995Date of Patent: October 22, 1996Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hiroshi Inada, Michitomo Iiyama
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Patent number: 5552375Abstract: Disclosed are methods of forming superconducting devices including a type having a structure of a superconductor--a normal-conductor (or a semiconductor)--a superconductor, and a type having a superconducting weak-link portion between superconductors.The superconductors constituting the superconducting device are made of an oxide of either of perovskite type and K.sub.2 NiF.sub.4 type crystalline structures, containing at least one element selected from the group consisting of Ba, Sr, Ca, Mg, and Ra; at least one element selected from the group consisting of La, Y, Ce, Sc, Sm, Eu, Er, Gd, Ho, Yb, Nd, Pr, Lu, and Tb; Cu; and O. In addition, the c-axis of the crystal of the superconductor is substantially perpendicular to the direction of current flowing through this superconductor.Type: GrantFiled: February 7, 1994Date of Patent: September 3, 1996Assignee: Hitachi, Ltd.Inventors: Toshikazu Nishino, Ushio Kawabe, Yoshinobu Tarutani, Shinya Kominami, Toshiyuki Aida, Tokuumi Fukazawa, Mutsuko Hatano
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Patent number: 5547923Abstract: For manufacturing a superconducting device, a first oxide superconductor thin film having a very thin thickness is formed on a principal surface of a substrate, and a stacked structure of a gate insulator and a gate electrode is formed on a portion of the first oxide superconductor thin film. A second oxide superconductor thin film is grown on an exposed surface of the first oxide superconductor thin film, using the gate electrode as a mask, so that first and second superconducting regions having a relatively thick thickness are formed at opposite sides of the gate electrode, electrically isolated from the gate electrode. A source electrode and a drain electrode is formed on the first and second oxide superconducting regions. The superconducting device thus formed can functions as a super-FET.Type: GrantFiled: June 7, 1995Date of Patent: August 20, 1996Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
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Patent number: 5547922Abstract: Superconductivity is inhibited in selected regions of a HTS material by subjecting the material to impurity ion bombardment at an energy level selected to implant ions in the material at a selected depth. The concentration of deposited ions varies with depth in the material according to a peaked depth distribution function which has a maximum at the selected depth. The material may be masked before implantation. After low temperature annealing, the material loses its superconducting characteristics in the selected regions but such characteristics are preserved at depths above and below the selected depth. The material's crystalline structure is preserved so additional layers can be epitaxially grown atop the inhibited material Multilayer HTS devices and circuits may be made by repeating the ion implantation and/or masking steps at with different ion energy levels.Type: GrantFiled: February 17, 1995Date of Patent: August 20, 1996Assignee: The University of British ColumbiaInventor: Qi Y. Ma
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Patent number: 5539215Abstract: A superconducting device comprising a substrate having a principal surface, a non-superconducting oxide layer having a similar crystal structure to that of the oxide superconductor, a first and a second superconducting regions formed of c-axis oriented oxide superconductor thin films on the non-superconducting oxide layer separated from each other and gently inclining to each other, a third superconducting region formed of an extremely thin c-axis oriented oxide superconductor thin film between the first and the second superconducting regions, which is continuous to the first and the second superconducting regions.Type: GrantFiled: December 29, 1994Date of Patent: July 23, 1996Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
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Patent number: 5536471Abstract: A bubble flushing syringe for aspirating and dispensing fluids through an open-ended tip with precision and volumetric accuracy is disclosed. The syringe comprises a piston within a bore formed by a generally cylindrical wall having a closed end and an open end, wherein the piston forms an annulus with the wall and closed end of the bore, and is capable of reciprocating therein. The syringe further comprises an annular seal seated in the open end of the bore and circumventing the piston to close the annulus sufficiently snug to retain fluid when the piston reciprocates therethrough. An inlet for directing fluid to the annulus through the wall of the bore and an outlet for directing fluid from the annulus through the wall of the bore to the open-ended tip are positioned proximal to the annular seal and the line generally axially therebetween. A drive device is connected to the piston for reciprocating the piston within the bore.Type: GrantFiled: January 3, 1994Date of Patent: July 16, 1996Assignee: Abbott LaboratoriesInventors: Frederic L. Clark, Richard R. Martin, Donny R. Walker
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Patent number: 5528052Abstract: Proposed is a method for operating a field-effect device comprised of a superconducting current channel having source and drain electrodes connected thereto, said superconducting current channel being separated from a gate electrode by an insulating layer, where the resistance of said current channel is controlled by varying the critical current of the superconducting material through the application of an electrical field across the superconducting current channel, which in turn changes the density of the mobile charge carriers in the superconducting material. Taught is also an inverted MISFET device for performing that method, the device being characterized in that on an electrically conductive substrate an insulating layer is provided which in turn carries a layer consisting of a superconducting material, and that a gate electrode is attached to said substrate, and source and drain electrodes are electrically connected to said superconductor layer.Type: GrantFiled: December 22, 1993Date of Patent: June 18, 1996Assignee: International Business Machines CorporationInventors: Johannes G. Bednorz, Jochen D. Mannhart, Carl A. Mueller, Darrell G. Schlom
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Patent number: 5525582Abstract: A Josephson junction device comprising a single crystalline substrate including a principal surface, a layer of the same material as the substrate formed on the principal surface of the substrate so as to form a step on the principal surface, and an oxide superconductor thin film formed on the principal surface of the substrate. The oxide superconductor thin film includes a first and a second superconducting portions respectively positioned above and below the step, which are constituted of single crystals of the oxide superconductor, a junction portion between the first and the second superconducting portions, which is constituted of a single crystal of the oxide superconductor of which crystal orientation is different from those of the first and second superconducting portions, and grain boundaries between the first superconducting portion and the junction portion and between the second superconducting portion and the junction portion, which constitute one weak link of the Josephson junction.Type: GrantFiled: October 20, 1994Date of Patent: June 11, 1996Assignee: Sumitomo Electric Industries, Ltd.Inventors: Saburo Tanaka, Takashi Matsuura, Hideo Itozaki
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Patent number: 5514877Abstract: A superconducting device or a super-FET has a pair of superconducting electrode regions (20b,20c) consisting of a thin film (20)oxide superconductor being deposited on a substrate (5) and a weak link region (20a), the superconducting electrode regions (20b, 20c) being positioned at opposite sides of the weak link region (20a) these superconducting electrode regions (20b, 20c) and the weak link region (20a) being formed on a common plane surface of the substrate (5). The weak link region (20a) is produced by local diffusion of constituent element(s) of the substrate (5) into the thin film (20) of the oxide superconductor in such a manner that a substantial wall thickness of the thin film (20) of the oxide superconductor is reduced at the weak link region (20a) so as to leave a weak link or superconducting channel (10) in the thin film (20) of oxide superconductor over a non-superconducting region (50) which is produced by the diffusion.Type: GrantFiled: January 21, 1994Date of Patent: May 7, 1996Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
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Patent number: 5512540Abstract: A manufacturing method of a superconducting pattern is described. A superconducting ceramic film is deposited on a non-conductive surface and partly spoiled in order to form a barrier film by which two superconducting regions is separated. The spoiling is performed by adding a spoiling element into the ceramic film by ion implantation.Type: GrantFiled: October 14, 1994Date of Patent: April 30, 1996Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 5510324Abstract: The invention relates to a method of manufacturing a superconducting device, which comprises the steps of forming on a principal surface of a substrate a non-superconducting oxide layer having a similar crystal structure to that of a c-axis oriented oxide superconductor thin film and a flat-top projection at its center portion, forming a c-axis oriented oxide superconductor thin film having an extremely thin thickness on the non-superconducting oxide layer so as to form a superconducting channel on the projecting portion of the non-superconducting oxide layer, forming an insulating layer on the c-axis oriented oxide superconductor thin film so as to form a gate insulating layer on the superconducting channel, and forming an a-axis oriented oxide superconductor thin film so as to form a superconducting source region and a superconducting drain region of which upper surfaces have the same level as that of the superconducting channel.Type: GrantFiled: December 2, 1994Date of Patent: April 23, 1996Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Michitomo Iiyama, Hiroshi Inada
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Patent number: 5494891Abstract: A superconducting device comprises a substrate, a non-superconducting layer formed in a principal surface of said substrate, an extremely thin superconducting channel formed of an oxide superconductor thin film on the non-superconducting layer. A superconducting source region and a superconducting drain region of a relatively thick thickness are formed of the oxide superconductor at the both sides of the superconducting channel separated from each other but electrically connected through the superconducting channel, so that a superconducting current can flow through the superconducting channel between the superconducting source region and the superconducting drain region.Type: GrantFiled: December 6, 1994Date of Patent: February 27, 1996Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Michitomo Iiyama
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Patent number: 5480861Abstract: A layered structure formed on a substrate comprising an oxide superconductor thin film deposited on the substrate, a noble metal monolayer deposited on the oxide superconductor thin film and an insulator thin film deposited on the noble metal monolayer. The noble metal monolayer prevents interdiffusion between the oxide superconductor thin film and the insulator thin film so that they have excellent properties.Type: GrantFiled: July 14, 1994Date of Patent: January 2, 1996Assignee: Sumitomo Electric Industries Ltd.Inventors: So Tanaka, Michitomo Iiyama
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Patent number: 5471069Abstract: A superconducting device includes a superconducting channel constituted in an oxide superconductor the film deposited on a deposition surface of a substrate. A source electrode and a drain electrode are formed on the oxide superconductor thin film at opposite ends of the superconducting channel, so that a superconducting current can flow through be superconducting channel between the superconductor source electrode and the superconductor drain electrode. A gate electrode is formed through a gate insulator layer on the superconducting channel so as to control the superconducting current flowing through the superconducting channel. The gate electrode is in the form of a thin film and stands upright with respect to the gate insulator layer.Type: GrantFiled: May 13, 1994Date of Patent: November 28, 1995Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
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Patent number: 5468723Abstract: A superconducting device has a structure of superconductor--normal--conductor (semiconductor)--superconductor. The superconducting regions and the normal-conductor region can be made of the same elements but having different relative proportions of the elements. The device can be fabricated by introducing at least one element into an unmasked region of the superconductor to form a normal conductor region or into unmasked regions of the normal conductor to form superconductor regions.Type: GrantFiled: May 4, 1994Date of Patent: November 21, 1995Assignee: Hitachi, Ltd.Inventors: Toshikazu Nishino, Haruhiro Hasegawa, Ushio Kawabe
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Patent number: 5466664Abstract: A method of manufacturing a superconducting device involves forming a thin film on the surface of a substrate, forming a superconducting gate electrode on a portion of the thin film, etching the portions of the thin film using the gate electrode as a mask thereby providing a superconducting channel under the gate, forming a step portion on the superconducting channel and under the gate, converting the oxide portion of the step portion into a gate insulation portion by heating the substrate in a vacuum, forming a second oxide superconducting film on the exposed surface of the channel so that superconducting source and drain electrodes are formed on each side of the gate such that the drain and source have a thickness greater than that of the channel and are electrically isolated from the gate electrode.Type: GrantFiled: July 26, 1994Date of Patent: November 14, 1995Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hiroshi Inada, Takao Nakamura, Michitomo Iiyama
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Patent number: 5466480Abstract: Three-dimensional RF coils suitable for use in NMR spectroscopy or imaging are described, as well as methods for making such coils. The coil is made from a thin-walled, non-magnetic, electrically insulating tube. The tube is then masked and a first conducting layer is applied, e.g., by evaporation. An additional insulating layer is provided on top of the first conducting layer, and then a second conducting layer is applied. An optional additional insulating layer may then be applied over the second conducting layer. The first and second conducting layer, in combination, are electrically connected to form a self-resonant structure at the selected frequency of the NMR apparatus. The coil may be fine-tuned conventionally by means of a series or parallel capacitor, or by changing the position of a conductive ring around the outside of the coil. Alternately, two tubes may be used, with only one conducting layer deposited on each.Type: GrantFiled: November 12, 1993Date of Patent: November 14, 1995Assignee: University of FloridaInventors: Dawei Zhou, Thomas Mareci, Michael Burns, Ward Ruby
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Patent number: 5462762Abstract: A method of fabricating a superconducting quantum interference device (DC-SQUID) constructed from short weak links with untrafine wires. The method comprises the following steps: successive forming a niobium nitride film and a silicon nitride film on a substrate; oblique etching of the niobium nitride film and said silicon nitride film with respect to the substrate by a reactive ion etching process using a mixture of oxygen and CF.sub.4 gases to form an olique edge; and successive forming a barrier thin film and a counterelectrode of niobium on the said edge. The short weak links wire fabricated by field evaporation technique. The counterelectrode material were field-evaporated and formed the conductive paths in the pinholes in the insulating thin film.Type: GrantFiled: June 13, 1994Date of Patent: October 31, 1995Assignee: Shinko Electric Industries Co., Ltd.Inventors: Yoshio Onuma, Katsuyoshi Hamasaki
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Patent number: 5455451Abstract: Superconductized electronic devices, such as a Josephson junction device, or superconductized optical devices represented by a light emitting and receiving devices of semiconductor laser are available using semiconductor materials which normally have no superconducting characteristics. The devices can operate by controlling the behavior of a Cooper pair in an active region which is formed in the semiconductor in advance using the penetrating phenomenon of the Cooper pair caused in the semiconductor proximate to the superconductor.Type: GrantFiled: April 22, 1993Date of Patent: October 3, 1995Assignee: Hitachi, Ltd.Inventors: Toshiyuki Usagawa, Masashi Kawasaki, Kensuke Ogawa, Toshiyuki Aida
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Patent number: 5446016Abstract: A method for forming a patterned oxide superconductor thin film on a substrate comprises steps of forming a metal or semi-metal layer on a portion of the substrate, on which the oxide superconductor thin film will be formed, forming a layer of a material including silicon on a portion of the substrate, on which an insulating layer will be formed, removing the metal or semi-metal layer and depositing an oxide superconductor thin film over the substrate.Type: GrantFiled: February 15, 1994Date of Patent: August 29, 1995Assignee: Sumitomo Electric Industries, Ltd.Inventors: So Tanaka, Takao Nakamura, Michitomo Iiyama
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Patent number: 5441926Abstract: A superconducting transistor having a source region and a drain region are formed by a YBCO film on a barrier layer, which is composed of a PBCO film formed on an STO substrate. A gate electrode is disposed on the thinner wall at the back of the STO substrate. In a superconducting transistor so constructed the electric field created by the gate voltage works effectively at an interface with the barrier layer, more carriers can be drawn out relative to the applied gate voltage, and it becomes possible for a large superconduction current to flow.Type: GrantFiled: November 12, 1993Date of Patent: August 15, 1995Assignee: Fuji Electric Co., Ltd.Inventors: Hiroshi Kimura, Toshiyuki Matsui, Takeshi Suzuki, Kazuo Mukae, Akihiko Ohi
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Patent number: 5434127Abstract: For manufacturing a superconducting device, a first c-axis orientated oxide superconductor thin film having a very thin thickness is formed on a principal surface of a substrate, and a stacked structure of a gate insulator and a gate electrode is formed on a portion of the first oxide superconductor thin film. An a-axis orientated oxide superconductor thin film is grown, using the gate electrode as a mask, so that second and third superconducting regions having a relatively thick thickness are formed at both sides of the gate electrode, electrically isolated from the gate electrode. The superconducting device thus formed can functions as a super-FET.Type: GrantFiled: July 25, 1994Date of Patent: July 18, 1995Assignee: Sumitomo Electric Industries, ltd.Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
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Patent number: 5432149Abstract: A weak link is patterned from a high-temperature superconducting film using standard lithographic techniques. Once the area in which the weak link is to be located is defined, the remainder of the film is covered with an oxygen-impermeable material. The oxygen is then removed in the weak link area by placing the sample in a vacuum furnace at a sufficient temperature to drive out the oxygen. Once the oxygen is removed, the weak link becomes non-superconducting. A high power solid state laser is placed in front of the weak link, and superconductivity is restored in the weak link area, in situ. The process is performed in a liquid nitrogen environment.Type: GrantFiled: April 8, 1994Date of Patent: July 11, 1995Assignee: Regents of the University of CaliforniaInventors: Ivan K. Schuller, Gladys L. Nieva, Julio J. Guimpel, Eduardo Osquiguil, Yvan Bruynseraede
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Patent number: 5430011Abstract: A superconducting thin film formed on a substrate, comprising at least one oxide superconductor layer formed on the principal surface of said substrate and at least one oxide layer formed of an oxide which compensates for crystalline incompleteness at the surface of said oxide superconductor layer, and which is arranged on or under the superconducting layer.Type: GrantFiled: September 17, 1992Date of Patent: July 4, 1995Assignee: Sumitomi Electric Industries, Ltd.Inventors: So Tanaka, Michitomo Iiyama
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Patent number: 5422336Abstract: A superconducting transistor with superior withstand voltage having source region and a drain region formed of oxide superconductors 3, a PrBa.sub.2 Cu.sub.3 O.sub.7-x layer 2 or an ScBa.sub.2 Cu.sub.3 O.sub.7-x layer 2 forming an intermediate region sandwiched by the source and drain regions. The regions are disposed on a substrate 1. An insulation layer 4 is disposed on the intermediate region. A transistor uses the intermediate region as an insulator when the gate is turned off, and as a superconductor when the gate is turned on.Type: GrantFiled: September 22, 1993Date of Patent: June 6, 1995Assignee: Fuji Electric Co., Ltd.Inventors: Koichi Tsuda, Toshiyuki Matsui, Takeshi Suzuki, Hiroshi Kimura, Takashi Ishii, Akihiko Ohi, Kazuo Mukae
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Patent number: 5420101Abstract: The invention relates to a structured superconductive track and a process for making it from epitaxial high temperature superconductor (HTSC) layers using lift off technique, in which a HTSC track deposited on an elevated substrate region is surrounded by an insulating layer of doped HTSC lying on a lower substrate region, and the substrate region with the superconductive track formed thereon is elevated such that the superconductive track is isolated from the insulating layer.Type: GrantFiled: December 23, 1993Date of Patent: May 30, 1995Assignee: Forschungszentrum Julich GmbHInventors: Carlo Copetti, Jurgen Schubert, Willi Zander, Christoph Buchal
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Patent number: 5416063Abstract: Disclosed is a method for forming a superconductive oxide layer on a substrate. The method comprises applying a precursor solution to a major surface of the substrate such that a metal-containing layer is formed on the surface, and heat treating the substrate/layer combination such that at least a substantial portion of the layer material is transformed into superconductive oxide. Exemplarily, the precursor solution is formed by dissolving Ba--, Y--, and Cu-containing compounds in acetic acid and water, spinning the solution on a MgO substrate, driving of unwanted constituents of the resulting layer at 400.degree. C., heating the combination to about 830.degree. C. in O.sub.2 such that the (perovskite) phase that is associated with superconductivity in YBa.sub.2 Cu.sub.3 O.sub.7 is formed, and oxygenating the layer at about 400.degree. C. in O.sub.2.Type: GrantFiled: November 30, 1987Date of Patent: May 16, 1995Assignee: AT&T Corp.Inventors: Michal E. Gross, Catherine E. Rice