Discontinuous Surface Component Patents (Class 428/601)
  • Patent number: 6733899
    Abstract: There are provided a step of forming a structure in which a first concave portion is formed in a predetermined portion on one surface of a metal plate and also a convex portion that protrudes from other surface of the metal plate is formed by formation of the first concave portion and a second concave portion is formed in a predetermined portion on an outside of a peripheral portion of the convex portion, by shaping the metal plate by means of stamping using a die, and a step of cutting the convex portion formed on the other surface of the metal plate.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: May 11, 2004
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Sumio Uehara, Yoshihisa Nagamine, Toshifumi Iizuka
  • Patent number: 6703697
    Abstract: An electronic package with improved power delivery performance, lowering the impedance associated with the power delivery. The electronic package includes an integrated circuit die mounted on the substrate of the electronic package and decoupling capacitors placed underneath the substrate. The package further includes stand-offs placed underneath the substrate, sized for maintaining a distance between the capacitors and another substrate.
    Type: Grant
    Filed: December 7, 2001
    Date of Patent: March 9, 2004
    Assignee: Intel Corporation
    Inventors: Anne Leahy, Ajit Sathe
  • Patent number: 6673470
    Abstract: A surface treated tin-plated steel sheet which has an alloy layer formed on the surface of a steel sheet, a tin plating layer being formed on said alloy layer with a remaining exposed portion of the alloy layer having an area of 30% or more of that of the alloy layer and, formed on said tin plating layer and said exposed portion of the alloy layer, a coating film containing P and Si in an amount of 0.5 to 100 mg/m2 and 0.1 to 250 mg/m2, respectively; and a chemical treatment solution for use in preparing the steel sheet which comprises a phosphate ion, a tin ion and a silane coupling agent and has a pH of 1.5 to 5.5. The surface treated tin-plated steel sheet is free from chromium which causes problems from an environmental view point, and also is excellent in adhesion with a paint, corrosion resistance after being coated, rust resistance, and formability.
    Type: Grant
    Filed: July 8, 2002
    Date of Patent: January 6, 2004
    Assignee: Kawasaki Steel Corporation
    Inventors: Tomofumi Shigekuni, Hisatada Nakakoji, Kazuo Mochizuki, Chiaki Kato
  • Publication number: 20030228542
    Abstract: A magnetic material structure is provided according to the present invention that is capable of being lithographically patterned for various uses, such as, but not limited to, magnetic read/write devices. The magnetic material structure includes a layer of magnetic material provided on a wafer or other substrate, a layer of non-magnetic material provided on top of the layer of magnetic material, and a layer of soft magnetic material provided on top of the layer of non-magnetic material. The magnetic material which is to be patterned will have a magnetic field component normal to a plane of the layer of magnetic material. To minimize the effect this normal magnetic field component will have on electrons as they impinge the structure surface during e-beam lithography, the soft magnetic material has a high-plane permeability sufficient to divert the normal magnetic field component of the magnetic material into a plane of the layer of soft magnetic material.
    Type: Application
    Filed: October 25, 2002
    Publication date: December 11, 2003
    Applicant: Seagate Technology LLC
    Inventors: Michael Kevin Minor, Andrew Robert Eckert, Xiaomin Yang, Keith Robert Mountfield
  • Patent number: 6576345
    Abstract: Thin films possessing low dielectric constants (e.g., dielectric constants below 3.0) are formed on integrated circuits or other substrates. Caged-siloxane precursors are linked in such a way as to form dielectric layers, which exhibit low dielectric constants by virtue of their silicon dioxide-like molecular structure and porous nature. Supercritical fluids may be used as the reaction medium and developer both to the dissolve and deliver the caged-siloxane precursors and to remove reagents and byproducts from the reaction chamber and resultant porous film created.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: June 10, 2003
    Inventors: Patrick A. Van Cleemput, Ravi Kumar Laxman, Jen Shu, Michelle T. Schulberg, Bunsen Nie
  • Patent number: 6531232
    Abstract: The invention relates to a system comprising a first substrate (100) with at least one bonding area (110a, 110b), liable to be assembled with a second substrate (200), the bonding area (110a, 110b) comprising an area made of a material (104) that can be wetted with a meltable material. According to the invention, the bonding area (110a, 110b) comprises at least one cavity (120) to receive meltable material.
    Type: Grant
    Filed: April 16, 2001
    Date of Patent: March 11, 2003
    Assignee: Commissariat a l'Energie Atomique
    Inventors: François Baleras, Pierre Renard
  • Patent number: 6492036
    Abstract: The present invention relates to a porous electrode wire for use in electrical discharge machining and the method of manufacturing the same. The wire improves the machining speed at least 15% compared with a conventional zinc coated wire, which results from an increased cooling ability of the wire with a cooling liquid because of the increase in the surface area of the wire having porous surface morphology. Since the surface of the porous wire presents uniform profile of outer periphery rather than surface protrusions, it does not affect machining accuracy. Further, the porous nature of the wire is expected to improve flushability during the electrical discharge machining, providing spaces to eliminate particles of the machining. Therefore, in accordance with the method of the present invention, a zinc coated wire having improved performance of machining speed and flushability compared with a conventional coated wire can be provided without additional processes.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: December 10, 2002
    Inventor: Ki Chul Seong
  • Publication number: 20020179201
    Abstract: A method of forming extruded structures from a polycrystalline material and structures formed thereby. The method generally entails forming a structure that comprises a polycrystalline material constrained by a second material in all but one direction, with the polycrystalline material having a patterned surface that is normal to the one direction. The polycrystalline material is then selectively heated, during which the second material restricts thermal expansion of the polycrystalline material in all but the one direction normal to the surface of the polycrystalline material. As a result, stresses are induced in the polycrystalline material that cause grain growth from the surface of the polycrystalline material in the one direction. The growth of an individual grain produces an extruded structure that projects above the surface of the polycrystalline material.
    Type: Application
    Filed: June 13, 2002
    Publication date: December 5, 2002
    Inventors: Munir D. Naeem, Lawrence A. Clevenger
  • Patent number: 6482535
    Abstract: The present invention relates to a porous electrode wire for use in electrical discharge machining device and the method of manufacturing the same. The wire improves the machining speed at least 15% compared with a conventional zinc coated wire, which results from an increased ability to cool the wire with a cooling liquid, because of the increase in the surface area of the wire due to its having porous surface morphology. Since the surface of the porous wire presents uniform profile of outer periphery rather than surface protrusions, it does not affect machining accuracy. Further, the porous nature of the wire is expected to improve flushability during electrical discharge machining, providing spaces to eliminate particles resulting from the machining. Therefore, in accordance with the method of the present invention, a zinc coated wire having improved performance of machining speed and flushability compared with a conventional coated wire can be provided without additional processes.
    Type: Grant
    Filed: January 3, 2002
    Date of Patent: November 19, 2002
    Inventor: Ki Chul Seong
  • Patent number: 6471881
    Abstract: A method is disclosed for providing a TBC system including grooves or other features between the bond coat/substrate and the ceramic thermally insulating layer. The features are initially provided by selectively removing material to define the features, for example by laser. Any disturbed surface layer, e.g., re-cast material in the case of a laser or plastically worked material in the case of machining, is then chemically removed, leaving the remaining material with a microstructure of a more uniform geometry, and free of disturbed material. The ceramic layer is then applied. TBC systems using the method show improved durability, with lives up to 4× longer than prior TBC systems.
    Type: Grant
    Filed: November 23, 1999
    Date of Patent: October 29, 2002
    Assignee: United Technologies Corporation
    Inventors: Yan Chai, Gary M. Lomasney, Keith Douglas Sheffler
  • Patent number: 6451448
    Abstract: A surface treated metallic material according to the present invention comprises a metallic substrate and a metallic compound layer formed thereon, wherein the entire surface of the metallic compound layer is covered with minute, upright, scaly protrusions. The width in the major axial direction of the scaly protrusions is between 0.05˜0.5 &mgr;m and the thickness between 0.01˜0.1 &mgr;m, and the thickness of the metallic compound layer is between 0.1˜1.0 &mgr;m. The metallic compound layer incorporates one, or two or more of, the materials selected from the group consisting of chromium oxide, chromium hydroxide, niobium oxide, niobium hydroxide, rhodium oxide, rhodium hydroxide, vanadium oxide, vanadium hydroxide, palladium oxide, palladium hydroxide, nickel oxide, and nickel hydroxide. By using surface treated metallic materials of this type, bonding strength to a resin layer can be improved.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: September 17, 2002
    Assignee: Mitsubishi Shindoh Co. Ltd.
    Inventors: Yuichi Kanda, Sin-ei Satoh, Shigenari Ohtake, Takeshi Suzuki, Hiroyuki Natume
  • Patent number: 6440578
    Abstract: An adhesive composition is provided for bonding two or more different members which can give a bonded material having excellent heat resistance characteristics while inhibiting breakage of the materials to be bonded by reducing the expansion coefficient, the Young's modulus and the proof stress value. A method for bonding two or more different members using the adhesive composition, and a composite member comprising two or more different members bonded by the above method can be provided by the adhesive composition which comprises a hard solder and a mixture of at least two fine particle materials differing in wettability with the hard solder and which is controlled in expansion coefficient, Young's modulus and proof stress value.
    Type: Grant
    Filed: October 12, 2000
    Date of Patent: August 27, 2002
    Assignee: NGK Insulators, Ltd.
    Inventors: Masayuki Shinkai, Masahiro Kida
  • Patent number: 6426154
    Abstract: The present invention provides a ceramic circuit board comprising: a ceramic substrate and a metal circuit plate bonded to the ceramic substrate through a brazing material layer; wherein the brazing material layer is composed of Al—Si group brazing material and an amount of Si contained in the brazing material is 7 wt % or less. In addition, it is preferable to form a thinned portion, holes, or grooves to outer peripheral portion of the metal circuit plate. According to the above structure of the present invention, there can be provided a ceramic circuit board having both high bonding strength and high heat-cycle resistance, and capable of increasing an operating reliability as electronic device.
    Type: Grant
    Filed: September 25, 2000
    Date of Patent: July 30, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayuki Naba, Hiroshi Komorita, Noritaka Nakayama, Kiyoshi Iyogi
  • Patent number: 6426152
    Abstract: Castings for gas turbine parts exposed on one side to a high-temperature fluid medium have cast-in bumps on an opposite cooling surface side to enhance heat transfer. Areas on the cooling surface having defectively cast bumps, i.e., missing or partially formed bumps during casting, are coated with a braze alloy and cooling enhancement material to salvage the part.
    Type: Grant
    Filed: December 14, 2000
    Date of Patent: July 30, 2002
    Assignee: General Electric Company
    Inventors: Robert Alan Johnson, Jon Conrad Schaeffer, Ching-Pang Lee, Nesim Abuaf, Wayne Charles Hasz
  • Publication number: 20020038764
    Abstract: A continuous layer of a metal is electrodeposited onto a substrate having both hydrodynamically inaccessible recesses and hydrodynamically accessible recesses on its surface by a twostep process in which the hydrodynamically inaccessible recesses are plated using a pulsed reversing current with cathodic pulses having a duty cycle of less than about 50% and anodic pulses having a duty cycle of greater than about 50% and the hydrodynamically accessible recesses are then plated using a pulsed reversing current with cathodic pulses having a duty cycle of greater than about 50% and anodic pulses having a duty cycle of less than about 50%.
    Type: Application
    Filed: April 3, 2001
    Publication date: April 4, 2002
    Inventors: E. Jennings Taylor, Jenny J. Sun, Maria E. Inman
  • Publication number: 20020033341
    Abstract: A smooth layer of a metal is electroplated onto a microrough electrically conducting substrate by immersing the substrate and a counterelectrode in an electroplating bath of the metal to be electroplated and passing a modulated reversing electric current between the electrodes. The current contains pulses that are cathodic with respect to said substrate and pulses that are anodic with respect to said substrate. The cathodic pulses have a duty cycle less than about 50% and said anodic pulses have a duty cycle greater than about 50%, the charge transfer ratio of the cathodic pulses to the anodic pulses is greater than one, and the frequency of said pulses ranges from about 10 Hertz to about 12000 Hertz. The plating bath is substantially devoid of levelers and may be devoid of brighteners.
    Type: Application
    Filed: April 3, 2001
    Publication date: March 21, 2002
    Inventors: E. Jennings Taylor, Chengdong Zhou, Jenny J. Sun
  • Publication number: 20020031678
    Abstract: A method for mechanically cutting a continuous circular shaped groove in a foil sheet for use in a metal matrix composite product. In one form the foil sheet is held adjacent a rotating machine tool by vacuum and a cutting tool is moved relative thereto to cut a spiral groove.
    Type: Application
    Filed: September 12, 2001
    Publication date: March 14, 2002
    Inventors: Robert A. Ress, Jason E. Dundas, Preston E. Light, Brian P. King
  • Patent number: 6306523
    Abstract: The present invention relates to a porous electrode wire for use in electrical discharge machining and the method of manufacturing the same. The wire improves the machining speed at least 15% compared with a conventional zinc coated wire, which results from an increased cooling ability of the wire with a cooling liquid because of the increase in the surface area of the wire having porous surface morphology. Since the surface of the porous wire presents uniform profile of outer periphery rather than surface protrusions, it does not affect machining accuracy. Further, the porous nature of the wire is expected to improve flushability during the electrical discharge machining, providing spaces to eliminate particles of the machining. Therefore, in accordance with the method of the present invention, a zinc coated wire having improved performance of machining speed and flushability compared with a conventional coated wire can be provided without additional processes.
    Type: Grant
    Filed: May 28, 1999
    Date of Patent: October 23, 2001
    Inventor: Ki Chul Seong
  • Patent number: 6159957
    Abstract: A method of treatment or inhibition of tumors involves administering a compound to a subject. The compound is one in which one or more of the eight phenyl substituents in the compound [M(dppe).sub.2 ].sup.+, in which M is selected from Au(I), Ag(I) and Cu(I), is substituted by 2, 3, or 4 pyridyl substituents. The compound has anti-tumor activity and an octanol/water partition coefficient between 0.01 and 25.5. The compound has selective toxicity to cancer cells, including cisplatin resistant human carcinoma cells lines.
    Type: Grant
    Filed: August 18, 1999
    Date of Patent: December 12, 2000
    Assignee: Griffith University
    Inventors: Susan Jane Berners-Price, Richard John Bowen, Peter Gordon Parsons
  • Patent number: 6103399
    Abstract: The invention relates to a method for manufacturing a micromachined structure to be at least partly released from a substrate surface. A surface contact area, over which structure and the said substrate surface are in surface contact with each other during the manufacturing step, is divided into at least a first and a second contact zone, the adhesiveness between the structure and the substrate being greater in the first contact zone than in the second contact zone. As a manufacturing step, or as a step subsequent to the manufacturing, the structure can be released from the substrate surface at least over said second contact zone. The completed structure may also be completely loose from the substrate. The invention is also directed to a micromachined structure manufactured according to the method.
    Type: Grant
    Filed: December 30, 1997
    Date of Patent: August 15, 2000
    Assignees: Elisabeth Smela, Olle Inganas, Ingemar Lundstrom
    Inventors: Elisabeth Smela, Olle Inganas, Ingemar Lundstrom, Ove Ohman
  • Patent number: 6096131
    Abstract: A multi-layer stencil is disclosed for applying solder paste to a printed circuit board. The stencil is formed from first and second layers of stencil material, e.g., stainless steel sheet, the second layer overlying the first layer in selected areas thereby forming a region of increased stencil thickness in those areas. A first plurality of apertures is defined through the thickness of the first layer only and a second plurality of apertures is defined through the combined thickness of the first and second layers in the selected regions. This type of multilevel stencil is useful for depositing differing thicknesses of solder paste onto a circuit board comprising a hybrid of through-hole and SMT devices.
    Type: Grant
    Filed: May 1, 1997
    Date of Patent: August 1, 2000
    Assignee: International Business Machines Corporation
    Inventor: Paul Hewett
  • Patent number: 6063481
    Abstract: A process for removal of undesirable conductive material (e.g., catalyst material and seeped circuit material) on a circuitized substrate and the resultant circuitized substrates disclosed. Such process and resultant circuit effectively address the electrical shorting problems caused by nonremoval of the residual catalyst material and circuit material which has seeped under the residual catalyst material. The process includes the steps of: a) providing a catalyst layer (e.g., palladium and tin) having circuit pattern (e.g., copper) thereon; b) pretreating the catalyst layer and the circuit pattern (e.g., with a cyanide dip) for removal of undesirable portions of each which cause electrical leakage between circuit lines of the circuit pattern; c) oxidizing the catalyst layer and the circuit pattern (e.g.
    Type: Grant
    Filed: March 6, 1998
    Date of Patent: May 16, 2000
    Assignee: International Business Machines Corporation
    Inventors: Edward Lee Arrington, John Christopher Camp, Robert Jeffrey Day, Edmond Otto Fey, Curtis Michael Gunther, Thomas Richard Miller
  • Patent number: 5998228
    Abstract: Resilient contact structures are mounted directly to bond pads on semiconductor dies, prior to the dies being singulated (separated) from a semiconductor wafer. This enables the semiconductor dies to be exercised (e.g., tested and/or burned-in) by connecting to the semiconductor dies with a circuit board or the like having a plurality of terminals disposed on a surface thereof. Subsequently, the semiconductor dies may be singulated from the semiconductor wafer, whereupon the same resilient contact structures can be used to effect interconnections between the semiconductor dies and other electronic components (such as wiring substrates, semiconductor packages, etc.). Using the all-metallic composite interconnection elements of the present invention as the resilient contact structures, burn-in can be performed at temperatures of at least 150.degree. C., and can be completed in less than 60 minutes.
    Type: Grant
    Filed: April 15, 1997
    Date of Patent: December 7, 1999
    Assignee: Form Factor, Inc.
    Inventors: Benjamin N. Eldridge, Gary W. Grube, Igor Y. Khandros, Gaetan L. Mathieu
  • Patent number: 5962151
    Abstract: A conductor (112), a method for forming the conductor (112), and a method for attaching a discrete circuit device, such as a bond pad, chip capacitor, chip resistor, etc., to the conductor (112) with solder connections (16). Solder connections (16) formed by the method are characterized as being accurately located on the conductor (112) and having a shape and location that achieves an adequate and uniform stand-off height for the device, and improves thermal cycle fatigue life. Such benefits are achieved by forming a nonsolderable layer (114) on a substrate (10), and then forming a solderable conductor (112) on the substrate (10) such that a first portion of the conductor (112) overlies the nonsolderable layer (114) and a second portion of the conductor (112) does not overlie the nonsolderable layer (114).
    Type: Grant
    Filed: December 5, 1997
    Date of Patent: October 5, 1999
    Assignee: Delco Electronics Corp.
    Inventors: Christine Ann Paszkiet, Carl William Berlin, Stephanie Yolanda Oden
  • Patent number: 5902685
    Abstract: A grinding roll for use in a material bed roll mill for the comminution of brittle material has a cylindrical body in the periphery of which are alternating grooves and lands. To the exterior of each land is secured a wear strip. The grooves of the confronting rolls may be directly opposite one another or the grooves may be offset axially so that the grooves in one roll confront a land of the opposite roll.
    Type: Grant
    Filed: January 11, 1996
    Date of Patent: May 11, 1999
    Assignee: Krupp Polysius AG
    Inventors: Heinz Schroder, Oswald Haberhauer
  • Patent number: 5747180
    Abstract: A method of fabricating two-dimensional regimented and quasi periodic arrays of metallic and semiconductor nanostructures (quantum dots) with diameters of .about.100 .ANG.(10 nm) includes the steps of polishing and anodizing a substrate to form a regimented quasi-periodic array of nanopits. The array forms a template for metallic or semiconductor material. The desired material is deposited in the nanopits by immersing the substrate in an appropriate solution and using the substrate as one cathode and inserting a second cathode in the solution.
    Type: Grant
    Filed: December 5, 1996
    Date of Patent: May 5, 1998
    Assignee: University of Notre Dame Du Lac
    Inventors: Albert E. Miller, Supriyo Bandyopadhyay
  • Patent number: 5729042
    Abstract: A novel raised polycide fusible link structure is described. This structure enables a highly reliable laser-cutting process to be used in which the fuse can be easily and totally severed over a wide range of laser energy levels. The primary feature of the structure is that the fusible link is located on a pedestal that raises it above the surface of the main body of the integrated circuit, thereby providing a measure of thermal isolation for the fuse when it is irradiated by the laser. An efficient process for manufacturing the structure is also described.
    Type: Grant
    Filed: April 2, 1997
    Date of Patent: March 17, 1998
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yung-Song Lou, Ching-Cherng Rou, Ting Chou, Chao-Ming Koh, Shin-Chi Lee, Chuen-Nan Chen
  • Patent number: 5681661
    Abstract: The performance of many macroscopic structures (those whose dimensions are on the order of centimeters, meters, or even larger) can be greatly improved by covering their surfaces with microstuctures. There are several applications in which "large," microstructure-covered sheets are useful. For example, dissimilar sheets of material that otherwise would not bond well to one another (such as a polymer and a metal) can be more strongly bonded with microstructures extending from one of the sheets and embedded into the other sheet. Such products make valuable laminate composites. As another example, the rate of heat transfer between an object and the surrounding medium can be dramatically changed (up or down) by covering the surface of the object with high aspect ratio microstructures, without significantly changing the component's size or weight.
    Type: Grant
    Filed: February 9, 1996
    Date of Patent: October 28, 1997
    Assignee: Board of Supervisors of Louisiana State University and Agricultural and Mechanical College
    Inventor: Kevin W. Kelly
  • Patent number: 5609967
    Abstract: Provided is a process for preparing a decorative plate in which delicate gradation and shadow of a pattern from a photograph or the like can be reproduced with improved sharpness and clarity. The decorative plate has improved adhesive characteristics allowing the pattern forming plating layers to adhere to a substrate with excellent durability.In the decorative plate, a plating layer is formed so that a desired pattern is formed on a substrate made of stainless steel. The portions other than the plating layer comprise a large number of lines having a predetermined line density. The decorative plate is prepared through a masking step, a plating step and a step of removing a masking layer. The masking process comprises a step of coating a light-sensitive resin on a screen having meshes, curing the light-sensitive resin using a photographic film, mounting the film on the screen and allowing the resin to cure by UV rays.
    Type: Grant
    Filed: January 5, 1995
    Date of Patent: March 11, 1997
    Assignee: Kayoh Technical Industry Co., Ltd.
    Inventor: Hiromi Matsunami
  • Patent number: 5462789
    Abstract: A substrate for electronic components has a layer of material covering at least a portion of the substrate. Recesses are formed in a layer of material and located in a pattern relative to each other to form a predetermined temperature distribution across the layer of material. The layer of material can be formed as a resistive film for a heating resistor element. The shape, size and pattern of the recesses are selected to balance the thermal stress across the surface of the layer of material.
    Type: Grant
    Filed: May 20, 1993
    Date of Patent: October 31, 1995
    Assignee: Robert Bosch GmbH
    Inventor: Hans Hecht
  • Patent number: 5458985
    Abstract: A method of manufacturing a stamper includes the steps of coating a flat surface of a substrate with photosensitive material; directing light to a specified position on the photosensitive material to expose it; developing the photosensitive material to make a minute photoresist pattern; etching the substrate to a specified depth with a mask of the photoresist pattern; removing the photoresist as the mask to make a glass master; arbitrarily forming a first nickel layer on a surface of the glass master; forming an intermediate layer of a metal having a smaller linear expansion coefficient than nickel over the first nickel layer; forming a second nickel layer on the intermediate layer to form a conductive film having a two- or three-stratum structure; arbitrarily subjecting the whole substrate to a process to make nickel passive; forming an electroformed layer on the conductive film by an electroforming process; and separating the conductive film from the glass master.
    Type: Grant
    Filed: August 16, 1994
    Date of Patent: October 17, 1995
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hitoshi Isono, Hirotoshi Takemori
  • Patent number: 5405493
    Abstract: A method of etching increases the surface area of a metal foil by creating uniformly distributed etch tunnels. The foil is pretreated by depositing a discontinuous surface layer of metal that is cathodic to the foil, followed by chemically etching the foil to remove a portion of the deposited metal. Finally, the foil is electrochemically etched to create the etch tunnels.
    Type: Grant
    Filed: January 26, 1994
    Date of Patent: April 11, 1995
    Assignee: KDK Corporation
    Inventor: David Goad
  • Patent number: 5403671
    Abstract: A printed circuit or hybrid circuit board with a formed solder deposit on a surface mount device (SMD) pad thereon, as well as for the formed solder deposit itself. This formed solder deposit is in a defined three-dimensional well having the proper profile and a defined solder gap. The solder before forming can be solid solder or a solder paste. By the placement of a mesh on the surface of the circuit board with the solder in place on the pads, applying a slight positive pressure on a rigid or elastic surface on the other side of the mesh or on the mesh itself, and subjecting this system to a temperature just low enough to reflow the solder by means of a heat transfer fluid, then cooling the board to solidify the solder, a product results having the above properties. The duration of the application of heat and pressure is made so brief, that the laminate structure of the board and the coating thereon remain substantially unaffected.
    Type: Grant
    Filed: April 2, 1993
    Date of Patent: April 4, 1995
    Assignee: Mask Technology, Inc.
    Inventor: Damian J. Holzmann
  • Patent number: 5391432
    Abstract: Disclosed are electrically conductive fibers which include zinc oxide particles having a substantially rod shape.
    Type: Grant
    Filed: April 28, 1993
    Date of Patent: February 21, 1995
    Inventors: Mark Mitchnick, Mamoun Muhammed
  • Patent number: 5368948
    Abstract: A tag or marker is disclosed which comprises a substrate; an `active` magnetic material which is a soft magnetic material having a high magnetic permeability and a low coercive force; and a deactivating material which is a hard or semi-hard magnetic material having a moderate or high coercive force and a moderate magnetic permeability, whereby the deactivating material, when subjected to a sufficiently high magnetising force, is able to clamp the magnetic properties of the `active` material so as to deactivate the `active` material. The tag or marker is characterised in that the deactivating material is formed by an electrodeposition process, and in that the deactivating layer is nickel.
    Type: Grant
    Filed: April 9, 1993
    Date of Patent: November 29, 1994
    Assignee: Esselte Meto International Produktions
    Inventor: Dafydd G. Davies
  • Patent number: 5364705
    Abstract: A hybrid resistance card (R-Card) is manufactured using a two-step process wherein an electrically conductive ink layer and an electrically resistive ink layer are printed onto a surface, which may be either a substrate or the part on which the R-Card is to be used. The conductive ink layer is selectively applied in a pattern of shapes to electrically short out portions of the resistive ink layer, thereby permitting the R-Card to have a predetermined resistive taper across its width according to a desired resistivity curve. The resistive ink layer comprises grid-like lines bordering and separating the conductive shapes. The resistive taper is substantially continuous along the length of the R-Card, at least linearly, though if the card is designed to cover an entire part, it is substantially continuous along a plurality of directions on the card, with the tapers being designed to round into one another.
    Type: Grant
    Filed: June 25, 1992
    Date of Patent: November 15, 1994
    Assignee: McDonnell Douglas Helicopter Co.
    Inventor: Stephen A. Callahan
  • Patent number: 5256464
    Abstract: A substrate for electronic components has a layer of material covering at least a portion of the substrate. Recesses are formed in a layer of material and located in a pattern relative to each other to form a predetermined temperature distribution across the layer of material. The layer of material can be formed as a resistive film for a heating resistor element. The shape, size and pattern of the recesses are selected to balance the thermal stress across the surface of the layer of material.
    Type: Grant
    Filed: July 11, 1991
    Date of Patent: October 26, 1993
    Assignee: Robert Bosch GmbH
    Inventor: Hans Hecht
  • Patent number: 5230965
    Abstract: Selective electrolytic deposition on either conductive or non-conductive bodies is provided by forming a layer of a metal which forms a plating-preventing compound on the surface of the body to be plated, and selectively interdiffusing a plating-enabling metal into the surface of that compound-forming metal in those locations where plating is desired and electroplating the body. The interdiffusion may be done before or after the plating-preventing compound has formed on the surface of the compound-forming layer. During the electroplating, the electroplating metal deposits only in those locations where the plating-enabling metal has interdiffused with the compound-forming metal. At the end of the process, the compound-forming metal may be removed in those locations where it is not covered by the electroplated metal to provide a plurality of separate plated conductors.
    Type: Grant
    Filed: June 8, 1992
    Date of Patent: July 27, 1993
    Assignee: General Electric Company
    Inventors: Herbert S. Cole, Jr., James W. Rose
  • Patent number: 5187020
    Abstract: A contact pad including a compliant, electrically conductive polymer is provided in a substrate. The contact pad may include a metallic base, and a metallic upper surface wherein said polymer is intermediate said base and upper surfaces. The pad also may have a recessed upper surface, or have a metallic bump thereon depending upon the specific use intended. The contact pad may be incorporated into a substrate including a base substrate material having an upper surface, an interconnecting layer on the upper surface, a dielectric layer on the interconnecting layer, and at least one compliant, electrically conductive polymeric contact pad extending through the dielectric layer and in contact with the interconnecting layer. The substrate so formed may be a temporary substrate used, for example, in testing of integrated circuit chips.
    Type: Grant
    Filed: November 5, 1991
    Date of Patent: February 16, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Oh-Kyong Kwon, Satwinder Malhi, Masahi Hashimoto
  • Patent number: 5108812
    Abstract: A substrate for a magnetic disk, having fine roughness formed on its surface by subjecting aluminum or an aluminum alloy to anodic oxidation, packing pores in the anodized layer thereby formed, with a material different in the physicochemical properties from the anodized layer, and letting a plating material grow selectively by an epitaxial method.
    Type: Grant
    Filed: September 18, 1989
    Date of Patent: April 28, 1992
    Inventors: Toshiro Takahashi, Noboru Tsuya, Tadao Tokushima
  • Patent number: 5106700
    Abstract: Disclosed hereis is a casting having a cast exterior surface and a gate portion extending adjacently and integrally from the cast exterior surface and including a polished outer face located in adjacently raised relation to the cast exterior surface and having a perimeter or outline defining a desired indicia. The casting is produced by a method comprising the steps of forming a casting with a cast exterior surface and a gate which extends from the cast exterior surface and which includes a gate portion located adjacent the cast exterior surface and defined by an outline in the form of the desired indicia and a projection portion extending from the gate portion, severing the gate to remove the projecting portion, to retain, as part of the casting, the adjacent gate portion, and to provide a surface raised with respect to the cast exterior surface and having the outline in the form of the desired indicia, and polishing the raised surface.
    Type: Grant
    Filed: May 10, 1990
    Date of Patent: April 21, 1992
    Assignee: Outboard Marine Corporation
    Inventor: Francis V. Bailey
  • Patent number: 5077137
    Abstract: A process for providing a slip resistant surface by thermally applying a metallic spray coat from materials in a hollow wire with the characteristics of the final coated surface being selectively variable by varying the materials in the hollow wire and an article formed by such process, the slip resistant surface on the article being jagged and generally defined by randomly distributed sharp ridges and pointed peaks of varying depths.
    Type: Grant
    Filed: April 4, 1990
    Date of Patent: December 31, 1991
    Assignee: W. S. Molnar Co.
    Inventor: William S. Molnar
  • Patent number: 5061547
    Abstract: A multilayer substrate provides predetermined connections to and between a plurality of integrated circuit chips mounted thereon. A plurality of layers mounted on a surface of a substrate has a plurality of layers comprising a plurality of dielectric layers, a first plurality of metallic layers, and a second plurality of metallic layers. The first plurality of metallic layers has a predetermined pattern for forming the predetermined connections, these being the x-lines and y-lines. Each of the second plurality of metallic layers provides a predetermined voltage level to the integrated circuit chips, and each of the second metallic layers has a screen-like structure. Each of the first and second metallic layers is insulated from the other metallic layers by one of the dielectric layers, except for desired interconnections between the x-lines y-lines, and power layer (or power plane).
    Type: Grant
    Filed: March 28, 1986
    Date of Patent: October 29, 1991
    Inventors: Boris Plesinger, Lynn H. Brown, Edward D. Pisacich
  • Patent number: 5039990
    Abstract: An article comprising a non-conductive substrate having a sub-micron thickness of an oxidizable conductive first metal coating thereon, and a second (promoter) metal which is galvanically effective to promote the corrosion of the first metal, discontinuously coated on the first metal coating. Optionally, the second metal-doped, first metal-coated substrate may be further coated with a salt, to accelerate the galvanic corrosion reaction by which the conductive first metal coating is oxidized. Also disclosed is a related method of forming such articles, comprising chemical vapor depositing the first metal on the substrate and chemical vapor depositing the second metal on the applied first metal coating, and of optionally applying a salt by salt solution contacting of the second metal-doped, first metal-coated substrate. When utilized in a form comprising fine-diameter substrate elements such as glass or ceramic filaments, the resulting product may be usefully employed as an evanescent chaff.
    Type: Grant
    Filed: December 11, 1989
    Date of Patent: August 13, 1991
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Ward C. Stevens, Edward A. Sturm, Delwyn F. Cummings
  • Patent number: 5024896
    Abstract: A process and structure for depositing metal lines in a lift-off process is disclosed. The process comprises the deposition of a four-layer structure or lift-off stencil, comprising a first layer of a lift-off polymer etchable in oxygen plasma, a first barrier layer of hexamethyldisilizane (HMDS) resistant to an oxygen plasma, a second lift-off layer and a second barrier layer. Once these layers are deposited, a layer of photoresist is deposited and lithographically defined with the metal conductor pattern desired. The layers are then sequentially etched with oxygen and CF.sub.4, resulting in a dual overhang lift-off structure. Metal is then deposited by evaporation or sputtering through the lift-off structure. Following metal deposition, the stencil is lifted-off in a solvent such as N-methylpyrrolidone (NMP).
    Type: Grant
    Filed: July 6, 1989
    Date of Patent: June 18, 1991
    Assignee: International Business Machines Corporation
    Inventors: Gangadhara S. Mathad, David Stanasolovich, Giorgio G. Via
  • Patent number: 4963974
    Abstract: The present invention relates to an electroless gold plating solution, a method of plating by using the same, and an electronic device plated with gold by using the same.According to the present electroless gold plating solution, the plating solution components contain no cyanide ions, the amount of a reducing agent used is small, and gold plating can be carried out without causing the gold plating on conducting paths having a fine interval between them to short-circuit the conducting paths.Therefore, according to the method of gold plating by using said electroless gold plating solution, a plating method that is safe in the plating work and in the treatment of its waste liquor can be accomplished. The method has a feature that the method can provide an electronic device on which parts can be mounted highly densely, and wherein the joint reliability to the parts is high.
    Type: Grant
    Filed: April 20, 1988
    Date of Patent: October 16, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Jiro Ushio, Osamu Miyazawa, Akira Tomizawa, Hitoshi Yokono, Naoya Kanda, Naoko Matsuura, Setsuo Ando, Hiroaki Okudaira
  • Patent number: 4925525
    Abstract: A method of making a printed circuit board includes providing a substrate coated with a conductive layer, developing a first photoresist layer on the conductive layer to define a first conductive pattern of the desired circuit configuration having a plurality of discontinuous segments, and a second conductive pattern interconnecting the discontinuous segments of the desired circuit configuration. A second layer of photoresist is positioned across the whole surface of the substrate except at least a selected portion of the first conductive pattern, and the substrate is electrically activated during a coating process for depositing conductive material on the selected portion of the first conductive pattern. The first conductive pattern is subsequently coated with photoresist, and the second conductive pattern, which is now exposed on the substrate, is subject to an etching process to effectively remove all of the second conductive pattern.
    Type: Grant
    Filed: April 10, 1989
    Date of Patent: May 15, 1990
    Assignee: Minolta Camera Kabushiki Kaisha
    Inventors: Shunji Oku, Yoshiyuki Mizumo, Kiyoshi Seigenji
  • Patent number: 4902556
    Abstract: Multi-layer laminates are provided of alternating or non alternating layers of reinforced epoxy and reinforced polynorbornene. The laminates are made by a process which includes an adhesion promotion step wherein at least one of the layers, prior to lamination, is pretreated with an adhesion promotion agent. Preferred adhesion promotion agents include silanes. One or more layers of copper foil can also be employed between exterior surfaces of the layers at the interface between the layers, as well as on the exterior of the laminates. The copper films can be etched to form patterns such as those suitable for printed circuit wiring boards.
    Type: Grant
    Filed: January 27, 1989
    Date of Patent: February 20, 1990
    Assignee: The B. F. Goodrich Company
    Inventors: George M. Benedikt, David M. Aleksa
  • Patent number: 4900637
    Abstract: A tag structure for labeling an article cast from molten material including a portion which submerges in the molten material and a portion which contacts the surface of the molten material, and preferably floats on the surface of the molten material. The submerged portion forms a bond with the material forming the article as the material solidifies. A bath of the molten material is provided and the tag is brought into contact with surface of the molten material in the bath, for example, it is dropped onto the surface of the molten material in the bath. The tag if dropped sinks under its own weight into the molten material forming the bond noted above. The portion of the tag which is not submerged bears information relative to the article to be formed. The completed article has, therefore, a tag firmly attached thereto which is placed on the article during formation of the article and not thereafter.
    Type: Grant
    Filed: October 7, 1988
    Date of Patent: February 13, 1990
    Assignee: Aluminum Company of America
    Inventor: James L. Darovec
  • Patent number: 4880684
    Abstract: Sealing and stress relief are provided to a low-fracture strength glass-ceramic substrate. Hermeticity is addressed through the use of capture pads in alignment with vias and through polymer overlays with interconnection between the underlying via or pad metallurgy and the device, chip, wire or pin bonded to the surface of the layer. Multilevel structures are taught along with a self-aligned sealing and wiring process.
    Type: Grant
    Filed: March 11, 1988
    Date of Patent: November 14, 1989
    Assignee: International Business Machines Corporation
    Inventors: David W. Boss, Timothy W. Carr, Derry J. Dubetsky, George M. Greenstein, Warren D. Grobman, Carl P. Hayunga, Amanda H. Kumar, Walter F. Lange, Robert H. Massey, Paul H. Palmateer, John A. Romano, Da-Yuan Shih