Ga-, In-, Tl- Or Group Va Metal-base Component Patents (Class 428/642)
  • Patent number: 7655280
    Abstract: A extreme low resistivity light attenuation anti-reflection coating structure includes a substrate, a coating module, and a composed protection coating layer. The coating module is formed on a front surface of the substrate. The coating module is composed of a plurality of Ti-based oxide coating layers and a plurality of metal coating layers that are alternately stacked with each other. The composed protection coating layer is formed on the coating module.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: February 2, 2010
    Assignee: Innovation & Infinity Global Corp.
    Inventors: Cheng-Chieh Chang, Shiu-Feng Liu, Pi-Jui Kuo
  • Patent number: 7651784
    Abstract: The invention describes a sliding element, in particular a sliding bearing, with a support element and a sliding layer, between which a bearing metal layer is arranged, wherein the sliding layer is made from bismuth or a bismuth alloy, and wherein the crystallites of the bismuth or the bismuth alloy in the sliding layer adopt a preferred direction with respect to their orientation, expressed by the Miller index of the lattice plane (012), wherein the X-ray diffraction intensity of the lattice plane (012) is the greatest compared to the X-ray diffraction intensities of other lattice planes. The X-ray diffraction intensity of the lattice plane with the second-largest X-ray diffraction intensity is a maximum of 10% of the X-ray diffraction intensity of the lattice plane (012).
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: January 26, 2010
    Assignee: Miba Gleitlager GmbH
    Inventor: Thomas Rumpf
  • Patent number: 7629058
    Abstract: A sliding member has a coating layer deposited on a base material through an intermediate layer, wherein the intermediate layer is formed of a lead-free metal, and the coating layer is formed of Bi or a lead-free Bi alloy; and wherein a grain in the intermediate layer becomes gradually large toward a coating layer side from a base material side, and a grain in the coating layer forms a columnar grain of which the major axis directs toward the surface of the coating layer from the intermediate layer side. Thus formed configuration improves a bonding strength between the base material and the coating layer owing to the intermediate layer, and has the grain of the coating layer formed into a desirable shape for bearing a load from an opposite material to improve fatigue resistance.
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: December 8, 2009
    Assignee: Daiso Metal Company, Ltd.
    Inventors: Satoshi Takayanagi, Toshiaki Kawachi, Masahito Fujita
  • Publication number: 20090242249
    Abstract: A bonding material that has a melting temperature of 270° C. or higher and that does not contain lead is inexpensively provided. An electronic element and an electrode of an electronic component are bonded using a bonding material containing an alloy that contains Bi as the main component and that contains 0.2 to 0.8 wt % Cu and to 0.2 wt % Ge.
    Type: Application
    Filed: May 18, 2007
    Publication date: October 1, 2009
    Inventors: Akio Furusawa, Kenichiro Suetsugu, Shigeki Sakaguchi, Kimiaki Nakaya
  • Publication number: 20090233123
    Abstract: A method of manufacturing a decorative article, including a first coating formation step of forming a first coating of primarily TiN on a base member, and a second coating formation step of forming a second coating on the first coating by means of a dry plating method using an Au—Pd—Ag—In alloy of primarily Au and containing 6.0-9.0 wt % Pd, 6.0-8.0 wt % Ag, and 7.0-9.0 wt % In as a target.
    Type: Application
    Filed: March 10, 2009
    Publication date: September 17, 2009
    Applicant: Seiko Epson Corporation
    Inventors: Atsushi KAWAKAMI, Yoshiyuki OBI
  • Patent number: 7569282
    Abstract: An electromagnetic shielding copper foil superior in electromagnetic shielding ability, high in transmittance, and free from particle shedding comprising a copper foil on at least one surface of which a fine roughening particle layer of copper or an alloy is provided and having on the fine roughening particle layer a smoothening layer comprised of cobalt, nickel, indium, or an alloy of the same and an electromagnetic shield able to be suitably used for a PDP using the same. The fine roughening particle layer may also be a layer comprised of a fine particle roughening particle layer of copper on which a fine roughening particle layer of a copper alloy is stacked or may also be formed by a copper-cobalt-nickel alloy. The smoothening layer of the copper foil may be treated for stainproof or by a silane coupling agent to protect the surface of the copper foil.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: August 4, 2009
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Yasuhisa Yoshihara, Hisao Kimijima
  • Patent number: 7442445
    Abstract: A brazing clad material is a composite material that comprises a base material and a brazing material layer formed integrally on the base material. The brazing material layer has a Ni or Ni alloy layer, a Ti or Ti alloy layer and a Fe—Ni alloy layer that are sequentially stacked in this order on the base material. The brazing material layer has a Fe concentration of 25 to 40 wt % in the entire brazing material layer. The brazing material layer satisfies a ratio of W1/W2 to be 0.56 to 0.66, where W1 is a weight of Ni contained in the entire brazing material layer and W2 is a total weight of Ni and Ti contained in the entire brazing material layer.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: October 28, 2008
    Assignee: Hitachi Cable, Ltd.
    Inventors: Hideyuki Sagawa, Hiromitsu Kuroda, Kazuma Kuroki, Humio Horii, Tetsuya Tokumitu, Nobuhito Sakuyama, Shigeru Okamoto
  • Publication number: 20080145687
    Abstract: A method of producing titanium metal from a titanium-containing material includes the steps of producing a solution of M?TiF6 from the titanium-containing material, selectively precipitating M?2TiF6 from the solution by the addition of (M?)aXb and using the selectively precipitated M?2TiF6 to produce titanium. M? is a cation of the type which forms a hexafluorotitanate, M? is selected from ammonium and the alkali metal cations, X is an anion selected from halide, sulphate, nitrite, acetate and nitrate and a and b are 1 or 2.
    Type: Application
    Filed: December 14, 2005
    Publication date: June 19, 2008
    Inventor: Gerard Pretorius
  • Patent number: 7368046
    Abstract: The invention is a method for the production of a composite multilayer material having a backing layer, a bearing metal layer of a copper alloy or an aluminum alloy, a nickel intermediate layer and an overlay consisting of about 0-20 wt. % copper and about 0-20 wt. % silver, the combined maximum wt. % of copper and silver being about 20 wt. %, the rest being bismuth, and the layer thickness of the nickel layer amounts to more than 4 ?m by electrodeposition, in which the overlay is deposited from methyl sulphonic acid-based electrolyte.
    Type: Grant
    Filed: August 5, 2004
    Date of Patent: May 6, 2008
    Assignee: Federal-Mogul Wiesbaden GmbH & Co. KG
    Inventors: Achim Adam, Klaus Staschko
  • Publication number: 20080102307
    Abstract: The invention describes a multi-layered bearing with a supporting metal layer, optionally a bearing metal layer disposed on top of it, an anti-friction layer on top of the latter as well as a wearing layer on top of it. The wearing layer is made from bismuth or a bismuth alloy and the anti-friction layer is made from a copper-bismuth or silver-bismuth alloy or silver.
    Type: Application
    Filed: June 8, 2007
    Publication date: May 1, 2008
    Applicants: Miba Gleitlager GmbH, KS Gleitlager GmbH
    Inventor: Jakob Zidar
  • Patent number: 7128981
    Abstract: Disclosed is a sliding member including an overlay layer made of a Bi based alloy comprising Cu as an essential element and at least one element selected from the group of Sn and In, wherein the Bi based alloy comprises 0.1 to 10 mass % of Cu and 0.5 to 10 mass % in total of the at least one element selected from the group of Sn and In.
    Type: Grant
    Filed: May 27, 2004
    Date of Patent: October 31, 2006
    Assignee: Daido Metal Company, Ltd.
    Inventors: Toshiaki Kawachi, Hideo Ishikawa, Masaaki Sakamoto
  • Patent number: 7067200
    Abstract: A joined body and method of producing the joined body are provided. A first member containing at least a ceramic and a second member containing at least one of a metal and a metal composite are joined with each other via a metal adhesive. The metal adhesive contains at least indium and at least one material containing at least a component capable of reducing the melting point of indium and is provided between the first and second members to provide a laminate. The laminate is heated at a temperature in a solid-liquid coexisting range of an alloy comprising indium and the indium melting point reducing component to join the first and second members.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: June 27, 2006
    Assignee: NGK Insulators, Ltd.
    Inventors: Tomoyuki Fujii, Hideyoshi Tsuruta, Tetsuya Kawajiri
  • Patent number: 7063897
    Abstract: A Bi base material of which a Miller index (202) face has the index of orientation of not less than 30% and in which the (202) face has the index of orientation assuming a maximum value as compared with those of other faces forms a minute structure and has a surface which is not a mirror finished surface but a fine, irregular surface on which minute and uniform projections in the form of a triangular pyramid or a quadrangular pyramid congregate. Therefore, the surface easily retains oil thereon to be improved thereby in oil wettability, as a result of which an improvement in anti-seizure is achieved.
    Type: Grant
    Filed: April 12, 2004
    Date of Patent: June 20, 2006
    Assignee: Daido Metal Company Ltd.
    Inventors: Toshiaki Kawachi, Hideo Ishikawa, Masaaki Sakamoto
  • Patent number: 7033435
    Abstract: A process for preparing p-n or n-p junctions having a p-type oxide film is disclosed. In one embodiment, a p-type zinc oxide film has a net acceptor concentration of at least about 1015 acceptors/cm3.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: April 25, 2006
    Assignee: The Curators of the University of Missouri
    Inventors: Henry W. White, Shen Zhu, Yungryel Ryu
  • Patent number: 7022460
    Abstract: An optical recording material for binary, multibit or volume data storage is described. The optical recording material comprises: (a) at least one dyestuff selected from polymeric azo dyestuffs and oligomeric azo dyestuffs, the dyestuff changing its spatial arrangement upon irradiation with polarized electromagnetic radiation; and (b) optionally at least one grouping having form anisotropy.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: April 4, 2006
    Assignee: Bayer Aktiengesellschaft
    Inventors: Horst Berneth, Thomas Bieringer, Rainer Hagen, Serguei Kostromine
  • Patent number: 6940721
    Abstract: A multi-layer thermal interface structure for placement between a microelectronic component package and a heat sink so that the structure has a total thermal resistance of no greater than about 0.03° C.-in2/W. The structure comprises a plurality of superimposed metallic layers including a core layer of a solid metal or metal alloy of high thermal conductivity preferably composed of aluminum or copper, a second layer having phase change properties and a third layer of nickel separating the solid metal layer from the layer having phase change properties.
    Type: Grant
    Filed: September 3, 2002
    Date of Patent: September 6, 2005
    Inventor: Richard F. Hill
  • Patent number: 6908782
    Abstract: A p-type transparent conducting oxide film is provided which is consisting essentially of, the transparent conducting oxide and a molecular doping source, the oxide and doping source grown under conditions sufficient to deliver the doping source intact onto the oxide.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: June 21, 2005
    Assignee: Midwest Research Instittue
    Inventors: Yanfa Yan, Shengbai Zhang
  • Patent number: 6869689
    Abstract: A joined structure of a metal terminal and a ceramic member has a joining layer between the terminal and the ceramic member. The joining layer has a metal adhesive layer containing at least indium metal. The invention further provides a joined structure of a metal member and a ceramic member. The metal member has a tip face and a side face. A hollow is formed in the ceramic member. A joining layer is formed between a bottom surface facing the hollow and the tip face of the member, and further formed between a side wall surface facing the hollow and the side face of the member. The joining layer has a metal adhesive layer containing at least indium metal.
    Type: Grant
    Filed: May 14, 2004
    Date of Patent: March 22, 2005
    Assignee: NGK Insulators, Ltd.
    Inventors: Tomoyuki Fujii, Mitsuru Ohta, Tsuneaki Ohashi
  • Patent number: 6861158
    Abstract: A method of forming a substantially relaxed, high-quality SiGe-on-insulator substrate material using SIMOX and Ge interdiffusion is provided. The method includes first implanting ions into a Si-containing substrate to form an implanted-ion rich region in the Si-containing substrate. The implanted-ion rich region has a sufficient ion concentration such that during a subsequent anneal at high temperatures a barrier layer that is resistant to Ge diffusion is formed. Next, a Ge-containing layer is formed on a surface of the Si-containing substrate, and thereafter a heating step is performed at a temperature which permits formation of the barrier layer and interdiffusion of Ge thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: March 1, 2005
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Joel P. de Souza, Keith E. Fogel, Devendra K. Sadana, Ghavam G. Shahidi
  • Patent number: 6861157
    Abstract: Articles for use in a high-temperature, oxidative environment, methods for manufacturing such articles, and a material system for protecting articles in such an environment are provided where, for example, one article comprises a substrate and a protective layer disposed over the substrate, the protective layer comprising at least about 60 atomic percent of a metal selected from the group consisting of platinum (Pt), palladium (Pd), rhodium (Rh), osmium (Os), iridium (Ir), and mixtures thereof.
    Type: Grant
    Filed: March 18, 2002
    Date of Patent: March 1, 2005
    Assignee: General Electric Company
    Inventors: Ji-Cheng Zhao, Melvin Robert Jackson
  • Patent number: 6858287
    Abstract: The invention is a formable, bright metallized laminate that has superior optical and deformation properties. The metallized laminate is made from a plurality of discontinuous metal island layers deposited on a formable clear coat film. The invention is also a method that includes depositing a first discontinuous layer of metal islands upon a formable clear coat film and then depositing a second discontinuous layer of metal islands onto the first discontinuous layer of metal islands.
    Type: Grant
    Filed: August 10, 2001
    Date of Patent: February 22, 2005
    Assignee: Soliant LLC
    Inventor: Thomas R. Fields
  • Patent number: 6855436
    Abstract: A method of forming a substantially relaxed, high-quality SiGe-on-insulator substrate material using SIMOX and Ge interdiffusion is provided. The method includes first implanting ions into a Si-containing substrate to form an implant rich region in the Si-containing substrate. The implant rich region has a sufficient ion concentration such that during a subsequent anneal at high temperatures a barrier layer that is resistant to Ge diffusion is formed. Next, a Ge-containing layer is formed on a surface of the Si-containing substrate, and thereafter a heating step is performed at a temperature which permits formation of the barrier layer and interdiffusion of Ge thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: February 15, 2005
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Keith E. Fogel, Devendra K. Sadana, Ghavam G. Shahidi
  • Patent number: 6852210
    Abstract: To provide a plating method, which enables wide industrial use of the redox system electroless plating method having excellent characteristics, and a plating bath precursor which is preferable for the plating method. The plating method comprises a process oxidizing first metal ions of a redox system of a plating bath from a lower oxidation state to a high oxidation state, and second metal ions of said redox system are reduced and deposited onto the surface of an object to be plated, wherein a process is provided in which by supplying the electrical current to the plating bath, the first metal ions are reduced from said lower oxidation state to thereby activate the plating bath. The plating bath precursor is formed stabilizing the plating bath so that reduction and deposition of the second metal ions substantially do not occur in order to improve its storing performance.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: February 8, 2005
    Assignees: Daiwa Fine Chemicals Co., Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Keigo Obata, Dong-Hyun Kim, Takao Takeuchi, Seiichiro Nakao, Shinji Inazawa, Ayao Kariya, Masatoshi Majima, Shigeyoshi Nakayama
  • Patent number: 6835246
    Abstract: Selected micro- and nanoscale, 1-dimensional and 2-dimensional periodic and random structures generated on silicon and other substrates are expected to perform as compliant, thin films for gettering defects and for accommodating lattice and thermal expansion mismatches during heteroepitaxial growth thereon, thereby leading to relatively defect-free, heteroepitaxial films of chosen thicknesses. The as-grown epilayers or completed electronic and optoelectronic devices can be bonded to a second substrate such as glass, or plastic following separation thereof from the substrate on which they were formed using preferential etching of a readily detachable, nanoporous silicon or silicon dioxide layer introduced between the generated structures and the substrate.
    Type: Grant
    Filed: November 18, 2002
    Date of Patent: December 28, 2004
    Inventor: Saleem H. Zaidi
  • Publication number: 20040241489
    Abstract: Disclosed is a sliding member including an overlay layer made of a Bi based alloy comprising Cu as an essential element and at least one element selected from the group of Sn and In, wherein the Bi based alloy comprises 0.1 to 10 mass % of Cu and 0.5 to 10 mass % in total of the at least one element selected from the group of Sn and In.
    Type: Application
    Filed: May 27, 2004
    Publication date: December 2, 2004
    Applicant: Daido Metal Company Ltd.
    Inventors: Toshiaki Kawachi, Hideo Ishikawa, Masaaki Sakamoto
  • Publication number: 20040209108
    Abstract: A joined structure of a metal terminal and a ceramic member has a joining layer between the terminal and the ceramic member. The joining layer has a metal adhesive layer containing at least indium metal. The invention further provides a joined structure of a metal member and a ceramic member. The metal member has a tip face and a side face. A hollow is formed in the ceramic member. A joining layer is formed between a bottom surface facing the hollow and the tip face of the member, and further formed between a side wall surface facing the hollow and the side face of the member. The joining layer has a metal adhesive layer containing at least indium metal.
    Type: Application
    Filed: May 14, 2004
    Publication date: October 21, 2004
    Applicant: NGK Insulators, Ltd.
    Inventors: Tomoyuki Fujii, Mitsuru Ohta, Tsuneaki Ohashi
  • Publication number: 20040202887
    Abstract: A Bi base material of which a Miller index (202) face has the index of orientation of not less than 30% and in which the (202) face has the index of orientation assuming a maximum value as compared with those of other faces forms a minute structure and has a surface which is not a mirror finished surface but a fine, irregular surface on which minute and uniform projections in the form of a triangular pyramid or a quadrangular pyramid congregate. Therefore, the surface easily retains oil thereon to be improved thereby in oil wettability, as a result of which an improvement in anti-seizure is achieved.
    Type: Application
    Filed: April 12, 2004
    Publication date: October 14, 2004
    Applicant: Daido Metal Company, Inc.
    Inventors: Toshiaki Kawachi, Hideo Ishikawa, Masaaki Sakamoto
  • Publication number: 20040132275
    Abstract: A process of synthesizing metal and metal nitride nanowires, the steps comprising of: forming a catalytic metal (such as gallium, and indium) on a substrate (such as fused silica quartz, pyrolytic boron nitride, alumina, and sapphire), heating the combination in a pressure chamber, adding gaseous reactant and/or solid metal source, applying sufficient microwave energy (or current in hot filament reactor) to activate the metal of interest (such as gold, copper, tungsten, and bismuth) and continuing the process until nanowires of the desired length are formed. The substrate may be fused silica quartz, the catalytic metal a gallium or indium metal, the gaseous reactant is nitrogen and/or hydrogen and the nanowires are tungsten nitride and/or tungsten.
    Type: Application
    Filed: November 10, 2003
    Publication date: July 8, 2004
    Inventors: Mahendra Kumar Sunkara, Hari Chandrasekaran, Hongwei Li
  • Patent number: 6759117
    Abstract: A multilayer ceramic composite is described which contains at least one supporting zone having oxidation-sensitive reinforcing fibers as well as a matrix. The matrix optionally contains oxidation-sensitive components. The composite further contains at least one surface layer, as well as at least one additional protective layer disposed between the supporting zone and surface layer, and whose matrix is composed substantially of at least one component of the matrix of the supporting zone or cover layer. The protective layer further contains additives that form self-healing layers.
    Type: Grant
    Filed: July 8, 2002
    Date of Patent: July 6, 2004
    Assignee: SGL Carbon AG
    Inventors: Moritz Bauer, Martin Christ, Udo Gruber, Michael Heine, Andreas Kienzle, Jens Rosenlöcher, Rainer Zimmermann-Chopin
  • Patent number: 6756132
    Abstract: A joined structure includes a metal terminal, a ceramic member and a joining layer between the metal terminal and the ceramic member. The joining layer includes a metal adhesive layer containing at least indium metal. The invention further provides a joined structure including a metal member, a ceramic member, and a joining layer. The metal member includes a tip face and a side face. A hollow portion is formed in the ceramic member. The joining layer is formed between a bottom surface facing the hollow portion and the tip face of member, and further formed between a side wall surface facing the hollow portion and the side face of the metal member. The joining layer also includes a metal adhesive layer containing at least indium metal.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: June 29, 2004
    Assignee: NGK Insulators, Ltd.
    Inventors: Tomoyuki Fujii, Mitsuru Ohta, Tsuneaki Ohashi
  • Publication number: 20040096632
    Abstract: Provided is a Pb-free solder composition having an excellent heat resistance which does not damage a glass substrate and parts on the substrate when the soldering is carried out on to an electrode pattern formed on the substrate. The Pb-free solder composition contains, for example, not less than about 90% by weight of Bi, from about 0.1% to 9.9% by weight of Ag and from about 0.1% to 3.0% by weight of Sb, based on the whole solder composition.
    Type: Application
    Filed: November 12, 2003
    Publication date: May 20, 2004
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Hidekiyo Takaoka, Kunihiko Hamada
  • Publication number: 20040048092
    Abstract: With regard to a function device formed by filling a porous structure with a functional material and a method for manufacturing the functional device, a technique for realizing a structure on a nanometer scale is not fully established. However, a method for manufacturing a function device characterized by including a step of providing a structure including columnar members and an area surrounding the columnar members, a step of removing the columnar members from the structure to form a porous body and a step of filling the porous body with a functional material allows various types of function device to be provided.
    Type: Application
    Filed: September 8, 2003
    Publication date: March 11, 2004
    Inventors: Nobuhiro Yasui, Tohru Den, Kazuhiko Fukutani
  • Patent number: 6703144
    Abstract: A semiconductor structure including a first substrate, and an epitaxial layer bonded to the substrate. The epitaxial layer has a threading dislocation density of less than 107 cm−2 and an in-plane lattice constant that is different from that of the first substrate and a second substrate on which the epitaxial layer is fabricated. In another embodiment, there is provided a method of processing a semiconductor structure including providing a first substrate; providing a layered structure including a second substrate having an epitaxial layer provided thereon, the epitaxial layer having an in-plane lattice constant that is different from that of the first substrate and a threading dislocation density of less than 107 cm−2; bonding the first substrate to the layered structure; and removing the second substrate.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: March 9, 2004
    Assignee: AmberWave Systems Corporation
    Inventor: Eugene A. Fitzgerald
  • Publication number: 20040016792
    Abstract: A first member 10 containing at least ceramics and a second member 12 containing at least a metal or a metal composite was joined with each other. An adhesive 2 composed of a metal containing at least indium and materials 1A, 1B containing at least a component capable of reducing the melting point of indium between the first and second members to provide a laminate 13. The laminate 13 is heated at a temperature in solid-liquid coexisting range of an alloy comprising indium and said component to join the first member 10 and second member 12.
    Type: Application
    Filed: July 18, 2003
    Publication date: January 29, 2004
    Applicant: NGK Insulators, Ltd.
    Inventors: Tomoyuki Fujii, Hideyoshi Tsuruta, Tetsuya Kawajiri
  • Patent number: 6673469
    Abstract: Arrangement (1) for decreasing galvanic corrosion between metal components that includes at least a first component (2) in which a first metal is a part, and at least a second component (3) in which a second metal is a part, whereby the first metal has a higher normal-electrode potential (e0) than the second metal. The first component (2) is intended, after mounting, to be in electrical contact with the second component (3). The first component (2) is coated with a substantially continuous surface layer (4) that is adjusted to give the second component (3) an insignificant galvanic corrosion velocity after mounting. The invention is preferably applied in association with attachment elements such as bolt or screw joint reinforcements, which include a more noble metal than the component or the components with which the attachment element should be in contact with after mounting, and is particularly, preferred for vehicle components.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: January 6, 2004
    Assignee: Volvo Personvagnar AB
    Inventors: Malte Isaccsson, Henrik Hyttel, Thomas Hermansson, Stig Andersen, Kalsten Andersen, Mikael Fransson
  • Patent number: 6649281
    Abstract: A voltage variable composite structure comprising: a first layer of metal; a second layer of low-loss dielectric material impregnated with an array of first metal vias; a third layer of a voltage variable dielectric material; a fourth layer of a patterned thin metallic film; a fifth layer of low-loss dielectric material impregnated with an array of second metal vias; and a sixth layer of metal.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: November 18, 2003
    Assignee: Raytheon Company
    Inventor: William H. Henderson
  • Patent number: 6638629
    Abstract: A method and structure for fabricating a semiconductor wafer that may be used to monitor the temperature distribution across a wafer surface. A substrate that includes a semiconductor material and a first dopant, has an amorphous layer formed from a top portion of the substrate, and the amorphous layer is doped with a second dopant of polarity opposite to a polarity of the first dopant. Heating of the wafer at 450 to 625 degree C. recrystallizes a portion of the amorphous layer that is adjacent to the substrate at a recrystallization rate that depends on a local temperature on the wafer surface. The measured spatial distribution of sheet resistance may be utilized to readjust the spatial distribution of heat input to another wafer in order to achieve a more uniform temperature across the other wafer's surface.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: October 28, 2003
    Assignee: International Business Machines Corporation
    Inventors: Donna K. Johnson, Jerome B. Lasky, Glenn R. Miller
  • Patent number: 6635323
    Abstract: The present invention provides a raw material 1 used for production of GaAs crystals by utilizing solidification of melt, wherein As 12 is accommodated in the inside of Ga 10, 11. Because As 12 is covered with Ga 10, 11, As 12 is not brought into contact with the air and can thus be conveyed without oxidizing As 12. The raw material 1 can be heated and melted as such to produce GaAs crystals by the Czochralski method.
    Type: Grant
    Filed: February 6, 2001
    Date of Patent: October 21, 2003
    Inventors: Tadashi Kihara, Takeharu Yamamura, Kenichi Tayama
  • Publication number: 20030186073
    Abstract: A semiconductor structure including a first substrate, and an epitaxial layer bonded to the substrate. The epitaxial layer has a threading dislocation density of less than 107cm−2 and an in-plane lattice constant that is different from that of the first substrate and a second substrate on which the epitaxial layer is fabricated. In another embodiment, there is provided a method of processing a semiconductor structure including providing a first substrate; providing a layered structure including a second substrate having an epitaxial layer provided thereon, the epitaxial layer having an in-plane lattice constant that is different from that of the first substrate and a threading dislocation density of less than 107 cm−2; bonding the first substrate to the layered structure; and removing the second substrate.
    Type: Application
    Filed: March 18, 2003
    Publication date: October 2, 2003
    Applicant: AmberWave Systems Corporation
    Inventor: Eugene A. Fitzgerald
  • Patent number: 6613448
    Abstract: A magnetoresistance effect film includes a substrate, a plurality of ferromagnetic particles disposed on the substrate, a nonmagnetic film deposited on the substrate and covering the plurality of ferromagnetic particles, and a pair of electrodes arranged on the nonmagnetic film, in which the resistance across the pair of electrodes is changed by applying a magnetic field. The magnetoresistance effect film is manufactured by vapor-depositing ferromagnetic particle starting material on a substrate at a temperature not exceeding 300° C., the starting material being vapor-deposited in an amount enough to cover the substrate surface to a thickness ranging from 0.5 to 15 nm, and, after formation of ferromagnetic particles on the substrate, vapor-depositing at a temperature not exceeding room temperature a nonmagnetic film over the ferromagnetic particles, the nonmagnetic film having a thickness ranging from 1 to 100 nm, and providing a pair of electrodes each at a predetermined position on the nonmagnetic film.
    Type: Grant
    Filed: March 13, 2000
    Date of Patent: September 2, 2003
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Hiroyuki Akinaga, Masaharu Oshima, Masaki Mizuguchi
  • Patent number: 6610421
    Abstract: A spin electronic material exhibiting a spin-dependent electronic effect includes zincblende TE-VE, where TE stands for V, Cr or Mn and VE stands for As or Sb.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: August 26, 2003
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Hiroyuki Akinaga, Masafumi Shirai, Takashi Manago
  • Patent number: 6602613
    Abstract: A semiconductor structure including a first substrate, and an epitaxial layer bonded to the substrate. The epitaxial layer has a threading dislocation density of less than 107 cm−2 and an in-plane lattice constant that is different from that of the first substrate and a second substrate on which the epitaxial layer is fabricated. In another embodiment, there is provided a method of processing a semiconductor structure including providing a first substrate; providing a layered structure including a second substrate having an epitaxial layer provided thereon, the epitaxial layer having an in-plane lattice constant that is different from that of the first substrate and a threading dislocation density of less than 107 cm−2; bonding the first substrate to the layered structure; and removing the second substrate.
    Type: Grant
    Filed: January 17, 2001
    Date of Patent: August 5, 2003
    Assignee: AmberWave Systems Corporation
    Inventor: Eugene A. Fitzgerald
  • Patent number: 6586113
    Abstract: Systems and methods of manufacturing etchable heterojunction interfaces and etched heterojunction structures are described. A bottom layer is deposited on a substrate, a transition etch layer is deposited over the bottom layer, and a top layer is deposited over the transition etch layer. The transition etch layer substantially prevents the bottom layer and the top layer from forming a material characterized by a composition substantially different than the bottom layer and a substantially non-selective etchability with respect to the bottom layer. By tailoring the structure of the heterojunction interface to respond to heterojunction etching processes with greater predictability and control, the transition etch layer enhances the robustness of previously unreliable heterojunction device manufacturing processes. The transition etch layer enables one or more vias to be etched down to the top surface of the bottom layer in a reliable and repeatable manner.
    Type: Grant
    Filed: July 19, 2000
    Date of Patent: July 1, 2003
    Assignee: Agilent Technologies, Inc.
    Inventors: Sandeep R. Bahl, Yu-Min Houng, Virginia M. Robbins, Fred Sugihwo
  • Patent number: 6527858
    Abstract: A p-type ZnO single crystal having a low resistance; and a method for producing the same providing a substrate (2) in a vacuum chamber (1), supplying to the substrate (2) atomic gases of Zn, O, and N (p-type dopant) and Ga (n-type dopant) in a manner wherein the feeds of N and Ga are controlled in such a manner that the ratio of N:Ga in a crystal is 2:1, and thereby growing a p-type ZnO single crystal containing N and Ga.
    Type: Grant
    Filed: May 7, 2001
    Date of Patent: March 4, 2003
    Assignee: Rohm Co. Ltd.
    Inventors: Hiroshi Yoshida, Tetsuya Yamamoto
  • Publication number: 20020168856
    Abstract: A semi-insulating InP substrate in which a Ru-doped semi-insulating semiconductor layer is formed on the surface is provided, wherein the Ru-doped semi-insulating semiconductor layer has a complete semi-insulating property. The semiconductor optical device is fabricated by forming the Ru-doped semi-insulating semiconductor layer on a Fe-doped semi-insulating InP substrate, and forming a semiconductor crystal layer to which a p-type impurity is doped.
    Type: Application
    Filed: May 10, 2002
    Publication date: November 14, 2002
    Inventors: Ryuzo Iga, Matsuyuki Ogasawara, Susumu Kondo, Yasuhiro Kondo
  • Publication number: 20020136931
    Abstract: High quality epitaxial layers of monocrystalline piezoelectric materials (106) and acousto-optic materials (108) can be grown overlying monocrystalline substrates (102) such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer (104) on a silicon wafer (102). The accommodating buffer layer (104) is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide (110). The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Acousto-Optic devices (1018) may be formed using the piezoelectric materials (106) and the acousto-optic materials (108) and integrated with devices formed within the substrate (102) or other devices (1016, 1018) formed using other epitaxially grown monocrystalline layers.
    Type: Application
    Filed: March 20, 2001
    Publication date: September 26, 2002
    Applicant: Motorola, Inc.
    Inventors: Kurt W. Eisenbeiser, Jeffrey M. Finder
  • Patent number: 6432558
    Abstract: A semiconductor ceramic device comprises a body composed of a semiconductor ceramic having a positive resistance-temperature coefficient primarily composed of barium titanate and electrodes provided on the body, in which the resistance-temperature coefficient is 9%/° C. or more, resistivity is 3.5 ∩·cm or less, and withstand voltage is 50 V/mm or more. As the semiconductor ceramic forming the body provided in a thermistor having positive resistance-temperature characteristics, a semiconductor ceramic having a positive resistance-temperature coefficient is used, in which the semiconductor ceramic has an average particle diameter of about 7 to 12 &mgr;m and comprises barium titanate as a major component and sodium in an amount of about 70 ppm or less on a weight basis.
    Type: Grant
    Filed: August 8, 2000
    Date of Patent: August 13, 2002
    Assignee: Murata Manufacturing Co. Ltd.
    Inventors: Yasuhiro Nabika, Tetsukazu Okamoto, Toshiharu Hirota, Yoshitaka Nagao
  • Patent number: 6432521
    Abstract: This invention provides a Group III-V compound semiconductor that is free from the limitation of the shape and the size, is economical, is excellent in photo-electric characteristics (photo-electric conductivity photo-electromotive current, photo-electromotive force, quantum efficiency), can freely select the optical gap over a broad range, has high performance as a photo-semiconductor, has limited change with time, and is excellent in response, environmental resistance characteristics and high temperature resistance. The Group III-V compound semiconductor contains a Group III element and a Group V element of the Periodic Table as principal components, and contains also 0.1 atom % to 40 atom % of hydrogen atoms and 100 ppm to 20 atom %, based on the sum of the atomic numbers of the Group III element and the Group V element, of at least one element selected from among Be, Mg, Ca, Zn and Sr.
    Type: Grant
    Filed: May 24, 2000
    Date of Patent: August 13, 2002
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Shigeru Yagi, Seiji Suzuki
  • Publication number: 20020086178
    Abstract: Arrangement (1) for decreasing galvanic corrosion between metal components that includes at least a first component (2) in which a first metal is a part, and at least a second component (3) in which a second metal is a part, whereby the first metal has a higher normal-electrode potential (e0) than the second metal. The first component (2) is intended, after mounting, to be in electrical contact with the second component (3). The first component (2) is coated with a substantially continuous surface layer (4) that is adjusted to give the second component (3) an insignificant galvanic corrosion velocity after mounting. The invention is preferably applied in association with attachment elements such as bolt or screw joint reinforcements, which include a more noble metal than the component or the components with which the attachment element should be in contact with after mounting, and is particularly, preferred for vehicle components.
    Type: Application
    Filed: December 28, 2001
    Publication date: July 4, 2002
    Inventors: Malte Isacsson, Henrik Hyttel, Thomas Hermansson, Stig Andersen, Kalsten Andersen, Mikael Fransson
  • Patent number: 6410162
    Abstract: A p-type zinc oxide film and a process for preparing the film and p-n or n-p junctions is disclosed. In a preferred embodiment, the p-type zinc oxide film contains arsenic and is grown on a gallium arsenide substrate. The p-type zinc oxide film has a net acceptor concentration of at least about 1015 acceptors/cm3, a resistivity of no greater than about 1 ohm-cm, and a Hall mobility of between about 0.1 and about 50 cm2/Vs.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: June 25, 2002
    Assignee: The Curators of the University of Missouri
    Inventors: Henry W. White, Shen Zhu, Yungryel Ryu