Printed Circuit Patents (Class 428/901)
  • Patent number: 6376050
    Abstract: An electrically connecting device and an electrical connecting method in which electrical connections can be positively realized via electrically conductive particles despite slight irregularities of objects to be eclectically connected to each other. The electrical connecting device 100 electrically connects an electrically connection portion 5 of the first object and the electrically connection portion 3 of the second object. The electrical connecting device 100 is made up of a first film-shaped adhesive layer 6 and a second film-shaped adhesive layer 9. The first film-shaped adhesive layer 6, arranged on the first object 4, is made up of plural electrically conductive particles 7 and a binder 8 containing the electrically conductive particles 7. The second film-shaped adhesive layer 9, arranged on the first film-shaped adhesive layer 6 containing the electrically conductive particles, is made up only of a fluid binder.
    Type: Grant
    Filed: December 23, 1999
    Date of Patent: April 23, 2002
    Assignees: Sony Corporation, Sony Chemicals Corporation
    Inventors: Tohru Terasaki, Noriyuki Honda, Seiichi Miyachi, Yasuhiro Suga
  • Patent number: 6372364
    Abstract: A thin film product having a nanostructured surface, a laminate product including the thin film and a temporary substrate opposite the nanostructured surface, a laminate product including the thin film and a final substrate attached to the nanostructured surface and a method of producing the thin film products. The thin film is particularly useful in the electronics industry for the production of integrated circuits, printed circuit boards and EMF shielding. The nanostructured surface includes surface features that are mostly smaller than one micron, while the dense portion of the thin film is between 10-1000 nm. The thin film is produced by coating a temporary substrate (such as aluminum foil) with a coating material (such as copper) using any process. One such method is concentrated heat deposition or a combustion, chemical vapor deposition process.
    Type: Grant
    Filed: August 18, 1999
    Date of Patent: April 16, 2002
    Assignee: MicroCoating Technologies, Inc.
    Inventors: Andrew T. Hunt, Henry A. Luten, III
  • Patent number: 6372061
    Abstract: A rolled copper foil for flexible printed circuits comprising, all by weight, from 0.0100 to 0.0400% of Ag, from 0.0100 to 0.0500% of oxygen, not more than 0.0030% in total of one or more elements selected from the group consisting of S, As, Sb, Bi, Se, Te, Pb, and Sn, and the balance copper, the foil having a thickness in the range of 5 to 50 &mgr;m, a half-softening temperature of 120 to 150° C., being capable of retaining a tensile strength of at least 300 N/mm2 at 30° C., and possessing excellent flex fatigue property and adequate softening property. The intensity (I) of the (200) plane determined by X-ray diffraction of the rolled surface after annealing at 200° C. for 30 minutes is I/Io>20 with respect to the X-ray diffraction intensity (Io) of the (200) plane of fine copper powder.
    Type: Grant
    Filed: November 2, 1999
    Date of Patent: April 16, 2002
    Assignee: Nippon Mining & Metals Co., Ltd.
    Inventors: Takaaki Hatano, Yoshio Kurosawa
  • Patent number: 6368698
    Abstract: A printed circuit board is made from at least one non-woven sheet or web layer comprising at least 50% by weight acrylic fibers, with any balance substantially electrically non-conductive fibers, filler, and binder. The sheet or web is preferably made by the foam process, and may contain 60-80% straight polyacrylonitrile fibers and 40-20% fibrillated (pulp) ones. The web or sheet is preferably compressed by thermal calendering so that it has a density of about 0.1-1 grams per cubic centimeter; and the web or sheet may have a basis weight of between about 20-120 grams per square meter. The web or sheet may also have a 1-40% of substantially electrically non-conductive organic or inorganic binder, or may be substantially binder free.
    Type: Grant
    Filed: May 19, 2000
    Date of Patent: April 9, 2002
    Assignee: Ahlstrom Glassfibre Oy
    Inventors: Kay Rokman, Rod Komlenic, Kelly Rennels, Hakan Sabel
  • Publication number: 20020039644
    Abstract: Provided is a printed wiring board for a chip size scale package, which overcomes the poor adhesion of solder balls to a base material which poor adhesion is caused by a recent decrease in the size of the solder balls, and in the chip size scale package, the distortion of the printed wiring board is decreased and the distortion of a semiconductor plastic package formed by mounting a semiconductor chip on the printed wiring board by wire bonding or flip chip bonding is decreased.
    Type: Application
    Filed: October 11, 2001
    Publication date: April 4, 2002
    Inventors: Hidenori Kimbara, Nobuyuki Ikeguchi, Katsuji Komatsu
  • Patent number: 6365260
    Abstract: A heat dissipation arrangement for chip modules on multilayer ceramic substrates, in particular multichip modules, in which passages for a heat-conducting medium are provided in the ceramic substrate. The multilayer ceramic substrate is mounted on a metal heat sink. Thermal passages, in particular in the form of a hole pattern or array, are provided in the top layer of the multilayer ceramic substrate, in the region of the chip to be mounted. A cavity functioning as an evaporation chamber is provided in the layer of the multilayer ceramic substrate directly beneath the top layer, in the region of the chip to be mounted, and a trough-shaped recess functioning as a condenser is provided in the metal heat sink, in the region of the chip to be mounted.
    Type: Grant
    Filed: July 8, 1999
    Date of Patent: April 2, 2002
    Assignee: Robert Bosch GmbH
    Inventors: Günther Stecher, Annette Seibold
  • Publication number: 20020037397
    Abstract: A compression function layer 60 is provided on at least one board surface. The compression function layer 60 adds a function of being compressed by receiving pressure in the direction of the board thickness to the resin board 10 which includes this layer. Thereby a sufficient pressure is applied to conductors 14.
    Type: Application
    Filed: September 26, 2001
    Publication date: March 28, 2002
    Applicant: Matsushita Electric Industrial Co. Ltd.
    Inventors: Takeshi Suzuki, Satoru Tomekawa, Yoshihiro Kawakita, Yasushi Nakagiri, Fumio Echigo
  • Publication number: 20020037434
    Abstract: A method of manufacturing an integrated circuit and an integrated circuit employing the same. In one embodiment, the method of manufacturing the integrated circuit includes (1) conformally mapping a micromagnetic device, including a ferromagnetic core, to determine appropriate dimensions therefor, (2) depositing an adhesive over an insulator coupled to a substrate of the integrated circuit and (3) forming the ferromagnetic core of the appropriate dimensions over the adhesive.
    Type: Application
    Filed: October 15, 2001
    Publication date: March 28, 2002
    Inventors: Anatoly Feygenson, Dean P. Kossives, Ashraf W. Lotfi, Lynn F. Schneemeyer, Michael L. Steigerwald, R. Bruce Van Dover
  • Patent number: 6361866
    Abstract: Provided are a halogen-free and phosphorus-free prepreg having good flame retardancy and having excellent electric characteristics and heat resistance, and a laminated board. The prepreg is formed of a resin composition comprising, as essential components, a phenol compound (I) having a structural unit of the formula (1), wherein R1 is hydrogen or phenol, R2 is a hydrogen or methyl and n is an integer of 0 to 10, an epoxy resin (II) prepared by epoxidizing the same phenol compound as said phenol compound, a metal hydrate (III) and a molybdenum compound (IV), and a substrate which is impregnated with said resin composition or to which said resin composition is applied. The laminated board for an insulating material, which is formed of the prepreg.
    Type: Grant
    Filed: March 13, 2000
    Date of Patent: March 26, 2002
    Assignees: Mitsubishi Gas Chemical Company, Inc., The Sherwin-Williams Company
    Inventors: Masahiko Ogima, Takeshi Narushima, Norio Nagai
  • Publication number: 20020034620
    Abstract: In a mounting structure including a first electrode and a second electrode electrically connected to each other via a conductive adhesive, the periphery of an adhesion portion between at least one of the electrodes and the conductive adhesive is covered with an electrical insulating layer, whereby the adhesion portion is reinforced from the periphery. The electrical insulating layer may be formed by dissolving a binder resin component of the conductive adhesive in a solvent. This increases the concentration of a conductive filler in the conductive adhesive, so that the conductivity of the adhesion portion is also enhanced.
    Type: Application
    Filed: September 27, 2001
    Publication date: March 21, 2002
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaki Takezawa, Tsutomu Mitani, Minehiro Itagaki, Yoshihiro Bessho, Kazuo Eda
  • Patent number: 6359233
    Abstract: Disclosed is a printed circuit board multipack, having a plurality of printed circuit boards (for example, a plurality of PCI compliant cards) provided using a common web of substrate material for a printed circuit board. Also disclosed is printed circuit board multipack structure, from which the multipack is formed, and individual printed circuit boards formed from the multipack, and methods of manufacture of each. Printed circuit board structures of the multipack have an internal edge, spaced from the periphery of the web, that is bevelled, and have conductive fingers, e.g., with an electrodeposited gold uppermost layer, extending to the internal edge. The multipack structure includes a common bus bar running adjacent the inner boundary of the printed circuit board structures, and conductive extensions from a conductive base layer of the conductive fingers to the bus bar. Due to the conductive extensions and common bus bar, electrode-position of the gold for the conductive fingers can easily be performed.
    Type: Grant
    Filed: October 26, 1999
    Date of Patent: March 19, 2002
    Assignee: Intel Corporation
    Inventors: Steven C. Joy, Michael J. Lane
  • Patent number: 6356451
    Abstract: Conductive layers have at least a portion of a conductive member arranged in a nonlinear or polygonal configuration and having a greater layout area and an insulating layer is alternately stacked relative to the conductive layer, wherein a variation in amount of the conductive member at the conductive layer with a middle of a board thickness direction as a reference is set in a range in which a warp is less likely to be produced and in a range near to zero.
    Type: Grant
    Filed: January 15, 1999
    Date of Patent: March 12, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasutada Nakagawa, Nobuko Nakamura, Yasuo Fujii
  • Patent number: 6355324
    Abstract: The present invention provides a metal substrate parts gang having a frame, multiple substrates and multiple connective portions. The connective portions include a notched portion or break-out zone. A coating of resist or mask material is applied in the immediate proximity of the notched portion and then a layer of dielectric coating material is applied to the carrier gang. The resist serves to prevent the deposition of the dielectric coating material in the proximity of the notched portion. After coating, the carrier gang is fired in order to cure the dielectric material. The piece of base metal may be further processed, for example, screen printed with thick or think film inks. When required, the piece of base metal can be easily removed or separated from the frame by bending and/or twisting.
    Type: Grant
    Filed: November 15, 2000
    Date of Patent: March 12, 2002
    Assignee: The Erie Ceramic Arts Company
    Inventors: Richard N. Giardina, Craig C. Sundberg, Timothy A. Kuzma
  • Publication number: 20020025417
    Abstract: A conductive via pattern (110) between the uppermost metal interconnect layer (Mn ) and next underlying metal interconnect layer (Mn−1) in the bond pad areas strengthens the interlevel dielectric (ILD3) between metal layers (Mn and Mn−1). The conductive via layer (110) may, for example, comprise parallel rails (114) or a grid of cross-hatch rails (116). By spreading the stress concentration laterally, the conductive via layer (110) inhibits micro-cracking from stress applied to the bond pad (112).
    Type: Application
    Filed: August 23, 2001
    Publication date: February 28, 2002
    Inventors: Michael F. Chisholm, Darvin R. Edwards, Gregory B. Hotchkiss, Reynaldo Rincon, Viswanathan Sundararaman
  • Publication number: 20020018880
    Abstract: A stamping foil includes a carrier film, a layer of heat activated adhesive, a layer of vacuum deposited copper, a substrate and a release layer. The layers are activated by heat and pressure by a die which causes the layers to delaminate from the carrier film and adhere to a surface of a substrate in a predetermined electrically conductive pattern. The release layer releasably couples the layer of vacuum deposited copper to the substrate.
    Type: Application
    Filed: April 2, 2001
    Publication date: February 14, 2002
    Inventor: Robert P. Young
  • Publication number: 20020015833
    Abstract: A process for producing an electrodeposited copper foil, comprising the steps of: preparing an electrolyte having a copper concentration of 60 to 90 g/lit., preferably 60 to 85 g/lit., a free sulfuric acid concentration of 80 to 250 g/lit., preferably 100 to 250 g/lit., a chloride (Cl) ion concentration of 1 to 3 ppm and a gelatin additive concentration of 0.3 to 5 ppm and electrolyzing at 40 to 60° C. and at a current density of 30 to 120 A/dm2 preferably 30 to 75 A/dm2, to thereby electrodeposit a copper foil. The obtained electrodeposited copper foil is excellent in tensile strength and elongation.
    Type: Application
    Filed: August 2, 2001
    Publication date: February 7, 2002
    Inventors: Naotomi Takahashi, Yutaka Hirasawa
  • Patent number: 6342680
    Abstract: A lead-free super-highly conductive plastic is formed of a conductive resin composition which includes a thermoplastic resin, a lead-free solder that melts during plasticization, and metal powder or a mixture of metal powder and metal short fibers that promotes the fine dispersion of particles of the lead-free solder within the thermoplastic resin. In the lead-free super-highly conductive plastic, since particles of the lead-free solder are connected with each other via solder melted within the plastic, the particles of the lead-free solder are mutually joined, so that high conductivity is attained.
    Type: Grant
    Filed: February 20, 1998
    Date of Patent: January 29, 2002
    Assignee: Japan Science and Technology Corporation
    Inventors: Takeo Nakagawa, Hiroyuki Noguchi
  • Patent number: 6342670
    Abstract: A photoelectric module device comprising a multiple layer printed circuit board and at least one photoelectric module device is provided. The multiple layer printed circuit board has at least an upper circuit board substrate, a lower circuit board substrate, and a circuit. A plurality of photoelectric elements are installed on the multiple layer printed circuit board and is electrically connected to the circuit. The photoelectric elements are packaged above the multiple layer printed circuit board by injection molding a transparent resin thereon. The lower substrate has a plurality of through holes formed therein and the inner wall of the through holes is plated with metal, as an electric terminal. The upper circuit board substrate serves to seal the through holes and prevent resin from permeating therein during the injection molding process.
    Type: Grant
    Filed: September 19, 2000
    Date of Patent: January 29, 2002
    Assignee: Lite-On Electronics, Inc.
    Inventors: Ching Kai Lin, Hsu Keng Tseng
  • Patent number: 6338767
    Abstract: A circuit component built-in module of the present invention includes an insulating substrate formed of a mixture comprising 70 wt % to 95 wt % of an inorganic filler and a thermosetting resin, a plurality of wiring patterns formed on at least a principal plane of the insulating substrate, a circuit component arranged in an internal portion of the insulating substrate and electrically connected to the wiring patterns, and an inner via formed in the insulating substrate for electrically connecting the plurality of wiring patterns. Thus, a highly reliable circuit component built-in module having high-density circuit components can be obtained.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: January 15, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Seiichi Nakatani, Kouichi Hirano
  • Patent number: 6338893
    Abstract: A ceramic printed circuit substrate includes a glass ceramic substrate and a surface circuit pattern, which is formed on the substrate by use of a conductive paste. The conductive paste contains conductive components of silver and platinum and filler components of molybdenum, tungsten, manganese dioxide, silicon dioxide and copper oxide. A ceramic green sheet and a surface circuit pattern formed thereon by use of the conductive paste are simultaneously fired at a temperature not higher than 1000° C., thereby yielding the ceramic printed circuit substrate.
    Type: Grant
    Filed: October 25, 1999
    Date of Patent: January 15, 2002
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Eiji Kodera, Hitoshi Nagura, Hironori Sato, Shigeru Taga
  • Publication number: 20020004125
    Abstract: A method of manufacturing a low loss printed circuit board material including the steps of: providing a substrate comprising at least one layer of cross-linked polyethylene, providing a conducting foil, bringing a surface of the foil together with a surface of the substrate, casting a bonding layer of molten polyethylene between the surfaces, laminating the foil onto the substrate and cross-linking the bonding layer.
    Type: Application
    Filed: May 17, 2001
    Publication date: January 10, 2002
    Inventor: Valery Ostrovsky
  • Patent number: 6337123
    Abstract: A multilayered ceramic substrate which includes at least two types of ceramic layers respectively containing different ceramic materials, and which can be produced by simultaneous firing without causing layer peeling is described. A green composite laminated product is prepared in a state in which two substrate green sheets respectively contain different types of low-temperature sintered ceramic materials, and a shrinkage inhibiting green sheet containing an inorganic material which is not sintered at the sintering temperature of each of the low-temperature sintered ceramic material is arranged between the two substrate green sheets, followed by firing.
    Type: Grant
    Filed: August 23, 2000
    Date of Patent: January 8, 2002
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Koji Ryugo, Mitsuyoshi Nishide
  • Patent number: 6337148
    Abstract: Copper precursors useful in liquid delivery CVD for forming a copper-containing material on a substrate. The disclosed copper precursors are particularly useful for metallization of interconnections in semiconductor device structures.
    Type: Grant
    Filed: May 25, 1999
    Date of Patent: January 8, 2002
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Chongying Xu, Thomas H. Baum
  • Publication number: 20020001699
    Abstract: In a manufacturing method of a printed circuit board comprising a process of coating insulative resin on a surface of a printed circuit board having a blind hole and a process of filling up the insulative resin in the blind hole, the printed circuit board coated with the insulative resin is kept in a low pressure atmosphere of 1.3 to 666 hPa, and then the insulative resin is hardened, so that the insulative resin is filled up in the blind hole appropriately.
    Type: Application
    Filed: July 20, 2001
    Publication date: January 3, 2002
    Applicant: Victor Company of Japan, Ltd.
    Inventors: Yasuaki Seki, Shigenori Shiratori, Kenji Suzuki
  • Patent number: 6335077
    Abstract: As an electrically conductive paste for via-holes, an organic vehicle and an electrically conductive metal powder coated with a resin which is insoluble in the organic vehicle are prepared. Filling via-holes with the electrically conductive paste for via-holes produces a monolithic ceramic. Filling characteristics of the electrically conductive paste into via-holes are improved, and cracks and elevations of the conductive metal and cracks of the ceramic barely form during the baking step. Further, the resulting monolithic ceramic substrate can maintain excellent soldering wettability and plating characteristics.
    Type: Grant
    Filed: September 24, 1998
    Date of Patent: January 1, 2002
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hiroji Tani, Kazuhito Ohshita
  • Patent number: 6335076
    Abstract: A plurality of double-sided circuit boards 1 in which a circuit 4 is provided on either side of an insulating layer 3 comprising an organic high molecular resin with an alloy foil 2 as a basic substance, and two circuits 4 are electrically connected by a via with a soldered conductor 5a filled therein are laminated via an adhesive layer 6. The adhesive layer 6 has a bore opened at a predetermined position of a portion in direct contact with the circuits 4 of two double-sided circuit boards 1. A bore portion is provided with a soldered conductor 7. The circuits 4 of the two double-sided circuit boards 1 are electrically connected by the soldered conductor 7.
    Type: Grant
    Filed: July 13, 2000
    Date of Patent: January 1, 2002
    Assignee: Nitto Denko Corporation
    Inventors: Kei Nakamura, Masakazu Sugimoto, Yasushi Inoue, Megumu Nagasawa, Takuji Okeyui
  • Patent number: 6335107
    Abstract: In accordance with the invention, a metal substrate is coated with a multilayer surface finish comprising, in succession, an amorphous metal underlayer, a corrosion-resistent metal middle layer and one or more outer layers of precious metal. In an exemplary embodiment the metal substrate comprises copper alloy, the amorphous metal underlayer is Ni—P, the middle layer is nickel and the outer layer is palladium. The resulting structure is particularly useful as an electrical connector.
    Type: Grant
    Filed: September 23, 1999
    Date of Patent: January 1, 2002
    Assignee: Lucent Technologies Inc.
    Inventors: Joseph Anthony Abys, Chonglun Fan
  • Publication number: 20010055676
    Abstract: Disclosed is a metal-clad laminate product having a carrier film, a aqueous soluble release or parting layer deposited onto the carrier film and which can be mechanically separated from the carrier film, and an ultra thin metal layer deposited onto the parting layer. Also disclosed is a method for making the metal-clad laminate product.
    Type: Application
    Filed: May 11, 1998
    Publication date: December 27, 2001
    Inventor: GORDON C. SMITH
  • Patent number: 6331678
    Abstract: A device with a multi-layered micro-component electrical connector. The multi-layer micro-component electrical connector includes a dielectric layer, a micro-mesh of a first electrical conductor secured to the dielectric layer, and a second electrical conductor secured to and contacting the micro-mesh to provide electrical communication. The dielectric layer has a dielectric layer thermal expansion coefficient and the first electrical conductor has a thermal expansion coefficient different from the dielectric layer thermal expansion coefficient. Due to the presence of the micro-mesh the device is operable at temperatures above 250° C. without delamination or blistering of the first electrical conductor from the dielectric layer.
    Type: Grant
    Filed: October 29, 1999
    Date of Patent: December 18, 2001
    Assignee: Agilent Technologies, Inc.
    Inventors: Tak Kui Wang, Phillip W. Barth, Michel G. Goedert
  • Patent number: 6331348
    Abstract: Paste comprising metallic organic compound, in particular, gold-based metallic organic compound is used as a conductive material for repairing the broken defective part and is baked. This can produce a very thin metallic film having low electric resistance. Further, a semiconductor laser is used as a heating unit to heat only the broken defective part, and a heating profile having a baking process of provisional baking and main baking and a cooling process is provided to produce the high-quality thin metallic film having no crack and a dense texture.
    Type: Grant
    Filed: October 15, 1998
    Date of Patent: December 18, 2001
    Assignee: Alps Electric Co., Ltd.
    Inventors: Osamu Sakai, Keiji Takagi
  • Patent number: 6331347
    Abstract: A circuit pattern 2a, made of copper foil, is arranged on a substrate 1. A nickel-containing barrier metal layer 2b is formed on the circuit pattern 2a. A gold layer 2c is formed on the barrier metal layer 2b by electroless substitution plating. Then, substrate 1 is heated up to impel nickel contained in the gold layer 2c to move toward a surface zone of the gold layer 2c to deposit nickel compound in the surface zone of the gold layer 2c, thereby enhancing the fineness of a remaining part of the gold layer 2c at at least an inside zone immediately below the surface zone. Then, the surface zone containing the crowded nickel compound is removed off the gold layer 2c so as to expose a purified surface of the inside zone of the gold layer 2c. Therefore, it becomes possible to form an excellent electrode having satisfactory bondability to the wire by using a less amount of gold at low costs.
    Type: Grant
    Filed: April 1, 1998
    Date of Patent: December 18, 2001
    Assignee: Matsushita Electric Industrial Co., LTD
    Inventor: Hiroshi Haji
  • Patent number: 6331680
    Abstract: A multilayer, monolithic electrical interconnection device includes a substrate and a plurality of overlaying, alternating conducting and insulating layers deposited atop the substrate and one another. The layers are deposited by thermal spraying of respective insulating or conducting material through defined apertures in respective spray masks. Interlayer electrical connections are intrinsically formed by direct metallurgical bonding between the conducting material of an overlaying layer and the conducting material of a previously sprayed layer.
    Type: Grant
    Filed: August 7, 1996
    Date of Patent: December 18, 2001
    Assignee: Visteon Global Technologies, Inc.
    Inventors: David John Klassen, Morgan Merritt Whitney, Jr., Thomas Randall Peterman, Paul Earl Pergande, David Robert Collins
  • Patent number: 6329065
    Abstract: A wiring board having an insulating substrate of aluminum oxide ceramics and a surface wiring layer formed on the surface of said insulating substrate, wherein the aluminum oxide ceramics constituting said insulating substrate contains a manganese compound in an amount of from 2.0 to 10.0% by weight in terms of MnO2, and has a relative density of not smaller than 95%, and said surface wiring layer contains copper in an amount of from 10 to 70% by volume and at least one high-melting metal selected from the group consisting of tungsten and molybdenum in an amount of from 30 to 90% by volume, and further contains copper as a matrix, said copper matrix having a diffusion structure in which are diffused the particles of said high-melting metal having an average particle diameter of from 1 to 10 &mgr;m.
    Type: Grant
    Filed: August 23, 1999
    Date of Patent: December 11, 2001
    Assignee: Kyocera Corporation
    Inventors: Masanobu Ishida, Shigeki Yamada, Yasuhiko Yoshihara, Masamitsu Onitani
  • Patent number: 6329074
    Abstract: This invention provides a copper foil for a printed wiring board, which comprises a copper foil, an alloy layer (A) comprising copper, zinc, tin and nickel which is formed on a surface of the copper foil, said surface to be brought into contact with a substrate for a printed wiring board, and a chromate layer which is formed on a surface of the alloy layer (A,. The copper foil for a printed wiring board has the following features: even if a printed wiring board is produced using a long-term stored copper foil, the interface between the copper foil and the substrate is only slightly corroded with chemicals; even if the copper foil contacts a varnish containing an organic acid, e.g., a varnish for an acrylic resin, in the formation of a copper-clad laminate, the bond strength is sufficient. Even if a printed circuit board made by using the copper foil is placed in a high temperature environment, e.g.
    Type: Grant
    Filed: November 29, 1999
    Date of Patent: December 11, 2001
    Assignee: Mitsui Mining & Smelting Co., Ltd.
    Inventors: Kazuhisa Fujiwara, Hiroshi Tan, Mitsuo Fujii, Masanobu Tsushima
  • Patent number: 6329603
    Abstract: Conductive materials that have low coefficients of thermal expansion (CTEs) and that are used for power and ground planes are disclosed. Fibrous materials (such as carbon, graphite, glass, quartz, polyethylene, and liquid crystal polymer fibers) with low CTEs are metallized to provide a resultant conductive material with a low CTE. Such fibers may be metallized in their individual state and then formed into a fabric, or these materials may be formed into a fabric and then metallized or a combination of both metallizations may be used. In addition, a graphite or carbon sheet may be metallized on one or both sides to provide a material that has a low CTE and high conductivity. These metallized, low CTE power and ground planes may be laminated with other planes/cores into a composite, or laminated into a core which is then laminated with other planes/cores into a composite. The resultant composite may be used for printed circuit boards (PCBs) or PCBs used as laminate chip carriers.
    Type: Grant
    Filed: April 7, 1999
    Date of Patent: December 11, 2001
    Assignee: International Business Machines Corporation
    Inventors: Robert M. Japp, Mark D. Poliks
  • Patent number: 6329045
    Abstract: A composition for substrate materials according to the present invention includes 70-95 wt. % of inorganic powder and 5-30 wt. % of thermosetting resin composition and is in a finely crushed condition. The composition for substrate materials is prepared, for example, by crushing into fine pieces and mixing the inorganic powder and the thermosetting resin composition. A heat conductive substrate is provided with an insulator body formed by heating and pressurizing said composition for substrate materials and a wiring pattern is provided in such a condition that it is exposed on the surface of the insulator body. A process for manufacturing the heat conductive substrate comprises forming said composition for substrate materials into the insulator body by casting the above mentioned composition for substrate materials into a metal mold to be heated and pressurized so that said thermosetting resin is cured.
    Type: Grant
    Filed: February 17, 2000
    Date of Patent: December 11, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koichi Hirano, Seiichi Nakatani, Hiroyuki Handa
  • Patent number: 6325110
    Abstract: A woven fabric reinforcement characterized by a weight of up to 190 grams per square meter, with a number of warp yarns which is at least 55% of the total number of yarns, and where the crossovers between warp yarns and weft yarns is between 200 and 315 crossovers per square centimeter. Yarn deposition is such that the sum of each yarn torsion component in warp and in weft is balanced and equal to zero. This fabric is used in laminated composite structures, in particular printed circuit boards.
    Type: Grant
    Filed: May 13, 1999
    Date of Patent: December 4, 2001
    Assignee: Gividi Italia S.p.A.
    Inventors: Diego Scari, Marco Scari
  • Patent number: 6321443
    Abstract: The method for the manufacture of multilayer connecting substrates with multiple functions comprises the design of the connecting substrate taking place in functionally separated manner, in that signal conducting substrate parts (19), power supplying substrate parts (2), mechanical substrate parts (7), as well as the arrangement of components (4) or component-carrying substrate parts is separately planned and optimized as independent functions or modules and finally associated with spatially separated functional areas (inner/outer) of the overall circuit, the design taking place by the connection of the modules to an overall circuit embodying the connecting substrate. The resulting multilayer circuit with conductor network (19, 2), components (4) and mechanical stiffening elements (7) has the following structure.
    Type: Grant
    Filed: May 13, 1998
    Date of Patent: November 27, 2001
    Assignees: Dyconex Patente AG, Atotech Deutschland GmbH, Ciba Specialty Chemicals Holding, Inc., Fraunhofer-Gesellschaft zur Foerderung der Angewandten, Forschung E.V., Techn. Universitaet Dresden
    Inventors: Hans-Jürg Barte, Ewald Losert, Heinrich Meyer, Günter Röhrs, Frank Rudolf, Wolfgang Scheel, Walter Schmidt, Theis Zur Nieden
  • Patent number: 6324067
    Abstract: A printed wiring board (PWB) and assembly are described which are suitable for high density mounting of an electronic component and which can provide a thin and light assembly. A recess is formed in one part of a PWB and components are received in this recess. The components are lower than the surface of the PWB. A conductive pad is provided to the bottom of the recess and a connecting terminal and the conductive pad are electrically connected by using a solder ball or a conductive adhesive material. The recess is formed by partially removing one or more layers of plural conductive layers and insulating layers which make up the multilayer PWB.
    Type: Grant
    Filed: April 20, 2000
    Date of Patent: November 27, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Tousaku Nishiyama
  • Patent number: 6322904
    Abstract: A copper foil having improved resistance to abrasion damage during the manufacture of printed circuit boards has a uniform deposit of benzotriazole (BTA) or BTA derivative, optionally a mixture thereof, of at least about 5 mg/m2.
    Type: Grant
    Filed: March 20, 1997
    Date of Patent: November 27, 2001
    Assignee: Mitsui Mining & Smelting Co., Ltd.
    Inventors: Makoto Dobashi, Hiroaki Kurihara, Toshiko Yokota, Hiroshi Hata, Naotomi Takahashi, Tatsuya Sudo
  • Patent number: 6319620
    Abstract: This invention provides a composite foil comprising an organic release layer between a metal carrier layer and an ultra-thin copper foil, and a process for producing such composite foils comprising the steps of depositing the organic release layer on the metal carrier layer and then forming an ultra-thin copper foil layer on said organic release layer, preferably by electrodeposition. The organic release layer preferably is a heterocyclic compound selected from triazoles, thiazoles, imidazoles, or their derivatives, and provides a uniform bond strength which is adequate to prevent separation of the carrier and ultra-thin copper foil during handling and lamination, but which is significantly lower than the peel strength of a copper/substrate bond, so that the carrier can easily be removed after lamination of the composite foil to an insulating substrate. The invention also includes laminates made from such composite foils and printed wiring boards made from such laminates.
    Type: Grant
    Filed: March 16, 1998
    Date of Patent: November 20, 2001
    Assignee: Mitsui Mining & Smelting Co., Ltd.
    Inventors: Takashi Kataoka, Yutaka Hirasawa, Takuya Yamamoto, Kenichiro Iwakiri
  • Patent number: 6319616
    Abstract: A method of forming a conductive line structure is provided. An adhesion layer is formed on a substrate surface. A seed layer is formed on the adhesion layer. A conductor is formed on the seed layer to form a partially complete structure. The partially complete structure is exposed to an electrolyte and undergoes an anodization process. At least a portion of the seed layer and a portion of the conductor are transformed to seed layer metal oxide and conductor metal oxide, respectively. At least a portion of the adhesion layer is transformed to an adhesion layer metal oxide and a further portion of the conductor is transformed to the conductor metal oxide.
    Type: Grant
    Filed: October 29, 1999
    Date of Patent: November 20, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sergey Lopatin, Robin Cheung
  • Publication number: 20010038911
    Abstract: A polyphenylene sulfide film has a heat distortion temperature of 200° C. or more. The polyphenylene sulfide film of the present invention has superior soldering heat resistance, dimensional stability to heat, low hygroscopicity, fire retardance, and high-frequency properties, and also the polyphenylene sulfide film is suitable for use as an insulating substrate which has superior processability in a circuit board.
    Type: Application
    Filed: January 24, 2001
    Publication date: November 8, 2001
    Inventors: Kenji Tsunashima, Tetsuya Machida, Jun Sakamoto
  • Patent number: 6309737
    Abstract: A circuit substrate which has a ceramic substrate and an Al circuit comprising Al or an Al alloy bonded to said ceramic substrate via a layer comprising Al and Cu.
    Type: Grant
    Filed: May 26, 2000
    Date of Patent: October 30, 2001
    Assignee: Denki Kagaku Kogyo Kabushiki Kaisha
    Inventors: Yutaka Hirashima, Yoshitaka Taniguchi, Yasuhito Hushii, Yoshihiko Tujimura, Katsunori Terano, Takeshi Gotoh, Syoji Takakura, Nobuyuki Yoshino, Isao Sugimoto, Akira Miyai
  • Patent number: 6310775
    Abstract: The present invention for solving the problem of suppressing the load caused by heat stress applied on an insulation substrate, reducing the manufacturing coat of a power module substrate, and improving productivity provides a power module substrate in which a buffer layer having a surface area one to three times as large as the surface area of the insulation substrate is laminated and bonded between the insulation substrate and the heat sink, wherein the buffer layer is formed using a material having a thermal expansion coefficient between the thermal expansion coefficients of the insulation substrate and the heat sink, the insulation substrate being preferably formed using AlN, Si3N4 or Al2O3, the buffer layer being preferably formed using AlSiC, and a carbon plate or a composite material of AlC, besides the thickness of the buffer layer being preferably 1.
    Type: Grant
    Filed: March 20, 2000
    Date of Patent: October 30, 2001
    Assignee: Mitsubishi Materials Corporation
    Inventors: Yoshiyuki Nagatomo, Toshiyuki Nagase, Kazuaki Kubo, Shoichi Shimamura
  • Patent number: 6306481
    Abstract: A multilayer circuit board having a resolution in the range of 25-80 &mgr;m, and blind via-holes between layers, the blind via-holes having an aspect ratio in the range of 2.0-0.6 for effecting access between the layers, wherein an insulating layer having the blind via-holes between the layers has a glass transition temperature in the range of 150-220° C., and an epoxy group photosensitive resin composition is used therefor. A photosensitive resin composition having a preferable resolution and heat resistance is obtained. A multilayer circuit board is provided in which the thermal stress generated in the steps of a reflow process, a gold wire bonding process and a repairing process in a bare chip mounting process are reduced, and peeling off of the conductor wiring and deformation of the multilayer circuit board caused by mechanical stresses during the heating processes are suppressed. Accordingly, a decrease in the size and weight of an electronic apparatus is possible.
    Type: Grant
    Filed: June 22, 1999
    Date of Patent: October 23, 2001
    Assignees: Hitachi, Ltd., Hitachi Chemical Company, Ltd.
    Inventors: Satoru Amou, Masao Suzuki, Tokihito Suwa, Mineo Kawamoto, Akio Takahashi, Masanori Nemoto, Hiroyuki Fukai, Mitsuo Yokota, Shiro Kobayashi, Masashi Miyazaki
  • Patent number: 6303871
    Abstract: An organic land grid array having multiple built up layers of metal sandwiching non-conductive layers, having a staggered pattern of degassing holes in the metal layers. The staggered pattern occurs in two substantially perpendicular directions. Traces between the metal layers have reduced impedance variation due to the degassing hole pattern.
    Type: Grant
    Filed: June 11, 1999
    Date of Patent: October 16, 2001
    Assignee: Intel Corporation
    Inventors: Longqiang Zu, Huong Do
  • Patent number: 6294744
    Abstract: The present invention provides a multilayer print circuit board having at least an inner print circuit pattern and an outer print circuit pattern which are laminated on a substrate through an insulation layer and being electrically connected to each other through a blind hole provided in the insulation layer. The insulation layer is composed of a resin insoluble in an oxidization agent and inorganic powder dispersed in the resin. The inorganic powder is soluble in the oxidization agent. The surface of insulation layer and the wall of the blind hole are roughed by the oxidization agent before the outer print circuit pattern is formed on the surface of the insulation layer by plating, whereby the inorganic powder exposed to the oxidization agent is melted therein, resulting in the roughed surface of the insulation layer and the wall of the blind hole.
    Type: Grant
    Filed: October 6, 1999
    Date of Patent: September 25, 2001
    Assignee: Victor Company of Japan, Ltd.
    Inventor: Tohru Kinoshita
  • Patent number: 6294743
    Abstract: The present invention provides a multilayer print circuit board having at least an inner print circuit pattern and an outer print circuit pattern which are laminated on a substrate through an insulation layer and being electrically connected to each other through a blind hole provided in the insulation layer. The insulation layer is composed of a resin insoluble in an oxidization agent and inorganic powder dispersed in the resin. The inorganic powder is soluble in the oxidization agent. The surface of insulation layer and the wall of the blind hole are roughed by the oxidization agent before the outer print circuit pattern is formed on the surface of the insulation layer by plating, whereby the inorganic powder exposed to the oxidization agent is melted therein, resulting in the roughed surface of the insulation layer and the wall of the blind hole.
    Type: Grant
    Filed: October 6, 1999
    Date of Patent: September 25, 2001
    Assignee: Victor Company of Japan, Ltd.
    Inventor: Tohru Kinoshita
  • Patent number: RE37599
    Abstract: A method is disclosed for making hydroxy-substituted ethynylated biphenyl compounds and for reacting such compounds with a family of noncross-linking thermosetting poly(arylene ethers) to produce novel poly(arylene ether) compositions which, when cured at glass transition temperatures greater than about 350° C. to form thin films, possess properties such as low dielectric constant, low moisture absorption, and high thermal stability. These films are suitable for use as intermetal dielectrics for multilevel interconnection.
    Type: Grant
    Filed: September 8, 2000
    Date of Patent: March 19, 2002
    Assignee: AlliedSignal Inc.
    Inventors: Kreisler Lau, Neil Hendricks, William Wan, Aaron Smith