Printed Circuit Patents (Class 428/901)
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Patent number: 6589639Abstract: A composition usable in hole filling of a metal layer and to planarize the metal layer is provided. The metal layer is part of a substrate which can be part of a multilayer printed circuit board or chip carrier. The composition comprises a fluoropolymer dielectric metal, a filler material, and a coupling agent, the filler material having at least a partial coating of the coupling agent thereon.Type: GrantFiled: May 23, 2001Date of Patent: July 8, 2003Assignee: International Business Machines CorporationInventors: Donald S. Farquhar, Konstantinos I. Papathomas
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Publication number: 20030124326Abstract: A thermally conductive substrate having a structure in which inorganic filler for improving the thermal conductivity and thermosetting resin composition are included. The thermosetting resin composition has a flexibility in the not-hardened state, and becomes rigid after hardening. The thermally conductive substrate has excellent thermal radiation characteristics. The method of manufacturing the thermally conductive substrate includes: piling up (a) the thermally conductive sheets comprising 70 to 95 weight parts of an inorganic filler, and 4.Type: ApplicationFiled: December 4, 2002Publication date: July 3, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Seiichi Nakatani, Hiroyuki Handa
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Publication number: 20030124319Abstract: A material having a conductive pattern, the material comprising a support and a conductive element, the conductive element being 500 nm thick or less and containing a polyanion and an intrinsically conductive polymer, characterized in that one surface of the conductive element is an outermost surface of the material and the other surface of the conductive element is contiguous with a patterned surface, the patterned surface consisting of at least two types of surface element, and those parts of the conductive element contiguous with a type A surface element exhibiting a surface resistance at least a factor of ten greater than those parts of the conductive element contiguous with a type B surface element; a material for making a conductive pattern, the material comprising a support and a conductive element, the conductive element containing a polyanion and an intrinsically conductive polymer, characterized in that one surface of the conductive element is an outermost surface of the material, the other surfaceType: ApplicationFiled: June 20, 2002Publication date: July 3, 2003Applicant: AGFA-GEVAERTInventors: Johan Lamotte, David Terrell
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Patent number: 6586526Abstract: A multilayer printed circuit board having resinous insulating layers and conductor layers alternately superposed on a circuit board with ample adhesive strength, a method for the production thereof, and a curable resin composition useful for the formation of resinous insulating layers are disclosed. The manufacture of the multilayer printed circuit board is accomplished by applying the curable resin composition to the surface of conductor layer of the circuit board, thermally curing the applied layer thereby forming resinous insulating layer, then boring a through-hole in the circuit board, treating the resinous insulating layer with a coarsening agent thereby imparting undulating coarsened surface thereto, subsequently coating the surface of resinous insulating layer and the inner surface of the through-hole with a conductor layer as by electroless plating, and thereafter forming a prescribed circuit pattern in the conductor layer.Type: GrantFiled: May 9, 1995Date of Patent: July 1, 2003Assignee: Taiyo Ink Manufacturing Co., Ltd.Inventors: Akio Sekimoto, Shinichi Yamada
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Patent number: 6586105Abstract: The invention provides a packaging structure applied to an automotive component having semiconductors and electronic parts mounted on a ceramic base, characterized in that the semiconductors and electronic parts are partly or entirely sealed with a thixotropic silicone gel which has a thixotropy index of about 1.5-3.6 and a penetration depth of about 6-10 mm and a rate of change in viscosity of less than 10% of the initial value.Type: GrantFiled: April 3, 2001Date of Patent: July 1, 2003Assignee: Hitachi, Ltd.Inventors: Shuji Eguchi, Masahiko Asano, Mutsumi Watanabe, Kunito Nakatsuru, Hiroatsu Tokuda
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Patent number: 6586081Abstract: Polyimide/metal laminates having a polyimide film and a metal layer laminated thereon, wherein the polyimide film contains titanium element and flexible print wiring boards with the use of the same are disclosed. The polyimide/metal laminates are excellent in adhesion under the ordinary conditions and, moreover, can sustain the adhesive strength at a high ratio after exposure to high temperature or high temperature and high humidity. Owing to these characteristics, these polyimide/metal laminates are appropriately usable in flexible print wiring boards, multi-layered print wiring boards, rigid flex wiring boards, tapes for TAP, semiconductor packages such as CFOs and multi chip modules (MCMs), magnetic recording films, coating films for aerospace materials and filmy resistance elements.Type: GrantFiled: March 9, 2000Date of Patent: July 1, 2003Assignee: Kaneka CorporationInventors: Masaru Nishinaka, Kiyokazu Akahori
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Publication number: 20030117775Abstract: A coated heat spreader for a die includes a body and a coating on a surface of the body, wherein the outermost coating is an organic surface protectant. An IC package includes a die thermally coupled to a heat spreader coated with an organic surface protectant. A PCB assembly including a die thermally coupled to a heat spreader coated with an organic surface protectant, where the die is part of an IC package or is directly attached to the PCB. A method of making a coated heat spreader includes coating the organic surface protectant onto a surface of the heat spreader.Type: ApplicationFiled: December 20, 2001Publication date: June 26, 2003Inventors: Joan K. Vrtis, Joni G. Hansen, Thomas J. Fitzgerald, Carl L. Deppisch
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Publication number: 20030118797Abstract: A multi-layer conductive via structure and multi-layer circuit structure containing such multi-layer via structure are described along with the methods for making the structures. The structures include conductive material filled opening(s) located within flexible substrate layers that are supported by an adhesive layer.Type: ApplicationFiled: December 26, 2001Publication date: June 26, 2003Inventors: Robin Fluman, Ken Gann
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Patent number: 6583073Abstract: A process for the drying of woven glass fabric to be used in a reinforcing laminate in sensitive electronic equipment is disclosed. The process adopts a drying technique of utilizing dielectric or radio frequency heating which results in a cleaner product.Type: GrantFiled: November 21, 2000Date of Patent: June 24, 2003Assignee: BGF Industries, Inc.Inventors: Michael I. Bryant, Charles E. Jones
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Publication number: 20030113521Abstract: The present invention provides a laminate used for a printed wiring substrate and a multilayer printed wiring board which have high heat resistance, wiring patterns with narrow pitches, vias with a small diameter, insulating layer having uniform thickness and stable adhesion between the metal layer and the synthetic resin film, and which contribute to miniaturization, high capability and functional improvement of electronic equipment. The present invention relates to a metal laminate comprising a metal layer laminated on one or both faces of a synthetic resin film, wherein the metal layer is a metal foil having a thickness of at most 5 &mgr;m.Type: ApplicationFiled: October 28, 2002Publication date: June 19, 2003Inventors: Masaru Nishinaka, Takashi Itoh, Kanji Shimo-Ohsako
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Patent number: 6579600Abstract: A multilayer capacitor includes a unitary, net-shape molded dielectric ceramic body having first and second cavities molded into at least one side to divide the ceramic body into a plurality of ceramic layers disposed generally parallel to the top. The first cavities alternate with the second cavities in the ceramic body. Each of the ceramic layers except an uppermost and a lowermost of the ceramic layers is joined at one edge to one ceramic layer adjacent thereto by a first ceramic bridge and at the same or a different edge to another ceramic layer adjacent thereto by a second ceramic bridge. The first and second cavities are filled with one or more materials to form first and second electrically conductive electrode layers, respectively, each electrode layer being bonded to the ceramic layers adjacent thereto.Type: GrantFiled: July 25, 1996Date of Patent: June 17, 2003Assignee: Materials Systems, Inc.Inventors: Leslie J. Bowen, Brian G. Pazol, Craig D. Near, Richard L. Gentilman
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Patent number: 6576382Abstract: An improved photoimagable cationically polymerizable epoxy based solder mask is provided that contains a non-brominated epoxy resin system and from about 0.1 to about 15 parts, by weight per 100 parts of resin system, of a cationic photoinitiator. The non-brominated epoxy-resin system has solids that are comprised of from about 10% to about 80% by weight, of a polyol resin having epoxy functionality; from about 0% to about 90% by weight of a polyepoxy resin; and from about 25% to about 85% by weight of a difunctional epoxy resin. The photosensitive cationically polymerizable epoxy based system is especially useful as a solder mask and does not contain bromine.Type: GrantFiled: May 9, 2002Date of Patent: June 10, 2003Assignee: International Business Machines CorporationInventors: Richard Allen Day, David John Russell, Donald Herman Glatzel
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Patent number: 6572954Abstract: The invention relates to an electromechanical component which is configured as a sandwich-type structure. In the interior of said structure, a support layer consisting of foamed plastic is arranged. Said support layer is placed between covering layers which consist of compact materials. All layers are produced from hardly inflammable plastic material, for example LCP or PEI plastics so that it is not necessary to add any flame-retardant additives. The component can be configured in the shape of a slab but it can also have a more complex three-dimensional structure and can optionally be provided with mechanical functional elements. Accordingly to an aspect of the invention, the support layer of the component can consist of silicone. The composition of the inventive component provides a means for simplifying recycling a product at the end of its lifetime.Type: GrantFiled: April 25, 2001Date of Patent: June 3, 2003Assignee: Thomson Licensing, S.A.Inventors: Hans-Otto Haller, Volker Strubel
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Patent number: 6572968Abstract: Printed wiring boards improved in the drilling processability and insulation properties are produced either by treating the surfaces of base materials or inorganic fillers with silicone oligomers having specified structures, particularly, a three-dimensionally crosslinked silicone oligomer, or by using resin varnish prepared by compounding such a silicone oligomer with a resin varnish for impregnation of the base materials, or by dipping the inorganic fillers in a solution of such a silicone oligomer for surface treatment and then directly compounding resin materials with the solution.Type: GrantFiled: May 7, 2001Date of Patent: June 3, 2003Assignee: Hitachi Chemical Co., Ltd.Inventors: Nozomu Takano, Shigeo Sase, Tomio Fukuda, Michitoshi Arata
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Patent number: 6572955Abstract: High-frequency ceramics containing SiO2, Al2O3, MgO, ZnO and B2O3 as constituent components, said ceramics comprising: 30 to 50% by weight of a crystal phase containing ZnO and Al2O3; 5 to 15% by weight of a crystal phase containing SiO2 and MgO; and 40 to 60% by weight of an amorphous phase comprising substantially SiO2 or SiO2 and B2O3; wherein the content of the SiO2 crystal phase is suppressed to be not larger than 6% by weight. The ceramics has a dielectric loss at 60 GHz of not larger than 15×10−4, exhibiting excellent high-frequency characteristics, and is very useful as an insulating substrate for the wiring boards that deal with high-frequency signals.Type: GrantFiled: April 27, 2001Date of Patent: June 3, 2003Assignee: Kyocera CorporationInventors: Yoshitake Terashi, Masahiro Tomisako, Satoshi Hamano, Kazuyoshi Kodama, Katsuhiko Onitsuka
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Patent number: 6569512Abstract: In a mounting structure including a first electrode and a second electrode electrically connected to each other via a conductive adhesive, the periphery of an adhesion portion between at least one of the electrodes and the conductive adhesive is covered with an electrical insulating layer, whereby the adhesion portion is reinforced from the periphery. The electrical insulating layer may be formed by dissolving a binder resin component of the conductive adhesive in a solvent. This increases the concentration of a conductive filler in the conductive adhesive, so that the conductivity of the adhesion portion is also enhanced.Type: GrantFiled: September 27, 2001Date of Patent: May 27, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroaki Takezawa, Tsutomu Mitani, Minehiro Itagaki, Yoshihiro Bessho, Kazuo Eda
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Patent number: 6569513Abstract: A prepreg exhibiting excellent formability and producing laminated boards and multiple layer circuit boards exhibiting high thickness precision is disclosed. The prepreg comprises an inner layer made from a glass fiber substrate, having a weight of 40 g or more and less than 115 g per square meter and an air permeability or 20 cm3/cm2/sec or less, impregnated with an epoxy resin, and an outer layer of an epoxy resin coating provided on at least one side of the inner layer, wherein the epoxy resin reaction rate in the inner layer is 85% or more and the epoxy resin reaction rate in the outer layer is 60% or less.Type: GrantFiled: October 29, 2001Date of Patent: May 27, 2003Assignee: Sumitomo Bakelite Company LimitedInventors: Takashi Yamaji, Mamoru Komatsu
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Patent number: 6566288Abstract: A non-woven fabric comprising a principal component of para-aramid fiber chops bonded with each other by a binder, the para-aramid fiber chops having a mixture of (a) poly-p-phenylene-3,4′-diphenylether-terephthalamide fibers and (b) poly-p-phenylene-terephthalamide fibers and having a blend ratio by weight of (a)/(b)=10/90˜90/10 and preferably (a)/(b)=30/70˜70/30.Type: GrantFiled: February 6, 2001Date of Patent: May 20, 2003Assignees: Shin-Kobe Electric Machinery Co., Ltd., Oji Paper Co., Ltd.Inventors: Shigeru Kurumatani, Hirokazu Hiraoka, Masayuki Noda, Tomoyuki Terao, Setsuo Toyoshima, Yoshihisa Kato, Hiroyoshi Ueno
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Patent number: 6565954Abstract: Through holes formed in an electrical insulating substrate having adhesive layers on its both surfaces are filled with a conductor. Then, supporting bases having wiring layers with a predetermined pattern are laminated on both the surfaces of the electrical insulating substrate, which are then heated and pressurized. After that, the supporting bases are removed, thus obtaining a circuit board in which the wiring layers have been embedded in the adhesive layers. The conductor within the through holes are compressed sufficiently, thus forming minute via holes with high reliability.Type: GrantFiled: December 1, 2000Date of Patent: May 20, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Daizou Andou, Toshio Sugawa, Tadashi Nakamura, Hideki Higashitani, Masahide Tsukamoto
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Patent number: 6565977Abstract: In an insulating film having improved adhesive strength and a multilayer printed circuit board having the same, the insulating film made of an epoxy resin, a rubber and a filler, for use in an insulating layer of a multilayer printed circuit board, is composed of a first coating layer and a second coating layer. The first coating layer has a greater amount of rubber and filler and a smaller amount of epoxy resin than the second coating layer.Type: GrantFiled: July 17, 2001Date of Patent: May 20, 2003Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Sang-Jun Bae, Sung-Il Oh
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Patent number: 6565956Abstract: A multilayer ceramic wiring board prepared from a plurality of sheets formed from a ceramic-incorporating material containing a ceramic powder and a binder resin and each having a pattern of one or a plurality of circuit elements printed on a surface thereof with use of a conductive mixture material containing an electrically conductive powder and a binder resin, by placing the sheets over one another to form a laminate, and compressing and firing the laminate. The mean particle size Rs of the ceramic powder is not greater than the value of (Rd−&sgr;d) wherein Rd is the mean particle size of the conductive powder, and &sgr;d is the standard deviation obtained when the distribution of the particle sizes of the conductive powder is expressed by a normal distribution function. This feature prevents formation of projections which would otherwise extend from the surface of one circuit element toward another circuit element when the elements are formed by firing the laminate.Type: GrantFiled: November 28, 2001Date of Patent: May 20, 2003Assignees: Sanyo Electric Co., Ltd., Sanyo Electric Components, Ltd.Inventors: Takashi Ogura, Shigehiro Horimoto, Masanori Hongo
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Patent number: 6562925Abstract: An organic anti-reflective polymer having the following Formula 1, its preparation method, an anti-reflective coating composition comprising the organic anti-reflective polymer and a preparation method of an anti-reflective coating made therefrom. The anti-reflective coating comprising the polymer eliminates standing waves caused by the optical properties of lower layers on the wafer and by the thickness changes of the photoresist, prevents back reflection and CD alteration caused by the diffracted and reflected light from such lower layers. Such advantages enable the formation of stable ultrafine patterns suitable for 64M, 256M, 1G, 4G, and 16G DRAM semiconductor devices, improving the production yields and controlling the k values. It is also possible to prevent undercutting due to an unbalanced acidity after finishing the coating.Type: GrantFiled: June 25, 2001Date of Patent: May 13, 2003Assignee: Hynix Semiconductor IncInventors: Sung-eun Hong, Min-ho Jung, Jae-chang Jung, Geun-su Lee, Ki-ho Baik
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Publication number: 20030087137Abstract: A system makes a run of cross-linked non-halogenated flame retardant polyolefin material. The system includes an extruder having a die that defines an elongated opening which is at least 7.5 centimeters wide (e.g., substantially 40 centimeters wide). The extruder is configured to extrude molten non-halogenated flame retardant polyolefin material through the die. The system further includes a cooling assembly coupled to the extruder. The cooling assembly is configured to cool the extruded non-halogenated flame retardant polyolefin material so that the extruded non-halogenated flame retardant polyolefin material hardens into a sheet of non-halogenated flame retardant polyolefin material. The system further includes a cross-linking assembly which is configured to cross-link the sheet of non-halogenated flame retardant polyolefin material. Such material is well-suited for use in a variety of applications such as cables, construction materials and furniture, among other things.Type: ApplicationFiled: November 8, 2001Publication date: May 8, 2003Inventors: John P. Gagnon, Todd Pihl, Michael Quarrey, Charlie Thebeau
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Patent number: 6558797Abstract: An adhesive-coated copper foil which comprises a copper foil and disposed on one side thereof a layer of an adhesive composition comprising (a) an epoxy resin, (b) a polyfunctional phenol, (c) a curing accelerator as an optional ingredient, and (d) a compound having a triazine ring or isocyanuric ring. The adhesive layer has low hygroscopicity, excellent heat resistance, and satisfactory adhesion to copper foils. By using the adhesive-coated copper foil, a copper-clad laminate and a printed circuit board both having excellent properties can be obtained.Type: GrantFiled: June 22, 2001Date of Patent: May 6, 2003Assignee: Hitachi Chemical Company, Ltd.Inventors: Michitoshi Arata, Nozomu Takano, Kazuhito Kobayashi
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Patent number: 6558780Abstract: A circuit board includes an electrical insulator layer formed of a reinforcer sheet with density distribution in its in-plane direction, an electrical conductor filled in a plurality of inner via holes provided in the electrical insulator layer in its thickness direction, and a wiring layer connected to the electrical conductor. The inner via holes provided in a high-density portion of the reinforcer sheet are formed to have a smaller cross-section than the inner via holes provided in a low-density portion of the reinforcer sheet. In this manner, it is possible to provide a circuit board that can achieve a high-density wiring and an inner via connection resistance with less variation, when a base material including a reinforcer sheet with density distribution in its in-plane direction such as a glass-epoxy base material is used for an insulator layer.Type: GrantFiled: October 25, 2001Date of Patent: May 6, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takeshi Suzuki, Toshihiro Nishii, Satoru Tomekawa, Fumio Echigo
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Publication number: 20030082356Abstract: In the formation of through wirings in a silicon substrate and so forth, there was a need for the development of a technology that would allow metal to be reliably filled particularly in the vicinity of openings of through holes and other fine holes. This invention provides a metal filling method and member with filled metal sections in which, in the inflow and filling of a plating solution into through holes 11 of a substrate 10 by immersing said substrate 10 in heated and melted conductive metal, filled metal sections are formed by preliminarily forming a metal layer 15 on the inner surface of one of the ends of through holes 11 of this substrate 10 as well as on substrate top surface 13 around those openings, removing substrate 10 on which inflow and filling of the plating solution into through holes 11 has been completed from the plating solution, and then cooling to solidify the plating solution that has been filled into the through holes.Type: ApplicationFiled: September 19, 2002Publication date: May 1, 2003Applicant: Fujikura Ltd.Inventors: Tatsuo Suemasu, Takashi Takizawa
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Publication number: 20030081384Abstract: A heat sink structure increasing the dielectric strength of isolation for power integrated circuits is formed from a common layer on which laterally spaced isolated layers for each individual integrated circuit are mounted. At least the isolated layers are formed of anodized aluminum coated with aluminum oxide on exterior surfaces. The aluminum and aluminum oxide of the isolated layers provide good thermal conduction for heat dissipation while the electric isolation from the common electric potential of the common layer is improved, at least in part, by increasing the distance between the integrated circuits and the common layer. The heat sink structure may be mounted within a weatherproof enclosure with one externally exposed surface for heat dissipation.Type: ApplicationFiled: October 31, 2001Publication date: May 1, 2003Inventors: Jerald Ray Rider, Vester Ray Raynor
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Patent number: 6555227Abstract: Combination compounds from curing agents/accelerators and flame-protection agents for the latent curing/acceleration of epoxide resin systems and their endowment with flame-retarding properties, the epoxide resin systems being able to be thermally cured, as well as the products prepared from the epoxide resin systems.Type: GrantFiled: February 2, 2001Date of Patent: April 29, 2003Assignee: Schill & Seilacher (GmbH & Co.)Inventors: Stephan Sprenger, Rainer Utz, Michael Ciesielski, Manfred Doering
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Patent number: 6555200Abstract: A method of making semiconductor devices comprising the steps of: preparing non-defective individual film packages having good quality, wherein leads are formed and a semiconductor chip is mounted on each of the film packages; attaching each of the non-defective individual packages to each of mounting portions of a plate; and cutting the plate into separate pieces, each of the separated pieces corresponding to each of the mounting portions on which each of the non-defective individual film packages is mounted.Type: GrantFiled: March 16, 2000Date of Patent: April 29, 2003Assignee: Seiko Epson CorporationInventor: Nobuaki Hashimoto
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Patent number: 6555208Abstract: A solder resist comprising a thermosetting resin is printed on a surface of an insulating board (7) having a conductor circuit (6). The solder resist is then heat-cured to form an insulating film (1) having a low thermal expansion coefficient. A laser beam (2) is then applied to the portion of the insulating film in which an opening is to be formed, to burn off the same portion for forming an opening (10), whereby the conductor circuit (6) is exposed. This opening may be formed as a hole for conduction by forming a metal plating film on an inner surface thereof. It is preferable that an external connecting pad be formed so as to cover the opening. The film of coating of a metal is formed by using an electric plating lead, which is preferably cut off by a laser beam after the electric plating has finished.Type: GrantFiled: June 26, 2001Date of Patent: April 29, 2003Assignee: Ibiden Co., Ltd.Inventors: Masaru Takada, Hiroyuki Kobayashi, Kenji Chihara, Hisashi Minoura, Kiyotaka Tsukada, Mitsuhiro Kondo
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Publication number: 20030075270Abstract: A method of forming a circuit material comprises disposing an adhesion promoting elastomer composition between a conductive copper foil and a thermosetting composition; and laminating the copper foil, adhesion promoting composition, and thermosetting composition to form the circuit material. The adhesion promoting layer may be uncured or partially cured before contacting with the curable thermosetting composition. Preferably the adhesion promoting layer has electrical characteristics such as dissipation factor, dielectric breakdown strength, water absorption, and dielectric constant that are similar to and/or compatible with the electrical characteristics of the thermosetting composition.Type: ApplicationFiled: August 21, 2002Publication date: April 24, 2003Inventors: Vincent R. Landi, Bryan C. McAlister, John T. Neill
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Patent number: 6551427Abstract: The present invention provides a method for readily and efficiently manufacturing a ceramic substrate having an excellent dimensional accuracy and small degree of warp comprising the steps of: preparing a non-sintered multilayer ceramic body formed by laminating ceramic layers and conductor layers; forming a multilayer ceramic body with constraint layers by adhering a first constraint layer and a second constraint layer on one major surface and the other major surface, respectively, of the multilayer ceramic body, the first and second constraint layers being prepared by dispersing a ceramic powder that is not sintered under the sintering condition of the multilayer ceramic body; firing the multilayer ceramic body with the constraint layers under the firing condition of the multilayer ceramic body; and removing the first constraint layer and the second constraint layer after sintering the multilayer ceramic body, wherein the thickness of the first constraint layer is made to be larger than the thickness of theType: GrantFiled: March 11, 2002Date of Patent: April 22, 2003Assignee: Murata Manufacturing Co. Ltd.Inventors: Sadaaki Sakamoto, Hirofumi Sunahara
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Patent number: 6548122Abstract: Methods and apparatus are provided in which a metal precursor is formed in a process that includes the following steps: depositing a metal precursor on a substrate; adding an energy to reduce the metal precursor and to precipitate metal on the substrate as a continuous metal layer; and selecting the metal precursor and the energy such that the purity of the continuous metal layer is greater than 85%, and/or the deposited layer has an electrical conductivity substantially that of a pure metal. Methods and apparatus are also provided in which a metal is deposited onto a substrate by a process which includes the following steps: depositing the metal precursor onto the substrate in a desired pattern; and applying sufficient energy to decompose the precursor to precipitate metal in a continuous metal layer in the desired pattern.Type: GrantFiled: November 19, 1999Date of Patent: April 15, 2003Assignee: SRI InternationalInventors: Sunity Sharma, Subhash Narang, Kuldip Bhasin, Madan Lal Sharma
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Publication number: 20030068537Abstract: There is provided a metal/ceramic circuit board capable of eliminating discrepancy during mounting of parts to improve the reliability of mounting of the parts. The metal/ceramic circuit board has a ceramic substrate 10, and a metal circuit plate (a copper plate 14) bonded to the ceramic substrate 10, the metal circuit plate having a thickness of 0.1 mm to 0.5 mm, and the metal circuit plate having a skirt spreading length (a dimensional difference between the bottom and top portion of the peripheral edge portion of the metal circuit plate) of less than 50 &mgr;m.Type: ApplicationFiled: September 25, 2002Publication date: April 10, 2003Inventors: Nobuyoshi Tsukaguchi, Masami Kimura
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Patent number: 6544652Abstract: Disclosed are a cyanate ester based resin-containing insulating composition, an insulating film made therefrom and a multilayer printed board having the insulating film. The insulating composition comprises 1-75% by weight of epoxy resin, 1-60% by weight of cyanate ester resin, up to 20% by weight of a filler, a curing agent and a metal catalyst, from which the insulating film can be prepared, and the film-applied multilayer printed board can be manufactured. Use of epoxy resins having excellent electrical properties and cyanate ester based resins having high heat resistance causes the reaction of hydroxy groups in some epoxy resins with cyanate ester, thus forming such net structures as to increase the heat resistance of the insulating composition, the insulating film and the multilayer printed circuit board.Type: GrantFiled: June 13, 2001Date of Patent: April 8, 2003Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Sang-Jun Bae, Choong-Nam Park
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Patent number: 6544663Abstract: An object of the present invention is to provide a copper foil having excellent adhesion to an etching resist layer, without performing physical polishing such as buffing in pre-treatment of an etching process to form a circuit from the copper foil. To attain the object, in electroforming, a titanium material having a grain size number of 6.0 or more is employed as a copper deposition surface of the rotating drum cathode, and glue and/or gelatin is added in an amount of 0.2-20 mg/l to a copper sulfate solution, thereby producing a drum foil. An electrodeposited copper foil obtained from the drum foil, wherein 20% or more of the crystals present in a shiny side surface of the electrodeposited copper foil have a twin-crystal structure, is used for producing copper-clad laminates.Type: GrantFiled: August 28, 2001Date of Patent: April 8, 2003Assignee: Mitsui Mining & Smelting Co., Ltd.Inventors: Osamu Nakano, Takashi Kataoka, Sakiko Taenaka, Naohito Uchida, Noriko Hanzawa
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Publication number: 20030064254Abstract: This invention pertains to a siloxane resin composition comprising HSiO3/2 siloxane units, and (R2O)bSiO(4-b)/2 siloxane units wherein R2 is independently selected from the group consisting of branched alkyl groups having 3 to 30 carbon atoms and substituted branched alkyl groups having 3 to 30 carbon atoms, b is from 1 to 3. The siloxane resin contains a molar ratio of HSiO3/2 units to (R2O)bSiO(4-b)/2 units of 0.5:99.5 to 99.5. The siloxane resin is useful to make insoluble porous resins and insoluble porous coatings. Heating a substrate with the siloxane resin at a sufficient temperature effects removal of the R2O groups to form an insoluble porous coating having a porosity in a range of 1 to 40 volume percent and a modulus in the range of 4 to 80 GPa.Type: ApplicationFiled: July 26, 2001Publication date: April 3, 2003Inventors: Katsuya Eguchi, Ronald Paul Boisvert, Duane Raymond Bujalski, Pierre Maurice Chevalier, Duan-Li Ou, Kai Su
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Patent number: 6540927Abstract: A semiconductor packaging part and a method of forming the part by applying a minute plating with a high positional accuracy to a semiconductor chip to be packaged. A pair of alignment holes 2, 3 are formed at a pitch equal to n-times (n=1, 2 . . .Type: GrantFiled: February 18, 1998Date of Patent: April 1, 2003Assignee: Sumitomo Metal Mining Company, Ltd.Inventors: Makoto Nishida, Shinichi Nakamura
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Patent number: 6539626Abstract: A curved multilayer ceramic moulded part, particularly curved in directions perpendicular to one another, is limited by two virtually parallel surfaces and an edge. Electrically conductive path(s) parallel to the surface are provided internally. The molded part may be produced by deforming a dish-shaped green moulding, formed from a composite of a self-supporting ceramic film having at least one electrically conductive path and at least one additional ceramic film, with or without electrically conductive path(s), to pressure from all sides. The deformed part is subjected to burning out and sintering. The moulded articles are virtually free of defects. Absolute deviation from the average shrinking of less than 2% may be obtained.Type: GrantFiled: December 5, 2000Date of Patent: April 1, 2003Assignee: DSM N.V.Inventors: Johannes W. H. Kolnaar, Johannes L. M. Op Den Kamp, Jolanda I. M. Colnot, Hans H. H. Hornman
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Patent number: 6537675Abstract: In one embodiment, the present invention relates to a composite article, comprising a metal foil having a first side and a second side; a protective film of at least one inert silane, titanate or zirconate overlying the first side of the metal foil; and a metal sheet having a first side and a second side, the first side overlying the protective film. In another embodiment, the present invention relates to a method of increasing tarnish resistance of metal foil comprising contacting the metal foil with an inert silane, titanate or zirconate compound to form a protective film having a thickness from about 0.001 microns to about 1 micron on a surface of the metal foil; and attaching the foil to a metal sheet.Type: GrantFiled: November 15, 2000Date of Patent: March 25, 2003Assignee: Ga-Tek, Inc.Inventors: Sidney J. Clouser, Michael A. Centanni
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Patent number: 6537685Abstract: An electronic component includes external electrodes formed on a base member, each external electrode including a plurality of layers of which the outermost layer is a tin plating layer. The tin plating layer has a polycrystalline structure, and atoms of a metal other than tin are diffused into the tin crystal grain boundaries. Alternatively, each external electrode includes a plurality of layers including a thick-film electrode formed on the base member, a nickel layer or a nickel alloy layer formed on the thick-film electrode and a tin plating layer formed on the nickel layer or the nickel alloy layer. The tin plating layer has a polycrystalline structure and nickel atoms are diffused into the tin crystal grain boundaries. Methods for fabricating electronic components and a circuit board provided with a plurality of electronic components are also disclosed.Type: GrantFiled: May 22, 2001Date of Patent: March 25, 2003Assignee: Murata Manufacturing Co., Ltd.Inventor: Shoichi Higuchi
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Patent number: 6534186Abstract: A substrate that is substantially non-wettable to adhesive resin is disclosed. The substrate is coated with a fluorinated silane composition. Preferable fluorosilane compositions include perfluoroalkyl alkylsilanes of Formula III: R5nR6mSiX4−(n+m) III wherein R5 is a perfluoroalkyl alkyl radical; R6 is alkyl or alkenyl; X is acetoxy, halogen or alkoxy; n is 1 or 2; and m is 0 or 1. The composition is preferably applied in solution and upon evaporation of the solvent, forms a durable, non-wetting, yet well-adhering surface. In a preferred embodiment, the substrate is a chip carrier with enhanced wire bondability for use in the manufacture of a semiconductor device.Type: GrantFiled: March 27, 2001Date of Patent: March 18, 2003Assignee: International Business Machines CorporationInventors: Konstantinos Papathomas, Bernd Karl Appelt, John Joseph Konrad
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Patent number: 6534245Abstract: Apertures in a circuit board or chip carrier are filled with a cured photosensitive dielectric material by substantially filling the apertures in the circuit board or chip carrier and applying a layer of a thickness to the circuit board or chip carrier with a positive photosensitive dielectric material, exposing the photosensitive dielectric material to actinic radiation in such a way as to leave material located in apertures unexposed to the radiation; baking the structure so as to harden the unexposed photosensitive dielectric material and developing the exposed dielectric material in order to remove it leaving behind cured photosensitive dielectric material in the apertures.Type: GrantFiled: February 21, 2001Date of Patent: March 18, 2003Assignee: International Business Machines CorporationInventors: Bernd Karl Appelt, Gary Alan Johansson, Konstantinos I. Papathomas
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Patent number: 6534181Abstract: A resin blend that includes a copolymer of styrene and maleic anhydride (SMA), an epoxy resin (brominated, phosphonated, or bromine-free), and a multifunctional amine cross-linking agent is disclosed. The cross-linking agent generally contains at least two primary amino groups to promote formation of imide functionalities upon reaction with the anhydride moieties of the SMA copolymer. Particularly useful cross-linking agents include triazine-centered diamino and triamino compounds such as benzoguanamine, acetoguanamine, and melamine. The disclosed resin blend finds use as a polymer matrix in composite materials and as an impregnating resin in laminates. Compared to conventional SMA copolymer/epoxy resin blends, the disclosed resin exhibits lower dielectric constant and dissipation factor, as well as higher thermal and moisture resistance, making it especially useful in high-speed, low-loss printed wire board applications.Type: GrantFiled: March 27, 2001Date of Patent: March 18, 2003Assignee: Neltec, Inc.Inventor: David K. Luttrull
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Publication number: 20030044646Abstract: An electroluminescent device containing an anode, an organic electroluminescent element, and a cathode wherein the electroluminescent element contains, for example, a fluorescent hydrocarbon component of Formula (I) 1Type: ApplicationFiled: August 29, 2002Publication date: March 6, 2003Applicant: Xerox CorporationInventors: Nan-Xing Hu, Hany Aziz, Poonam Jain, Zoran D. Popovic
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Patent number: 6528145Abstract: A composite electronic and/or optical substrate including polymeric and ceramic material wherein the composite substrate has a dielectric constant less than 4 and a coefficient of thermal expansion of 8 to 14 ppm/°C. at 100° C. The composite substrate may be either ceramic-filled polymeric material or polymer-filled ceramic material.Type: GrantFiled: June 29, 2000Date of Patent: March 4, 2003Assignee: International Business Machines CorporationInventors: Daniel George Berger, Shaji Farooq, Lester Wynn Herron, James N. Humenik, John Ulrich Knickerbocker, Robert William Pasco, Charles H. Perry, Krishna G. Sachdev
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Publication number: 20030038038Abstract: The present invention relates to a method for forming a planar conductive surface on a wafer. In one aspect, the present invention uses a no-contact process with electrochemical deposition, followed by a contact process with electrochemical mechanical deposition.Type: ApplicationFiled: July 22, 2002Publication date: February 27, 2003Inventors: Bulent M. Basol, Cyprian E. Uzoh, Homayoun Talieh
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Patent number: 6524700Abstract: A pressure sensitive adhesive sheet for wafer sticking, comprising a base of polyvinyl chloride containing a plasticizer and, superimposed thereon, an energy radiation curable pressure sensitive adhesive layer of vinyl acetate copolymer, the energy radiation curable pressure sensitive adhesive layer, before exposure to energy radiation, having an elastic modulus ranging from 4.0×104 to 5.0×106 Pa at 50° C. The use of this pressure sensitive adhesive sheet for wafer sticking enables inhibiting the vibration of wafer at the time of dicing of the wafer so that chipping of the wafer can be minimized.Type: GrantFiled: February 16, 2001Date of Patent: February 25, 2003Assignees: NEC Corporation, Lintec CorporationInventors: Yasushi Masuda, Hideki Numazawa, Osamu Yamazaki
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Patent number: 6523446Abstract: A punched adhesive tape for semiconductor which is made by punching an adhesive tape comprising a base film and an adhesive layer provided on one or each side of the base film to mark the regions in the adhesive tape where contaminants or defects are contained; a method of producing an adhesive tape-bearing lead frame by punching the punched adhesive tape for semiconductor, with the parts containing the punched holes skipped over, and applying the adhesive tape pieces punched out from the punched adhesive tape for semiconductor to a lead frame; a semiconductor device fabricated by using the adhesive-bearing lead frame.Type: GrantFiled: January 18, 2000Date of Patent: February 25, 2003Assignee: Hitachi Chemical Company, Ltd.Inventors: Yoshiyuki Tanabe, Yoshihiro Nomura, Hiroshi Kirihara, Youichi Hosokawa, Shinji Iioka, Satoru Yanagisawa
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Patent number: H2066Abstract: Films having islands of noble metal protruding from and surrounded by a layer of a superconductor are formed by depositing a layer a noble metal on a substrate, and depositing a superconducting layer at a temperature that converts the noble metal film into puddles. The resulting film is useful as a two-dimensional array of superconductor-normal metal-superconductor Josephson junctions.Type: GrantFiled: August 5, 1996Date of Patent: June 3, 2003Assignee: The United States of America as represented by the Secretary of the NavyInventors: Edward J. Cukauskas, Laura H. Allen, Michael A. Fisher