Registration Or Layout Process Other Than Color Proofing Patents (Class 430/22)
  • Patent number: 10416578
    Abstract: A method for pre-aligning a substrate includes the steps of: 1) providing a substrate having a plurality of marks are arranged circumferentially on a surface thereof, wherein each of the plurality of marks consists of at least one first stripe extending in a first direction and at least one second stripe extending in a first direction; 2) aligning a center of the substrate with a given point on a substrate carrier stage; 3) illuminating a mark selected from the plurality of marks on the surface of the substrate with light and obtaining an image of the selected mark; 4) processing the image to obtain first projection data corresponding to the first direction and second projection data corresponding to the second direction; 5) identifying a set of first peak values corresponding to the at least one first stripe of the selected mark from the first projection data and a set of second peak values corresponding to the at least one second stripe of the selected mark from the second projection data; 6) selecting firs
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: September 17, 2019
    Assignee: SHANGHAI MICRO ELECTRONICS EQUIPMENT (GROUP) CO., LTD.
    Inventors: Xiwen Zhou, Weiwang Sun, Cuixia Tian, Jiaozeng Zheng
  • Patent number: 10401837
    Abstract: A method disclosed herein includes: converting an image of a manufactured circuit to a plurality of representative contours, the plurality of representative contours corresponding to printed features in the manufactured circuit; generating a risk inventory for the manufactured circuit based on the plurality of representative contours, the risk inventory being configured to identify at least one process sensitive geometry (PSG) in the manufactured circuit; generating a common process window (CPW) for the manufactured circuit based on the plurality of representative contours and the risk inventory, the CPW being indicative of manufacturing reliability of each feature in the manufactured circuit; and generating instructions to adjust a manufacturing tool for creating the manufactured circuit, based on the generated CPW.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 3, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hongxin Zhang, Shaowen Gao, Norman Chen
  • Patent number: 10379447
    Abstract: A method for simulation of lithography overlay is disclosed which comprises storing alignment parameters used to align a semiconductor wafer prior to a lithography step; storing process control parameters used during the lithography step on the semiconductor wafer; storing overlay parameters measured after the lithography step; calculating alternative alignment parameters and alternative process control parameters. The alternative alignment parameters and the alternative process control parameters are added to cleansed overlay parameters to obtain simulated lithography overlay data.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: August 13, 2019
    Assignee: Qoniac GmbH
    Inventor: Boris Habets
  • Patent number: 10365568
    Abstract: In a beam irradiation apparatus in which a movable body holds an object, a mark detection system detects a first mark on the movable body while moving the movable body in a first direction and changing an irradiation position of a measurement beam in the first direction, the mark detection system detects a second mark while moving the movable body in the first direction and changing the irradiation position of the measurement beam in the first direction, a controller controls a position of the movable body in a second direction intersecting the first direction during a time period between the detection of the first mark and the detection of the second mark, and the controller controls the movement of the movable body to adjust a positional relation between the object on the movable body and a processing beam, based on results of the detection of the first and second marks.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: July 30, 2019
    Assignee: NIKON CORPORATION
    Inventor: Akihiro Ueda
  • Patent number: 10355209
    Abstract: A vapor deposition mask includes a metal mask and a resin mask having an opening. An inner wall surface for composing the opening has an inflection point in a thicknesswise cross section of the resin mask. When an intersection of a first surface, not facing the metal mask, of the resin mask and the inner wall surface is set to be a first intersection, an intersection of a second surface, facing the metal mask, of the resin mask and the inner wall surface is set to be a second intersection, and there is set a first inflection point first positioned from the first intersection toward the second intersection, an angle formed by a line connecting the first intersection and the first inflection point and the first surface is larger than an angle formed by a line connecting the first inflection point and the second intersection and the second surface.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: July 16, 2019
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Toshihiko Takeda, Katsunari Obata, Hiroshi Kawasaki
  • Patent number: 10331036
    Abstract: In various embodiments, an exposure mask may include a carrier, a first exposure structure in a first structure plane of the carrier, and a second exposure structure in a second structure plane of the carrier. The two structure planes differ from one another.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: June 25, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Heiko Assmann, Markus Dankelmann, Uwe Winkler
  • Patent number: 10324371
    Abstract: The present disclosure provides a system for generating a mask pattern, a method for generating a mask pattern, and an exposure system. According to an embodiment of the present disclosure, the system for generating a mask pattern comprises: a mask pattern provision device configured to provide a mask pattern signal via a wired or wireless network; a mask pattern transmission device configured to process the mask pattern signal provided by the mask pattern provision device to generate mask pattern information, and to transmit the generated mask pattern information over a Radio Frequency Identification (RFID) signal; and a mask pattern generation device configured to generate a mask pattern corresponding to the mask pattern information based on the mask pattern information and display the generated mask pattern.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: June 18, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Tailiang Li, Junmin Sun, Hongli Ding, Hongtao Guan
  • Patent number: 10317757
    Abstract: A manufacture method of a black matrix is provided. The COA technology is utilized to manufacture organic photoresist blocks with an increased thickness on alignment marks. Then, a black matrix thin film is set on and covers the organic photoresist blocks to tremendously increase the level differences of the positions of the alignment marks and adjacent areas. A contour recognition apparatus can accurately recognize positions of the alignment marks. The issue that the alignment marks are difficult to recognize after the black matrix thin film is coated in the BOA process can be solved.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: June 11, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yuan Xiong
  • Patent number: 10310385
    Abstract: An optical system for producing lithographic structures is disclosed. Also disclosed is a method for determining relative coordinates of a position of a writing field relative to a position of a preview field in such an optical system, and a method for producing lithographic structures using such an optical system.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: June 4, 2019
    Assignee: Carl Zeiss AG
    Inventors: Philipp Huebner, Gerhard Krampert, Stefan Richter, Timo Mappes
  • Patent number: 10303050
    Abstract: This disclosure provides an imprint apparatus configured to form a pattern with an imprint material by bringing the imprint material on a substrate and a pattern of the mold into contact with each other including a drive unit to bring part of the pattern of the mold into contact with the imprint material, and bring the pattern into contact with the imprint material so a contact surface area between the pattern of the mold and the imprint material increases, an interference fringe detecting unit to detect an interference fringe generated by reflected light from the pattern of the mold and reflected light from the substrate, and a state detecting unit to detect a contact state between the pattern of the mold and the imprint material on the basis of the interference fringe.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: May 28, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hiroshi Sato
  • Patent number: 10303068
    Abstract: A projection exposure tool for microlithography for imaging mask structures of an image-providing substrate onto a substrate to be structured includes a measuring apparatus configured to determine a relative position of measurement structures disposed on a surface of one of the substrates in relation to one another in at least one lateral direction with respect to the substrate surface and to thereby simultaneously measure a number of measurement structures disposed laterally offset in relation to one another.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: May 28, 2019
    Assignee: Carl Zeiss SMT GmbH
    Inventors: Jochen Hetzler, Aksel Goehnermeier
  • Patent number: 10275562
    Abstract: A method of decomposing a layout for multiple-patterning lithography includes receiving an input that represents a layout of a semiconductor device. The layout includes a plurality of conductive lines of a cell. A first set of conductive lines are overlaid by a second set of conductive lines. The method further includes partitioning the second set of conductive lines into groups. A first group has a different number of conductive lines from the second set than a second group. The method further includes assigning conductive lines from the first set overlaid by conductive lines of the first group to a first photomask and assigning conductive lines from the first set overlaid by conductive lines of the second group to second and third photomasks.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Meng-Kai Hsu, Wen-Hao Chen
  • Patent number: 10241419
    Abstract: At least one lithography apparatus that suppresses a decrease in the accuracy of stage control is provided. A lithography apparatus includes a moving unit configured to move with an original or a substrate mounted thereon, a plurality of measurement units configured to obtain information about a position of the moving unit, measurement areas of the respective measurement units overlapping each other, and a control unit configured to switch the measurement units used to obtain the information about the position of the moving unit, based on a switching position lying in an overlapping measurement area, wherein, in a case where a plurality of processes is performed on one of a plurality of processing targets on the original or on the substrate, the control unit makes the switching position changeable and controls the measurement units so that the same one of the measurement units is used in performing the plurality of processes.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: March 26, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Masanori Yamada
  • Patent number: 10234775
    Abstract: The present invention provides an exposure apparatus which exposes a substrate, comprising a measurement unit configured to measure a height of the substrate at each of a plurality of measurement points, and a control unit configured to control the height of the substrate based on measurement results obtained by the measurement unit, and control an operation to arrange a shot region of the substrate in a first position and expose the shot region, wherein the shot region includes a plurality of partial regions, and the control unit causes the measurement unit to measure the height of the substrate by arranging the shot region in a second position different from the first position so that the number of measurement points arranged in the plurality of partial regions is larger than that when arranging the shot region in the first position.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: March 19, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Shinichiro Hirai, Junichi Motojima, Naoto Ohkawa
  • Patent number: 10214012
    Abstract: A liquid ejecting apparatus includes a head unit that ejects ink onto a medium, a transport unit that transports the medium, and a control unit that forms an adjustment pattern on the medium, and the control unit forms, as the adjustment pattern, a pattern including a first pattern that is formed in a transport direction, a plurality of scales that are formed in the transport direction, and a second pattern that is formed at a position corresponding to the scales in the transport direction while the position thereof in a main-scanning direction that intersects the transport direction is changed.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: February 26, 2019
    Assignee: Seiko Epson Corporation
    Inventor: Hiroya Hochi
  • Patent number: 10197923
    Abstract: In an exposure apparatus and a method for defocus and tilt error compensation, each of alignment sensors (500a, 500b, 500c, 500d, 500e, 500f) corresponds to and has the same coordinate in the first direction as a respective one of focusing sensors (600a, 600b, 600c, 600d, 600e, 600f), so that each of the alignment sensors (500a, 500b, 500c, 500d, 500e, 500f) is arranged on the same straight line as a respective one of the focusing sensors (600a, 600b, 600c, 600d, 600e, 600f). As such, alignment marks can be characterized with both focusing information and alignment information. This enables the correction of errors in the alignment information and thus achieves defocus and tilt error compensation, resulting in significant improvements in alignment accuracy and the production yield.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: February 5, 2019
    Assignee: SHANGHAI MICRO ELECTRONICS EQUIPMENT (GROUP) CO., LTD.
    Inventors: Feibiao Chen, Chang Zhou, Yuefei Chen, Qi Cheng, Lei Diao, Jingchao Qi
  • Patent number: 10197863
    Abstract: A mask including a plurality of baffles, a frame and a light transmission region, and a photo alignment method are provided. A support component and a movable component are disposed on the frame. The baffle is configured to block the light transmission region. The support component is configured to support the baffle which blocks the light transmission region. The movable component is configured to move the baffle to a position blocking the light transmission region.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: February 5, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Guojing Ma, Changjian Xu, Dan Wang
  • Patent number: 10186662
    Abstract: A mask frame assembly for deposition includes: a frame including an opening portion; a first support extending in a first direction across the opening portion and including opposing ends in the first direction which are each coupled to the frame; a mask stick through which a deposition material passes to a plurality of display regions of a substrate, the mask stick disposed on the first support and extending in a second direction crossing the first direction, the mask stick including: opposing ends in the second direction which are each coupled to the frame, and a deposition region common to each of the plurality of display regions of the substrate; and a magnet coupled to the first support and overlapping the deposition region of the mask stick.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: January 22, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Yonghwan Kim
  • Patent number: 10133177
    Abstract: An exposure method of exposing a plurality of exposure regions on a substrate includes the steps of acquiring first reference information indicating a reference height of the substrate, measuring heights of some exposure regions among the plurality of exposure regions, acquiring temporary height information indicating a temporary height of the substrate on the basis of a measurement result in the measuring step, and exposing one exposure region among the plurality of exposure regions after the substrate is moved on the basis of second reference information indicating a reference height of the one exposure region and a difference between the first reference information and the temporary height information.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: November 20, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Mitsuhide Nishimura
  • Patent number: 10118315
    Abstract: Techniques for producing composites outside of an autoclave that have smooth surface finishes are disclosed. The smooth composite surface, free of porosity, can be fabricated by curing the prepreg in a tool that includes a novel microstructure. In conventional composite manufacturing, some degree of porosity appears to originate from trapped gas bubbles that form during curing. The microstructure can provide a mechanism for the gas bubbles to escape from the tooling, thereby eliminating porosity and yielding a smooth surface finish on the out-of-autoclave composite. The microstructure can be applied to the tool surface using an inkjet process applying an acrylic resin curable with ultraviolet light.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: November 6, 2018
    Assignee: Surfx Technologies LLC
    Inventors: Siu F. Cheng, Mikhail M. Grigoriev, Robert F. Hicks
  • Patent number: 10112324
    Abstract: An imprint method for forming a pattern on a substrate by using a mold includes carrying the substrate into an imprint apparatus, removing, after the substrate is carried into the imprint apparatus, a whole or a portion of foreign particles adhering to a pattern formed on the mold by bringing into contact the mold and an imprint material supplied to a member different from the substrate within the imprint apparatus, and curing the imprint material so as to form the pattern, and forming the pattern on the substrate that has carried into the imprint apparatus, by using the mold from which the foreign particles are removed.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: October 30, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshikazu Miyajima, Yukio Takabayashi, Shinichi Shudo
  • Patent number: 10094658
    Abstract: To address the problem in which when measuring the overlay of patterns formed on upper and lower layers of a semiconductor pattern by comparing a reference image and measurement image obtained through imaging by an SEM, the contrast of the SEM image of the pattern of the lower layer is low relative to that of the SEM image of the pattern of the upper layer and alignment state verification is difficult even if the reference image and measurement image are superposed on the basis of measurement results, the present invention determines the amount of positional displacement of patterns of an object of overlay measurement from a reference image and measurement image obtained through imaging by an SEM, carries out differential processing on the reference image and measurement image, aligns the reference image and measurement image that have been subjected to differential processing on the basis of the positional displacement amount determined previously, expresses the gradation values of the aligned differential r
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: October 9, 2018
    Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Yuji Takagi, Fumihiko Fukunaga, Yasunori Goto
  • Patent number: 10062543
    Abstract: Methods and systems for determining overlay error between different patterned features of a design printed on a wafer in a multi-patterning step process are provided. For multi-patterning step designs, the design for a first patterning step is used as a reference and designs for each of the remaining patterning steps are synthetically shifted until the synthetically shifted designs have the best global alignment with the entire image based on global image-to-design alignment. The final synthetic shift of each design for each patterning step relative to the design for the first patterning step provides a measurement of relative overlay error between any two features printed on the wafer using multi-patterning technology.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: August 28, 2018
    Assignee: KLA-Tencor Corp.
    Inventors: Ajay Gupta, Thanh Huy Ha, Olivier Moreau, Kumar Raja
  • Patent number: 10061215
    Abstract: In a method for fabricating a resist pattern, a substrate coated with a photo resist is loaded on a stage of an exposure apparatus. Underlying patterns are fabricated on the substrate. A surface slope of an exposure area on the substrate is measured. An alignment measurement is performed by detecting an alignment pattern formed in the underlying patterns. An alignment measurement result is corrected based on the measured surface slope. The substrate is aligned to a photo mask by using the corrected alignment measurement result. The photo resist is exposed to radiation passing through the photo mask to form patterns.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: August 28, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yung-Yao Lee, Jui-Chun Peng, Ho-Ping Chen, Heng-Hsin Liu
  • Patent number: 10053766
    Abstract: A mask frame assembly and a method of manufacturing the same are disclosed. In one aspect, the mask frame assembly for an organic light-emitting diode display includes a frame including a supporting unit, wherein an opening is formed in the frame. The assembly also includes a unit mask including a deposition pattern portion, wherein the unit mask extends in a first direction, and is fixed to the supporting unit. The assembly further includes a first supporter configured to support the unit mask, wherein a magnet is placed on at least one portion of the first supporter.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: August 21, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventor: Yonghwan Kim
  • Patent number: 10042269
    Abstract: The present disclosure provides apparatus and methods for overlay measurement. An exemplary overlay measurement apparatus includes an illuminating unit, configured to generate light to illuminate a first overlay marker having a first sub-overlay marker along a first direction and a second overlay marker along a second direction; a first measuring unit, configured to receive light reflected from the first overlay marker to cause the reflected light to laterally shift and shear to generate interference light, to receive the interference light to form a first image and to determine existence of overlay offsets along the first direction and the second direction and values of the overlay offset; and a first drive unit connected to the first measuring unit, and configured to drive the first measuring unit to rotate from a first position to a second position to measure the first sub-overlay marker and the second sub-overlay marker, respectively.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: August 7, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Liwan Yue, Qiang Wu, Yang Liu
  • Patent number: 10036968
    Abstract: A control method of a movable body includes: a step of detecting a part of a plurality of grating marks provided at a wafer placed on a movable body that is movable within an XY plane, while scanning a measurement beam, that is irradiated from a mark detection system, in a Y-axis direction with respect to the part of plurality of grating marks, as moving the movable body in the Y-axis direction; a step of measuring an irradiation position of the measurement beam on the part of the plurality of grating marks; and a step of relatively moving the measurement beam and the movable body in an X-axis direction on the basis of the measurement result of the irradiation position and also detecting another grating mark while scanning the measurement beam in the Y-axis direction.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: July 31, 2018
    Assignee: NIKON CORPORATION
    Inventor: Akihiro Ueda
  • Patent number: 10031429
    Abstract: The present invention provides a method of obtaining a position of a second shot region next to a first shot region, out of a plurality of shot regions formed on a substrate, comprising a first detection step of detecting a position of a first mark arranged in the first shot region, a second detection step of detecting a position of a mark more distant from the first mark, out of a second mark and a third mark arranged in the second shot region, and a determination step of determining the position of the second shot region based on a detection result in the first detection step and a detection result in the second detection step.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: July 24, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Masatoshi Endo, Akihiko Kawamura, Naoto Ohkawa, Tetsuji Kazaana, Takanori Morooka
  • Patent number: 9996011
    Abstract: A method provides an integrated circuit (IC) substrate having first and second alignment marks defined in a first pattern layer, and third and fourth alignment marks defined in a second pattern layer. The first and second alignment marks are illuminated, through a photomask, with a first light to determine a first layer alignment error including a first alignment error and a second alignment error. The first alignment error has more weight than the second alignment error in determining the first layer alignment error. The third and fourth alignment marks are illuminated with a second light to determine a second layer alignment error including a third alignment error in relation to the third alignment mark and a fourth alignment error in relation to the fourth alignment mark. The third alignment error has more weight than the fourth alignment error in determining the second layer alignment error.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: June 12, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hsien Lin, Hung-Chang Hsieh, Feng-Jia Shiu, Chun-Yi Lee
  • Patent number: 9975291
    Abstract: A nanostructure that is visually recognized as being seamless by its more regularly and more uniformly formed fine concave-convex structure and that exhibits an excellent antireflection effect against light in a visible wavelength range is provided. Such a nanostructure is configured by a number of rows of tracks each including structures, formed by protrusions or depressions on a surface of a substrate, arranged at a predetermined fine pitch. In this nanostructure, a distance between centers of the structures adjacent to each other across a strip-shaped portion (seam) in which portions with no structures within the predetermined pitch are continuously formed in a track arrangement direction is adjusted so as to prevent visual recognition of the seam.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: May 22, 2018
    Assignee: DEXERIALS CORPORATION
    Inventor: Sohmei Endoh
  • Patent number: 9966284
    Abstract: According to one embodiment, an alignment method includes calculating a position gap of a predetermined point in a device area of a wafer based on a stress applied to the device area, and correcting an exposure condition in a lithography process of the device area based on the position gap of the predetermined point.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: May 8, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Manabu Takakuwa
  • Patent number: 9927725
    Abstract: A lithography apparatus has a plurality of processing units configured to respectively perform patternings on a plurality of substrates that belong to a lot, and a controller configured to perform, based on specific information that specifies one of the plurality of substrates, determination of one of the plurality of processing units that processes the one of the plurality of substrates, and control the plurality of processing units such that the patternings are performed on the plurality of substrates respectively with the plurality of processing units in parallel based on recipe information corresponding to the lot.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: March 27, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yoshikazu Miyajima, Hitoshi Nakano
  • Patent number: 9927717
    Abstract: A method of correcting an image characteristic of a substrate onto which one or more product features have been formed using a lithographic process, and an associated inspection apparatus method. The method includes measuring an error in the image characteristic of the substrate, and determining a correction for a subsequent formation of the product features based upon the measured error and a characteristic of one or more of the product feature(s).
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: March 27, 2018
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Kyu Kab Rhe, David Deckers, Hubertus Johannes Gertrudus Simons, Thomas Theeuwes
  • Patent number: 9904330
    Abstract: One feature pertains to an advanced computer device configured for storing data on a plurality of non-volatile memory mass storage devices. The mass storage devices may interface with the computer device through a plurality of base boards mounted in an enclosure that are configured to couple with at least one non-volatile memory storage drive. Each base board may further be configured to couple with a high speed interconnect cable to exchange data to be loaded or stored with the computer device. According to one aspect, the high speed cable transfers Serially Attached SCSI (SAS) or PCIe data packets or frames.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: February 27, 2018
    Assignee: Sanmina Corporation
    Inventors: Franz Michael Schuette, Lawrence Allan Freymuth, Ritesh Kumar
  • Patent number: 9891464
    Abstract: The present invention provides a color resist mask sheet and a method of use thereof. The color resist mask sheet includes an align coat mark region and an align test mark region. The align coat mark region includes a plurality of equally spaced align coat marks of coat color resist; the align test mark region includes a plurality of equally spaced align test marks for coating the test color resist, wherein each align test mark corresponds to each align coat mark.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: February 13, 2018
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yuan Xiong
  • Patent number: 9870435
    Abstract: Disclosed are methods and systems for determining and displaying a simulated deformation of a 3D object data model. In one aspect, a method is disclosed that includes causing a force to be applied to an object to cause a deformation of the object and causing a plurality of reference scans of the object to be captured. The method further includes, based on the plurality of reference scans, generating a 3D object data model representing the object and, further based on the plurality of reference scans, identifying a constraint point of the 3D object data model, where the constraint point represents a point of minimum deformation of the object. The method still further includes selecting a predefined deformation model, where the predefined deformation model defines a simulated deformation, and where the simulated deformation simulates at least a portion of the deformation of the object proximate to the point of minimum deformation.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: January 16, 2018
    Assignee: Google LLC
    Inventors: Ryan Hickman, Arshan Poursohi, Thor Lewis
  • Patent number: 9864280
    Abstract: A calibration curve for a wafer comprising a layer on a substrate is determined. The calibration curve represents a local parameter change as a function of a treatment parameter associated with a wafer exposure to a light. The local parameter of the wafer is measured. An overlay error is determined based on the local parameter of the wafer. A treatment map is computed based on the calibration curve to correct the overlay error for the wafer. The treatment map represents the treatment parameter as a function of a location on the wafer.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: January 9, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Mangesh Bangar, Bruce E. Adams, Kelly E. Hollar, Abhilash J Mayur, Huixiong Dai, Jaujiun Chen
  • Patent number: 9858658
    Abstract: A method for classification includes receiving an image of an area of a semiconductor wafer on which a pattern has been formed, the area containing an image location of interest, and receiving computer-aided design (CAD) data relating to the pattern comprising a CAD location of interest corresponding to the image location of interest. At least one value for one or more attributes of the image location of interest is computed based on a context of the CAD location of interest with respect to the CAD data.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: January 2, 2018
    Assignee: Applied Materials Israel Ltd
    Inventors: Idan Kaizerman, Ishai Schwarzband, Efrat Rozenman
  • Patent number: 9841687
    Abstract: The present disclosure relates to a method of semiconductor processing. The method includes, receiving a first wafer having a photoresist coating on a face of the first wafer. An exposure unit is used to perform a first number of radiation exposures on the photoresist coating, thereby forming an exposed photoresist coating. The exposed photoresist coating is developed, thereby forming a developed photoresist coating. An OVL measurement zone pattern is selected from a number of different, pre-determined OVL measurement zone patterns based on at least one of: the first number of radiation exposures performed on the first wafer or a previous number of radiation exposures performed on a previously processed wafer, which was processed before the first wafer. A number of OVL measurements are performed on the developed photoresist coating within the selected OVL measurement zone pattern.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: December 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Yao Lee, Heng-Hsin Liu, Jui-Chun Peng, Yung-Cheng Chen
  • Patent number: 9791790
    Abstract: The present invention provides a method of aligning a quadrate wafer in a first photolithography process. The method includes: step A: fabricating mask aligning markers in a periphery region of a mask, which is used for a first exposure process of the quadrate wafer, around a mask pattern of the mask; step B: during the first exposure process, positioning the quadrate wafer in a preset region by using the mask aligning markers on the mask, and exposing the quadrate wafer through the mask; and step C: performing alignment for the quadrate wafer during a second exposure process and subsequent exposure processes by using aligning markers on the quadrate wafer that are obtained during the first exposure process. The method may be easily and reliably performed to ensure intact dies at periphery of a quadrate wafer to be produced and thus render increased yield of chips.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: October 17, 2017
    Assignee: INSTITUTE OF SEMICONDUCTORS, CHINESE ACADEMY OF SCIENCES
    Inventors: Jinmin Li, Junxi Wang, Qingfeng Kong, Jinxia Guo, Xiaoyan Yi
  • Patent number: 9772561
    Abstract: An overlay measurement and correction method and device is provided. In an embodiment the measurement device takes measurements of a first semiconductor wafer and uses the measurements in a plurality of correction techniques to generate an overlay correction model. The plurality of correction techniques include a first order correction, a first intra-field high order parameter correction and a first inter-field high order parameter correction. The model is used to adjust the exposure parameters for the exposure of the next semiconductor wafer. The process is repeated on each semiconductor wafer for a run-to-run analysis.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: September 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Yao Lee, Heng-Hsin Liu, Yi-Ping Hsieh, Ying Ying Wang
  • Patent number: 9719163
    Abstract: A method of manufacturing a deposition mask is disclosed. In one aspect, the method includes depositing a first photoresist layer on a substrate, aligning a first photomask over the first photoresist layer and developing the first photoresist layer to form a plurality of first photoresist patterns having sides that gradually narrow toward the substrate. The method also includes forming a metal layer over the first photoresist patterns and a portion of the substrate exposed by the first photoresist patterns, depositing a second photoresist layer over the metal layer and aligning a second photomask over the second photoresist layer and developing the second photoresist layer to form a plurality of second photoresist patterns between the first photoresist patterns. The method further includes etching the metal layer to form a pattern hole, removing the first and second photoresist patterns and separating the substrate so as to form a deposition mask.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: August 1, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jeongwon Han
  • Patent number: 9709902
    Abstract: A projection exposure tool for microlithography for imaging mask structures of an image-providing substrate onto a substrate to be structured includes a measuring apparatus configured to determine a relative position of measurement structures disposed on a surface of one of the substrates in relation to one another in at least one lateral direction with respect to the substrate surface and to thereby simultaneously measure a number of measurement structures disposed laterally offset in relation to one another.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: July 18, 2017
    Assignee: Carl Zeiss SMT GmbH
    Inventors: Jochen Hetzler, Aksel Goehnermeier
  • Patent number: 9666537
    Abstract: Methods and apparatus for front-to-back alignment using narrow scribe lines are disclosed. An apparatus is disclosed that includes a semiconductor wafer comprising a plurality of areas for the fabrication of integrated circuit devices on a device side, the integrated circuit devices arranged in rows and columns and spaced from one another by a plurality of scribe lines disposed on the semiconductor wafer in areas between the integrated circuit devices and free from integrated circuit devices; and one or more alignment marks disposed on the semiconductor wafer, the alignment marks positioned in an intersection of two of the scribe lines; wherein the scribe lines have a first minimum dimension and the one or more alignment marks have a second minimum dimension that is greater than the first minimum dimension. Methods and additional apparatus are disclosed.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: May 30, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Simon Y S Chang, Arnold C. Conway
  • Patent number: 9659873
    Abstract: The present invention provides a semiconductor structure comprising a wafer and an aligning mark. The wafer has a dicing region which comprises a central region, a middle region surrounds the central region, and a peripheral region surrounds the middle region. The aligning mark is disposed in the dicing region, wherein the alignment mark is a mirror symmetrical pattern. The aligning mark comprises a plurality of second patterns in the middle region and a plurality of third patterns disposed in peripheral region, wherein each third pattern comprises a plurality of lines, and a width of the line is 10 times less than a width of the L-shapes. The present invention further provides a method of forming the same.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: May 23, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ying-Chiao Wang, Yu-Hsiang Hung, Chao-Hung Lin, Ssu-I Fu, Chih-Kai Hsu, Jyh-Shyang Jenq
  • Patent number: 9646902
    Abstract: Among other things, one or more systems and techniques for scanner alignment sampling are provided. A set of scan region pairs are defined along a periphery of a sampling area associated with a semiconductor wafer. Alignment marks are formed within scan regions of the set of scan region pairs, but are not formed within other regions of the sampling area. In this way, scan region pairs are scanned to determine alignment factors for respective scan region pairs. An alignment for the sampling area, such as layers or masks used to form patterns onto such layers, is determined based upon alignment factors determined for the scan region pairs.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: May 9, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Lee Yung-Yao, Ying Ying Wang, Yi-Ping Hsieh
  • Patent number: 9627558
    Abstract: Methods and apparatuses for manufacturing self-aligned integrated back contact heterojunction solar cells are provided. In some embodiments, systems for forming a solar cell on a substrate are provided, the systems comprising: a master shadow mask positioned adjacent to the substrate on a first side of the master shadow mask; a first blocking mask placed adjacent to a second side of the master shadow mask; and a deposition machine that deposits material on the substrate through holes in the master shadow mask and the first blocking mask.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: April 18, 2017
    Assignee: Arizona Board of Regents on behalf of Arizona State University
    Inventors: Clarence J. Tracy, Stanislau Herasimenka
  • Patent number: 9613174
    Abstract: One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: April 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: William Wu Shen, Yun-Han Lee, Chin-Chou Liu, Hsien-Hsin Lee, Chung-Sheng Yuan, Chao-Yang Yeh, Wei-Cheng Wu, Ching-Fang Chen
  • Patent number: 9606461
    Abstract: The present invention provides a measuring apparatus for measuring a position of an alignment mark formed on a substrate and including a first mark having position information in a first direction and a second mark having position information in a second direction different from the first direction, the apparatus including a detector configured to detect an image of the alignment mark, a controller configured to control movement of a stage for holding the substrate and detection by the detector, and a processor configured to obtain a position of the alignment mark whose image is detected by the detector, wherein the controller is configured to cause the detector to detect the image of the alignment mark with the stage moving in the first direction, and cause the detector to detect the image of the alignment mark with the stage moving in the second direction.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: March 28, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Tadaki Miyazaki
  • Patent number: 9601459
    Abstract: Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: March 21, 2017
    Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU Leuven R&D
    Inventors: Vikas Dubey, Ingrid De Wolf, Eric Beyne