Registration Or Layout Process Other Than Color Proofing Patents (Class 430/22)
  • Patent number: 11043239
    Abstract: A laser beam is directed through a transmissive axicon telescope or a reflective axicon telescope such as in a magneto-optic Kerr effect metrology system. With the transmissive axicon telescope, a Gaussian beam profile is directed through a first axicon lens and a second axicon lens. The first axicon lens and second axicon lens transfer the Gaussian beam profile of the laser beam to a hollowed laser ring. The laser beam with a hollowed laser ring can be directed through a Schwarzschild reflective objective. With the reflective axicon telescope, the laser beam is directed through two conical mirrors that are fully reflective. One of the conical mirrors defines a central hole that the laser beam passes through.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: June 22, 2021
    Assignee: KLA Corporation
    Inventors: Jun Wang, Yaolei Zheng, Chunxia Li, Changfei Yan, Lansheng Dong, Yang Zhou, Hai-Yang You, Haijing Peng, Jianou Shi, Rui Ni, Shankar Krishnan, David Y. Wang, Walter H. Johnson
  • Patent number: 11022896
    Abstract: Corrections are calculated for use in controlling a lithographic apparatus. Using a metrology apparatus a performance parameter is measured at sampling locations across one or more substrates to which a lithographic process has previously been applied. A process model is fitted to the measured performance parameter, and an up-sampled estimate is provided for process-induced effects across the substrate. Corrections are calculated for use in controlling the lithographic apparatus, using an actuation model and based at least in part on the fitted process model. For locations where measurement data is available, this is added to the estimate to replace the process model values. Thus, calculation of actuation corrections is based on a modified estimate which is a combination of values estimated by the process model and partly on real measurement data.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: June 1, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Emil Peter Schmitt-Weaver, Amir Bin Ismail, Kaustuve Bhattacharyya, Paul Derwin
  • Patent number: 11003100
    Abstract: In a beam irradiation apparatus in which a movable body holds an object, a mark detection system detects a first mark on the movable body while moving the movable body in a first direction and changing an irradiation position of a measurement beam in the first direction, the mark detection system detects a second mark while moving the movable body in the first direction and changing the irradiation position of the measurement beam in the first direction, a controller controls a position of the movable body in a second direction intersecting the first direction during a time period between the detection of the first mark and the detection of the second mark, and the controller controls the movement of the movable body to adjust a positional relation between the object on the movable body and a processing beam, based on results of the detection of the first and second marks.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: May 11, 2021
    Assignee: NIKON CORPORATION
    Inventor: Akihiro Ueda
  • Patent number: 10994368
    Abstract: There is provided a wafer for examination that is a wafer for examination with which energy distribution in a region of a light condensing spot of a laser beam with which irradiation is carried out from the upper surface side of a wafer is checked, and is a wafer for examination in which a first metal layer and a second metal layer different in specific heat or a melting point are formed over an upper surface of a wafer. In an examination method of energy distribution, the energy distribution of the laser beam is checked based on a processing mark formed in the first and second metal layers of the wafer for examination.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: May 4, 2021
    Assignee: DISCO CORPORATION
    Inventor: Seiichi Sai
  • Patent number: 10991657
    Abstract: A method for fabricating a semiconductor device is provided. The method includes obtaining a pattern density of an integrated circuit (IC) design layout; adjusting a density of an alignment mark pattern of the IC design layout according to the pattern density; and patterning a material layer according to the IC design layout after adjusting the density of the alignment mark pattern.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: April 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chiu-Hsiang Chen, Shih-Chun Huang, Yung-Sung Yen, Ru-Gun Liu
  • Patent number: 10990022
    Abstract: A metrology system may include a controller coupled to a metrology tool. The controller may receive a metrology target design including at least a first feature formed by exposing a first exposure field on a sample with a lithography tool, and at least a second feature formed by exposing a second exposure field on the sample with the lithography tool, where the second exposure field overlaps the first exposure field at a location of a metrology target on the sample. The controller may further receive metrology data associated with the metrology target fabricated according to the metrology target design, determine one or more fabrication errors during fabrication of the metrology target based on the metrology data, and generate correctables to adjust one or more fabrication parameters of the lithography tool in one or more subsequent lithography steps based on the one or more fabrication errors.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: April 27, 2021
    Assignee: KLA Corporation
    Inventors: Enna Leshinsky-Altshuller, Inna Tarshish-Shapir, Mark Ghinovker, Diana Shaphirov, Guy Ben Dov, Roie Volkovich, Chris Steely
  • Patent number: 10977420
    Abstract: A method of decomposing a layout for multiple-patterning lithography includes receiving an input that represents a layout of a semiconductor device. The layout includes a plurality of conductive lines of a cell. A first set of conductive lines are overlaid by a second set of conductive lines. The method further includes partitioning the second set of conductive lines into groups. A first group has a different number of conductive lines from the second set than a second group. The method further includes assigning conductive lines from the first set overlaid by conductive lines of the first group to a first photomask and assigning conductive lines from the first set overlaid by conductive lines of the second group to second and third photomasks.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Meng-Kai Hsu, Wen-Hao Chen
  • Patent number: 10962883
    Abstract: Systems and methods described herein relate to the manufacture of optical elements and optical systems. An example method includes overlaying a first mask on a photoresist material and a substrate, and causing a light source to illuminate the photoresist material through the first mask during a first exposure so as to define a first feature. During the first exposure, the light source is positioned at a non-normal angle with respect to a plane parallel to the substrate. The method includes developing the photoresist material so as to retain an elongate portion of the photoresist material on the substrate. A first end of the elongate portion includes an angled portion that is sloped at an angle with respect to a long axis of the elongate portion. The method also includes depositing a reflective material through a second mask onto the angled portion.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: March 30, 2021
    Assignee: Waymo LLC
    Inventors: Bernard Fidric, Pierre-yves Droz, David Hutchison
  • Patent number: 10955530
    Abstract: A scanning lidar system includes an external frame, an internal frame attached to the external frame by vibration-isolation mounts, and an electro-optic assembly movably attached to the internal frame and configured to be translated with respect to the internal frame during scanning operation of the scanning lidar system.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: March 23, 2021
    Assignee: Cepton Technologies, Inc.
    Inventors: Jun Pei, Mark Mccord, Jun Ye, Yupeng Cui, Liqun Han
  • Patent number: 10921722
    Abstract: According to one embodiment, there is provided an exposure apparatus which projects a pattern of an original onto a substrate by a projection optical system so as to expose the substrate. The exposure apparatus includes a substrate stage, an alignment detecting system, and a controller. The substrate stage holds the substrate on which shot areas each including multiple chip areas are placed. The alignment detecting system detects multiple first alignment marks placed in a peripheral region in a first chip area in the shot area. The controller obtains the first amount of positional deviation for the first chip area according to results of detecting the multiple first alignment marks and controls exposure conditions for the first chip area in the shot area according to the first amount of positional deviation.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: February 16, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Manabu Takakuwa
  • Patent number: 10895809
    Abstract: A photomask alignment method for a manufacturing process of an integrated circuit in a semiconductor material wafer (20), the method envisaging: at a first level, defining, by means of a single photolithography process, at least one alignment structure (10; 10?) on the wafer (20), the alignment structure (10; 10?) having at least a first (4a) and a second (4b) reference mark; and, at an upper level, higher than the first one, aligning a first field mask (11a) relative to the at least one first reference mark (4a); and aligning a second field mask (11b), which is used, together with the first field mask (11a), for the photolithography formation of the integrated circuit inside a respective die (22) in the wafer (20), relative to the at least one second reference mark (4b), so that the first and second field masks (11a, 11b) are arranged on the wafer (20) adjacent to one another in a first coupling direction, without any mutual overlapping.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: January 19, 2021
    Inventor: Gianluca Eugeni
  • Patent number: 10892285
    Abstract: A display panel is provided. The display panel includes a substrate, a light-shielding positioning layer and a transparent positioning layer. The substrate has a first surface and a second surface opposite to the first surface. The light-shielding positioning layer is disposed on the first layer and has at least one first alignment pattern. The transparent positioning layer is disposed on the second layer and has at least one second alignment pattern. In a direction perpendicular to the substrate, the at least one first alignment pattern overlaps with the at least one second alignment pattern. A manufacturing method of the display panel is also provided.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: January 12, 2021
    Assignee: Au Optronics Corporation
    Inventors: Peng-Bo Xi, Chun-Cheng Cheng
  • Patent number: 10859924
    Abstract: A method for manufacturing a structure on a substrate includes projecting an image of a reference pattern onto a substrate having a first patterned layer, the first patterned layer including first alignment marks and first overlay measurement marks, and the reference pattern including second alignment marks and second overlay measurement marks, aligning, based on the first alignment marks and the second alignment marks, the first patterned layer to the image of the reference pattern, obtaining a pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks, and determining compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Yun Wang, Hua-Tai Lin, Chia-Chu Liu
  • Patent number: 10838295
    Abstract: A method of manufacturing a photomask includes depositing a first absorbing layer over a substrate, patterning the first absorbing layer using a photoresist, and depositing a conformal second absorbing layer along surfaces of the first absorbing layer.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: You-Hua Chou, Kuo-Sheng Chuang
  • Patent number: 10831111
    Abstract: A method of measuring a target, an associated lithographic method, an associated computer program product and an associated litho cell is provided, wherein the method includes measuring the target subsequent to exposure of structures by a lithographic process in a current layer on a substrate over one or more preceding layers, wherein the one or more preceding layers have each undergone an etch step, and wherein the target is only in at least one of the one or more preceding layers. In this way, an after-etch measurement of the target can be obtained.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: November 10, 2020
    Assignee: ASML Netherlands B.V.
    Inventor: Kaustuve Bhattacharyya
  • Patent number: 10802409
    Abstract: A method of measuring n values of a parameter of interest (e.g., overlay) relating to a structure forming process, where n>1. The method includes performing n measurements on each of n+1 targets, each measurement performed with measurement radiation having a different wavelength and/or polarization combination and determining the n values for a parameter of interest from the n measurements of n+1 targets, each of the n values relating to the parameter of interest for a different pair of the layers. Each target includes n+1 layers, each layer including a periodic structure, the targets including at least n biased targets having at least one biased periodic structure formed with a positional bias relative to the other layers, the biased periodic structure being in at least a different one of the layers per biased target. Also disclosed is a substrate having such a target and a patterning device for forming such a target.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: October 13, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Chi-Hsiang Fan, Maurits Van Der Schaar, Youping Zhang
  • Patent number: 10805596
    Abstract: A stereoscopic image sensor apparatus including a pair of image sensors adjacently fabricated on a common carrier is disclosed, the common carrier being a diced portion of a carrier on which an aligned plurality of image sensors have been fabricated within an alignment tolerance, the alignment tolerance including a target lateral offset between the adjacent image sensors, and a target orientation between corresponding rows of light sensitive elements on the adjacent image sensors. An alternative stereoscopic image sensor apparatus includes a common window having first and second image sensors bonded to the common window within the alignment tolerance. Another alternative stereoscopic image sensor apparatus includes rear faces of respective first and second image sensors being bonded to a common circuit substrate within the alignment tolerance. Methods for fabricating the stereoscopic image sensors are also disclosed.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: October 13, 2020
    Assignee: TITAN MEDICAL INC.
    Inventors: Randal B. Chinnock, Jason P. Julian, George Grubner, William L. Weber
  • Patent number: 10796055
    Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ping Chiang, Ming-Hui Chih, Chih-Wei Hsu, Ping-Chieh Wu, Ya-Ting Chang, Tsung-Yu Wang, Wen-Li Cheng, Hui En Yin, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 10788765
    Abstract: As increasing numbers of layers, using increasing numbers of specific materials, are deposited on substrates, it becomes increasingly difficult to detect alignment marks accurately for, for example, applying a desired pattern onto a substrate using a lithographic apparatus, in part due to one or more of the materials used in one or more of the layers being wholly or partially opaque to the radiation used to detect alignment marks. In a first step, the substrate is illuminated with excitation radiation. In a second step, at least one effect associated with a reflected material effect scattered by a buried structure is measured. The effect may, for example, include a physical displacement of the surface of the substrate. In a third step, at least one characteristic of the structure based on the measured effect is derived.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: September 29, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Stefan Michiel Witte, Alessandro Antoncecchi, Stephen Edward, Hao Zhang, Paulus Clemens Maria Planken, Kjeld Sijbrand Eduard Eikema, Sebastianus Adrianus Goorden, Simon Reinald Huisman, Irwan Dani Setija
  • Patent number: 10782617
    Abstract: A method, including: measuring a first plurality of instances of a metrology target on a substrate processed using a patterning process to determine values of at least one parameter of the patterning process using a first metrology recipe for applying radiation to, and detecting radiation from, instances of the metrology target; and measuring a second different plurality of instances of the metrology target on the same substrate to determine values of the at least one parameter of the patterning process using a second metrology recipe for applying radiation to, and detecting radiation from, instances of the metrology target, wherein the second metrology recipe differs from the first metrology recipe in at least one characteristic of the applying radiation to, and detecting radiation from, instances of the metrology target.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: September 22, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Anagnostis Tsiatmas, Elliott Gerard McNamara
  • Patent number: 10750318
    Abstract: A positioning method including following steps is provided. Firstly, several base stations are commanded to detect a tracked object. Then, a first position of the tracked object is obtained according to the first return information. Then, several fixed-type signal transceivers are selected according to the first position. Then, the selected fixed-type signal transceivers are commanded to detect the tracked object, and a second position of the tracked object is obtained according to the second return information received from the fixed-type signal transceivers.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: August 18, 2020
    Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, LITE-ON TECHNOLOGY CORPORATION
    Inventors: Pei-Yuan Lien, Johnson Lee, Chun-Tao Chen, Yao-Chung Yeh
  • Patent number: 10727126
    Abstract: A method for forming a semiconductor device includes forming a laser marking buried within a semiconductor substrate and thinning the semiconductor substrate from a backside of the semiconductor substrate. For example, a semiconductor device includes a semiconductor substrate located in a semiconductor package. A laser marking is buried within the semiconductor substrate. For example, another semiconductor device includes a semiconductor substrate. A laser marking is located at a backside surface of the semiconductor substrate. Further, a portion of the backside surface located adjacent to the laser marking is free of recast material.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: July 28, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Korbinian Kaspar, Franco Mariani
  • Patent number: 10702044
    Abstract: A cosmetic activator system for activating a cosmetic is provided including: an activator having an energy source configured to emit an energy pulse and a controller; and an imprinter having an imprint pattern and at least one activation element configured to be in communication with the energy source, wherein the imprinter is configured to create an imprint on the cosmetic.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: July 7, 2020
    Assignee: L'OREAL
    Inventor: John Streeter
  • Patent number: 10649346
    Abstract: A table for a lithographic apparatus, the table having an encoder plate located on the table, a gap between the encoder plate and a top surface of the table, the gap located radially inward of the encoder plate relative to the periphery of the table, and a fluid extraction system with an opening in the surface of the gap to extract liquid from the gap.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: May 12, 2020
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Takeshi Kaneko, Joost Jeroen Ottens, Raymond Wilhelmus Louis Lafarre
  • Patent number: 10629698
    Abstract: Sacrificial gate structures having an aspect ratio of greater than 5:1 are formed on a substrate. In some embodiments, each sacrificial gate structure straddles a portion of a semiconductor fin that is present on the substrate. An anchoring element is formed orthogonal to each sacrificial gate structure rendering the sacrificial gate structures mechanically stable. After formation of a planarization dielectric layer, each anchoring element can be removed and thereafter each sacrificial gate structure can be replaced with a functional gate structure.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ryan O. Jung, Fee Li Lie, Jeffrey C. Shearer, John R. Sporre, Sean Teehan
  • Patent number: 10570499
    Abstract: Disclosed are a mask frame, for mask frame manufacturing method and mask. The mask frame includes a main frame and shielding bars, an evaporation-deposition area penetrating the main frame in a thickness direction being formed on the main frame, the main frame being provided with pairs of first receiving slots, the two first receiving slots in each pair being located on both sides of the evaporation-deposition area in a first direction, respectively, each shielding bar corresponding to a pair of first receiving slot, two ends of shielding bars being disposed within corresponding two first receiving slots, respectively. The mask frame comprises at least one pair of first positioning holes, each pair of which corresponds to one pair of first receiving slots, and the two first positioning holes in each pair correspond to positions of the two first receiving slots in a corresponding pair, respectively.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: February 25, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventor: Zhiming Lin
  • Patent number: 10566252
    Abstract: A method of correcting an overlay includes: forming a first pattern on a first substrate; forming a second pattern on the first pattern; obtaining a first overlay error profile of the second pattern and obtaining a first overlay correction profile from the first overlay error profile; forming a third pattern on the second pattern; obtaining a second overlay error profile of the third pattern and obtaining a second overlay correction profile from the second overlay error profile; and forming the second pattern on a second substrate, wherein the forming of the second pattern on the second substrate includes: determining whether the second overlay correction profile has a non-correctable model parameter; and when the second overlay correction profile has the non-correctable model, obtaining a preliminary correction profile to correct a position of the second pattern to be formed on the second substrate.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: February 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seungyoon Lee, Chan Hwang
  • Patent number: 10558127
    Abstract: The purpose of the present invention is to provide an exposure condition evaluation device that appropriately evaluates a wafer exposure condition or calculates an appropriate exposure condition, on the basis of information obtained from an FEM wafer, without relying on the formation state of the FEM wafer. In order to achieve the foregoing, the present invention proposes an exposure condition evaluation device which evaluates an exposure condition of a reduction projection exposure device, on the basis of the information of patterns exposed on a sample by the reduction projection exposure device, and which uses a second feature amount of a plurality of patterns formed by making exposure conditions uniform to correct a first feature amount of a plurality of patterns formed by a plurality of different exposure condition settings.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: February 11, 2020
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Shinichi Shinoda, Yasutaka Toyoda, Hiroyuki Ushiba, Hitoshi Sugahara
  • Patent number: 10527953
    Abstract: A method including evaluating a plurality of substrate measurement recipes for measurement of a metrology target processed using a patterning process, against stack sensitivity and overlay sensitivity, and selecting one or more substrate measurement recipes from the plurality of substrate measurement recipes that have a value of the stack sensitivity that meets or crosses a threshold and that have a value of the overlay sensitivity within a certain finite range from a maximum or minimum value of the overlay sensitivity.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: January 7, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Kaustuve Bhattacharyya, Arie Jeffrey Den Boef, Martin Jacobus Johan Jak
  • Patent number: 10520839
    Abstract: In a beam irradiation apparatus in which a movable body holds an object, a mark detection system detects a first mark on the movable body while moving the movable body in a first direction and changing an irradiation position of a measurement beam in the first direction, the mark detection system detects a second mark while moving the movable body in the first direction and changing the irradiation position of the measurement beam in the first direction, a controller controls a position of the movable body in a second direction intersecting he first direction during a time period between the detection of the first mark and the detection of the second mark, and the controller controls the movement of the movable body to adjust a positional relation between the object on the movable body and a processing beam, based on results of the detection of the first and second marks.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: December 31, 2019
    Assignee: NIKON CORPORATION
    Inventor: Akihiro Ueda
  • Patent number: 10515186
    Abstract: A method of decomposing a layout for multiple-patterning lithography includes receiving an input that represents a layout of a semiconductor device. The layout includes a plurality of conductive lines of a cell. A first set of conductive lines are overlaid by a second set of conductive lines. The method further includes partitioning the second set of conductive lines into groups. A first group has a different number of conductive lines from the second set than a second group. The method further includes assigning conductive lines from the first set overlaid by conductive lines of the first group to a first photomask and assigning conductive lines from the first set overlaid by conductive lines of the second group to second and third photomasks.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Meng-Kai Hsu, Wen-Hao Chen
  • Patent number: 10509881
    Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ping Chiang, Ming-Hui Chih, Chih-Wei Hsu, Ping-Chieh Wu, Ya-Ting Chang, Tsung-Yu Wang, Wen-Li Cheng, Hui En Yin, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 10503071
    Abstract: Systems and methods described herein relate to the manufacture of optical elements and optical systems. An example method includes overlaying a first mask on a photoresist material and a substrate, and causing a light source to illuminate the photoresist material through the first mask during a first exposure so as to define a first feature. During the first exposure, the light source is positioned at a non-normal angle with respect to a plane parallel to the substrate. The method includes developing the photoresist material so as to retain an elongate portion of the photoresist material on the substrate. A first end of the elongate portion includes an angled portion that is sloped at an angle with respect to a long axis of the elongate portion. The method also includes depositing a reflective material through a second mask onto the angled portion.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: December 10, 2019
    Assignee: Waymo LLC
    Inventors: Bernard Fidric, Pierre-yves Droz, David Hutchison
  • Patent number: 10495983
    Abstract: Methods are provided and generally relate to adjusting exposure parameters of a substrate in response to an overlay error. The method includes partitioning the substrate into one or more sections. Each section corresponds to an image projection system. A total overlay error of a first layer deposited on the substrate is determined. For each section, a sectional overlay error is calculated. For each overlap area, in which two or more sections overlap, an average overlay error is calculated. The exposure parameters are adjusted in response to the total overlay error.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: December 3, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Tamer Coskun, Hwan J. Jeong
  • Patent number: 10453876
    Abstract: In the present invention, a gate electrode is formed on a substrate surface, and an insulation film is formed on the substrate surface whereon the gate electrode has been formed. A first amorphous silicon layer is formed on the substrate surface whereon the insulation film has been formed. An energy beam is irradiated onto a plurality of required sites spaced from each other in the first amorphous silicon layer to transform each of the required sites into a polysilicon layer. Each of the required sites is situated on the upper side of the gate electrode and serves as a channel region between a source and a drain. This allows other sites, which are in the first amorphous silicon layer and related to the plurality of required sites, to also be irradiated by the energy beam and ablated so as to form at the other sites a cleared portion having a required shape.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: October 22, 2019
    Assignee: Sakai Display Products Corporation
    Inventors: Nobutake Nodera, Shigeru Ishida, Ryohei Takakura, Yoshiaki Matsushima, Takao Matsumoto
  • Patent number: 10444639
    Abstract: A process control system includes a controller configured to generate a reference overlay signature based on one or more overlay reference layers of a sample, extrapolate the reference overlay signature to a set of correctable fields for the exposure of a current layer of the sample to generate a full-field reference overlay signature, identify one or more alignment fields of the set of correctable fields, generate an alignment-correctable signature by modeling alignment corrections for the set of correctable fields, subtract the alignment-correctable signature from the full-field reference overlay signature to generate feedforward overlay corrections for the current layer when the one or more overlay reference layers are the same as the one or more alignment reference layers, generate lithography tool corrections based on the feedforward overlay corrections, and provide the lithography tool corrections for the current layer to the lithography tool.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: October 15, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Onur Nihat Demirer, William Pierson, Mark D. Smith, Jeremy S. Nabeth, Miguel Garcia-Medina, Lipkong Yap
  • Patent number: 10446430
    Abstract: A chuck for wafer processing that counters the deleterious effects of thermal expansion of the wafer. Also, a combination of chuck and shadow mask arrangement that maintains relative alignment between openings in the mask and the wafer in spite of thermal expansion of the wafer. A method for fabricating a solar cell by ion implant, while maintaining relative alignment of the implanted features during thermal expansion of the wafer.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: October 15, 2019
    Assignee: INTEVAC, INC.
    Inventors: Terry Bluck, Babak Adibi, Vinay Prabhakar, William Eugene Runstadler, Jr.
  • Patent number: 10429743
    Abstract: An embodiment of the invention may include a method for ensuring semiconductor design integrity. The method may include analyzing a photomask design for a semiconductor circuit. The photomask may include an electrical design necessary for the operation of the semiconductor circuit, and white space, which has no electrical design. The method may include inserting an optical design into the white space of the photomask design for the semiconductor circuit. The optical design may have known optical patterns for validating the semiconductor circuit design. In an embodiment of the invention, the optical design may be physically isolated from the electrical design. In another embodiment of the invention, the optical design may comprise one or more photomask layers and overlay the electrical design. In another embodiment of the invention, the optical design may comprise covershapes.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: October 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Daniel Corliss, Derren N. Dunn, Michael A. Guillorn, Shawn P. Fetterolf
  • Patent number: 10416578
    Abstract: A method for pre-aligning a substrate includes the steps of: 1) providing a substrate having a plurality of marks are arranged circumferentially on a surface thereof, wherein each of the plurality of marks consists of at least one first stripe extending in a first direction and at least one second stripe extending in a first direction; 2) aligning a center of the substrate with a given point on a substrate carrier stage; 3) illuminating a mark selected from the plurality of marks on the surface of the substrate with light and obtaining an image of the selected mark; 4) processing the image to obtain first projection data corresponding to the first direction and second projection data corresponding to the second direction; 5) identifying a set of first peak values corresponding to the at least one first stripe of the selected mark from the first projection data and a set of second peak values corresponding to the at least one second stripe of the selected mark from the second projection data; 6) selecting firs
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: September 17, 2019
    Assignee: SHANGHAI MICRO ELECTRONICS EQUIPMENT (GROUP) CO., LTD.
    Inventors: Xiwen Zhou, Weiwang Sun, Cuixia Tian, Jiaozeng Zheng
  • Patent number: 10401837
    Abstract: A method disclosed herein includes: converting an image of a manufactured circuit to a plurality of representative contours, the plurality of representative contours corresponding to printed features in the manufactured circuit; generating a risk inventory for the manufactured circuit based on the plurality of representative contours, the risk inventory being configured to identify at least one process sensitive geometry (PSG) in the manufactured circuit; generating a common process window (CPW) for the manufactured circuit based on the plurality of representative contours and the risk inventory, the CPW being indicative of manufacturing reliability of each feature in the manufactured circuit; and generating instructions to adjust a manufacturing tool for creating the manufactured circuit, based on the generated CPW.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 3, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hongxin Zhang, Shaowen Gao, Norman Chen
  • Patent number: 10379447
    Abstract: A method for simulation of lithography overlay is disclosed which comprises storing alignment parameters used to align a semiconductor wafer prior to a lithography step; storing process control parameters used during the lithography step on the semiconductor wafer; storing overlay parameters measured after the lithography step; calculating alternative alignment parameters and alternative process control parameters. The alternative alignment parameters and the alternative process control parameters are added to cleansed overlay parameters to obtain simulated lithography overlay data.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: August 13, 2019
    Assignee: Qoniac GmbH
    Inventor: Boris Habets
  • Patent number: 10365568
    Abstract: In a beam irradiation apparatus in which a movable body holds an object, a mark detection system detects a first mark on the movable body while moving the movable body in a first direction and changing an irradiation position of a measurement beam in the first direction, the mark detection system detects a second mark while moving the movable body in the first direction and changing the irradiation position of the measurement beam in the first direction, a controller controls a position of the movable body in a second direction intersecting the first direction during a time period between the detection of the first mark and the detection of the second mark, and the controller controls the movement of the movable body to adjust a positional relation between the object on the movable body and a processing beam, based on results of the detection of the first and second marks.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: July 30, 2019
    Assignee: NIKON CORPORATION
    Inventor: Akihiro Ueda
  • Patent number: 10355209
    Abstract: A vapor deposition mask includes a metal mask and a resin mask having an opening. An inner wall surface for composing the opening has an inflection point in a thicknesswise cross section of the resin mask. When an intersection of a first surface, not facing the metal mask, of the resin mask and the inner wall surface is set to be a first intersection, an intersection of a second surface, facing the metal mask, of the resin mask and the inner wall surface is set to be a second intersection, and there is set a first inflection point first positioned from the first intersection toward the second intersection, an angle formed by a line connecting the first intersection and the first inflection point and the first surface is larger than an angle formed by a line connecting the first inflection point and the second intersection and the second surface.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: July 16, 2019
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Toshihiko Takeda, Katsunari Obata, Hiroshi Kawasaki
  • Patent number: 10331036
    Abstract: In various embodiments, an exposure mask may include a carrier, a first exposure structure in a first structure plane of the carrier, and a second exposure structure in a second structure plane of the carrier. The two structure planes differ from one another.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: June 25, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Heiko Assmann, Markus Dankelmann, Uwe Winkler
  • Patent number: 10324371
    Abstract: The present disclosure provides a system for generating a mask pattern, a method for generating a mask pattern, and an exposure system. According to an embodiment of the present disclosure, the system for generating a mask pattern comprises: a mask pattern provision device configured to provide a mask pattern signal via a wired or wireless network; a mask pattern transmission device configured to process the mask pattern signal provided by the mask pattern provision device to generate mask pattern information, and to transmit the generated mask pattern information over a Radio Frequency Identification (RFID) signal; and a mask pattern generation device configured to generate a mask pattern corresponding to the mask pattern information based on the mask pattern information and display the generated mask pattern.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: June 18, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Tailiang Li, Junmin Sun, Hongli Ding, Hongtao Guan
  • Patent number: 10317757
    Abstract: A manufacture method of a black matrix is provided. The COA technology is utilized to manufacture organic photoresist blocks with an increased thickness on alignment marks. Then, a black matrix thin film is set on and covers the organic photoresist blocks to tremendously increase the level differences of the positions of the alignment marks and adjacent areas. A contour recognition apparatus can accurately recognize positions of the alignment marks. The issue that the alignment marks are difficult to recognize after the black matrix thin film is coated in the BOA process can be solved.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: June 11, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yuan Xiong
  • Patent number: 10310385
    Abstract: An optical system for producing lithographic structures is disclosed. Also disclosed is a method for determining relative coordinates of a position of a writing field relative to a position of a preview field in such an optical system, and a method for producing lithographic structures using such an optical system.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: June 4, 2019
    Assignee: Carl Zeiss AG
    Inventors: Philipp Huebner, Gerhard Krampert, Stefan Richter, Timo Mappes
  • Patent number: 10303050
    Abstract: This disclosure provides an imprint apparatus configured to form a pattern with an imprint material by bringing the imprint material on a substrate and a pattern of the mold into contact with each other including a drive unit to bring part of the pattern of the mold into contact with the imprint material, and bring the pattern into contact with the imprint material so a contact surface area between the pattern of the mold and the imprint material increases, an interference fringe detecting unit to detect an interference fringe generated by reflected light from the pattern of the mold and reflected light from the substrate, and a state detecting unit to detect a contact state between the pattern of the mold and the imprint material on the basis of the interference fringe.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: May 28, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hiroshi Sato
  • Patent number: 10303068
    Abstract: A projection exposure tool for microlithography for imaging mask structures of an image-providing substrate onto a substrate to be structured includes a measuring apparatus configured to determine a relative position of measurement structures disposed on a surface of one of the substrates in relation to one another in at least one lateral direction with respect to the substrate surface and to thereby simultaneously measure a number of measurement structures disposed laterally offset in relation to one another.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: May 28, 2019
    Assignee: Carl Zeiss SMT GmbH
    Inventors: Jochen Hetzler, Aksel Goehnermeier
  • Patent number: 10275562
    Abstract: A method of decomposing a layout for multiple-patterning lithography includes receiving an input that represents a layout of a semiconductor device. The layout includes a plurality of conductive lines of a cell. A first set of conductive lines are overlaid by a second set of conductive lines. The method further includes partitioning the second set of conductive lines into groups. A first group has a different number of conductive lines from the second set than a second group. The method further includes assigning conductive lines from the first set overlaid by conductive lines of the first group to a first photomask and assigning conductive lines from the first set overlaid by conductive lines of the second group to second and third photomasks.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Meng-Kai Hsu, Wen-Hao Chen