Registration Or Layout Process Other Than Color Proofing Patents (Class 430/22)
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Patent number: 11815811Abstract: A method and system for supplying control signals to two or more force actuators wherein each of the two or more force actuators having a defined force value. The method includes sending a first set of control signals to each of the actuators to ramp forces supplied to reach the defined force value at a same initial defined value time and sending a second set of control signals to each of the actuators to reduce the forces supplied starting at a same final defined value time to individual set point values, and wherein each of the two of more force actuators reach their individual set point values at a same set point time.Type: GrantFiled: March 23, 2021Date of Patent: November 14, 2023Assignee: Canon Kabushiki KaishaInventors: Jeffrey Dean Klein, Steven T. Jenkins, Atsushi Kusaka
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Patent number: 11733606Abstract: A method for assigning features into at least first features and second features, the first features being for at least one first patterning device configured for use in a lithographic process to form corresponding first structures on a substrate and the second features being for at least one second patterning device configured for use in a lithographic process to form corresponding second structures on a substrate, wherein the method including assigning the features into the first features and the second features based on a patterning characteristic of the features.Type: GrantFiled: April 29, 2019Date of Patent: August 22, 2023Assignee: ASML NETHERLANDS B.V.Inventors: Thomas Theeuwes, Koenraad Van Ingen Schenau, Pieter Joseph Marie Wöltgens
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Patent number: 11726408Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.Type: GrantFiled: July 27, 2022Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Peter Yu, Chih-Tung Hsu, Kevin Wang, Chih-Chia Hu, Roger Chen
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Patent number: 11686999Abstract: The invention relates a method for producing a radiation-emitting component including a step A, in which a laser having an optical resonator and an output mirror is provided, wherein during the intended operation, laser radiation exits the optical resonator via the output mirror. In a step B), a photoresist layer is applied to the output mirror. In a step C), an optical structure is generated from the photoresist layer by means of a 3D lithography method, wherein the optical structure is designed to influence the beam path of the laser radiation by refraction and/or reflection.Type: GrantFiled: November 29, 2018Date of Patent: June 27, 2023Assignee: OSRAM OLED GMBHInventor: Alexander Schlehahn
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Patent number: 11650445Abstract: Provided are a method for manufacturing a transparent panel formed with a wall member having high accuracy, a uniform height from a surface to adhere to an optical member, and smoothness. This method comprises: a step of preparing a transparent panel 4 for an optical device 1 to be bonded to an optical member 2; a step of forming a mask layer 15 so as to form an opening 6 along a periphery of an outer shape of the transparent panel 4; a step of applying a curable resin material 7 to the opening 6 and the mask layer 15; a step of pressing a flat plate 10 against the curable resin material 7; a step of curing the resin composition 7 to form a cured resin layer 11; a step of detaching the flat plate 10; and a step of removing the mask layer 15 together with the cured resin layer 11 formed on the mask layer 15 to obtain a wall member 12 along the periphery of the outer shape of the transparent panel 4.Type: GrantFiled: September 11, 2018Date of Patent: May 16, 2023Assignee: DEXERIALS CORPORATIONInventor: Yoshikazu Nagasawa
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Patent number: 11602697Abstract: Disclosed herein are system, method, and computer program product embodiments for assessing performance of a player of a game. An embodiment operates by monitoring for an input from the player of the game, receiving the input from the player of the game, and determining a characteristic of the game resulting from the input from the player. Based on the input from the player, a performance of the player is assessed. The performance of the player relating to one or more metrics of the game is monitored, and is assessed by comparing the input from the player during the period of time to an optimal input during the period of time in the game.Type: GrantFiled: September 4, 2018Date of Patent: March 14, 2023Assignee: State Space Labs Inc.Inventors: Jason R. Fuller, David J. Heeger, Wayne E. Mackey
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Patent number: 11567419Abstract: In a beam irradiation apparatus in which a movable body holds an object, a mark detection system detects a first mark on the movable body while moving the movable body in a first direction and changing an irradiation position of a measurement beam in the first direction, the mark detection system detects a second mark while moving the movable body in the first direction and changing the irradiation position of the measurement beam in the first direction, a controller controls a position of the movable body in a second direction intersecting the first direction during a time period between the detection of the first mark and the detection of the second mark, and the controller controls the movement of the movable body to adjust a positional relation between the object on the movable body and a processing beam, based on results of the detection of the first and second marks.Type: GrantFiled: April 16, 2021Date of Patent: January 31, 2023Assignee: NIKON CORPORATIONInventor: Akihiro Ueda
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Patent number: 11521882Abstract: An optical system may include a light source to provide a beam of light. The optical system may include a reflector to receive and redirect the beam of light. The optical system may include a light gate having an opening to permit the beam of light, from the reflector, to travel through the opening. The optical system may include a light sensor to receive a portion of the beam of light after the beam of light travels through the opening, and convert the portion of the beam of light to a signal. The optical system may include a processing device to determine whether a notch of a wafer is in an allowable position based on the signal.Type: GrantFiled: August 20, 2020Date of Patent: December 6, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-An Chuang, Kuang-Wei Hsueh, Shih-Huan Chen, Yung-Shu Kao
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Patent number: 11507231Abstract: A display device may include a display panel, an input sensing unit, and an alignment structure. The display panel may include a sealing member. The input sensing unit may be disposed on the display panel. The input sensing unit may include first-type sensor electrodes directly contacting a face of a first insulator of the display device, a first-type connector electrically connecting the first-type sensor electrodes, second-type sensor electrodes directly contacting the face of the first insulator of the display device, and a second-type connector electrically connecting the second-type sensor electrodes. The alignment structure may overlap the sealing member and may include a transparent member that directly contacts the face of the first insulator of the display device.Type: GrantFiled: October 15, 2020Date of Patent: November 22, 2022Inventors: Jong Seon Park, Hwan Hee Jeong
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Patent number: 11500300Abstract: In a beam irradiation apparatus in which a movable body holds an object, a mark detection system detects a first mark on the movable body while moving the movable body in a first direction and changing an irradiation position of a measurement beam in the first direction, the mark detection system detects a second mark while moving the movable body in the first direction and changing the irradiation position of the measurement beam in the first direction, a controller controls a position of the movable body in a second direction intersecting the first direction during a time period between the detection of the first mark and the detection of the second mark, and the controller controls the movement of the movable body to adjust a positional relation between the object on the movable body and a processing beam, based on results of the detection of the first and second marks.Type: GrantFiled: April 16, 2021Date of Patent: November 15, 2022Assignee: NIKON CORPORATIONInventor: Akihiro Ueda
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Patent number: 11482517Abstract: An integrated circuit process includes the following steps. A substrate including a first area and a second area is provided. A plurality of line patterns cover the substrate of the first area, and a sacrificial line pattern covers the substrate of the second area, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern. The present invention also provides an integrated circuit formed by said process. A substrate includes a first area and a second area; a plurality of line patterns cover the substrate of the first area; a slot pattern is in the substrate of the second area, wherein these line patterns are orthogonal to the slot pattern. Additionally, a plurality of line patterns cover the substrate; a sacrificial line pattern is at ends of the line patterns, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern.Type: GrantFiled: May 16, 2018Date of Patent: October 25, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: En-Chiuan Liou, Chih-Wei Yang, Kuei-Chun Hung
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Patent number: 11456222Abstract: An overlay correction method may include obtaining a first central line of a lower pattern on a substrate, forming a photoresist pattern on the lower pattern, obtaining an ADI overlay value corresponding to a first distance between a second central line of an upper flat surface of the lower pattern and a third central line of the photoresist pattern, obtaining an asymmetrical overlay value corresponding to a second distance between the first and second central lines, form an upper pattern using the photoresist pattern, obtaining an ACI overlay value corresponding to a third distance between the first central line and a fourth central line of the upper pattern, subtracting the ADI overlay value from the ACI overlay value to obtain a first overlay skew value, and adding the asymmetrical overlay value to the first overlay skew value to obtain a second overlay skew value.Type: GrantFiled: May 28, 2020Date of Patent: September 27, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Woo-Yong Jung, Jinsun Kim, Seungyoon Lee, Jeongjin Lee, Chan Hwang
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Patent number: 11429029Abstract: A method includes projecting an illumination beam of radiation onto a metrology target on a substrate, detecting radiation reflected from the metrology target on the substrate, and determining a characteristic of a feature on the substrate based on the detected radiation, wherein a polarization state of the detected radiation is controllably selected to optimize a quality of the detected radiation.Type: GrantFiled: October 27, 2020Date of Patent: August 30, 2022Assignee: ASML NETHERLANDS B.V.Inventors: Maurits Van Der Schaar, Patrick Warnaar, Youping Zhang, Arie Jeffrey Den Boef, Feng Xiao, Martin Ebert
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Patent number: 11422479Abstract: Systems and methods described herein relate to the manufacture of optical elements and optical systems. An example method includes overlaying a first mask on a photoresist material and a substrate, and causing a light source to illuminate the photoresist material through the first mask during a first exposure so as to define a first feature. During the first exposure, the light source is positioned at a non-normal angle with respect to a plane parallel to the substrate. The method includes developing the photoresist material so as to retain an elongate portion of the photoresist material on the substrate. A first end of the elongate portion includes an angled portion that is sloped at an angle with respect to a long axis of the elongate portion. The method also includes depositing a reflective material through a second mask onto the angled portion.Type: GrantFiled: March 1, 2021Date of Patent: August 23, 2022Assignee: Waymo LLCInventors: Bernard Fidric, Pierre-Yves Droz, David Hutchison
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Patent number: 11414739Abstract: A mask frame assembly, including: a hollow frame, which is provided with a hollow area; and a first howling stick, disposed across the hollow area of the hollow frame in a first direction; wherein the mask frame assembly is configured to support a fine metal mask plate which includes a mask pattern area and an invalid mask area surrounding the mask pattern area; in a state of the fine metal mask plate being supported by the mask frame assembly, opposite ends of the fine metal mask plate are fixed on the hollow frame in a second direction; the mask pattern area of the fine metal mask plate is disposed in the hollow area of the hollow frame; and a projection of the first howling stick on the fine metal mask plate is in the invalid mask area. An evaporation device is also disclosed.Type: GrantFiled: December 6, 2017Date of Patent: August 16, 2022Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.Inventors: Zhiming Lin, Zhen Wang, Jian Zhang
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Patent number: 11392742Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.Type: GrantFiled: October 5, 2020Date of Patent: July 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Ping Chiang, Ming-Hui Chih, Chih-Wei Hsu, Ping-Chieh Wu, Ya-Ting Chang, Tsung-Yu Wang, Wen-Li Cheng, Hui En Yin, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau
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Patent number: 11392045Abstract: A method for manufacturing a structure on a substrate includes projecting an image of a reference pattern onto a substrate having a first patterned layer, the first patterned layer including first alignment marks and first overlay measurement marks, and the reference pattern including second alignment marks and second overlay measurement marks, aligning, based on the first alignment marks and the second alignment marks, the first patterned layer to the image of the reference pattern, obtaining a pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks, and determining compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.Type: GrantFiled: December 7, 2020Date of Patent: July 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Yun Wang, Hua-Tai Lin, Chia-Chu Liu
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Patent number: 11360378Abstract: A display panel includes a method of fabricating an array substrate. The method includes forming a metal layer (1) on a substrate, and patterning the metal layer (1) using a phase shift mask to form a pattern of metal wiring. The phase shift mask includes a substrate and a wiring light shielding portion (02) on the substrate (01). The wiring light shielding portion (02) includes a light shielding region (021) and a phase shift region (022). In a direction perpendicular to the extending direction of the wiring light shielding portion (02) a width of the light shielding region (021) is larger than a width of the pattern of the metal wiring formed by the wiring light shielding portion (02).Type: GrantFiled: November 1, 2018Date of Patent: June 14, 2022Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Xiaoxiang Zhang, Mingxuan Liu, Huibin Guo, Wenqing Xu, Xiaolong Li, Zumou Wu, Yongzhi Song
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Patent number: 11287752Abstract: A lithographic apparatus comprising a projection system configured to project a patterned radiation beam to form an exposure area on a substrate, a cooling apparatus located in use above the substrate adjacent to the exposure area, the cooling apparatus being configured to remove heat from the substrate during use, a plasma vessel located below the cooling apparatus with its opening facing towards the cooling apparatus, and a gas supply for supplying gas to the plasma vessel and an aperture for receipt of a radiation beam. In use, supplied gas and a received radiation beam react to form a plasma within the plasma vessel that is directed towards a surface of the cooling apparatus which faces the opening of the plasma vessel.Type: GrantFiled: June 7, 2018Date of Patent: March 29, 2022Assignee: ASML Netherlands B.V.Inventors: Adrianus Hendrik Koevoets, Cornelis Adrianus De Meijere, Willem Michiel De Rapper, Sjoerd Nicolaas Lambertus Donders, Jan Groenewold, Alain Louis Claude Leroux, Maxim Aleksandrovich Nasalevich, Andrey Nikipelov, Johannes Adrianus Cornelis Maria Pijnenburg, Jacobus Cornelis Gerardus Van Der Sanden
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Patent number: 11244827Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a photo-sensitive layer on a first surface of a semiconductor substrate. The photo-sensitive layer has a top surface. The method also includes obtaining a first profile of the first surface of the semiconductor substrate, and obtaining a second profile of the top surface of the photo-sensitive layer. The method also includes calculating a vertical displacement profile of the semiconductor substrate according to the first profile and the second profile. An apparatus for manufacturing a semiconductor structure is also disclosed.Type: GrantFiled: June 19, 2019Date of Patent: February 8, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yung-Yao Lee, Wen-Chih Wang
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Patent number: 11231657Abstract: A lithographic apparatus comprising a projection system configured to project a patterned radiation beam to form an exposure area on a substrate, a cooling apparatus located in use above the substrate adjacent to the exposure area, the cooling apparatus being configured to remove heat from the substrate during use, a plasma vessel located below the cooling apparatus with its opening facing towards the cooling apparatus, and a gas supply for supplying gas to the plasma vessel and an aperture for receipt of a radiation beam. In use, supplied gas and a received radiation beam react to form a plasma within the plasma vessel that is directed towards a surface of the cooling apparatus which faces the opening of the plasma vessel.Type: GrantFiled: June 7, 2018Date of Patent: January 25, 2022Assignee: ASML Netherlands B.V.Inventors: Adrianus Hendrik Koevoets, Cornelis Adrianus De Meijere, Willem Michiel De Rapper, Sjoerd Nicolaas Lambertus Donders, Jan Groenewold, Alain Louis Claude Leroux, Maxim Aleksandrovich Nasalevich, Andrey Nikipelov, Johannes Adrianus Cornelis Maria Pijnenburg, Jacobus Cornelis Gerardus Van Der Sanden
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Patent number: 11195293Abstract: An information processing device extracts an image of a marker from a photographed image, and obtains a position of a representative point of the marker in a three-dimensional space. Meanwhile, a position and an attitude corresponding to a time of photographing the image are estimated on the basis of an output value of a sensor included in a target object. A weight given to positional information of each marker is determined by using a target object model on the basis of the estimation, and positional information of the target object is calculated. Further, final positional information is obtained by synthesizing estimated positional information at a predetermined ratio, and the final positional information is output and fed back for a next estimation.Type: GrantFiled: July 13, 2018Date of Patent: December 7, 2021Assignee: Sony Interactive Entertainment Inc.Inventor: Masaki Uchida
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Patent number: 11181831Abstract: A method of manufacturing a semiconductor device includes forming a plurality of overlay molds on a semiconductor structure by developing a photoresist material layer of the semiconductor structure, the semiconductor structure including a first layer having a plurality of overlay marks, the plurality of overlay molds at least partially overlapping at least some of the plurality of overlay marks; and measuring one or more overlays by radiating a light having a wavelength band onto the semiconductor structure, each of the one or more overlays indicating an amount of consistency of the first layer and a second layer of the semiconductor structure, the wavelength band being set based on the plurality of overlay marks and the plurality of overlay molds, the second layer being between the first layer and the photoresist material layer.Type: GrantFiled: September 3, 2019Date of Patent: November 23, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyoung-hwan Lee, Young-ho Kwon, Souk Kim, Young-hoon Sohn, Yu-sin Yang
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Patent number: 11158509Abstract: A method for semiconductor manufacturing includes providing a substrate, forming a patterning layer over the substrate, and patterning the patterning layer to form a hole in the patterning layer. The method also includes applying a first directional etching to two inner sidewalls of the hole to expand the hole along a first direction and applying a second directional etching to another two inner sidewalls of the hole to expand the hole along a second direction that is different from the first direction.Type: GrantFiled: May 19, 2020Date of Patent: October 26, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Tien Shen, Chi-Cheng Hung, Chin-Hsiang Lin, Chien-Wei Wang, Ching-Yu Chang, Chih-Yuan Ting, Kuei-Shun Chen, Ru-Gun Liu, Wei-Liang Lin, Ya Hui Chang, Yuan-Hsiang Lung, Yen-Ming Chen, Yung-Sung Yen
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Patent number: 11150563Abstract: A technique of measuring a parameter of a patterning process is disclosed. In one arrangement, a target, formed by the patterning process, is illuminated. A sub-order diffraction component of radiation scattered from the target is detected and used to determine the parameter of the patterning process.Type: GrantFiled: December 10, 2019Date of Patent: October 19, 2021Assignee: ASML Netherlands B.V.Inventors: Sergei Sokolov, Sergey Tarabrin, Su-Ting Cheng, Armand Eugene Albert Koolen, Markus Franciscus Antonius Eurlings, Koenraad Remi André Maria Schreel
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Patent number: 11137684Abstract: A method of performing a lithography process includes receiving a lithography mask and performing overlay measurement. The lithography mask includes a substrate that contains a low thermal expansion material (LTEM); a reflective structure over a first side of the substrate; an absorber layer over the reflective structure and containing one or more first overlay marks; and a conductive layer over a second side of the substrate and containing one or more second overlay marks. The second side is opposite the first side. The overlay measurement includes using the one or more first overlay marks in an extreme ultraviolet (EUV) lithography process or using the one or more second overlay marks in a non-EUV lithography process.Type: GrantFiled: December 18, 2019Date of Patent: October 5, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yun-Yue Lin, Hsin-Chang Lee, Chia-Jen Chen, Chih-Cheng Lin, Anthony Yen, Chin-Hsiang Lin
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Patent number: 11079684Abstract: A measurement apparatus and method for determining a substrate grid describing a deformation of a substrate prior to exposure of the substrate in a lithographic apparatus configured to fabricate one or more features on the substrate. Position data for a plurality of first features and/or a plurality of second features on the substrate is obtained. Asymmetry data for at least a feature of the plurality of first features and/or the plurality of second features is obtained. The substrate grid based on the position data and the asymmetry data is determined. The substrate grid and asymmetry data are passed to the lithographic apparatus for controlling at least part of an exposure process to fabricate one or more features on the substrate.Type: GrantFiled: December 21, 2018Date of Patent: August 3, 2021Assignee: ASML Netherlands B.V.Inventors: Franciscus Godefridus Casper Bijnen, Edo Maria Hulsebos, Henricus Johannes Lambertus Megens, Robert John Socha, Youping Zhang
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Patent number: 11043239Abstract: A laser beam is directed through a transmissive axicon telescope or a reflective axicon telescope such as in a magneto-optic Kerr effect metrology system. With the transmissive axicon telescope, a Gaussian beam profile is directed through a first axicon lens and a second axicon lens. The first axicon lens and second axicon lens transfer the Gaussian beam profile of the laser beam to a hollowed laser ring. The laser beam with a hollowed laser ring can be directed through a Schwarzschild reflective objective. With the reflective axicon telescope, the laser beam is directed through two conical mirrors that are fully reflective. One of the conical mirrors defines a central hole that the laser beam passes through.Type: GrantFiled: March 17, 2020Date of Patent: June 22, 2021Assignee: KLA CorporationInventors: Jun Wang, Yaolei Zheng, Chunxia Li, Changfei Yan, Lansheng Dong, Yang Zhou, Hai-Yang You, Haijing Peng, Jianou Shi, Rui Ni, Shankar Krishnan, David Y. Wang, Walter H. Johnson
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Patent number: 11022896Abstract: Corrections are calculated for use in controlling a lithographic apparatus. Using a metrology apparatus a performance parameter is measured at sampling locations across one or more substrates to which a lithographic process has previously been applied. A process model is fitted to the measured performance parameter, and an up-sampled estimate is provided for process-induced effects across the substrate. Corrections are calculated for use in controlling the lithographic apparatus, using an actuation model and based at least in part on the fitted process model. For locations where measurement data is available, this is added to the estimate to replace the process model values. Thus, calculation of actuation corrections is based on a modified estimate which is a combination of values estimated by the process model and partly on real measurement data.Type: GrantFiled: February 22, 2017Date of Patent: June 1, 2021Assignee: ASML Netherlands B.V.Inventors: Emil Peter Schmitt-Weaver, Amir Bin Ismail, Kaustuve Bhattacharyya, Paul Derwin
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Patent number: 11003100Abstract: In a beam irradiation apparatus in which a movable body holds an object, a mark detection system detects a first mark on the movable body while moving the movable body in a first direction and changing an irradiation position of a measurement beam in the first direction, the mark detection system detects a second mark while moving the movable body in the first direction and changing the irradiation position of the measurement beam in the first direction, a controller controls a position of the movable body in a second direction intersecting the first direction during a time period between the detection of the first mark and the detection of the second mark, and the controller controls the movement of the movable body to adjust a positional relation between the object on the movable body and a processing beam, based on results of the detection of the first and second marks.Type: GrantFiled: November 29, 2019Date of Patent: May 11, 2021Assignee: NIKON CORPORATIONInventor: Akihiro Ueda
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Patent number: 10994368Abstract: There is provided a wafer for examination that is a wafer for examination with which energy distribution in a region of a light condensing spot of a laser beam with which irradiation is carried out from the upper surface side of a wafer is checked, and is a wafer for examination in which a first metal layer and a second metal layer different in specific heat or a melting point are formed over an upper surface of a wafer. In an examination method of energy distribution, the energy distribution of the laser beam is checked based on a processing mark formed in the first and second metal layers of the wafer for examination.Type: GrantFiled: August 21, 2018Date of Patent: May 4, 2021Assignee: DISCO CORPORATIONInventor: Seiichi Sai
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Patent number: 10990022Abstract: A metrology system may include a controller coupled to a metrology tool. The controller may receive a metrology target design including at least a first feature formed by exposing a first exposure field on a sample with a lithography tool, and at least a second feature formed by exposing a second exposure field on the sample with the lithography tool, where the second exposure field overlaps the first exposure field at a location of a metrology target on the sample. The controller may further receive metrology data associated with the metrology target fabricated according to the metrology target design, determine one or more fabrication errors during fabrication of the metrology target based on the metrology data, and generate correctables to adjust one or more fabrication parameters of the lithography tool in one or more subsequent lithography steps based on the one or more fabrication errors.Type: GrantFiled: November 8, 2019Date of Patent: April 27, 2021Assignee: KLA CorporationInventors: Enna Leshinsky-Altshuller, Inna Tarshish-Shapir, Mark Ghinovker, Diana Shaphirov, Guy Ben Dov, Roie Volkovich, Chris Steely
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Patent number: 10991657Abstract: A method for fabricating a semiconductor device is provided. The method includes obtaining a pattern density of an integrated circuit (IC) design layout; adjusting a density of an alignment mark pattern of the IC design layout according to the pattern density; and patterning a material layer according to the IC design layout after adjusting the density of the alignment mark pattern.Type: GrantFiled: August 27, 2018Date of Patent: April 27, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chiu-Hsiang Chen, Shih-Chun Huang, Yung-Sung Yen, Ru-Gun Liu
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Patent number: 10977420Abstract: A method of decomposing a layout for multiple-patterning lithography includes receiving an input that represents a layout of a semiconductor device. The layout includes a plurality of conductive lines of a cell. A first set of conductive lines are overlaid by a second set of conductive lines. The method further includes partitioning the second set of conductive lines into groups. A first group has a different number of conductive lines from the second set than a second group. The method further includes assigning conductive lines from the first set overlaid by conductive lines of the first group to a first photomask and assigning conductive lines from the first set overlaid by conductive lines of the second group to second and third photomasks.Type: GrantFiled: December 23, 2019Date of Patent: April 13, 2021Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Meng-Kai Hsu, Wen-Hao Chen
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Patent number: 10962883Abstract: Systems and methods described herein relate to the manufacture of optical elements and optical systems. An example method includes overlaying a first mask on a photoresist material and a substrate, and causing a light source to illuminate the photoresist material through the first mask during a first exposure so as to define a first feature. During the first exposure, the light source is positioned at a non-normal angle with respect to a plane parallel to the substrate. The method includes developing the photoresist material so as to retain an elongate portion of the photoresist material on the substrate. A first end of the elongate portion includes an angled portion that is sloped at an angle with respect to a long axis of the elongate portion. The method also includes depositing a reflective material through a second mask onto the angled portion.Type: GrantFiled: November 15, 2019Date of Patent: March 30, 2021Assignee: Waymo LLCInventors: Bernard Fidric, Pierre-yves Droz, David Hutchison
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Patent number: 10955530Abstract: A scanning lidar system includes an external frame, an internal frame attached to the external frame by vibration-isolation mounts, and an electro-optic assembly movably attached to the internal frame and configured to be translated with respect to the internal frame during scanning operation of the scanning lidar system.Type: GrantFiled: December 13, 2017Date of Patent: March 23, 2021Assignee: Cepton Technologies, Inc.Inventors: Jun Pei, Mark Mccord, Jun Ye, Yupeng Cui, Liqun Han
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Patent number: 10921722Abstract: According to one embodiment, there is provided an exposure apparatus which projects a pattern of an original onto a substrate by a projection optical system so as to expose the substrate. The exposure apparatus includes a substrate stage, an alignment detecting system, and a controller. The substrate stage holds the substrate on which shot areas each including multiple chip areas are placed. The alignment detecting system detects multiple first alignment marks placed in a peripheral region in a first chip area in the shot area. The controller obtains the first amount of positional deviation for the first chip area according to results of detecting the multiple first alignment marks and controls exposure conditions for the first chip area in the shot area according to the first amount of positional deviation.Type: GrantFiled: September 6, 2018Date of Patent: February 16, 2021Assignee: Toshiba Memory CorporationInventor: Manabu Takakuwa
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Patent number: 10895809Abstract: A photomask alignment method for a manufacturing process of an integrated circuit in a semiconductor material wafer (20), the method envisaging: at a first level, defining, by means of a single photolithography process, at least one alignment structure (10; 10?) on the wafer (20), the alignment structure (10; 10?) having at least a first (4a) and a second (4b) reference mark; and, at an upper level, higher than the first one, aligning a first field mask (11a) relative to the at least one first reference mark (4a); and aligning a second field mask (11b), which is used, together with the first field mask (11a), for the photolithography formation of the integrated circuit inside a respective die (22) in the wafer (20), relative to the at least one second reference mark (4b), so that the first and second field masks (11a, 11b) are arranged on the wafer (20) adjacent to one another in a first coupling direction, without any mutual overlapping.Type: GrantFiled: July 13, 2018Date of Patent: January 19, 2021Inventor: Gianluca Eugeni
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Patent number: 10892285Abstract: A display panel is provided. The display panel includes a substrate, a light-shielding positioning layer and a transparent positioning layer. The substrate has a first surface and a second surface opposite to the first surface. The light-shielding positioning layer is disposed on the first layer and has at least one first alignment pattern. The transparent positioning layer is disposed on the second layer and has at least one second alignment pattern. In a direction perpendicular to the substrate, the at least one first alignment pattern overlaps with the at least one second alignment pattern. A manufacturing method of the display panel is also provided.Type: GrantFiled: April 15, 2019Date of Patent: January 12, 2021Assignee: Au Optronics CorporationInventors: Peng-Bo Xi, Chun-Cheng Cheng
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Patent number: 10859924Abstract: A method for manufacturing a structure on a substrate includes projecting an image of a reference pattern onto a substrate having a first patterned layer, the first patterned layer including first alignment marks and first overlay measurement marks, and the reference pattern including second alignment marks and second overlay measurement marks, aligning, based on the first alignment marks and the second alignment marks, the first patterned layer to the image of the reference pattern, obtaining a pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks, and determining compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.Type: GrantFiled: April 27, 2018Date of Patent: December 8, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Yun Wang, Hua-Tai Lin, Chia-Chu Liu
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Patent number: 10838295Abstract: A method of manufacturing a photomask includes depositing a first absorbing layer over a substrate, patterning the first absorbing layer using a photoresist, and depositing a conformal second absorbing layer along surfaces of the first absorbing layer.Type: GrantFiled: May 4, 2017Date of Patent: November 17, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: You-Hua Chou, Kuo-Sheng Chuang
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Patent number: 10831111Abstract: A method of measuring a target, an associated lithographic method, an associated computer program product and an associated litho cell is provided, wherein the method includes measuring the target subsequent to exposure of structures by a lithographic process in a current layer on a substrate over one or more preceding layers, wherein the one or more preceding layers have each undergone an etch step, and wherein the target is only in at least one of the one or more preceding layers. In this way, an after-etch measurement of the target can be obtained.Type: GrantFiled: February 21, 2017Date of Patent: November 10, 2020Assignee: ASML Netherlands B.V.Inventor: Kaustuve Bhattacharyya
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Patent number: 10805596Abstract: A stereoscopic image sensor apparatus including a pair of image sensors adjacently fabricated on a common carrier is disclosed, the common carrier being a diced portion of a carrier on which an aligned plurality of image sensors have been fabricated within an alignment tolerance, the alignment tolerance including a target lateral offset between the adjacent image sensors, and a target orientation between corresponding rows of light sensitive elements on the adjacent image sensors. An alternative stereoscopic image sensor apparatus includes a common window having first and second image sensors bonded to the common window within the alignment tolerance. Another alternative stereoscopic image sensor apparatus includes rear faces of respective first and second image sensors being bonded to a common circuit substrate within the alignment tolerance. Methods for fabricating the stereoscopic image sensors are also disclosed.Type: GrantFiled: December 2, 2016Date of Patent: October 13, 2020Assignee: TITAN MEDICAL INC.Inventors: Randal B. Chinnock, Jason P. Julian, George Grubner, William L. Weber
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Patent number: 10802409Abstract: A method of measuring n values of a parameter of interest (e.g., overlay) relating to a structure forming process, where n>1. The method includes performing n measurements on each of n+1 targets, each measurement performed with measurement radiation having a different wavelength and/or polarization combination and determining the n values for a parameter of interest from the n measurements of n+1 targets, each of the n values relating to the parameter of interest for a different pair of the layers. Each target includes n+1 layers, each layer including a periodic structure, the targets including at least n biased targets having at least one biased periodic structure formed with a positional bias relative to the other layers, the biased periodic structure being in at least a different one of the layers per biased target. Also disclosed is a substrate having such a target and a patterning device for forming such a target.Type: GrantFiled: April 25, 2018Date of Patent: October 13, 2020Assignee: ASML Netherlands B.V.Inventors: Chi-Hsiang Fan, Maurits Van Der Schaar, Youping Zhang
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Patent number: 10796055Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.Type: GrantFiled: October 22, 2019Date of Patent: October 6, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Ping Chiang, Ming-Hui Chih, Chih-Wei Hsu, Ping-Chieh Wu, Ya-Ting Chang, Tsung-Yu Wang, Wen-Li Cheng, Hui En Yin, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau
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Patent number: 10788765Abstract: As increasing numbers of layers, using increasing numbers of specific materials, are deposited on substrates, it becomes increasingly difficult to detect alignment marks accurately for, for example, applying a desired pattern onto a substrate using a lithographic apparatus, in part due to one or more of the materials used in one or more of the layers being wholly or partially opaque to the radiation used to detect alignment marks. In a first step, the substrate is illuminated with excitation radiation. In a second step, at least one effect associated with a reflected material effect scattered by a buried structure is measured. The effect may, for example, include a physical displacement of the surface of the substrate. In a third step, at least one characteristic of the structure based on the measured effect is derived.Type: GrantFiled: January 10, 2018Date of Patent: September 29, 2020Assignee: ASML Netherlands B.V.Inventors: Stefan Michiel Witte, Alessandro Antoncecchi, Stephen Edward, Hao Zhang, Paulus Clemens Maria Planken, Kjeld Sijbrand Eduard Eikema, Sebastianus Adrianus Goorden, Simon Reinald Huisman, Irwan Dani Setija
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Patent number: 10782617Abstract: A method, including: measuring a first plurality of instances of a metrology target on a substrate processed using a patterning process to determine values of at least one parameter of the patterning process using a first metrology recipe for applying radiation to, and detecting radiation from, instances of the metrology target; and measuring a second different plurality of instances of the metrology target on the same substrate to determine values of the at least one parameter of the patterning process using a second metrology recipe for applying radiation to, and detecting radiation from, instances of the metrology target, wherein the second metrology recipe differs from the first metrology recipe in at least one characteristic of the applying radiation to, and detecting radiation from, instances of the metrology target.Type: GrantFiled: August 1, 2018Date of Patent: September 22, 2020Assignee: ASML Netherlands B.V.Inventors: Anagnostis Tsiatmas, Elliott Gerard McNamara
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Patent number: 10750318Abstract: A positioning method including following steps is provided. Firstly, several base stations are commanded to detect a tracked object. Then, a first position of the tracked object is obtained according to the first return information. Then, several fixed-type signal transceivers are selected according to the first position. Then, the selected fixed-type signal transceivers are commanded to detect the tracked object, and a second position of the tracked object is obtained according to the second return information received from the fixed-type signal transceivers.Type: GrantFiled: June 5, 2017Date of Patent: August 18, 2020Assignees: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, LITE-ON TECHNOLOGY CORPORATIONInventors: Pei-Yuan Lien, Johnson Lee, Chun-Tao Chen, Yao-Chung Yeh
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Patent number: 10727126Abstract: A method for forming a semiconductor device includes forming a laser marking buried within a semiconductor substrate and thinning the semiconductor substrate from a backside of the semiconductor substrate. For example, a semiconductor device includes a semiconductor substrate located in a semiconductor package. A laser marking is buried within the semiconductor substrate. For example, another semiconductor device includes a semiconductor substrate. A laser marking is located at a backside surface of the semiconductor substrate. Further, a portion of the backside surface located adjacent to the laser marking is free of recast material.Type: GrantFiled: May 24, 2017Date of Patent: July 28, 2020Assignee: INFINEON TECHNOLOGIES AGInventors: Korbinian Kaspar, Franco Mariani
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Patent number: 10702044Abstract: A cosmetic activator system for activating a cosmetic is provided including: an activator having an energy source configured to emit an energy pulse and a controller; and an imprinter having an imprint pattern and at least one activation element configured to be in communication with the energy source, wherein the imprinter is configured to create an imprint on the cosmetic.Type: GrantFiled: June 30, 2016Date of Patent: July 7, 2020Assignee: L'OREALInventor: John Streeter