Registration Or Layout Process Other Than Color Proofing Patents (Class 430/22)
  • Patent number: 8399160
    Abstract: Provided is a reflective mask blank, wherein even if inspection light for defect inspection is irradiated onto an uppermost surface of a multilayer reflective film or of an absorber film formed over a reference point mark, sufficient contrast is obtained between a position of the reference point mark and its peripheral portion so that the position of the reference point mark can be identified with high accuracy. By forming a reference point mark (11) in the form of a recess having a depth of 10 ?m or more and a width of 80 ?m or more on a main surface of a substrate (12), even if a multilayer reflective film (13), an absorber film (15), and so on are formed over the reference point mark (11), sufficient contrast for the inspection light is obtained so that the position of the reference point mark (11) can be identified with high accuracy.
    Type: Grant
    Filed: November 11, 2009
    Date of Patent: March 19, 2013
    Assignee: Hoya Corporation
    Inventor: Tsutomu Shoki
  • Patent number: 8399163
    Abstract: When an alignment mark does not exist within an area of an image obtained by a camera, the coordinate of the alignment mark is calculated based on an identification mark existing in the area of the image and a previously stored positional relationship between the alignment mark and the identification mark. A distance by which a long-sized base material is to be moved for causing the alignment mark to be positioned within the imaging area of the camera is calculated based on the calculated coordinate of the alignment mark, and the long-sized base material is moved by the calculated distance.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: March 19, 2013
    Assignee: Nitto Denko Corporation
    Inventors: Kousuke Murakami, Akira Arima, Tomohiro Hattori, Shuuhei Miyazaki
  • Patent number: 8383324
    Abstract: A method of manufacturing a semiconductor device comprising forming an active region in a device substrate using a first phase shift mask (PSM) having a first patterned light shielding layer formed thereon, forming a polysilicon feature on the device substrate over the active region using a second PSM having a second patterned light shielding layer formed thereon, forming a contact feature on the polysilicon feature using a third PSM having a third patterned light shielding layer formed thereon, and forming a metal feature on the contact feature using a fourth PSM having a fourth patterned light shielding layer formed thereon, wherein at least one of the third and fourth patterned light shielding layers is patterned substantially similarly to at least one of the first and second patterned light shielding layers.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: February 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Cheng-Ming Lin
  • Patent number: 8384900
    Abstract: An exposure apparatus includes a controller configured to calculate a position of an alignment mark detected by a detector, to approximate a deformation of a substrate by using an approximation equation, to calculate a correction amount of each of the plurality of shots, and to control driving of a stage in exposing each shot based on a correction amount that is calculated. The approximation equation is defined as a sum of a first term representative of a deformation of the entire substrate, and at least one of a second term representative of a distortion of a shot arrangement and a third term representative of a shot shape.
    Type: Grant
    Filed: October 21, 2009
    Date of Patent: February 26, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventor: Shinichiro Koga
  • Patent number: 8367284
    Abstract: An exposure device includes a determining unit determines specific transfer patterns, which are transfer patterns of predetermined portions of a unit pattern, among transfer patterns projected through a photomask including an internal pattern having a plurality of unit patterns that is arranged at a predetermined interval and has the same shape, for two or more unit patterns, an error calculating unit calculates an error between the transfer pattern and the specified transfer pattern on the basis of the comparison between the relative position between the specific transfer patterns and a specified value of it, a correction parameter calculating unit calculates correction parameters for correcting the transfer patterns on the basis of the calculated error, and a correction control unit corrects exposure conditions using the correction parameters such that the transfer patterns are corrected.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: February 5, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Kyoichi Tsubata
  • Patent number: 8361679
    Abstract: A phase shift mask having a first region and a second region in a transverse direction includes a transparent layer, a phase shift pattern disposed in the first region, a transmittance control layer pattern disposed in the second region, and a shading layer pattern disposed on the transmittance control layer pattern. The phase shift pattern has a first pattern including a transparent material and a second pattern including metal. The phase shift mask may prevent haze effects through a cleaning process using an alkaline cleaning solution.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: January 29, 2013
    Assignee: Samsung Electronics Co. Ltd.
    Inventors: Se-Gun Moon, Dong-Seok Nam, Hoon Kim
  • Patent number: 8361684
    Abstract: Methods for patterning integrated circuit (IC) features with varying dimensions are provided. In an example, a method includes forming a first patterned radiation-sensitive resist layer over a device substrate using a first mask, wherein the first patterned radiation-sensitive resist layer includes a first portion of an IC pattern; using the patterned first radiation-sensitive resist layer as a mask to form the first portion of the IC pattern in the device substrate; forming a second patterned radiation-sensitive resist layer over the device substrate using a second mask, wherein the second patterned radiation-sensitive resist layer includes a second portion of the IC pattern; and using the patterned second radiation-sensitive resist layer as a mask to form the second portion of the IC pattern in the device substrate. The combined first and second portions of the IC pattern in the device substrate form an IC feature having a dimension greater than dimensions of the first and second portions.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: January 29, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Kuo Hsieh, Hsin-Yi Tsai, Min Cao
  • Patent number: 8361683
    Abstract: A wafer includes an active region and a kerf region surrounding at least a portion of the active region. The wafer also includes a target region having a rectangular shape with a width and a length greater than the width, the target region including one or more target patterns, at least one of the target patterns being formed by two sub-patterns disposed at opposing corners of a target rectangle disposable within the target region.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: January 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Christopher P. Ausschnitt, Allen H. Gabor, Nelson M. Felix
  • Patent number: 8354209
    Abstract: A lithographic apparatus, includes a support structure configured to hold a patterning device, the patterning device configured to impart a beam of radiation with a pattern in its cross-section; a substrate table configured to hold a substrate; a projection system configured to project the patterned beam onto a target portion of the substrate; a liquid supply system configured to provide liquid to a space between the projection system and the substrate table; a sensor configured to measure an exposure parameter using a measuring beam projected through the liquid; and a correction system configured to determine an offset based on a change of a physical property impacting a measurement made using the measuring beam to at least partly correct the measured exposure parameter.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: January 15, 2013
    Assignee: ASML Netherlands B.V.
    Inventors: Bob Streefkerk, Johannes Jacobus Matheus Baselmans, Sjoerd Nicolaas Lambertus Donders, Jeroen Johannes Sophia Maria Mertens, Johannes Catharinus Hubertus Mulkens, Christiaan Alexander Hoogendam
  • Patent number: 8345244
    Abstract: An exposure apparatus includes a controller configured to calculate a position of an alignment mark detected by a detector, to approximate a deformation of a substrate by using an approximation equation, to calculate a correction amount of each of the plurality of shots, and to control driving of a stage in exposing each shot based on a correction amount that is calculated. The approximation equation is defined as a sum of a first term representative of a deformation of the entire substrate, and at least one of a second term representative of a distortion of a shot arrangement and a third term representative of a shot shape.
    Type: Grant
    Filed: October 21, 2009
    Date of Patent: January 1, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventor: Shinichiro Koga
  • Patent number: 8343693
    Abstract: A focus test reticle for measuring focus information includes an outer pattern. The outer pattern has a line pattern composed of a light shielding film extending in the Y direction, a phase shift portion provided on a side in the +X direction of the line pattern and formed to have a line width narrower than the line pattern, a transmitting portion provided on a side in the ?X direction of the line pattern and formed to have a line width narrower than the line pattern, a transmitting portion provided on a side in the +X direction of the phase shift portion, and a phase shift portion provided on a side in the ?X direction of the transmitting portion. Focus information of a projection optical system is measured at a high measuring reproducibility and a high measuring efficiency.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: January 1, 2013
    Assignee: Nikon Corporation
    Inventors: Shigeru Hirukawa, Shinjiro Kondo
  • Patent number: 8329360
    Abstract: Provided is an apparatus that includes an overlay mark. The overlay mark includes a first portion that includes a plurality of first features. Each of the first features have a first dimension measured in a first direction and a second dimension measured in a second direction that is approximately perpendicular to the first direction. The second dimension is greater than the first dimension. The overlay mark also includes a second portion that includes a plurality of second features. Each of the second features have a third dimension measured in the first direction and a fourth dimension measured in the second direction. The fourth dimension is less than the third dimension. At least one of the second features is partially surrounded by the plurality of first features in both the first and second directions.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: December 11, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Guo-Tsai Huang, Fu-Jye Liang, Li-Jui Chen, Chih-Ming Ke
  • Patent number: 8329366
    Abstract: A method is described for alignment of a substrate during a double patterning process. A first resist layer containing at least one alignment mark is formed on the substrate. After the first resist layer is developed, a second resist layer is deposited over the first resist layer, leaving a planar top surface (i.e., without topography). By baking the second resist layer appropriately, a symmetric alignment mark is formed in the second resist layer with little or no offset error from the alignment mark in the first resist layer. The symmetry of the alignment mark formed in the second resist can be enhanced by appropriate adjustments of the respective thicknesses of the first and second resist layers, the coating process parameters, and the baking process parameters.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: December 11, 2012
    Assignees: ASML Netherlands B.V., ASML Holding N.V.
    Inventors: Maya Angelova Doytcheva, Mircea Dusa, Richard Johannes Franciscus Van Haren, Harry Sewell, Robertus Wilhelmus Van Der Heijden
  • Patent number: 8323860
    Abstract: A solid-state imaging device producing method includes the steps of: applying a resist material onto a substrate in which a channel region is formed; forming a resist layer by exposure and development of the resist material using a mask, the resist layer having an opening and a thin-film portion, the mask having a first region through which light is transmitted and a second region through which a smaller quantity of light than that the light transmitted through the first region is transmitted; subjecting the substrate to ion implantation using the resist layer as a mask to form an impurity region; etching the substrate using the resist layer as a mask after the ion implantation to form an alignment mark; and forming an electrode on the impurity region and part of the channel region using the alignment mark as a reference.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: December 4, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shu Sasaki
  • Patent number: 8318392
    Abstract: An alignment method is disclosed, in which a distance between a substrate and a photomask is set at a predetermined exposure gap. The photomask is rectangular, and includes a first side, and a second side opposite to the first side. A distance between a midpoint of the first side and the substrate is matched with the exposure gap. The photomask is rotated about, as an axis, a line that connects the midpoint of the first side and a midpoint of the second side to each other, whereby distances between both ends of the first side and the substrate are individually matched with the exposure gap. The photomask is rotated about the first side taken as an axis, whereby a distance between the midpoint of the second side and the substrate is matched with the exposure gap.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: November 27, 2012
    Assignee: Panasonic Corporation
    Inventors: Ryota Hamada, Tomohiro Murakoso
  • Patent number: 8313877
    Abstract: A photolithography monitoring mark on a substrate includes a plurality of sets of lines. Individual of the sets include a plurality of substantially parallel lines comprising different widths arrayed laterally outward in opposing lateral directions from an axial center of the set. The different widths decrease in each of the opposing lateral directions laterally outward from the axial center of the set. Other implementations are disclosed.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: November 20, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Woong Jae Chung
  • Patent number: 8309282
    Abstract: An apparatus and method for aligning a mask that includes disposing and firstly aligning a mask over a first substrate, with a space interposed therebetween, bringing the mask into contact with the first substrate and then measuring the alignment state of the mask with respect to the first substrate to detect an alignment error, secondly aligning the mask with respect to the first substrate based on the alignment error, transferring the first substrate to the next process, disposing and thirdly aligning the mask over a second substrate with the space interposed therebetween, and bringing the mask into contact with the second substrate.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: November 13, 2012
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kyung-Hoon Chung, Hyung-Min Kim
  • Patent number: 8304173
    Abstract: The method of forming a pattern includes forming a first photosensitive layer pattern including a first pattern in a first region of a substrate and a second pattern in a second region of the substrate, by performing a first photolithography process using a photomask having a first mask region and a second mask region. The first pattern is transferred from the first mask region, and the second pattern is transferred from the second mask region. The method further includes forming a second photosensitive layer pattern including a third pattern in the second region of the substrate and a fourth pattern in the first region of the substrate, by performing a second photolithography process using the photomask. The third pattern is transferred from the first mask region, and the fourth pattern is transferred from the second mask region.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: November 6, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Yong Yu, Sung-Hyuck Kim, Gi-Sung Yoon
  • Patent number: 8289516
    Abstract: A method of measuring focus of a lithographic projection apparatus includes exposure of a photoresist covered test substrate with a plurality of verification fields. Each of the verification fields includes a plurality of verification markers, and the verification fields are exposed using a predetermined focus offset FO. After developing, an alignment offset for each of the verification markers is measured and translated into defocus data using a transposed focal curve. The method according to an embodiment of the invention may result in a focus-versus alignment shift sensitivity up to 50 times higher (typically dX,Y/dZ=20) than conventional approaches.
    Type: Grant
    Filed: November 19, 2008
    Date of Patent: October 16, 2012
    Assignee: ASML Netherlands B.V.
    Inventors: Gerardus Carolus Johannus Hofmans, Hubertus Antonius Geraets, Mark Zellenrath, Sven Gunnar Krister Magnusson
  • Patent number: 8288063
    Abstract: A method includes performing a lithography process on a wafer to form a patterned photo resist, and measuring the wafer to determine an overlay error of the patterned photo resist. A high/low specification is determined using the overlay error. An overlay process value setting is generated and compared with the high/low specification to determine whether the overlay process value setting is within a range defined by the high/low specification.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: October 16, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Rung Lu, Chih Ming Hong, Yen-Di Tsen
  • Patent number: 8278014
    Abstract: A photomask includes a transparent substrate having a transparent property against exposing light, a semi-light-shielding portion formed on the transparent substrate, a first opening formed in the semi-light-shielding portion and having a first dimension and a second opening formed in the semi-light-shielding portion and having a second dimension lager than the first dimension. A phase-shifting portion which transmits the exposing light in an opposite phase with respect to the first opening is formed on the transparent substrate around the first opening. A light-shielding portion is formed on the transparent substrate around the second opening.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: October 2, 2012
    Assignee: Panasonic Corporation
    Inventors: Shigeo Irie, Akio Misaka, Yuji Nonami, Tetsuya Nakamura, Chika Harada
  • Publication number: 20120244459
    Abstract: A mask for evaluating overlay error comprises a plurality of replicate device regions and an overlay mark. The plurality of replicate device regions are disposed uniformly on the mask, wherein each comprises a plurality of device patterns; and a plurality of current layer check patterns are formed adjacent to the plurality of device patterns. The overlay mark is formed on the corner of the mask's peripheral region. In particular, the current layer check patterns are configured to evaluate the pattern offset of a current mask, and the overlay mark and the current layer check patterns are configured to evaluate the overlay error by performing an exposure process using the current mask and a next mask.
    Type: Application
    Filed: March 24, 2011
    Publication date: September 27, 2012
    Applicant: NANYA TECHNOLOGY CORP.
    Inventors: Kuan Ting CHOU, Pei Cheng FAN
  • Patent number: 8260033
    Abstract: A method is provided for determining the relative overlay shift of stacked layers, said method comprising the steps of: a) providing a reference image including a reference pattern that comprises first and second pattern elements; b) providing a measurement image of a measurement pattern, which comprises a first pattern element formed by a first one of the layers and a second pattern element formed by a second one of the layers; c) weighting the reference or measurement image such that a weighted first image is generated, in which the first pattern element is emphasized relative to the second pattern element; d) determining the relative shift of the first pattern element on the basis of the weighted first image and of the measurement or reference image not weighted in step c); e) weighting the reference or measurement image such that a weighted second image is generated, in which the second pattern element is emphasized relative to the first pattern element; f) determining the relative shift of the second pat
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: September 4, 2012
    Assignee: Carl Zeiss SMS GmbH
    Inventors: Michael Arnz, Gerd Klose
  • Patent number: 8252489
    Abstract: A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift. The step of simulating the worst-case performance includes calculating capacitance values corresponding to mask shifts, and the capacitance values are calculated using a high-order equation or a piecewise equation.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: August 28, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ke-Ying Su, Chung-Hsing Wang, Jui-Feng Kuan, Hsiao-Shu Chao, Yi-Kan Cheng
  • Patent number: 8252491
    Abstract: A marker, for example an alignment marker or an overlay marker is formed in two steps. First, a pattern of two chemically distinct feature types having a pitch comparable to product features is formed. This pattern is then masked by resist in the form of the desired marker, which has a larger pitch than the pattern. Finally, one of the two feature types is selectively etched in the open areas. The result is a marker with a large pitch suitable to be read with long wavelength radiation but the edges of the features are defined in an exposure step having a pitch comparable to the product features.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: August 28, 2012
    Assignee: ASML Netherlands B.V.
    Inventors: Richard Johannes Franciscus Van Haren, Maurits Van Der Schaar
  • Patent number: 8243273
    Abstract: A semiconductor wafer may include a dummy field configured to enable overlay measurements. The enhanced dummy field may include a plurality of encoding blocs that enable OVL measurements to be made throughout the enhanced dummy field.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: August 14, 2012
    Assignee: KLA-Tencor Corporation
    Inventors: Vladimir Levinski, Michael Adel, Mark Ghinovker, Alexander Svizher
  • Patent number: 8236464
    Abstract: A method for making a mask, in which, an imprinting lithography process is employed to form a pattern in a first region of a mask substrate, and an E-beam writing process is employed to form another pattern in a second region of the mask substrate. Furthermore, these two patterns may be well stitched through an optical alignment process in an E-beam writing chamber.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: August 7, 2012
    Assignee: Inotera Memories, Inc.
    Inventor: Tah-Te Shih
  • Patent number: 8216382
    Abstract: A foreign matter removal method that removes foreign matter attached to a surface of a substrate having been subjected to predetermined processing. An edge of a rotating substrate mounted on a mounting stage is irradiated with misalignment measurement laser light. The misalignment measurement laser light other than the laser light blocked by the edge of the substrate is received, and power thereof is detected. The amount of misalignment of the substrate is calculated based on the detected power of the misalignment measurement laser light and a detected rotation angle of the rotating substrate. The misalignment of the substrate is corrected for based on the calculated amount of misalignment. After that, foreign matter removal laser light is irradiated, and a process gas that is to react with the foreign matter is jetted to the edge of the substrate. Consequently, the foreign matter attached to the substrate is decomposed and removed.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: July 10, 2012
    Assignee: Tokyo Electron Limited
    Inventor: Takehiro Shindo
  • Patent number: 8203223
    Abstract: A target and method for use in polarized light lithography. A preferred embodiment comprises a first structure located on a reference layer, wherein the first structure is visible through a second layer, and a second structure located on the second layer, wherein the second structure is formed from a photomask containing a plurality of sub-structures oriented in a first orientation, wherein a polarized light is used to pattern the second structure onto the second layer, and wherein a polarization of the polarized light is the same as the orientation of the plurality of sub-structures. The position, size, and shape of the second structure is dependent upon a polarity of the polarized light, permitting a single design for an overlay target to be used with different polarities of polarized light.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: June 19, 2012
    Assignee: Infineon Technologies AG
    Inventor: Sajan Marokkey
  • Patent number: 8187778
    Abstract: A method for correcting a position error of a lithography apparatus comprises inputting position data of exposure pattern, irradiating laser light onto a position reference mask from a position measurement laser system, calculating actual position data of the laser light irradiated onto the position reference mask, and comparing the position data of the exposure pattern with the actual position data of the laser light irradiated onto the position reference mask. With this method, circuit patterns can be accurately formed at predetermined positions on a photomask, and the circuit patterns on the photomask can be accurately formed at predetermined positions on a wafer.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: May 29, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Choi, Dong-Seok Nam
  • Patent number: 8187773
    Abstract: A method for generating data on mask pattern used to form a device pattern formed on a reflective exposure mask, wherein data on the mask pattern is generated based on a position correction amount table used to correct an amount of transfer position error occurring depending on at least one of pattern size and pattern pitch of the mask pattern when the mask pattern is transferred onto an exposure target member.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: May 29, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yumi Nakajima, Masaru Suzuki, Takashi Sato
  • Patent number: 8183123
    Abstract: A method of forming a mark in an IC fabricating process is described. Two parts of the mark each including a plurality of linear patterns are respectively defined by two exposure steps that either belong to two lithography processes respectively or constitute a double-exposure process including X-dipole and Y-dipole exposure steps.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: May 22, 2012
    Assignee: MACRONIX International Co., Ltd.
    Inventor: Chin-Cheng Yang
  • Patent number: 8137875
    Abstract: Methods and apparatuses for patterning workpieces are provided. The methods and apparatuses described herein improve overlay between subsequently patterned layers on a workpiece by introducing an improved alignment method that compensates for workpiece distortions.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: March 20, 2012
    Assignee: Micronic-Mydata AB
    Inventors: Fredrik Sjöström, Mikael Wahlsten
  • Patent number: 8129097
    Abstract: A method of obtaining information related to a defect present in the irradiation of a substrate coated with a layer of radiation sensitive material using immersion lithography is disclosed. The method includes irradiating an area of the radiation sensitive material with a non-patterned radiation beam, the area being irradiated with a dose which is sufficient for the radiation sensitive material to be substantially removed during subsequent development of the radiation sensitive material if the radiation sensitive material is a positive radiation sensitive material, or with a dose which is sufficient for the radiation sensitive material to be substantially insoluble during subsequent development of the radiation sensitive material if the radiation sensitive material is a negative radiation sensitive material.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: March 6, 2012
    Assignee: ASML Netherlands B.V.
    Inventors: Dirk De Vries, Richard Moerman, Cédric Désiré Grouwstra, Michel Franciscus Johannes Van Rooy
  • Patent number: 8119310
    Abstract: A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: February 21, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lee-Chung Lu, Yi-Kan Cheng, Hsiao-Shu Chao, Ke-Ying Su, Cheng-Hung Yeh, Dian-Hau Chen, Ru-Gun Liu, Wen-Chun Huang
  • Patent number: 8105736
    Abstract: A method of performing overlay error correction includes forming a photoresist layer over a substrate and exposing a first set of apertures to incident radiation. The method also includes determining an overlay error associated with the first set of apertures and determining an overlay correction as a function of the determined overlay error. The method further includes exposing a data area and a second set of apertures. The data area and the second set of apertures are exposed based, in part, on the determined overlay correction. Moreover, the method includes verifying the determined overlay correction.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: January 31, 2012
    Assignee: Miradia Inc.
    Inventors: Xiao Yang, Yuxiang Wang, Ye Wang, Justin Payne, Wook Ji
  • Patent number: 8107079
    Abstract: A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: January 31, 2012
    Assignees: International Business Machines Corporation, Nanometrics Incorporated
    Inventors: Christopher P. Ausschnitt, Lewis A. Binns, Jaime D. Morillo, Nigel P. Smith
  • Patent number: 8102507
    Abstract: A lithographic apparatus, includes a support structure configured to hold a patterning device, the patterning device configured to impart a beam of radiation with a pattern in its cross-section; a substrate table configured to hold a substrate; a projection system configured to project the patterned beam onto a target portion of the substrate; a liquid supply system configured to provide liquid to a space between the projection system and the substrate table; a sensor configured to measure an exposure parameter using a measuring beam projected through the liquid; and a correction system configured to determine an offset based on a change of a physical property impacting a measurement made using the measuring beam to at least partly correct the measured exposure parameter.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: January 24, 2012
    Assignee: ASML Netherlands B.V.
    Inventors: Bob Streefkerk, Johannes Jacobus Matheus Baselmans, Sjoerd Nicolaas Lambertus Donders, Jeroen Johannes Sophia Mertens, Johannes Catharinus Hubertus Mulkens, Christiaan Alexander Hoogendam
  • Publication number: 20120015289
    Abstract: An alignment method is disclosed, in which a distance between a substrate and a photomask is set at a predetermined exposure gap. The photomask is rectangular, and includes a first side, and a second side opposite to the first side. A distance between a midpoint of the first side and the substrate is matched with the exposure gap. The photomask is rotated about, as an axis, a line that connects the midpoint of the first side and a midpoint of the second side to each other, whereby distances between both ends of the first side and the substrate are individually matched with the exposure gap.
    Type: Application
    Filed: February 28, 2011
    Publication date: January 19, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Ryota Hamada, Tomohiro Murakoso
  • Patent number: 8092961
    Abstract: A position aligning apparatus performs position alignment of a pattern in a current process of a pattern exposure process by using a pattern formed before the current process. The position aligning apparatus includes: a correction calculating section configured to calculate a correction value set of a current lot about each of misalignments in scale and rotation of a pattern in a chip in the current process based on a correction value set in an immediately-preceding lot in the current process, a completeness value set in the immediately-preceding lot in the current process, a summation of completeness value sets in the immediately-preceding lot to a process immediately-preceding to the current process, and a summation of completeness value sets in the current lot to the immediately-preceding process; and a correction control unit configured to control correction of the scale and the rotation of the pattern in the chip by using the correction value sets.
    Type: Grant
    Filed: April 27, 2009
    Date of Patent: January 10, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiaki Yanagawa, Yuki Okada
  • Patent number: 8088539
    Abstract: In an exposure aligning method, a first shift amount indicating a shift amount of a lower layer pattern of an exposure target substrate from an origin point position is determined and a second shift amount indicating a shift amount of the lower layer pattern in at lease one past lot which has been processed before said exposure target substrate is processed, from the origin point position is determined. A third shift amount indicating a difference between the first shift amount and the second shift amount is calculated and a first correction value is determined based on the third shift amount. An exposure position of an exposure target pattern is adjusted based on the first correction value.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: January 3, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Eiichirou Yamanaka
  • Patent number: 8043772
    Abstract: In an exposure process forming a predetermined circuit pattern of a semiconductor device on a wafer, a resist dimension of the resist pattern formed on a wafer and a focus position in the exposure process at a past time are measured. A resist dimension and a focus position of a wafer to which the exposure process is secondly performed are estimated by using measurement results of the measured resist dimension and focus position, and a focus offset value is calculated by using estimated values of the estimated resist dimension and focus position. Then, an exposure dose is calculated with considering this focus offset value, and a resist pattern is formed on the wafer to which the exposure process is performed by using the calculated exposure dose and focus offset value.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: October 25, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiharu Miwa, Junko Konishi, Toshihide Kawachi, Shigenori Yamashita, Takeshi Tashiro, Hidekimi Fudo
  • Patent number: 8043797
    Abstract: A method for transferring an image of a mask pattern through a pitch range onto a substrate is presented. In an embodiment, the method includes illuminating the mask pattern of an attenuated phase shift mask using a multipole illumination that includes an on-axis component and an off-axis component, the mask pattern including non-printing assist features configured for a pitch larger than twice a minimum pitch of the mask pattern, and projecting an image of the illuminated mask pattern onto the substrate.
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: October 25, 2011
    Assignee: ASML Netherlands B.V.
    Inventor: Steven George Hansen
  • Patent number: 8040497
    Abstract: By encoding process-related non-uniformities, such as different height levels, which may be caused by CMP or other processes during the fabrication of complex device levels, such as metallization structures, respective focus parameter settings may be efficiently evaluated on the basis of well-established CD measurement techniques.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: October 18, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thomas Werner, Frank Feustel, Kai Frohberg
  • Patent number: 8039181
    Abstract: By taking into consideration the combination of the substrate holders in various lithography tools used during the imaging to two subsequent device layers, enhanced alignment accuracy may be accomplished. Furthermore, restrictive tool dedications for critical lithography processes may be significantly relaxed by providing specific overlay correction data for each possible process flow, wherein, in some illustrative embodiments, a restriction of the number of possible process flows may be accomplished by implementing a rule for selecting a predefined substrate holder when starting the processing of an associated group of substrates.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: October 18, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Rolf Seltmann, Jens Busch, Uwe Schulze
  • Patent number: 8034515
    Abstract: A pattern designing method according to an embodiment of the present invention includes: designing a first pattern for inspection formed by arraying a plurality of first mark rows, in which rectangular marks are arrayed at predetermined intervals in a first direction, in a second direction perpendicular to the first direction and designing a second pattern for inspection formed by arraying, in the second direction, a plurality of second mark rows in which rectangular marks are arranged among the marks arrayed in the first direction of the first mark row and a forming position in the second direction is arranged to overlap the first mark row by predetermined overlapping length.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: October 11, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Ishigo
  • Patent number: 8029953
    Abstract: A device manufacturing method includes a transfer of a pattern from a patterning device onto a substrate. The device manufacturing method further includes transferring a pattern of a main mark to a base layer for forming an alignment mark; depositing a pattern receiving layer on the base layer; in a first lithographic process, aligning, by using the main mark, a first mask that includes a first pattern and a local mark pattern, and transferring the first pattern and the local mark pattern to the pattern receiving layer; aligning, by using the local mark pattern, a second mask including a second pattern relative to the pattern receiving layer; and in a second lithographic process, transferring the second pattern to the pattern receiving layer; the first and second patterns being configured to form an assembled pattern.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: October 4, 2011
    Assignee: ASML Netherlands B.V.
    Inventors: Maurits Van Der Schaar, Richard Johannes Franciscus Van Haren
  • Patent number: 8029947
    Abstract: Methods, systems, and tool sets involving reticles and photolithography processing. Several embodiments of the invention are directed toward obtaining qualitative data from within the pattern area of a reticle that is indicative of the physical characteristics of the pattern area. Additional embodiments of the invention are directed toward obtaining qualitative data indicative of the physical characteristics of the reticle remotely from a photolithography tool. These two aspects of the invention can be combined in further embodiments in which qualitative data is obtained from within the pattern area of a reticle in a tool that is located remotely from the photolithography tool. As a result, several embodiments of methods and systems in accordance with the invention provide data taken from within the pattern area to more accurately reflect the contour of the pattern area of the reticle without using the photolithography tool to obtain such measurements.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: October 4, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Craig A. Hickman
  • Patent number: 8029952
    Abstract: There is provided a method for fabricating a magnetic recording medium that provides high throughput, low manufacturing cost, and no degradation in accuracy in pattern size in fine pattern formation. A resist layer is formed on a substrate or cutting work layer. The surface of the substrate is divided into two or more areas using the center of rotation of the substrate as a reference point. An optical, contactless pattern transfer method is used to transfer a figure pattern contained in the divided area through a mask to the resist layer so as to form a latent image of the figure pattern. The pattern transfer is similarly carried out for the divided area. After the pattern transfer processes for all the divided areas are completed, the entire resist layer is developed to form a resist pattern. The resist pattern is used as a mask to cut the substrate or cutting work layer. As a result, there is provided the substrate or cut work layer onto which a fine pattern has been transferred.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: October 4, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Yuko Tsuchiya, Chiseki Haginoya
  • Patent number: 8021804
    Abstract: A photomask manufacturing method includes a defect information storage step of storing defect information of a mask blank, provided with an identification marker on an end face thereof, into an information storage device in correspondence to the identification marker, a placing orientation determination step of determining a placing orientation of the mask blank with respect to an exposure/writing apparatus, and an orientation correction step of performing rotation control of a rotating apparatus so that an orientation of the mask blank coincides with the determined placing orientation.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: September 20, 2011
    Assignee: Hoya Corporation
    Inventors: Yasushi Okubo, Hisashi Kasahara