Registration Or Layout Process Other Than Color Proofing Patents (Class 430/22)
  • Patent number: 9184136
    Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first surface and a second surface opposite the first surface, forming an alignment key and a connection contact that penetrate a portion of the semiconductor substrate and extend from the first surface toward the second surface, forming a first circuit on the first surface of the semiconductor substrate such that the first circuit is electrically connected to the connection contact, recessing the second surface of the semiconductor substrate to form a third surface exposing the alignment key and the connection contact, and forming a second circuit on the third surface of the semiconductor substrate such that the second circuit is electrically connected to the connection contact.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: November 10, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jiyoung Kim, Daeik Kim, Kang-Uk Kim, Nara Kim, Jemin Park, Kyuhyun Lee, Hyun-Woo Chung, Gyoyoung Jin, HyeongSun Hong, Yoosang Hwang
  • Patent number: 9158210
    Abstract: At a time of aligning a thin plate-shaped work of which both front and rear surfaces are subjected to work, a deflection caused at a central portion of the thin plate-shaped work is corrected and the thin plate-shaped work is controlled to be parallel state with respect to a photomask.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: October 13, 2015
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventor: Eriko Inoue
  • Patent number: 9152118
    Abstract: A sheet conveying apparatus includes a sheet conveying unit that conveys a sheet including a drive roller, a driven roller, and a rotary encoder provided on a rotational axle of one of the drive roller and the driven roller; a conveying amount measuring unit that measures a conveying amount of the sheet; a first detection unit positioned downstream of the sheet conveying unit, the first detection unit being positioned apart from the drive roller and the driven roller not to overlap with the drive roller and the driven roller in the conveying direction; a second detection unit positioned upstream of the sheet conveying unit; and a conveying distance calculation unit that calculates a conveying distance of the sheet based on the measured result by the conveying amount measuring unit and the detected results detected by the first detection unit and the second detection unit.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: October 6, 2015
    Assignee: RICOH COMPANY, LTD.
    Inventors: Makoto Nakura, Takuro Kamiya, Shingo Takai, Naoto Ueda, Satoshi Ueda, Akira Kobashi, Koichi Kudo
  • Patent number: 9136223
    Abstract: Methods for forming an alignment mark and the resulting mark are disclosed. Embodiments may include forming a first shape having rotational symmetry; forming a second shape; and forming an alignment mark by combining the first shape and one or more of the second shape, wherein the alignment mark has rotational symmetry.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: September 15, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guoxiang Ning, Soon Yoeng Tan, Seok Yan Poh, Paul Ackmann
  • Patent number: 9127934
    Abstract: Embodiments of the invention discloses a space imaging overlay inspection method and an array substrate; the method comprises: forming a thin film having a space imaging overlay mark by photolithography; when the thin film is a transparent thin film, performing a color developing treatment on the space imaging overlay mark on the transparent thin film, so as to make the space imaging overlay mark appear in a non-transparent color; and conducting a space imaging overlay inspection between the transparent thin film and an adjacent thin film by using the space imaging overlay mark appear appearing in the non-transparent color. In the method, by conducting the color developing treatment to the space imaging overlay mark on the transparent thin film and then conducting positioning, the space imaging overlay mark can be positioned quickly and accurately, thus alignment condition between two photolithography procedures can be detected swiftly and effectively.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: September 8, 2015
    Assignee: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xiaohui Jiang, Jian Guo
  • Patent number: 9128388
    Abstract: A method of focus measurement of the embodiment irradiates exposure light from a first direction and projects first and second line-and-space patterns on a substrate. Further, exposure light is irradiated from a second direction and third and fourth line-and-space patterns are projected on the substrate. By measuring a distance between the first and third line-and-space patterns on the substrate, a sum of a dislocated amount caused by dislocation of focus and an overlap dislocation amount between the first and third line-and-space patterns is calculated as a first dislocated amount. Further, by measuring a distance between the second and fourth line-and-space patterns on the substrate, an overlap dislocation amount between the second and fourth line-and-space patterns is calculated as a second dislocation amount. Further, based on the first and second dislocation amounts, the focus dislocation amount is calculated.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: September 8, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Nobuhiro Komine
  • Patent number: 9128385
    Abstract: The embodiments described herein relate to methods, devices, and systems for masking a substrate using a photomasking process. An adaptive photomask configured to generate a photomasking pattern in accordance with dimensions of a surface feature on substrate is described. The adaptive photomask can be used to create customized photomask patterns for individual substrates. Methods and devices described herein can be used in manufacturing processes where similar parts having slight differences due to built-in tolerances are manufactured. Methods and a devices described herein can also be used in manufacture processes involving masking of three-dimensional portions of a part. A photomasking system that includes a translational mechanism for scanning a substrate surface is described.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: September 8, 2015
    Assignee: Apple Inc.
    Inventor: Napthaneal Yuen Tan
  • Patent number: 9086574
    Abstract: A compressed print having one or more compressed images of a symbol is disclosed. The compressed images are formed on an image forming surface under a lenticular sheet. The lenticular sheet has a plurality of lenticules and each of the compressed images has a plurality of image elements formed under a lenticule. Each of the image elements is corresponding to a different portion of the symbol. The lenticules are designed to be so small that the compressed image formed under each of the lenticules is not discernible when a viewer looks at the compressed print at a normal viewing distance. As such, the miniaturized compressed images of the symbol can be used as an identification tag, hidden in the compressed print.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: July 21, 2015
    Assignee: 3DV Co., Ltd.
    Inventor: Kwok Wah Allen Lo
  • Patent number: 9081287
    Abstract: One embodiment relates to a method of measuring overlay errors for a programmable pattern, area-imaging electron beam lithography apparatus. Patterned cells of an overlay measurement target array may be printed in swaths such that they are superposed on patterned cells of a first (base) array. In addition, the overlay array may have controlled-exposure areas distributed within the swaths. The superposed cells of the overlay and base arrays are imaged. The overlay errors are then measured based on distortions between the two arrays in the image data. Alternatively, non-imaging methods, such as using scatterometry, may be used. Another embodiment relates to a method for correcting overlay errors for an electron beam lithography apparatus. Overlay errors for a pattern to be printed are determined based on within-swath exposure conditions. The pattern is then pre-distorted to compensate for the overlay errors. Other embodiments, aspects and features are also disclosed.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: July 14, 2015
    Assignee: KLA-Tencor Corporation
    Inventors: Walter D. Mieher, Allen Carroll
  • Patent number: 9082798
    Abstract: Even in case that a wafer is so greatly deviated that a peripheral portion of the wafer cannot be detected, position determination of the wafer can be performed without inflicting a damage on the wafer. The wafer peripheral portion, which is a target, is detected based on output images from a plurality of imaging units disposed along a peripheral portion shape of the wafer (step S210), and a wafer position deviation correcting step (step S220) or a rough correcting step (step 230) is performed according to the number of the imaging units capable of detecting the wafer peripheral portion. In case that the wafer peripheral portion cannot be detected by all the imaging units, a wafer position adjusting step (step 240) for moving the wafer is performed in a position adjusting direction acquired by a combination of the output images by each imaging unit.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: July 14, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Takehiro Shindo
  • Patent number: 9060429
    Abstract: Provided is a circuit board in which visibility of an alignment mark is improved. In a case of manufacturing a substrate module in which a touch panel (20) and an FPC (50) are electrically connected, an alignment mark in the FPC (50) is formed by an opaque metal film, so that visibility is high. Consequently, when an alignment mark (25) in the touch panel (20) is also formed by an opaque metal film, the visibility of the alignment mark (25) also becomes high. By performing alignment using the alignment marks having high visibility, alignment between the touch panel (20) and the FPC (50) can be performed easily with high precision. As a result, the yield of the substrate module increases and modification of an alignment apparatus used for alignment becomes unnecessary, so that the manufacturing cost of the substrate module can be decreased.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: June 16, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Gen Nagaoka, Yasuhiro Hida, Hiroki Miyazaki
  • Patent number: 9057947
    Abstract: The invention relates to the technical field of an alignment method, and discloses a method for aligning substrate and mask, including: firstly forming at least one set of alignment marks on a mask plate; selecting a certain number of large-size substrates as sample substrates; forming a plurality of sets of alignment marks on each sample substrate using the mask plate and the at least one set of alignment marks formed thereon to divide the sample substrate into a plurality of sub-substrate areas; and then performing mask process on the respective sample substrates, accurate alignment for each sub-substrate area can be realized by means of the plurality of sets of alignment marks on the sample substrate, and one sub-substrate area can be accurately aligned by means of at least two sets of alignment marks formed on the sample substrate.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: June 16, 2015
    Assignees: BOE Technology Group Co., Ltd., Beijing BOE Display Technology Co., Ltd.
    Inventors: Guangming Lu, Chaoqin Xu, Kiyong Kim, Ziqing Zhou, Xiangnan Yun, Liping Luo
  • Patent number: 9046792
    Abstract: A projection exposure tool for microlithography for imaging mask structures of an image-providing substrate onto a substrate to be structured includes a measuring apparatus configured to determine a relative position of measurement structures disposed on a surface of one of the substrates in relation to one another in at least one lateral direction with respect to the substrate surface and to thereby simultaneously measure a number of measurement structures disposed laterally offset in relation to one another.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: June 2, 2015
    Assignee: Carl Zeiss SMT GmbH
    Inventors: Jochen Hetzler, Aksel Goehnermeier
  • Patent number: 9017904
    Abstract: A method of providing a photolithography pattern can be provided by identifying at least one weak feature from among a plurality of features included in a photolithography pattern based on a feature parameter that is compared to a predetermined identification threshold value for the feature parameter. A first region of the weak feature can be classified as a first dosage region and a second region of the weak feature can be classified as a second dosage region. Related methods and apparatus are also disclosed.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: April 28, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Choi, Heung-Suk Oh, Sin-jeung Park, Rae-won Yi
  • Patent number: 8976355
    Abstract: A substrate is loaded onto a substrate support of a lithographic apparatus, after which the apparatus measures locations of substrate alignment marks. These measurements define first correction information allowing the apparatus to apply a pattern at one or more desired locations on the substrate. Additional second correction information is used to enhance accuracy of pattern positioning, in particular to correct higher order distortions of a nominal alignment grid. The second correction information may be based on measurements of locations of alignment marks made when applying a previous pattern to the same substrate. The second correction information may alternatively or in addition be based on measurements made on similar substrates that have been patterned prior to the current substrate.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: March 10, 2015
    Assignee: ASML Netherlands B.V.
    Inventors: Stefan Cornelis Theodorus Van Der Sanden, Richard Johannes Franciscus Van Haren, Hubertus Johannes Gertrudus Simons, Remi Daniel Marie Edart, Xiuhong Wei, Michael Kubis, Irina Lyulina
  • Patent number: 8951698
    Abstract: A method forming a pattern includes a process in which self-assembly material is formed on the substrate where on which a fiducial mark is formed, and the self-assembly material is separated in micro phase to form a self-assembled pattern. The position error from a predetermined formation position of the self-assembled pattern is measured on the basis of the fiducial mark, and a pattern for an alignment as well as a peripheral circuit pattern are formed on the substrate. The formation position of at least one pattern among the pattern for alignment and peripheral circuit pattern is corrected using the position error.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: February 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Rikiya Taniguchi, Hideaki Sakurai, Shinichi Ito
  • Patent number: 8945800
    Abstract: In a multiple patterning techniques, where two or more exposures are used to form a single layer of a device, the splitting of features in a single layer between the multiple exposures is carried out additionally with reference to features of another associated layer and the splitting of that layer into two or more sets of features for separate exposure. The multiple exposure process can be a process involving repeated litho-etch steps desirably, the alignment scheme utilized during exposure of the split layers is optimized with reference to the splitting approach.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: February 3, 2015
    Assignee: ASML Netherlands B.V.
    Inventors: Tsann-Bim Chiou, Mircea Dusa, Alek Chi-Heng Chen
  • Patent number: 8921017
    Abstract: The present invention relates to a multilayer substrate containing a substrate and a multilayer film provided on the substrate, in which a concave or convex fiducial mark that indicates a fiducial position of the multilayer substrate is formed on the surface of the multilayer film on the opposite side to the side of the substrate; and a material of at least a part of the surface of the fiducial mark is different from a material of a most superficial layer of the multilayer film on the opposite side to the side of the substrate.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: December 30, 2014
    Assignee: Asahi Glass Company, Limited
    Inventors: Yuzo Okamura, Yoshiaki Ikuta
  • Patent number: 8916316
    Abstract: The present invention relates to a reflective mask blank containing in this order, a substrate, a multilayer reflective film that reflects exposure light, and an absorber layer that absorbs the exposure light, in which the reflective mask blank further contains a fiducial mark indicating a reference position of the multilayer reflective film, which is formed in a concave shape or in a convex shape on a surface of the multilayer reflective film or on a surface of one layer formed between the multilayer reflective film and the absorber layer, and the fiducial mark is formed so as to have a reflectivity different from an area surrounding the fiducial mark with respect to a light with a prescribed wavelength and is transferred to a layer formed on the fiducial mark.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: December 23, 2014
    Assignee: Asahi Glass Company, Limited
    Inventors: Yuzo Okamura, Yoshiaki Ikuta
  • Patent number: 8906584
    Abstract: A semiconductor device includes a cell mask pattern disposed in a cell region of a mask substrate and a vernier mask pattern disposed in a vernier region of the mask substrate. The vernier mask pattern includes a variable mask pattern portion to transfer a different shape of pattern depending on the magnitude of exposure energy.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: December 9, 2014
    Assignee: SK Hynix Inc.
    Inventors: Byoung Hoon Lee, Chang Moon Lim, Myoung Soo Kim, Jeong Su Park, Jun Taek Park, In Hwan Lee
  • Patent number: 8883380
    Abstract: On a film where an exposure material coating has been formed in a exposure pattern formation region on a film base material, a colored firing material, colored light-curable material, or colored ink is applied to at least one of two widthwise side edges to form a side part application coating, which is irradiated with laser light by an alignment mark formation unit to form an alignment mark. The alignment mark is then used to detect film meandering and adjust the positions of masks. This makes it easy to form the alignment mark and detect the alignment mark thus formed and makes it possible to accurately correct for meandering of a film and stably expose the film in the process of continuous exposure of a film where an exposure material coating has been formed in a exposure pattern formation region on a film base material.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: November 11, 2014
    Assignee: V Technology Co., Ltd.
    Inventors: Toshinari Arai, Kazushige Hashimoto
  • Patent number: 8859167
    Abstract: According to one embodiment, a positional deviation measuring method includes measuring a positional deviation of a device pattern formed in a lower layer portion using an alignment mark of the lower layer portion as a reference; measuring a positional deviation of a device pattern formed in an upper layer portion above the lower layer portion using an alignment mark of the upper layer portion as a reference; measuring a positional deviation between the alignment mark of the lower layer portion and the alignment mark of the upper layer portion; and calculating a positional deviation between the device patterns based on the positional deviation between the alignment marks.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: October 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshinori Hagio, Yosuke Okamoto
  • Patent number: 8828632
    Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary method includes receiving an integrated circuit (IC) layout design including a target pattern on a grid. The method further includes receiving a multiple-grid structure. The multiple-grid structure includes a number of exposure grid segments offset one from the other by an offset amount in a first direction. The method further includes performing a multiple-grid exposure to expose the target pattern on a substrate and thereby form a circuit feature pattern on the substrate. Performing the multiple-grid exposure includes scanning the substrate with the multiple-grid structure in a second direction such that a sub-pixel shift of the exposed target pattern occurs in the first direction, and using a delta time (?t) such that a sub-pixel shift of the exposed target pattern occurs in the second direction.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: September 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Chuan Wang, Shy-Jay Lin, Pei-Yi Liu, Jaw-Jung Shin, Burn Jeng Lin
  • Patent number: 8803542
    Abstract: A method for verifying stitching accuracy of a stitched chip on a wafer is disclosed. Initially, a set of test structures are inserted within a reticle layout. An exposure program is executed to control a photolithography equipment having a stepper to perform multiple exposures of the reticle on a wafer to generate a stitched chip on the wafer. Electrical measurements are then performed on the test structures at actual stitch boundaries of the stitched chip to evaluate stitching accuracy of the stitched chip.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: August 12, 2014
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Thomas J. McIntyre, Charles N. Alcorn, Matthew A. Gregory
  • Patent number: 8796645
    Abstract: An exposure apparatus for a photoalignment process includes; a first photomask including a plurality of transmission parts; and a second photomask including a plurality of transmission parts, where the first photomask and the second photomask partially overlap each other such that each of the first photomask and the second photomask includes an overlapping region and a non-overlapping region, the overlapping region of at least one of the first photomask and the overlapping region of the second photomask includes at least two subregions, and shapes or arrangements of the transmission parts in the at least two subregions are different from each other.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: August 5, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Soo-Ryun Cho, Jun Woo Lee, Kyoung Tae Kim, Joo Seok Yeom, Suk Hoon Kang, Eun Ju Kim
  • Patent number: 8790851
    Abstract: A photo mask for exposing according to an embodiment includes a mark pattern arranged in a mark region that is different from an effective region to form a semiconductor device; and a regular pattern arranged in the mark region and around the mark pattern and smaller than the mark pattern in size and pitch.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: July 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yosuke Okamoto, Kazutaka Ishigo, Taketo Kuriyama
  • Patent number: 8765495
    Abstract: A method of forming a pattern of doped region includes the following steps. At first, a device layout pattern including a gate layout pattern and a doped region layout pattern is provided to a computer system. Subsequently, the device layout pattern is split into a plurality of sub regions, and the sub regions have different pattern densities of the gate layout pattern. Then, at least an optical proximity correction (OPC) calculation is respectively performed on the doped region layout pattern in each of the sub regions to respectively form a corrected sub doped region layout pattern in each of the sub regions. Afterwards, the corrected sub doped region layout patterns are combined to form a corrected doped region layout pattern, and the corrected doped region layout pattern is outputted onto a mask through the computer system.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: July 1, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Yi-Hsiu Lee, Guo-Xin Hu, Qiao-Yuan Liu, Yen-Sheng Wang
  • Patent number: 8758964
    Abstract: Disclosed is an LCD panel photolithography process, employed in a lithography system for manufacturing a plurality of LCD panel, comprising steps of: performing photolithography to a glass substrate with a first mask, and the first mask comprises a plurality of sets of alignment marks corresponding to a plurality of following masks thereafter, and a plurality of sets of alignment marks corresponding to the plurality of following masks thereafter are formed on the glass substrate; and employing the plurality of sets of alignment marks on the glass substrate respectively, to perform alignment procedure and photolithography for the plurality of following masks with the plurality of sets of alignment marks on the glass substrate to form patterns; wherein corresponding to the same LCD panel area, the plurality of sets of alignment marks on the glass substrate have different position coordinates respectively.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: June 24, 2014
    Assignee: Shenzhen China Star Optoelectronics Technology Co. Ltd.
    Inventor: Cai-li Zhang
  • Patent number: 8748065
    Abstract: Reflection type blank masks are provided. The blank mask includes a substrate, a reflection layer substantially on the substrate, at least one fiducial mark substantially on the reflection layer, an absorption layer substantially on the at least one fiducial mark and the reflection layer, and a resist layer substantially on the absorption layer.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: June 10, 2014
    Assignee: SK Hynix Inc.
    Inventors: Yong Dae Kim, Byung Ho Nam
  • Patent number: 8741506
    Abstract: The present invention provides a mask and a repairing method therefor. A reference area is selected in a configuration pattern of a mask template, the reference area is corresponding to a to-be-shaded area of a mask; a repair area is formed on a drillable member according to the reference area; a hollow area is formed in the repair area of the drillable member, the hollow area is corresponding to the to-be-shaded area; the drillable member is attached to the mask, the hollow area is corresponding to the to-be-shaded area; and shading material is coated on the drillable member, so as to form a shaded layer on the to-be-shaded layer.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: June 3, 2014
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Jiaxing Ma
  • Patent number: 8735051
    Abstract: Exposure apparatus is equipped with an illumination optical device which illuminates a mask with an exposure beam, a mask table which holds a periphery of a pattern area of the mask from above so that a pattern surface of the mask becomes substantially parallel to an XY plane and makes a force at least parallel to an XY plane and on the mask, and a wafer stage which moves along the XY plane, holding a wafer substantially parallel to the XY plane. Therefore, an overlay with high precision of a pattern of a mask and an underlying pattern on the substrate can be realized, even though the exposure apparatus employs a proximity method, that is, the exposure apparatus does not use a projection optical system.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: May 27, 2014
    Assignee: Nikon Corporation
    Inventor: Yuichi Shibazaki
  • Patent number: 8728713
    Abstract: A method for producing a measurement structure for measuring alignment of patterns formed in one or more layers of patternable material uses multiple exposure tools having different resolution limits and maximum expose field sizes. The measurement structure includes multiple complementary and coincident parts. An abutting field pattern is exposed and stitched in a layer of patternable material using a first exposure tool and a first mask. The abutting field pattern includes a first portion of the multiple complementary parts. A periphery pattern is exposed in the same layer or in a different layer of patternable material using a second exposure tool and a second mask. The periphery pattern includes a second portion of the multiple complementary parts. A maximum expose field of the first exposure tool is smaller than the maximum expose field of the second exposure tool.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: May 20, 2014
    Assignee: Truesense Imaging, Inc.
    Inventors: Robert P. Fabinski, Eric J. Meisenzahl, James E. Doran
  • Patent number: 8717544
    Abstract: In the present invention, a number of times the brightness changes detected at the same position while a substrate conveys are added up in the conveying direction, thereby obtaining a plurality of edge count data, and then, a plurality of positions of long sides of patterns parallel to the conveying direction is identified based on the plurality of edge count data exceeding a predetermined threshold value, middle point positions of a plurality of proximity pairs are calculated, and a middle point position close to the target position preset in the imaging device is selected from the plurality of middle point positions of the proximity pairs, an amount of position displacement between the selected middle point position and the target position of imaging device is calculated, and the photomask in the direction substantially perpendicular to the conveying direction so that the amount of position displacement is a predetermined value.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: May 6, 2014
    Assignee: V Technology Co., Ltd.
    Inventor: Takamitsu Iwamoto
  • Patent number: 8709687
    Abstract: A pattern from a patterning device is applied to a substrate by a lithographic apparatus. The applied pattern includes product features and metrology targets. The metrology targets include large targets and small targets which are for measuring overlay. Some of the smaller targets are distributed at locations between the larger targets, while other small targets are placed at the same locations as a large target. By comparing values measured using a small target and large target at the same location, parameter values measured using all the small targets can be corrected for better accuracy. The large targets can be located primarily within scribe lanes while the small targets are distributed within product areas.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: April 29, 2014
    Assignee: ASML Netherlands B.V.
    Inventors: Maurits Van Der Schaar, Patrick Warnaar, Kaustuve Bhattacharyya, Hendrik Jan Hidde Smilde, Michael Kubis
  • Patent number: 8703368
    Abstract: A process for use in lithography, such as photolithography for patterning a semiconductor wafer, is disclosed. The process includes receiving an incoming semiconductor wafer having various features and layers formed thereon. A unit-induced overlay (uniiOVL) correction is received and a deformation measurement is performed on the incoming semiconductor wafer in an overlay module. A deformation-induced overlay (defiOVL) correction is generated from the deformation measurement results by employing a predetermined algorithm on the deformation measurement results. The defiOVL and uniiOVL corrections are fed-forward to an exposure module and an exposure process is performed on the incoming semiconductor wafer.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: April 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Yao Lee, Ying Ying Wang, Heng-Hsin Liu, Chin-Hsiang Lin
  • Patent number: 8703405
    Abstract: In a method of generating a three-dimensional process window qualification, a photoresist layer is coated on a substrate including an underlying structure. A plurality of circular-shaped regions of the substrate are distinguished into 1 to n regions to partition the substrate into a center portion and an edge portion, n being a natural number greater than 2. 1 to n exposing ranges are set, including a common exposing condition for the 1 to n regions. A photoresist pattern is fox led by exposing each shot portion in the 1 to n regions using a split exposing condition in the 1 to n exposing ranges. The photoresist pattern is detected, and a normal photoresist pattern with respect to each of the 1 to n regions is selected to generate the three-dimensional process window qualification.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: April 22, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Hoon Sohn, Sang-Kil Lee, Yu-Sin Yang
  • Patent number: 8685633
    Abstract: A method of printing an image on a wafer. The method includes the steps of printing a main image, wherein the main image includes fields which are fully on the wafer, and printing an alternate image, wherein the alternate image includes fields which are only partially on the wafer. The alternate image could be placed on a separate mask which is loaded onto the exposure tool after the mask with the main image has completed printing. Alternatively, it could be an extra image specially inserted on the mask with the main image for that layer.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: April 1, 2014
    Assignee: LSI Corporation
    Inventors: Duane B. Barber, David J. Sturtevant
  • Publication number: 20140072904
    Abstract: There is provided a photomask capable of improving alignment accuracy with respective photomasks disposed on the front and rear faces of a substrate. A photomask has a drawing pattern for exposure formed on one face opposing a substrate, a first alignment mark for alignment with a substrate side mark formed on the substrate, the first alignment mark being provided in a region of the one face, the region opposing the substrate when the substrate is retained and the drawing pattern is not formed in the region, and a second alignment mark for alignment with a third alignment mark provided on another photomask, the second alignment mark being provided in a region which does not oppose the substrate when the substrate is retained.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 13, 2014
    Applicant: NIPPON MEKTRON, LTD.
    Inventors: Shoji TAKANO, Fumihiko MATSUDA, Yoshihiko NARISAWA
  • Patent number: 8663877
    Abstract: Lithography masks, lithography systems, methods of manufacturing lithography masks, methods of altering material layers of semiconductor devices, and methods of manufacturing semiconductor devices are disclosed. In one embodiment, a lithography mask includes a first pattern for at least one material layer of at least one die, the first pattern being oriented in a first position. The lithography mask includes a second pattern for at least one material layer of the at least one die, the second pattern being oriented in a second position. The second position is different than the first position.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: March 4, 2014
    Assignee: Infineon Technologies AG
    Inventor: Uwe Paul Schroeder
  • Patent number: 8625096
    Abstract: A semiconductor wafer is aligned using a double patterning process. A first resist layer having a first optical characteristic is deposited and foams at least one alignment mark. The first resist layer is developed. A second resist layer having a second optical characteristic is deposited over the first resist layer. The combination of first and second resist layers and alignment mark has a characteristic such that radiation of a pre-determined wavelength incident on the alignment mark produces a first or higher order diffraction as a function of the first and second optical characteristics.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: January 7, 2014
    Assignees: ASML Holding N.V., ASML Netherlands B.V.
    Inventors: Harry Sewell, Mircea Dusa, Richard Johannes Franciscus Van Haren, Manfred Gawein Tenner, Maya Angelova Doytcheva
  • Patent number: 8625109
    Abstract: An apparatus and a method for determining an overlap distance of an optical head is disclosed. Positions and light amount distributions of each light spot can be measured, which may be provided from an optical head to a substrate. Gaussian distribution may be applied to the positions and the light amount distributions to calculate a compensation model of each of the light spots. A first accumulated light amount corresponding to each first area of the substrate may be calculated if the optical head is scanning along a first direction of the substrate using the compensation model. A second accumulated light amount corresponding to each second area overlapped with the each first area is calculated if the optical head is scanning along the first direction, which is moved in a second direction by a first distance using the compensation model. An overlap distance may be determined based on a uniformity of summations of the first and second accumulated light amount.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: January 7, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sang-Hyun Yun, Hi-Kuk Lee, Sang-Woo Bae, Cha-Dong Kim, Jung-In Park
  • Patent number: 8617774
    Abstract: A method for calibrating an apparatus for the position measurement of measurement structures on a lithography mask comprises the following steps: qualifying a calibration mask comprising diffractive structures arranged thereon by determining positions of the diffractive structures with respect to one another by means of interferometric measurement, determining positions of measurement structures arranged on the calibration mask with respect to one another by means of the apparatus, and calibrating the apparatus by means of the positions determined for the measurement structures and also the positions determined for the diffractive structures.
    Type: Grant
    Filed: April 10, 2010
    Date of Patent: December 31, 2013
    Assignee: Carl Zeiss SMS GmbH
    Inventors: Norbert Kerwien, Jochen Hetzler
  • Patent number: 8610944
    Abstract: A method of achieving process-direction sub-raster magnification adjustment using non-redundant overwriting. The raster imager provides overwriting while the image path provides non-redundant data for each pass according to the desired magnification adjustment. The same laser power level can be used for the multiple writes, or optionally, it may be varied to further improve spatial resolution of the adjustment.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: December 17, 2013
    Assignee: Xerox Corporation
    Inventors: Beilei Xu, Robert P. Loce, Jess R. Gentner
  • Patent number: 8609301
    Abstract: A circular cylinder-shaped mask is used to form an image of a pattern on a substrate via a projection optical system. The mask has a pattern formation surface on which the pattern is formed and that is placed around a predetermined axis, and the mask is able to rotate, with the predetermined axis taken as an axis of rotation, in synchronization with a movement of the substrate in at least a predetermined one-dimensional direction. When a diameter of the mask on the pattern formation surface is taken as D, and a maximum length of the substrate in the one-dimensional direction is taken as L, and a projection ratio of the projection optical system is taken as ?, and circumference ratio is taken as ?, then the conditions for D?(?×L)/? are satisfied.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: December 17, 2013
    Assignee: Nikon Corporation
    Inventor: Yuichi Shibazaki
  • Patent number: 8592111
    Abstract: Disclosed is an LCD panel photolithography process, employed in a lithography system for manufacturing a plurality of LCD panel, comprising steps of: performing photolithography to a glass substrate with a first mask, and the first mask comprises a plurality of sets of alignment marks corresponding to a plurality of following masks thereafter, and a plurality of sets of alignment marks corresponding to the plurality of following masks thereafter are formed on the glass substrate; and employing the plurality of sets of alignment marks on the glass substrate respectively, to perform alignment procedure and photolithography for the plurality of following masks with the plurality of sets of alignment marks on the glass substrate to form patterns; wherein corresponding to the same LCD panel area, the plurality of sets of alignment marks on the glass substrate have different position coordinates respectively.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: November 26, 2013
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Cai Ii Zhang
  • Patent number: 8592107
    Abstract: Provided is an apparatus that includes an overlay mark. The overlay mark includes a first portion that includes a plurality of first features. Each of the first features have a first dimension measured in a first direction and a second dimension measured in a second direction that is approximately perpendicular to the first direction. The second dimension is greater than the first dimension. The overlay mark also includes a second portion that includes a plurality of second features. Each of the second features have a third dimension measured in the first direction and a fourth dimension measured in the second direction. The fourth dimension is less than the third dimension. At least one of the second features is partially surrounded by the plurality of first features in both the first and second directions.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: November 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Guo-Tsai Huang, Fu-Jye Liang, Li-Jui Chen, Chih-Ming Ke
  • Patent number: 8592110
    Abstract: A plurality of reticles for printing structures in the same lithography level includes an alignment structure pattern within a same relative location in each reticle. Each set of process segmentations in a grating has a reticle segmentation pitch, which is common across all gratings in the plurality of reticles. Within each pair of alignment structure patterns that occupy the same relative location in any two of the plurality of reticles, the process segmentations in one reticle are shifted relative to the process segmentations in the other reticle by a fraction of a reticle segmentation pitch. After printing all patterns in the plurality of reticles, a composite printed process segmentation structure on the substrate includes printed segmentation structures that are spaced by 1/n times the printed segmentation pitch. The pattern for the next level can be aligned to the composite printed process segmentation structure in a single alignment operation.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: November 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Allen H. Gabor, Vinayan C. Menon
  • Patent number: 8587782
    Abstract: An optical-component fabricating method includes arranging a mask that has both an optical component pattern and an alignment mark pattern and a wafer that is developed through the mask at predetermined positions; exposing the optical component pattern and the alignment mark pattern onto the wafer; developing the alignment mark pattern that is exposed on the wafer; observing a position of the developed alignment mark pattern and moving the wafer in accordance with the position; repeating the exposing, the developing, and the moving a predetermined number of times; developing all the optical component patterns on the wafer; and etching the developed optical component patterns.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: November 19, 2013
    Assignee: Fujitsu Limited
    Inventor: Satoshi Kai
  • Patent number: 8585915
    Abstract: A method of fabricating semiconductor structures comprising sub-resolution alignment marks is disclosed. The method comprises forming a dielectric material on a substrate and forming at least one sub-resolution alignment mark extending partially into the dielectric material. At least one opening is formed in the dielectric material. Semiconductor structures comprising the sub-resolution alignment marks are also disclosed.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: November 19, 2013
    Assignee: Micron Technology, Inc.
    Inventors: David S. Pratt, Marc A. Sulfridge
  • Patent number: 8563202
    Abstract: A method for stitching a first field mask to a second field mask on a wafer includes providing a photomask with a first set of targets and a second set of targets, printing images of the first set of targets and the second set of targets onto the wafer where the photomask is applied to the wafer having no previous alignment marks formed thereon for the photomask to align to. A first set of alignment marks is formed from the first set of targets and a second set of alignment marks is formed from the second set of targets. The method includes aligning a first field mask to the first set of alignment marks and aligning a second field mask to the second set of alignment marks. The images of the first field mask and the second field mask are thereby stitched together on the wafer.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: October 22, 2013
    Assignee: Micrel, Inc.
    Inventor: Arthur Lam