Including Control Feature Responsive To A Test Or Measurement Patents (Class 430/30)
  • Patent number: 9760017
    Abstract: According to one embodiment, wafer lithography equipment includes an exposure unit transferring a circuit pattern onto a wafer, a measurement unit measuring a dimension of the circuit pattern and a calculator. The calculator includes calculating a first difference. The first difference is the difference between a first dimension and a second dimension. The first dimension is obtained by substituting a first exposure amount and a first focus distance into an approximate response surface function. The second dimension is measured by the measurement unit. The calculator also includes calculating a second difference. The second difference is the sum total of the first difference for all of the circuit patterns. The calculator also includes calculating a second exposure amount and a second focus distance causing the difference between the approximate response surface function and the second difference to be a minimum. The calculator also includes calculating a correction exposure amount.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: September 12, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazufumi Shiozawa, Toshihide Kawachi, Masamichi Kishimoto, Nobuhiro Komine, Yoshimitsu Kato
  • Patent number: 9748110
    Abstract: Provided is a method for increasing pattern density of a structure on a substrate using an integration scheme, the method comprising: providing a substrate having a first spacer pattern and an underlying layer, the underlying layer comprising a first underlying layer, a second underlying layer, and a target layer; performing a conformal spacer deposition using an oxide, the deposition creating a conformal layer; performing a spacer RIE process and a pull process, thereby generating a second spacer pattern, the spacer RIE process includes adsorption of N-containing gas on a surface of the substrate which activates the surface to react with an F- and/or an H-containing gas to form fluorosilicates; and wherein the integration targets include selectively etching spacer films within a target spacer etch rate, enhanced simultaneous selectivity to the first underlying layer and the second underlying layer and preventing pattern damage.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: August 29, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Subhadeep Kal, Angelique D. Raley, Nihar Mohanty, Aelan Mosden
  • Patent number: 9740814
    Abstract: A method, system, and computer program product for triple patterning technology (TPT) violation detection and visualization within an integrated circuit design layout are disclosed. In a first aspect, the method comprises mapping a plurality of violations of the integrated circuit design layout to a graph, generating a color graph corresponding to the graph, detecting at least one TPT violation from the color graph; and visualizing the at least one TPT violation on a layout canvas. In a second aspect, the system comprises a graph generator module for mapping a plurality of violations of the integrated circuit design layout to a graph and to generate a color graph corresponding to the graph, a detector module for detecting at least one TPT violation from the color graph, and a visualizer module for visualizing the at least one TPT violation on a layout canvas.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: August 22, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventor: Sanjib Ghosh
  • Patent number: 9709510
    Abstract: Methods and systems for determining a configuration for an optical element positioned in a collection aperture during wafer inspection are provided. One system includes a detector configured to detect light from a wafer that passes through an optical element, which includes a set of collection apertures, when the optical element has different configurations thereby generating different images for the different configurations. The system also includes a computer subsystem configured for constructing additional image(s) from two or more of the different images, and the two or more different images used to generate any one of the additional image(s) do not include only different images generated for single collection apertures in the set. The computer subsystem is further configured for selecting one of the different or additional configurations for the optical element based on the different images and the additional image(s).
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: July 18, 2017
    Assignee: KLA-Tencor Corp.
    Inventors: Pavel Kolchin, Mikhail Haurylau, Junwei Wei, Dan Kapp, Robert Danen, Grace Chen
  • Patent number: 9710903
    Abstract: Various systems and methods for detecting design and process defects on a wafer, reviewing defects on a wafer, selecting one or more features within a design for use as process monitoring features, or some combination thereof are provided. One system is configured to detect design defects and process defects at locations on a wafer at which images are acquired by an electron beam review subsystem based on defects in a design, additional defects in the design, which are detected by comparing an image of a die in the design printed on the wafer acquired by the electron beam review subsystem to an image of the die stored in a database, and defects detected on the wafer by a wafer inspection system.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: July 18, 2017
    Assignee: KLA-Tencor Corp.
    Inventors: Christophe Fouquet, Zain Saidin, Sergio Edelstein, Savitha Nanjangud, Carl Hess
  • Patent number: 9690898
    Abstract: Candidate layout patterns can be generated using a generative model trained based on known data, such as historical hot spot data, features extraction, and geometrical primitives. The generative model can be sampled to obtain candidate layouts that can be ranked and repaired using error optimization, design rule checking, optical proximity checking, and other methods to ensure that resulting candidates are manufacturable.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: June 27, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ioana C. Graur, Ian P. Stobert, Dmitry A. Vengertsev
  • Patent number: 9685378
    Abstract: Disclosed herein is a method of dividing rectangular plate-shaped workpieces into individual device chips including a detecting step wherein an annular frame to which a plurality of rectangular plate-shaped workpieces are stuck is held on a chuck table and the positions and angles of the projected dicing lines on each of the plate-shaped workpieces are detected, and a dividing step wherein a laser beam having a wavelength which is absorbable by the plate-shaped workpieces is applied from a laser beam applying unit to the plate-shaped workpieces while the chuck table and the laser beam applying unit are being relatively processing-fed and finely adjusted for each of the plate-shaped workpieces on the basis of the positions and angles detected in the detecting step, thereby dividing the plate-shaped workpieces into a plurality of device chips along the projected dicing lines.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: June 20, 2017
    Assignee: Disco Corporation
    Inventors: Toshiyuki Yoshikawa, Takashi Sampei
  • Patent number: 9678442
    Abstract: An analysis system that includes a processor and an memory module; wherein the memory module is arranged to store aerial images of an area of a mask, each aerial image corresponds to focus value out of a set of different focus values; wherein the processor is arranged to find weak points by processing the aerial images using different printability thresholds; and wherein the processor is arranged to determine focus and exposure values for generating a Process Window Qualification (PWQ) wafer to be manufactured using the mask in response to focus and exposure values associated with the weak points.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: June 13, 2017
    Assignee: APPLIED MATERIALS ISRAEL LTD.
    Inventors: Aviram Tam, Lei Zhong
  • Patent number: 9651872
    Abstract: A projection lens for imaging a pattern arranged in an object plane of the projection lens into an image plane of the projection lens via electromagnetic radiation having an operating wavelength ?<260 nm has a multiplicity of optical elements having optical surfaces which are arranged in a projection beam path between the object plane and the image plane. Provision is made of a wavefront manipulation system for dynamically influencing the wavefront of the projection radiation passing from the object plane to the image plane.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: May 16, 2017
    Assignee: Carl Zeiss SMT GmbH
    Inventor: Heiko Feldmann
  • Patent number: 9625692
    Abstract: Disclosed is a projection optical system including a first optical system configured to form a first image conjugate to an object and have an optical axis and a second optical system configured to project a second image conjugate to the first image onto a surface to be projected on, wherein the first image satisfies a condition of: Im×Tr?1.70 wherein Im denotes a length of the first image in a direction of an optical axis of the first optical system, normalized by a focal length of the first optical system, and Tr denotes a throw ratio for the projection optical system.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: April 18, 2017
    Assignee: Ricoh Company, Ltd.
    Inventors: Tatsuya Takahashi, Kazuhiro Fujita, Issei Abe
  • Patent number: 9607808
    Abstract: A method of electron-beam lithography by direct writing solves the reliability of design of etched components through rounding of the corners of contiguous patterns, notably in patterns to be etched of critical dimension of the order of 35 nm. The method determines critical patterns, and correction patterns by subtracting patterns of corrections of dimensions and of locations as a function of rounding of external or internal corners to be corrected and etching of the corrected design. The corrections may be by a correction model taking account of the parameters of the critical patterns. A correction of the proximity effects specific to these methods is also performed, by resizing of edges of blocks to be etched in combination optimized by the energy latitude with a modulation of the radiated doses. A rescaling and negation functions and eRIF functions may be used to optimize the parameters and the realization of the extrusion.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: March 28, 2017
    Assignee: Commissariat A L'Energie Atomique ET AUX Energies Alternatives
    Inventor: Serdar Manakli
  • Patent number: 9606452
    Abstract: A lithography metrology method is provided. Focus sensitivity data and dose sensitivity data of sample patterns to be formed on a substrate are acquired. At least one focus pattern selected in descending order of focus sensitivity from among the acquired focus sensitivity data of the sample patterns is determined. At least one low-sensitivity focus pattern in ascending order of the focus sensitivity from among the acquired dose sensitivity data of the sample patterns is selected, and at least one dose pattern selected in descending order of dose sensitivity from among the at least one low-sensitivity focus pattern is determined. A split substrate having a plurality of chip regions is prepared. A plurality of focus split patterns having a shape corresponding to the at least one focus pattern and a plurality of dose split patterns having a shape corresponding to the at least one dose pattern in the plurality of chip regions are formed.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: March 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Je Jung, Yong-Jin Chun, Byoung-Il Choi
  • Patent number: 9594311
    Abstract: The present invention makes the use of measurement of a diffraction spectrum in or near an image plane in order to determine a property of an exposed substrate. In particular, the positive and negative first diffraction orders are separated or diverged, detected and their intensity measured. The intensity of each of the first diffraction orders from the diffraction spectrum are compared to determine overlay (or other properties) of exposed layers on the substrate.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: March 14, 2017
    Assignee: ASML Netherlands B.V.
    Inventors: Marcus Adrianus Van De Kerkhof, Maurits Van Der Schaar, Andreas Fuchs, Martyn John Coogans
  • Patent number: 9594310
    Abstract: The present invention makes the use of measurement of a diffraction spectrum in or near an image plane in order to determine a property of an exposed substrate. In particular, the positive and negative first diffraction orders are separated or diverged, detected and their intensity measured. The intensity of each of the first diffraction orders from the diffraction spectrum are compared to determine overlay (or other properties) of exposed layers on the substrate.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: March 14, 2017
    Assignee: ASML Netherlands B.V.
    Inventors: Marcus Adrianus Van De Kerkhof, Maurits Van Der Schaar, Andreas Fuchs, Martyn John Coogans
  • Patent number: 9594866
    Abstract: A method includes receiving layout data representing a plurality of patterns. The layout data includes a plurality of layers and spaces identified between adjacent patterns. In at least one layer of the plurality of layers, the adjacent patterns violate a G0-rule. The method further includes determining whether each identified space is a critical G0-space. The identified space is determined to be a critical G0-space if a portion of at least one adjacent pattern that is removed merges two adjacent odd-loops of G0-spaces into a single even loop or G0 spaces or alternatively, if a portion of an adjacent pattern that is removed converts one odd-loop of G0-spaces to a non-loop of G0-spaces. The method further includes receiving a modification of at least one adjacent pattern and updating a spacing of a layer that is adjacent to the layers within the adjacent pattern that violate the G0-rule.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: March 14, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Dio Wang, Ken-Hsien Hsieh, Huang-Yu Chen, Li-Chun Tien, Ru-Gun Liu, Lee-Chung Lu
  • Patent number: 9588439
    Abstract: Embodiments of the present invention describe methods of selecting a subset of test patterns from an initial larger set of test patterns for calibrating a computational lithography model. An example method comprises: generating an information matrix for the initial larger set of test patterns, wherein the terms of the information matrix comprise one or more identified model parameters that represent a lithographic process response; and, executing a selection algorithm using terms of the information matrix to select the subset of test patterns that effectively determines values of the identified model parameters that contribute significantly in the lithographic process response, wherein the subset of test patterns characteristically represents the initial larger set of test patterns. The selection algorithm explores coverage relationships existing in the initial larger set of test patterns.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: March 7, 2017
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Antoine Jean Bruguier, Yu Cao, Jun Ye, Wenjin Shao
  • Patent number: 9551071
    Abstract: A substrate support device includes a plate portion including a heater plate that includes a heating element provided in the heater plate, and also including a first cooling plate provided on a bottom surface of the heater plate and having a first flow path, and a second cooling plate provided on a top surface of the heater plate and having a second flow path; and a shaft portion supporting the plate portion and including a line connected to the heating element to supply an electric current to the heating element, and a tube supplying a coolant to the first cooling plate and the second cooling plate, the line and the tube being provided inside the shaft portion.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: January 24, 2017
    Assignee: NHK SPRING CO., LTD.
    Inventors: Toshihiko Hanamachi, Daisuke Hashimoto, Yasuaki Ishioka
  • Patent number: 9543204
    Abstract: In order to provide a semiconductor device that includes a conductive layer on one surface of a semiconductor substrate with an insulating layer therebetween, a bump on the other surface of the semiconductor substrate, and a through-electrode through the semiconductor substrate connecting the conductive layer with the bump, a through-hole is formed from the other surface of the semiconductor substrate to be connected to the conductive layer, a seed metal film is formed on the through-hole and the other surface, a photoresist is formed thereon, a mask layer is formed by processing the photoresist with a pattern larger than the through-hole, a plated film is grown by electrolytic plating so as to integrally form the through-electrode and a part of the bump.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: January 10, 2017
    Assignee: Longitude Semicondutor S.A.R.L.
    Inventors: Yoshihiro Saeki, Nobuaki Hoshi
  • Patent number: 9535342
    Abstract: Methods are disclosed for measuring target structures formed by a lithographic process on a substrate. A grating or other structure within the target is smaller than an illumination spot and field of view of a measurement optical system. The position of an image of the component structure varies between measurements, and a first type of correction is applied to reduce the influence on the measured intensities, caused by differences in the optical path to and from different positions. A plurality of structures may be imaged simultaneously within the field of view of the optical system, and each corrected for its respective position. The measurements may comprise first and second images of the same target under different modes of illumination and/or imaging, for example in a dark field metrology application.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: January 3, 2017
    Assignee: ASML Netherlands B.V.
    Inventors: Hendrik Jan Hidde Smilde, Patrick Warnaar
  • Patent number: 9529959
    Abstract: The present disclosure provides a method for pattern correction for electron-beam (e-beam) lithography. In accordance with some embodiments, the method includes splitting a plurality of patterns into a plurality of pattern types; performing model fittings to determine a plurality of models for the plurality of pattern types respectively; and performing a pattern correction to an integrated circuit (IC) layout using the plurality of models.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: December 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chun Wang, Hsu-Ting Huang, Wen-Chun Huang, Ru-Gun Liu
  • Patent number: 9519227
    Abstract: Methods for measuring photosensitizer concentrations in a photo-sensitized chemically-amplified resist (PS-CAR) patterning process are described. Measured photosensitizer concentrations can be used in feedback and feedforward control of the patterning process and subsequent processing steps. Also described is a metrology target formed using PS-CAR resist, and a substrate including a plurality of such metrology targets to facilitate patterning process control.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: December 13, 2016
    Assignee: Tokyo Electron Limited
    Inventors: Michael A. Carcasi, Mark H. Somervell, Joshua S. Hooge, Benjamen M. Rathsack, Seiji Nagahara
  • Patent number: 9513109
    Abstract: A lithographic mask has a substrate substantially transmissive for radiation of a certain wavelength, the substrate having a radiation absorbing material in an arrangement, the arrangement configured to apply a pattern to a cross-section of a radiation beam of the certain wavelength, wherein the absorbing material has a thickness which is substantially equal to the certain wavelength divided by a refractive index of the absorbing material.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: December 6, 2016
    Assignee: ASML NETHERLANDS B.V.
    Inventor: Jozef Maria Finders
  • Patent number: 9502211
    Abstract: Methods and systems are provided for a scanning microscope to rapidly form a partial digital image of an area. The method includes performing an initial scan for the area and using initial scan to identify regions representing features of interest in the area. Then, the method performs additional adaptive scans of the regions representing structures of interest. Such scans adapt the path of the scanning beam to follow the edges of a feature of interest by performing localized scan patterns that intersect the feature edge, and directing the localized scan patterns to follow the feature edge.
    Type: Grant
    Filed: May 3, 2015
    Date of Patent: November 22, 2016
    Assignee: FEI COMPANY
    Inventors: Cornelis Sander Kooijman, Jacob Simon Faber
  • Patent number: 9471746
    Abstract: A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure “shots” are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. A simulation is run on the clusters of shots to estimate the resulting fabrication shapes that the clusters of shots create. The clusters of shots are modified to align the estimated fabrication shapes more closely with desired fabrication shapes. The process of simulating and modifying the shots is iterative, repeating until the estimated fabrication shapes are within a desired error difference of the planned fabrication shape.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: October 18, 2016
    Assignee: Synopsys, Inc.
    Inventors: Michael Lawrence Rieger, Thomas Christopher Cecil, Benjamin David Painter
  • Patent number: 9465906
    Abstract: Provided is an integrated circuit (IC) manufacturing method. The method includes receiving a design layout of an IC, the design layout having a main feature; performing a process correction to the main feature thereby generating a modified main feature; using a computer, generating a simulated contour of the modified main feature, the simulated contour having a plurality of points; generating a plurality of assistant data in computer readable format, wherein each assistant data includes at least one process performance factor associated with one of the points; and keeping the simulated contour and the assistant data for use by a further process stage, such as mask making, mask inspection, mask repairing, wafer direct writing, wafer inspection, and wafer repairing.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: October 11, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Shih-Ming Chang
  • Patent number: 9448495
    Abstract: A recording medium stores a program for causing a computer to execute a method of calculating a resist pattern.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: September 20, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Ryo Nakayama, Kouichirou Tsujita, Koji Mikami, Hiroyuki Ishii
  • Patent number: 9442398
    Abstract: A position detector configured to detect a position of an object to be detected. The position detector has an optical system configured to detect a mark on the object to be detected that includes a lens that has a positive refractive power, and a reflection member configured to reflect a light flux that passes through the lens in a convergent state or a divergent state. The reflection member is configured from at least one material of a material that exhibits a refractive index of less than 1.0 and an extinction coefficient of greater than 0.0, and a material that exhibits a refractive index of greater than 1.0 and an extinction coefficient of greater than 0.5.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: September 13, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventor: Ryo Sasaki
  • Patent number: 9411236
    Abstract: A patterning method may employ a particle beam, such as an electron beam (E-beam) and an exposure system that may include preparing an exposure layout defining a spatial distribution of an E-beam, performing an E-beam exposure process to a mask layer, based on the exposure layout, performing a developing process to the mask layer to form mask patterns including a first pattern. The first pattern may be a single solid pattern, and the exposure layout may include a first data associated with a plurality of E-beam conditions defined for a first region corresponding to the first pattern.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: August 9, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yongseok Jung, SangHee Lee
  • Patent number: 9390214
    Abstract: Methods of preparing layouts for semiconductor devices and semiconductor devices fabricated using the layouts are provided. Preparing the layouts for semiconductor devices may include disposing assistant patterns near a main gate pattern that is provided on a weak active pattern. The weak active pattern may be, for example, an outermost one of active patterns and may be one expected to have an increased width during a fabrication process.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: July 12, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: HunKook Lee, Hongsoo Kim, Juyeon Lee
  • Patent number: 9383649
    Abstract: A method of processing a substrate is described herein. The method includes positioning a substrate on a stage associated with a maskless direct writing pattern generator. The substrate has an undeveloped, unexposed photoresist layer formed thereon. The photoresist layer has a plurality of writing pixel locations. The method includes delivering predetermined doses of electromagnetic energy from the pattern generator to each writing pixel location. A first predetermined dose is a full tone dose, and the first predetermined dose is delivered to at least one writing pixel location. A second predetermined is a fractional tone dose, and the second predetermined dose is delivered to at least one writing pixel location. A third predetermined dose is either a fractional dose or a zero tone dose. The third predetermined dose is delivered to at least one writing pixel location, and the third predetermined dose is different from the second predetermined dose.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: July 5, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Christopher Dennis Bencher
  • Patent number: 9383657
    Abstract: A method for lithography exposing process is provided. The method includes performing a first lithography exposing process to a resist layer using a mask having a focus-sensitive pattern and an energy-sensitive pattern; measuring critical dimensions (CDs) of transferred focus-sensitive pattern and transferred energy-sensitive pattern on the resist layer; extracting Bossung curves from the CDs; and determining slopes of the Bossung curves.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: July 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jhih-Yu Wang, Chien-Yu Li, Iu-Ren Chen, Chi-Cheng Hung, Wei-Liang Lin, Chun-Kuang Chen
  • Patent number: 9361538
    Abstract: Systems and methods are disclosed for describing and tracking edges within the field of view of one or more imaging devices. In one example, the present system defines a row of pixels taken across a width of the edge, and then determines a binary edge descriptor for the edge by comparing at least one of grayscale values and contrast of pixels within respective pixel pairs from the row of pixels, the result of the comparisons setting bits within the binary descriptor.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: June 7, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Britta S. Hummel, Oliver Williams, Abdelrehim Ahmed
  • Patent number: 9360858
    Abstract: Deformation of a substrate due to one or more processing steps is determined by measuring substrate alignment data at lithographic processing steps before and after the one or more processing steps. Any abnormal pattern in the alignment data differential is identified by comparing the calculated alignment data differential with previous data accumulated in a database. By comparing the abnormal pattern with previously identified tool-specific patterns for alignment data differential, a processing step that introduces the abnormal pattern and/or the nature of the abnormal processing can be identified, and appropriate process control measures can be taken to rectify any anomaly in the identified processing step.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: June 7, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Christopher P. Ausschnitt, Timothy A. Brunner, Allen H. Gabor, Oleg Gluschenkov, Vinayan C. Menon
  • Patent number: 9349105
    Abstract: Machine learning solutions compensate for data missing from input (training) data and thereby arrive at a predictive model that is based upon, and consistent with, the training data. The predictive model can be generated within a learning algorithm framework by transforming the training data to generate modality or similarity kernels. Similarity values can be generated for these missing similarity values.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: May 24, 2016
    Assignee: International Business Machines Corporation
    Inventors: David J. Beymer, Karen W. Brannon, Ting Chen, Moritz A. W. Hardt, Ritwik K. Kumar, Tanveer F. Syeda-Mahmood
  • Patent number: 9341957
    Abstract: A method of operating an illumination system of a microlithographic projection exposure apparatus is provided. A set of illumination parameters that describe properties of a light bundle which converges at a point on a mask to be illuminated by the illumination system is first determined. Optical elements whose optical effect on the illumination parameters can be modified as a function of control commands are furthermore determined, as well as sensitivities with which the illumination parameters react to an adjustment of the optical elements, induced by the control commands. The control commands are then determined while taking the previously determined sensitivities into account, such that deviations of the illumination parameters from predetermined target illumination parameters satisfy a predetermined minimization criterion. These control commands are applied to the optical elements, before the mask is illuminated.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: May 17, 2016
    Assignee: Carl Zeiss SMT GmbH
    Inventors: Oliver Natt, Frank Schlesener
  • Patent number: 9342646
    Abstract: A method comprises: accessing data representing a layout of a layer of an integrated circuit (IC) comprising a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks for multi-patterning a single layer of a semiconductor substrate, where N is greater than one. For each set of N parallel polygons in the layout closer to each other than a minimum separation for patterning with a single photomask, at least N?1 stitches are inserted in each polygon within that set to divide each polygon into at least N parts, such that adjacent parts of different polygons are assigned to different photomasks from each other. Data representing assignment of each of the parts in each set to respective photomasks are stored in a non-transitory, computer readable storage medium that is accessible for use in a process to fabricate the N photomasks.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: May 17, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsien Yu-Tseng, Shih-Kai Lin, Chin-Shen Lin, Yu-Sian Jiang, Heng-Kai Liu, Mu-Jen Huang, Chien-Wen Chen
  • Patent number: 9318416
    Abstract: Some embodiments include a semiconductor device which includes a first conductive layer formed on the semiconductor substrate and a first contact plug connected to the first conductive layer. The first conductive layer includes a plurality of loops of conductive material over the semiconductor substrate. Each of the plurality of loops comprises a first opening and a second opening, a first portion and a second portion sandwiching the first opening, a third portion and a fourth portion sandwiching the second opening, a first tab portion connected to the first portion and the third portion and having a first length in a first direction and a first width in a second direction perpendicular to the first direction, and a second tab portion connected to the second portion and the fourth portion and having a second length in the first direction and a second width in the second direction.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: April 19, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Tsutomu Aya
  • Patent number: 9310692
    Abstract: A component for setting a scan-integrated illumination energy in an object plane of a microlithography projection exposure apparatus is disclosed. The component includes a plurality of diaphragms which are arranged alongside one another with respect to a direction perpendicular to the scan movement and which differ in their form and the position of which can be altered approximately in the scan direction so that a portion of the illumination energy can be vignetted by at least one diaphragm. The form of the individual diaphragm is specifically adapted to the form of the illumination in a diaphragm plane in which the component is arranged. This has the effect that at least parts of the delimiting edges of two diaphragms always differ in the case of an arbitrary displacement of the diaphragms.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: April 12, 2016
    Assignee: Carl Zeiss SMT GmbH
    Inventors: Ralf Stuetzle, Martin Endres, Jens Ossmann, Michael Layh
  • Patent number: 9305767
    Abstract: There is provided a liquid processing apparatus including a rotation unit configured to hold the target substrate and rotate the target substrate around a vertical axis; a processing solution supply nozzle configured to supply the processing solution to the surface of the target substrate being rotated; a first gas supply unit configured to form a downward flow of a first gas that flows over the entire surface of the target substrate and is introduced into a cup in order to form a processing atmosphere suitable for a liquid process to be performed; and a second gas supply unit configured to form a downward flow of a second gas different from the first gas in a region outside the downward flow of the first gas. The first gas supply unit and the second gas supply unit are provided at a ceiling portion of the housing serving as the processing space.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: April 5, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kenji Nishi, Kazuhiro Takeshita, Nobuhiro Ogata, Satoru Tanaka, Shogo Mizota
  • Patent number: 9305799
    Abstract: The present disclosure provides a method for electron-beam (e-beam) lithography patterning. The method includes forming a resist layer on a substrate; performing a first e-beam exposure process to the resist layer according to a first pattern; performing a second e-beam exposure process to the resist layer according to a second pattern, wherein the second patterned is overlapped to the first pattern on the resist layer; and developing the resist layer.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: April 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Shiang Chen, Hung-Chun Wang, Jeng-Horng Chen
  • Patent number: 9291920
    Abstract: The present disclosure is directed to a method of determining one or more focus values for a lithographic scanner. An optical signal including at least a first variable and a second variable is detected by an optical analysis system from at least one test sample for a plurality of programmed focus error values. A first variable value showing sensitivity to focus is selected based upon a corresponding responsiveness of the second variable to change of focus and/or a corresponding linearity of raw focus with respect to the programmed focus error. At least one focus value for the lithographic scanner is determined based upon at least one determined raw focus value corresponding to the selected first variable value.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: March 22, 2016
    Assignee: KLA-Tencor Corporation
    Inventors: James Manka, David Tien, Christian Sparka
  • Patent number: 9275449
    Abstract: A method of determining a dose-to-clear of a photoresist on a wafer includes providing an image of the wafer after the photoresist was exposed to a dose of energy and was developed, transforming the image of the wafer into frequency spectrum data, calculating an average frequency spectrum component of the frequency spectrum data, calculating a difference between the average frequency spectrum component and a noise average frequency spectrum component of a noise average frequency spectrum, and determining a dose-to-clear of the photoresist based on the difference between the average frequency spectrum component and the noise average frequency spectrum component.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: March 1, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Lei Sun, Obert Reeves Wood, II
  • Patent number: 9274433
    Abstract: An embodiment of the present invention provides a fly eye lens which is applied to a proximity exposure machine optical system. The fly lens includes a first lens assembly and a second lens assembly, wherein the first lens assembly includes a plurality of lenses which form a first lens face, and the second lens assembly includes a plurality of lenses which form a second lens face. The first lens face is used to split an incident broad light beam into narrow light beams and then refract the narrow light beams onto the second lens face, and the second lens face is used to dispersively refract the received narrow light beams onto a concave mirror in the optical system. A lens closer to a center of the second lens face has a higher transmittivity, and a lens farther from the center of the second lens face has a lower transmittivity.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: March 1, 2016
    Assignees: BOE Technology Group Co., Ltd., Beijing BOE Display Technology Co., Ltd.
    Inventors: Min Li, Hongjiang Wu, Gyuhyun Lee, Jikai Zhang, Tonghua Yang
  • Patent number: 9256703
    Abstract: A method of testing a scattering bar by simulation includes preparing an OPC mask model including a main pattern and a scattering bar pattern, forming a scattering bar OPC model by adjusting an image plane of the OPC mask model located at a middle portion of a photoresist layer to a top portion of the photoresist layer, simulating an exposure of the scattering bar OPC model, simulating a profile of the exposed scattering bar OPC model, and testing the simulated profile.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: February 9, 2016
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Wanjuan Zhang, Yibin Huang
  • Patent number: 9257434
    Abstract: A semiconductor device includes: a Through Silicon Via (TSV) region extending in a first direction and crossing a center portion of a semiconductor device; a plurality of cell regions disposed at both sides of the TSV region in a second direction crossing the first direction; a plurality of peripheral circuit regions each disposed between the TSV region and a corresponding cell region or between two neighboring cell regions in the first direction; a plurality of test pad regions each disposed at an edge portion of the semiconductor device and having a plurality of test pads, wherein the plurality of test pad regions encloses the cell regions, the peripheral circuit regions, and the TSV region; and a reservoir capacitor disposed below corresponding test pads in a test pad regions.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: February 9, 2016
    Assignee: SK HYNIX INC.
    Inventors: Seung Yeub Yang, Jin Ho Kim
  • Patent number: 9252021
    Abstract: Methods for patterning fins for fin-like field-effect transistor (FinFET) devices are disclosed. An exemplary method includes providing a semiconductor substrate, forming a plurality of elongated protrusions on the semiconductor substrate, the elongated protrusions extending in a first direction, and forming a mask covering a first portion of the elongated protrusions, the mask being formed of a first material having a first etch rate. The method also includes forming a spacer surrounding the mask, the spacer being formed of a second material with an etch rate lower than the etch rate of the first material, the mask and the spacer together covering a second portion of the elongated protrusions larger than the first portion of the elongated protrusions. Further, the method includes removing a remaining portion of the plurality of elongated protrusions not covered by the mask and spacer.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: February 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hoi-Tou Ng, Kuei-Liang Lu, Ming-Feng Shieh, Ru-Gun Liu
  • Patent number: 9250540
    Abstract: A lithography method for a pattern to be etched on a support, notably to a method using electron radiation with direct writing on the support. Hitherto, the methods for correcting the proximity effects for dense network geometries (line spacings of 10 to 30 nm) have been reflected in a significant increase in the radiated doses and therefore in the exposure time. According to the invention, the patterns to be etched are modified as a function of the energy latitude of the process, which allows a reduction of the radiated doses.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: February 2, 2016
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventor: Serdar Manakli
  • Patent number: 9245930
    Abstract: A method of manufacturing a display panel includes: a first step of forming a partition wall layer above a substrate; a second step of exposing the partition wall layer using a first photomask that has a mask pattern corresponding to a blue opening; a third step of exposing the partition wall layer using a second photomask that has a mask pattern corresponding to a red opening and a green opening; a fourth step of forming a partition wall by removing the partition wall layer to form the red opening, the green opening , and the blue opening in the partition wall layer; and a fifth step of forming a light emitting layer in each opening.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: January 26, 2016
    Assignee: JOLED INC.
    Inventor: Takashi Osako
  • Patent number: 9229337
    Abstract: A method of setting an exposure apparatus to expose exposure sectors defined on a resist film formed on a surface of a substrate with proper values of an exposure amount and a focus value for forming a pattern having a predetermined dimension includes exposing and developing an exposure sector defined on a reference substrate by a first exposure apparatus having a first state, and imaging the same. The method exposes and develops exposure sectors defined on an inspection substrate by a second exposure apparatus having a second state where at least one of the exposure amount and the focus value is unknown, and forms and images a pattern on the inspection substrate. The method determines the proper values for the exposure amount and the focus value for the second state based on luminance of the exposure sector of reference data and luminances of the exposure sectors of inspection data.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: January 5, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Shinobu Miyazaki, Hiroshi Tomita, Shuji Iwanaga
  • Patent number: 9213783
    Abstract: Disclosed herein is a computer-implemented method for improving a lithographic process for imaging a portion of a design layout onto a substrate using a lithographic projection apparatus, the method comprising defining a multi-variable cost function, the multi-variable cost function being a function of a stochastic effect of the lithographic process.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: December 15, 2015
    Assignee: ASML NETHERLANDS B.V.
    Inventor: Steven George Hansen