Abstract: A method includes receiving a pattern layout for a mask, shrinking the pattern layout to form a shrunk pattern, determining centerlines for each of a plurality of features within the shrunk pattern, and snapping the centerline for each of the plurality of features to a grid. The grid represents a minimum resolution size of a mask fabrication tool. The method further includes, after snapping the centerline for each of the plurality of features to the grid, fabricating the mask with the shrunk pattern.

Abstract: A method for improving a quality of a secondary electron image of a region of a sample, the method may include obtaining a backscattered electron (BSE) image of the region and a secondary electron (SE) image of the region; wherein the BSE image and the SE image are generated by scanning of the region with an electron beam; processing the BSE image and the SE image to provide a processed BSE image and a processed SE image; and generating a BSE compensated SE image, wherein the generating comprises applying one or more selected BSE correction factors on one or more parts of the processed BSE image.

Abstract: This application discloses a calibration method, a calibration system, and a calibration board. The calibration board includes checkerboard cells arranged on a surface of the calibration board, where at least one dot is arranged in each of the checkerboard cells, the dots of the calibration board include at least a first feature dot and a second feature dot, the first feature dot and the second feature dot are arranged in the checkerboard cells according to a random rule or a specific rule, and a diameter of the first feature dot is greater than a diameter of the second feature dot. The calibration board in this application improves the stability and accuracy of calibration board detection by utilizing characteristics such as a high detection accuracy and a strong anti-blur capability of a dot mark, combining with corner points of checkerboard cells.

Abstract: A light detection module, a light detection method and a display device are provided. The light detection module includes N light sensing circuits, a control circuit, a conversion circuits and a detection circuits; N being a positive integer; the N light sensing circuits respectively sense light signals of different colors to generate corresponding photocurrents; the control circuit is configured to control to provide the photocurrents generated by the light sensing circuits to the conversion circuit in a time division manner, and to control a transfer coefficient of the conversion circuit; the conversion circuit is configured to convert the photocurrent according to the transfer coefficient to obtain an analog output voltage; the detection circuit is configured to obtain characteristics of the light signal according to the analog output voltage.

Abstract: A lithography film stack applied to an immersion lithography process includes a photoresist, a wavelength adjusting layer and a top coating layer. The photoresist is disposed on a substrate. The wavelength adjusting layer is disposed on the photoresist. The top coating layer is disposed on the wavelength adjusting layer. A refractive index of the wavelength adjusting layer is greater than a refractive index of the top coating layer and a refractive index of an immersion fluid of the immersion lithography process.

Abstract: An exposure system according to an aspect of the present disclosure includes a laser apparatus that outputs pulsed laser light, an illuminating optical system that guides the pulsed laser light to a reticle, a reticle stage, and a processor that controls the output of the pulsed laser light from the laser apparatus and the movement of the reticle performed by the reticle stage. The reticle has a first region where a first pattern is disposed and a second region where a second pattern is disposed, and the first and second regions are each a region continuous in a scan width direction perpendicular to a scan direction of the pulsed laser light, with the first and second regions arranged side by side in the scan direction. The processor controls the laser apparatus to output the pulsed laser light according to each of the first and second regions by changing the values of control parameters of the pulsed laser light in accordance with each of the first and second regions.

Abstract: In an embodiment, a pattern transfer processing chamber includes a pattern transfer processing chamber and a loading area external to the pattern transfer processing chamber. The loading area is configured to transfer a wafer to or from the pattern transfer processing chamber. The loading area comprises a first region including a loadport, a second region including a load-lock between the first region and the pattern transfer processing chamber, and an embedded baking chamber configured to heat a patterned photoresist on the wafer.

Abstract: A robot calibration system includes a calibration fixture configured to be mounted on a substrate processing chamber. The calibration fixture includes at least one camera arranged to capture an image including an outer edge of a test substrate and an edge ring surrounding the test substrate. A controller is configured to receive the captured image, analyze the captured image to measure a distance between the outer edge of the test substrate and the edge ring, calculate a center of the test substrate based on the measured distance, and calibrate a robot configured to transfer substrate to and from the substrate processing chamber based on the calculated center of the test substrate.

Abstract: The present disclosure provides methods and systems for optically-induced auto-encapsulation. A method of the present disclosure comprises providing a media chamber comprising a medium comprising (i) a three-dimensional (3D) object comprising a photo-emitter, (ii) at least one polymeric precursor, and (iii) a photoinitiator, and subjecting the medium in the media chamber to a stimulus (e.g., an energy beam or a chemical stimulus) to induce photo-emission from the photo-emitter to trigger the formation of a polymer matrix from the at least one polymeric precursor, which polymer matrix at least partially encapsulates the 3D object.

Abstract: A method for manufacturing semiconductor devices include steps of depositing a first photoresist over a first dielectric layer, first exposing the first photoresist to a first light-exposure using a first lithographic mask, and second exposing the first photoresist to a second light-exposure using a second lithographic mask. An overlap region of the first photoresist is exposed to both the first light-exposure and the second light-exposure. The first dielectric layer is thereafter patterned to form a mask overlay alignment mark in the overlap region. The patterning includes etching the first dielectric layer form a trench, and filling the trench with a conductive material to produce the alignment mark. A second dielectric layer is deposited over the alignment mark, and a second photoresist is deposited over the second dielectric layer. A third lithographic mask is aligned to the second photoresist using the underlying mask overlay alignment mark for registration.

Abstract: A method for correcting critical dimension (CD) measurements of a lithographic tool includes steps as follows. A correction pattern having a first sub-pattern parallel to a first direction and a second sub-pattern parallel to a second direction is provided on a lithographic mask; wherein the first sub-pattern and the second sub-pattern come cross with each other. A first After-Develop-Inspection critical dimension (ADI CD) of a developed pattern formed on a photo-sensitive layer and transferred from the correction pattern is measured using the lithographic tool along a first scanning direction. A second ADI CD of the developed pattern is measured using the lithographic tool along a second scanning direction. The first ADI CD is subtracted from the second ADI CD to obtain a measurement bias value. Exposure conditions and/or measuring parameters of the lithographic tool are adjusted according to the measurement bias value.

Abstract: A photomask includes a plurality of main patterns, a plurality of first sub-resolution assist feature patterns and a plurality of second sub-resolution assist feature patterns. The first sub-resolution assist feature patterns are located aside the main patterns. The second sub-resolution assist feature patterns are disposed between and connected to adjacent two of the first sub-resolution assist feature patterns.

Abstract: A method for reducing M3D effects on imaging is described. The method includes identifying points within a source plane of the photolithography system that are associated with pattern shifts resulting from diffraction of light off a photomask under an angle of incidence between an imaging beam of radiation and the mask normal, determining pattern shifts associated with the identified source plane points, and modifying the source to reduce the determined pattern shifts.

Abstract: A three-dimensional object printing system includes: a printing table for a plurality of three-dimensional objects to be placed on, the printing table having a plurality of detection reference marks; detecting means for detecting positions and orientations of the three-dimensional objects placed on the printing table and the detection reference marks; printing data generating means generating printing data corresponding to the three-dimensional objects based on the positions and orientations of the three-dimensional objects detected by the detecting means, the printing data generating means obtaining reference coordinates of the detection reference marks based on part of the detection reference marks; and printing means for executing printing on the three-dimensional objects using the printing data generated by the printing data generating means.

Abstract: A lithographic system comprises a radiation source and a lithographic apparatus. The radiation source provides radiation to the lithographic apparatus. The lithographic apparatus uses the radiation for imaging a pattern onto multiple target areas on a layer of photo-resist on a semiconductor substrate. The imaging requires a pre-determined dose of radiation. The system is controlled so as to set a level of a power of the radiation in dependence on a magnitude of the pre-determined dose.

Abstract: A method for writing an imageable material using multiple beams includes preparing subsequent patterns each having Y rows of N pixel locations, said subsequent patterns including first and second patterns; where the first and the second pattern overlap with each other in an overlap area consisting of O columns and Y rows of pixel locations; selecting for each row i of said first pattern Mi1 pixel locations; selecting for each row i of said second pattern Mi2 pixel locations; writing simultaneously, for each row i, said Mi1 selected pixel locations by moving the N beams in a fast scan direction relative to said imageable material; and moving said N beams relative to said imageable material in a slow scan direction over (N-O) pixel locations; writing simultaneously, for each row i, said Mi2 selected pixel locations by moving the N beams in a fast scan direction relative to said imageable material.

Abstract: An integrated optical device includes a substrate, a waveguide structure and a grating structure. The substrate has a waveguide region and a grating region adjacent to each other. The waveguide structure is disposed on the substrate in the waveguide region. The grating structure is disposed on the substrate in the grating region. In some embodiments, the grating structure includes grating bars and grating intervals arranged alternately, and widths of the grating bars of the grating structure are varied.

Abstract: Air curtain devices can reduce defects on semiconductor wafers when implemented on a track equipped with robotic wafer transport. The air curtain devices can be added to one or more processing devices arranged along the track to prevent defects from landing on wafer surfaces. For example, the air curtain devices can prevent volatile organic solvent mist from drifting towards processing devices on the track and preventing contamination via a wafer transport system.

Abstract: A lithography system is provided capable of deterring contaminants, such as tin debris from entering into the scanner. The lithography system in accordance with various embodiments of the present disclosure includes a processor, an extreme ultraviolet light source, a scanner, and a hollow connection member. The light source includes a droplet generator for generating a droplet, a collector for reflecting extreme ultraviolet light into an intermediate focus point, and a light generator for generating pre-pulse light and main pulse light. The droplet generates the extreme ultraviolet light in response to the droplet being illuminated with the pre-pulse light and the main pulse light. The scanner includes a wafer stage. The hollow connection member includes an inlet that is in fluid communication with an exhaust pump. The hollow connection member provides a hollow space in which the intermediate focus point is disposed.

Abstract: A mask forming method includes providing preliminary mask data including a Manhattan path such as a quadrangle, a bar, a polygon or a combination thereof based on a layout. Mask data including a curvilinear shape is prepared by correcting the preliminary mask data through application of an elliptical function, a B-spline curve, or a combination thereof. A mask pattern is formed on a mask substrate based on the mask data.

Abstract: Methods and systems for loading an ion trap are provided herein in which the total ion beam intensity and/or content of the ion beam are quickly interrogated so as to determine an optimum fill time for an ion trap. In various aspects, the methods and systems described herein are effective to prevent overfilling of the ion trap while decreasing the time associated with known techniques utilized to obtain a survey scan of the ion beam.

Abstract: A method for lithography in semiconductor fabrication is provided. The method includes placing a semiconductor wafer over a wafer stage. The method also includes supplying an initial voltage to a plurality of electrodes of the wafer stage based on a topology of the semiconductor wafer, wherein the electrodes of the wafer stage are electrically isolated from each other. The method further includes measuring an adjusted topology of the semiconductor wafer after the initial voltage is supplied. In addition, the method includes supplying different first adjusted voltages to the electrodes of the wafer stage according to the adjusted topology of the semiconductor wafer.

Abstract: The present disclosure provides a method for fabricating a semiconductor structure, including disposing a mask at a first position in a first chamber, generating; a first plurality of ions toward the mask by an ionizer, forming a photoresist layer on a substrate, receiving the substrate in the first chamber, and exposing the photoresist layer with actinic radiation through the mask in the first chamber.

Abstract: A method for correcting distortion in image printing, the method includes receiving a digital image (200, 306, 376, 500, 600, 700, 810) acquired from a printed image. Based on the digital image (200, 306, 376, 500, 600, 700, 810), a geometric distortion in the printed image is estimated. One or more pixel locations (228, 504, 506, 514, 610, 620, 630, 640, 712, 716, 722, 724) are calculated, such that, when one or more dummy pixels (232, 234) are implanted therein, compensate for the estimated geometric distortion. The geometric distortion is corrected in a subsequent digital image to be printed, by implanting the one or more dummy pixels (232, 234) at the one or more calculated pixel locations (228, 504, 506, 514, 610, 620, 630, 640, 712, 716, 722, 724) in the subsequent digital image. The subsequent digital image having the corrected geometric distortion is printed.

Abstract: In a beam irradiation apparatus in which a movable body holds an object, a mark detection system detects a first mark on the movable body while moving the movable body in a first direction and changing an irradiation position of a measurement beam in the first direction, the mark detection system detects a second mark while moving the movable body in the first direction and changing the irradiation position of the measurement beam in the first direction, a controller controls a position of the movable body in a second direction intersecting the first direction during a time period between the detection of the first mark and the detection of the second mark, and the controller controls the movement of the movable body to adjust a positional relation between the object on the movable body and a processing beam, based on results of the detection of the first and second marks.

Abstract: A method for detecting a defect in a semiconductor fabrication process is disclosed. The method includes forming photoresist on a substrate; forming a fluorescent agent in the photoresist; and detecting the defect of the photoresist after being subjected to developing by utilizing the fluorescent agent.

Abstract: A structured light projectors includes an illuminator configured to emit illumination light, a pattern mask configured to project structured light by partially transmitting the illumination light, and a lens configured to project the structured light, wherein the pattern mask includes a first lens distortion compensation region including a plurality of opaque first light shielding patterns having a first pattern width, respectively, and a second lens distortion compensation region surrounding the first lens distortion compensation region, the second lens distortion compensation region including a plurality of opaque second light shielding patterns having a second pattern width, respectively, wherein the second pattern width is less than the first pattern width.

Abstract: A method of manufacturing a semiconductor device includes selecting a diffraction based focus (DBF) mark that is unaffected by a pattern of a lower layer; manufacturing a mask including a mark pattern for forming the DBF mark; forming the DBF mark in a cell region of a wafer by using the mask; measuring the DBF mark and monitoring defocus; correcting the defocus on the basis of a result of the monitoring; and forming a pattern in the cell region of the wafer, after correcting the defocus.

Abstract: A lithography system is provided with: a measurement device measuring position information of marks on a substrate held in a first stage; and an exposure apparatus on a second stage, the substrate for which the position information measurement for the marks has been completed, performs alignment measurement to measure position information for part of marks selected from among the marks on the substrate, and performs exposure. The measurement device measures position information of marks on the substrate to obtain higher-degree components of correction amounts of an arrangement of divided areas, and the exposure apparatus measures position information of a small number of marks on the substrate to obtain lower-degree components of the correction amounts of the arrangement of the divided areas and exposes the plurality of divided areas while controlling the position of the substrate by using the obtained lower-degree components and the higher-degree components obtained by the measurement device.

Abstract: A method for calibrating a resist model. The method includes: generating a modeled resist contour of a resist structure based on a simulated aerial image of the resist structure and parameters of the resist model, and predicting a metrology contour of the resist structure from the modeled resist contour based on information of an actual resist structure obtained by a metrology device. The method includes adjusting one or more of the parameters of the resist model based on a comparison of the predicted metrology contour and an actual metrology contour of the actual resist structure obtained by the metrology device.

Abstract: A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.

Abstract: A lithography system is provided with: a measurement device measuring position information of marks on a substrate held in a first stage; and an exposure apparatus on a second stage, the substrate for which the position information measurement for the marks has been completed, performs alignment measurement to measure position information for part of marks selected from among the marks on the substrate, and performs exposure. The measurement device measures position information of marks on the substrate to obtain higher-degree components of correction amounts of an arrangement of divided areas, and the exposure apparatus measures position information of a small number of marks on the substrate to obtain lower-degree components of the correction amounts of the arrangement of the divided areas and exposes the plurality of divided areas while controlling the position of the substrate by using the obtained lower-degree components and the higher-degree components obtained by the measurement device.

Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.

Abstract: A measurement result receiving apparatus receives measurement results transmitted from a plurality of measuring devices, the measurement results obtained by conducting a measurement at a predetermined sampling interval according to a reference clock of each measuring device. The measurement result receiving apparatus includes a receiving section that receives the measurement results from the plurality of measuring devices; and a sampling interval converting section that converts the measurement results into measurement values associated with a common sampling interval.

Abstract: A method of monitoring a semiconductor process includes the following steps. A process parameter is set to a first condition. A first process is performed to form a first film layer on a first wafer. The first film layer does not cover a wafer edge region of the first wafer. The first wafer having the first film layer is photographed by an image capturing device to obtain a first wafer image. Image recognition is performed to the first wafer image to obtain first data. Whether a position of the first film layer is offset is determined according to the first data.

Abstract: A multilayer capacitor includes: a body including a stack structure in which a first internal electrode and a second internal electrode are stacked on each other interposing a dielectric layer therebetween; and first and second external electrodes disposed on the body to be respectively connected to the first internal electrode and the second internal electrode. One of the first internal electrode and the second internal electrode includes a recess portion disposed in one surface thereof, and providing a deviation in a distance between the first and second internal electrodes, TD indicates a thickness of a portion of the dielectric layer, based on a portion positioned on the one surface and not in the recess portion, TR indicates a recession depth of a portion positioned on the one surface and recessed by the recess portion, and (TR/TD) is greater than zero and less than (½).

Abstract: The present invention relates to a monitor wafer measuring method and measuring apparatus. The monitor wafer measuring method comprises the following steps: fixing a product wafer, the product wafer having several alignment marks and product measuring sites corresponding respectively to the alignment marks; determining the product measuring sites according to the alignment marks; and placing a monitor wafer, a projection of the monitor wafer in a vertical direction being aligned with and coinciding with the product wafer. The present application can reduce or even eliminate positional errors of the monitor wafer during a measurement process, such that product-level measuring position accuracy can be achieved for the monitor wafer and further, the measuring machine itself and process changes can be monitored in a better way.

Abstract: A method for detecting a rare stochastic defect, the method may include searching for a rare stochastic defect in a dense pattern of a substrate, wherein the rare stochastic defect is (a) of nanometric scale, (b) appears in a functional pattern of the substrate with a defect density that is below 10?9, and (c) appears in the dense pattern with a defect density that is above 10?7; wherein the dense pattern is a dense representation of the functional pattern that differs from the functional pattern by at least one out of (a) a distance between features of the dense pattern, and (b) a width of the features of the dense pattern; and estimating the occurrence of the rare stochastic defect within the functional pattern based on an outcome of the searching.

Abstract: A method for making a IC is provided, including: identifying, in a schematic, first and second edge elements, which edge elements including devices whose layout patterns are configured to conform to a first layout grid; identifying all the elements between the first and second edge elements, at least one of the identified elements including a device whose layout pattern is configured to conform to a second layout grid that is finer than the first layout grid; and calculating a spatial quantity of a combined layout pattern of the identified elements between the first and second edge elements to determine whether the combined layout pattern conforms to the first layout grid.

Abstract: The invention discloses a pattern layout of an active region and a forming method thereof. The feature of the present invention is that in the sub-pattern unit, an appropriate active area pattern is designed according to the bit line pitch (BLP) and the word line pitch (WLP), the active area pattern is a stepped pattern formed by connecting a plurality of rectangular patterns in series, and the active area pattern is arranged along a first direction, the angle between the first direction and the horizontal direction is A. In addition, according to the angle A, the shortest distance (P) between adjacent stepped patterns, the length and width of sub-pattern units, etc., The positions of some stepped active area patterns are adjusted, so that the distance between multiple active area patterns can be consistent when being repeatedly arranged, thereby improving the uniformity of overall pattern distribution.

Abstract: A substrate inspection apparatus includes: a storage configured to store inspection image data obtained from a captured image of a periphery of a substrate on which a film is formed, and an inspection recipe; an edge detector configured to detect a target edge as an edge of an inspection target film on the basis of the inspection image data stored in the storage by using the inspection recipe stored in the storage; a periphery calculator configured to calculate a position of a theoretical periphery of the substrate; and a width calculator configured to calculate a width between the theoretical periphery of the substrate and the target edge on the basis of position data of the theoretical periphery of the substrate obtained by the periphery calculator and position data of the target edge obtained by the edge detector.

Abstract: A substrate processing apparatus which processes includes a thermal processor that performs thermal processing on the substrate; an imager that images the substrate; and a controller that executes adjustment processing of adjusting conditions of processing on the substrate.

Abstract: In a method of pattern formation information including a pattern size on a reticle is received. A width of an EUV radiation beam is adjusted in accordance with the information. The EUV radiation beam is scanned on the reticle. A photo resist layer is exposed with a reflected EUV radiation beam from the reticle. An increase of intensity per unit area of the EUV radiation beam on the reticle after the adjusting the width is greater when the width before adjustment is W1 compared to an increase of intensity per unit area of the EUV radiation beam on the reticle after the adjusting the width when the width before adjustment is W2 when W1>W2.

Abstract: Methods for reticle enhancement technology (RET) for use with variable shaped beam (VSB) lithography include inputting a desired pattern to be formed on a substrate; determining an initial mask pattern from the desired pattern for the substrate; optimizing the initial mask pattern for wafer quality using a VSB exposure system; and outputting the optimized mask pattern. Methods for fracturing a pattern to be exposed on a surface using VSB lithography include inputting an initial pattern; overlaying the initial pattern with a two-dimensional grid, wherein an initial set of VSB shots are formed by the union of the initial pattern with locations on the grid; merging two or more adjacent shots in the initial set of VSB shots to create a larger shot in a modified set of VSB shots; and outputting the modified set of VSB shots.

Abstract: A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.

Abstract: A method of disposing a substrate on a holding unit using a pattern forming apparatus which forms a pattern on the substrate, the pattern forming apparatus comprising: a stage, the holding unit removably attached to the stage and configured to suck and hold the substrate, an optical system, and configured to detect an alignment mark of the substrate from a suction surface side of the substrate, the optical system having plural optical elements, and a detection unit configured to detect a reference mark for measuring a position of a detection field of the optical system, the method comprising: detecting a position of the reference mark, and disposing the substrate on the holding unit using the detected position of the reference mark so that the alignment mark of the substrate detected from the suction surface side of the substrate by the optical system is disposed in the detection field.

Abstract: A method includes receiving a pattern layout for a mask, shrinking the pattern layout to form a shrunk pattern, determining centerlines for each of a plurality of features within the shrunk pattern, and snapping the centerline for each of the plurality of features to a grid. The grid represents a minimum resolution size of a mask fabrication tool. The method further includes, after snapping the centerline for each of the plurality of features to the grid, fabricating the mask with the shrunk pattern.

Abstract: Embodiments provide point-of-use blending of photoresist rinse solutions for patterned photoresists. Disclosed methods and systems form different mitigation solutions for multiple different photoresists through point-of-use variable blending of a mitigation solution with deionized water and/or other chemistries to adjust the formulation of the solution just prior to dispense within a process chamber. For one example embodiment, different surfactant rinse solutions are used for different photoresists, such as different extreme ultraviolet photoresists. In addition, the level of reactive components, the level of nonreactive components, or both within a mitigation solution can be adjusted using this point-of-use blending to provide an adjusted mitigation solution. The ability to make point-of-use adjustments to the solution chemistry just before dispense on a microelectronic workpiece, such as a semiconductor wafer, improves interactions between the adjusted mitigation solution and the patterned photoresist.

Abstract: The present disclosure provides an apparatus for manufacturing a semiconductor structure. The apparatus includes a stage, an optical transceiver over the stage, configured to obtain a first profile of a first surface of a substrate, an acoustic transceiver over the stage, configured to obtain a second profile of a top surface of a photo-sensitive layer over the substrate, wherein the stage is adapted to be displaced based on the first profile and the second profile.

Abstract: Disclosed is a method for selecting a structure for focus monitoring. The method comprises: simulating a Bossung response with focus of a focus dependent parameter, for one or more different structures; and selecting a structure for focus monitoring in a manufacturing process based on the results of said simulating step. The simulating step may be performed using a computational lithography simulation.