Including Control Feature Responsive To A Test Or Measurement Patents (Class 430/30)
  • Patent number: 10838824
    Abstract: A media agent is configured to perform substantially autonomously to initiate, continue, and manage information management operations such as a backup job of a certain client's primary data, manage the operations, and generate and store resultant system-level metadata from the operations, etc. The media agent is configured to do this even when out of communication with the storage manager that manages the information management system. When communications are restored, the media agent reports the relevant metadata to the storage manager. The storage manager comprises corresponding enhancements, including specialized logic for identifying the media agent as an intelligent media agent capable of some autonomous functionality, for transmitting management parameters thereto, and for seamlessly integrating the received metadata into the storage manager's associated management infrastructure such as a management database.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: November 17, 2020
    Assignee: Commvault Systems, Inc.
    Inventor: Michael Frank Klose
  • Patent number: 10824081
    Abstract: A method and apparatus is disclosed for monitoring critical dimensions in a pattern of 1-dimensional and/or 2-dimensional features, produced on a substrate in a process step that is part of or related to a manufacturing process for producing a semiconductor device, the process step being performed in accordance with a predefined pattern design, wherein one or more metrology targets (1) are added to the pattern design. The targets comprise one or more versions of an asymmetric metrology mark, each version of the mark comprising a uniform portion (2) and a periodic portion (3), the latter comprising a regular array of parallel line-shaped features or an array of 2-dimensional features. The design width of the features is situated in a range situated around a nominal design width w0. A position-related parameter S is defined that is essentially proportional to the design widths in the range.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: November 3, 2020
    Assignee: IMEC VZW
    Inventors: Christopher Ausschnitt, Vincent Truffert
  • Patent number: 10809627
    Abstract: An exposure mask includes an aligning portion and a boundary portion. The aligning portion may be aligned with pixel areas of a substrate and includes a first exposure member and a second exposure member. The boundary portion includes a first exposure element, a second exposure element, a third exposure element, and a fourth exposure element. The first exposure member, the first exposure element, and the second exposure element are positioned in a first row. The first exposure element is positioned between the first exposure member and the second exposure element and is larger than the second exposure element. The second exposure member, the third exposure element, and the fourth exposure element are positioned in a second row. The third exposure element is positioned between the second exposure member and the fourth exposure element and is smaller than the fourth exposure element. Each exposure member/element includes a light transmitter/blocker.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: October 20, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventor: Inwoo Kim
  • Patent number: 10796067
    Abstract: Systems, methods, media, and other such embodiments described herein relate to critical area analysis (CAA) operations as part of electronic design automation (EDA). One embodiment involves accessing a circuit design having a first layer (which may be a composite layer), sampling the first layer, and performing an initial CAA using the sampled portions of the layer with a set of predetermined defect sizes. The initial CAA is used to automatically generate a model which can be used to accurately select input parameters (e.g., selected defect sizes) for a full analysis. A CAA characteristic is then calculated for the first layer using the input parameters. In various embodiments, different sampling percentages and criteria for selecting input parameters can be used to reduce the computing resources to compute a CAA characteristic, such as theta-bar, while limiting error to a threshold amount (e.g. less than one percent).
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: October 6, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jonathan R. Fales, Frank E. Gennari, Jeffrey E. Nelson, Jeffrey Russell, Ya-Chieh Lai, Jac Paul Condella
  • Patent number: 10777422
    Abstract: In a method according to an embodiment, before etching a target layer of a wafer, a main surface of the target layer is divided into a plurality of areas. A difference value between a groove width of a mask and a reference value of the groove width is calculated for each of the plurality of areas, a temperature of the target layer is adjusted by using correspondence data indicating correspondence between a temperature of the target layer and a film thickness of a formed film. Then, a film is formed on the mask for each atom layer, and a film having a film thickness corresponding to the difference value is formed on the mask to correct the groove width in each of the plurality of areas to the reference value.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: September 15, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yoshihide Kihara, Toru Hisamatsu, Masanobu Honda
  • Patent number: 10757423
    Abstract: Apparatus and methods for encoding panoramic content, such as by a wide field of view and large image size. In one implementation, a panoramic image may be mapped to a cube, equirectangular or any other projection e.g., icosahedron or octahedron. Projection may be selected adaptively based on evaluation of the panoramic content. Content evaluation may include obtaining rate distortion cost metric for a given projection configuration including projection type, projection arrangement, and projection orientation. Projection configuration with the lowest cost may be selected as target projection for encoding content. As content composition changes (e.g., object motion, texture presence and/or location) projection may be adaptively selected to match changes in the content. Adaptive content selection methodology may provide for a lower encoded bitrate for a given encoded quality and/or higher quality for a given bitrate.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: August 25, 2020
    Assignee: GoPro, Inc.
    Inventor: Adeel Abbas
  • Patent number: 10755025
    Abstract: Disclosed herein is a computer-implemented method for determining an overlapping process window (OPW) of an area of interest on a portion of a design layout for a device manufacturing process for imaging the portion onto a substrate, the method including: obtaining a plurality of features in the area of interest; obtaining a plurality of values of one or more processing parameters of the device manufacturing process; determining existence of defects, probability of the existence of defects, or both in imaging the plurality of features by the device manufacturing process under each of the plurality of values; and determining the OPW of the area of interest from the existence of defects, the probability of the existence of defects, or both.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: August 25, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Frank Gang Chen, Joseph Werner De Vocht, Yuelin Du, Wanyu Li, Yen-Wen Lu
  • Patent number: 10739685
    Abstract: Photoresist layers are exposed to an exposure beam by using an exposure tool assembly, wherein the photoresist layers coat semiconductor substrates and wherein for each exposure a current exposure parameter set is used that includes at least a defocus value and an exposure dose. The exposed photoresist layers are developed, wherein resist patterns are formed from the photoresist layers. Feature characteristics in the resist patterns and/or in substrate patterns derived from the resist patterns are measured. The current exposure parameter set is updated in response to deviations of the measured feature characteristics from target feature characteristics. De-corrected feature characteristics of hypothetical resist patterns are estimated, which would be formed without updating the exposure parameter set. In response to information obtained from the de-corrected feature characteristics the measurement strategy for the feature characteristics may be changed or the current exposure parameter set may be updated.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: August 11, 2020
    Assignee: Qoniac GmbH
    Inventors: Stefan Buhl, Boris Habets, Wan-Soo Kim
  • Patent number: 10727143
    Abstract: A pattern of core material is formed on a wafer to include core features that have a critical dimension. A trim amount indicates an average amount of thickness to be removed from vertically oriented surfaces of the core features. A trim profile indicates how much variation in removal of thickness from vertically oriented surfaces of the core features is to be applied as a function of radial location on the wafer. A first set of data correlates the trim amount to one or more plasma trim process parameters. A second set of data correlates the trim profile to one or more plasma trim process parameters. Based on the trim amount, trim profile, and first and second sets of data, a set of plasma trim process parameters to achieve the trim amount and trim profile on the wafer is determined and a corresponding plasma trim process is performed on the wafer.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: July 28, 2020
    Assignee: Lam Research Corporation
    Inventors: Pulkit Agarwal, Adrien Lavoie, Ravi Kumar, Purushottam Kumar
  • Patent number: 10725383
    Abstract: Methods include inputting an array of pixels, where each pixel in the array of pixels has a pixel dose. The array of pixels represents dosage on a surface to be exposed with a plurality of patterns, each pattern of the plurality of patterns having an edge. A target bias is input. An edge of a pattern in the plurality of patterns is identified. For each pixel which is in a neighborhood of the identified edge, a calculated pixel dose is calculated such that the identified edge is relocated by the target bias. The array of pixels with the calculated pixel doses is output. Systems for performing the methods are also disclosed.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: July 28, 2020
    Assignee: D25, Inc.
    Inventor: Harold Robert Zable
  • Patent number: 10710355
    Abstract: A method of slicing printing color 3D object and a color 3D printing system; the method includes following steps: execute a slicing process to a color 3D object for obtaining a plurality of layers of slice objects; analyze one of the pluralities of layers of the slice objects for generating sintering control data and color control data; lay a layer of powder; color the layer of powder according to the color control data; sinter the colored powder according to the sintering control data for completing printing one layer of the slice objects; perform repeatedly above steps until all layers of the slice objects are printed and a color stereoscopic physical model is generated. The method can effectively generate a color stereoscopic physical model. In addition, because of the adoption of laser sintering technology, the color stereoscopic physical model generated by the present disclosed example has great strength.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: July 14, 2020
    Assignees: XYZPRINTING, INC., KINPO ELECTRONICS, INC.
    Inventor: Chung-Ju Chen
  • Patent number: 10691028
    Abstract: Methods and systems for providing overlay corrections are provided. A method may include: selecting an overlay model configured to perform overlay modeling for a wafer; obtaining a first set of modeled results from the overlay model, the first set of modeled results indicating adjustments applicable to a plurality of term coefficients of the overlay model; calculating a significance matrix indicating the significance of the plurality of term coefficients; identifying at least one less significant term coefficient among the plurality of term coefficients based on the calculated significance matrix; obtaining a second set of modeled results from the overlay model, the second set of modeled results indicating adjustments applicable to the plurality of term coefficients except for the identified at least one less significant term coefficient; and providing the second set of modeled results to facilitate overlay correction.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: June 23, 2020
    Assignee: KLA-Tencor Corporation
    Inventors: Hoyoung Heo, William Pierson, Jeremy Nabeth, Sanghuck Jeon, Onur N. Demirer, Miguel Garcia-Medina, Soujanya Vuppala
  • Patent number: 10663870
    Abstract: A method including obtaining a plurality of gauges of a plurality of gauge patterns for a patterning process, each gauge pattern configured for measurement of a parameter of the patterning process when created as part of the patterning process, and creating a selection of one or more gauges from the plurality of gauges, wherein a gauge is included in the selection provided the gauge and all the other gauges, if any, of the same gauge pattern, or all of the one or more gauges of the same gauge pattern linked to the gauge, pass a gauge printability check.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: May 26, 2020
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Jun Chen, Thomas I. Wallow, Bart Laenens, Yi-Hsing Peng
  • Patent number: 10663872
    Abstract: A lithographic apparatus includes a patterning device support to support a patterning device, the patterning device system including a moveable structure movably arranged relative to an object, a patterning device holder movably arranged relative to the movable structure to hold the patterning device, an actuator to move the movable structure relative to the object, and an ultra short stroke actuator to move the patterning device holder with respect to the movable structure; a substrate support to hold a substrate; a projection system to project a patterned radiation beam onto a target portion of the substrate; a transmission image sensor for measuring a position of the patterned radiation beam downstream of the projection system; and a calibrator for determining a relationship between magnitude of an applied control signal to the ultra short stroke actuator and resulting change in position of the patterned radiation beam and/or patterning device holder and/or patterning device.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: May 26, 2020
    Assignee: ASML Netherlands B.V.
    Inventor: Hans Butler
  • Patent number: 10663868
    Abstract: The present disclosure, in some embodiments, relates to a photolithography tool. The photolithography tool includes an illumination source configured to generate electromagnetic radiation and projection optics configured to focus the electromagnetic radiation onto a photosensitive material overlying a substrate according to a pattern on a photomask. A dynamic focal element is configured to dynamically change positions at which the electromagnetic radiation is focused over the substrate during exposure of the photosensitive material. The positions at which the electromagnetic radiation is focused define a plurality of depths of focus. The plurality of depths of focus respectively span a different spatial region within the photosensitive material that is smaller than a thickness of the photosensitive material.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jun-Yih Yu, De-Fang Huang, De-Chen Tseng, Jia-Feng Chang, Li-Fang Hsu
  • Patent number: 10656531
    Abstract: A process of characterizing a process window of a patterning process, the process including: obtaining a set of inspection locations for a pattern, the pattern defining features to be applied to a substrate with a patterning process, the set of inspection locations corresponding to a set of the features, the set of features being selected from among the features according to sensitivity of the respective features to variation in one or more process characteristics of the patterning process; patterning one or more substrates under varying process characteristics of the patterning process; and determining, for each of the variations in the process characteristics, whether at least some of the set of features yield unacceptable patterned structures on the one or more substrates at corresponding inspection locations.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: May 19, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Te-Sheng Wang, Xiang Wan
  • Patent number: 10656535
    Abstract: A method and apparatus is disclosed for monitoring critical dimensions in a pattern of 1-dimensional and/or 2-dimensional features, produced on a substrate in a process step that is part of or related to a manufacturing process for producing a semiconductor device, the process step being performed in accordance with a predefined pattern design, wherein one or more metrology targets (1) are added to the pattern design. The targets comprise one or more versions of an asymmetric metrology mark, each version of the mark comprising a uniform portion (2) and a periodic portion (3), the latter comprising a regular array of parallel line-shaped features or an array of 2-dimensional features. The design width of the features is situated in a range situated around a nominal design width w0. A position-related parameter S is defined that is essentially proportional to the design widths in the range.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: May 19, 2020
    Assignee: IMEC VZW
    Inventors: Christopher Ausschnitt, Vincent Truffert
  • Patent number: 10649335
    Abstract: A substrate processing method, includes acquiring a height distribution along a radial direction of a substrate in a peripheral edge portion of a front surface of the substrate, forming an underlayer film on the entire front surface of the substrate so as to correct a drop of a height of the peripheral edge portion based on the height distribution, and forming a resist film on the entire surface of the underlayer film.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: May 12, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Teruhiko Kodama, Masashi Enomoto, Masahide Tadokoro, Takafumi Hashimoto
  • Patent number: 10591851
    Abstract: An image forming apparatus, in which an image forming method is performed, includes an image forming device to form an image on a recording medium, a reading device to scan the recording medium having a mark and generate a scanned image, and circuitry to calculate a correction value to adjust a position of the image to be formed on the recording medium, based on the scanned image. The circuitry calculates the correction value to adjust a position of an image to be formed on a second face of the recording medium based on a first scanned image generated from a first face of the recording medium, within a period from when the first scanned image is generated from the first face to when the image starts to be formed on the second face.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: March 17, 2020
    Assignee: Ricoh Company, Ltd.
    Inventor: Yukifumi Kobayashi
  • Patent number: 10585361
    Abstract: A projection exposure apparatus is disclosed, including a focal plane measuring system (8) and an alignment measuring system (9) both disposed between a reticle stage (3) and a substrate stage (4). The alignment measuring system (9) is capable of focusing. The focal plane measuring system (8) measures variation in the surface profile of a substrate (5), and the alignment measuring system (9) effectuates focusing based on data obtained from the measurement performed by the focal plane measuring system (8). After the completion of the focusing, coordinates of various points on the substrate (5) in the alignment measuring system (9) are those of the points that have experienced the profile variation of the substrate (5). A relative positional relationship between the reticle (2) and the substrate (5) that has undergone the profile variation can be computationally derived from the changes in the coordinates of the points, and compensation can be accomplished by moving the substrate stage (4).
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: March 10, 2020
    Assignee: SHANGHAI MICRO ELECTRONICS EQUIPMENT (GROUP) CO., LTD.
    Inventor: Yuefei Chen
  • Patent number: 10570507
    Abstract: An apparatus for controlling an operation of a machine includes an optical recognition system, a control unit, and a remote control interface. The optical recognition system is configured to monitor and obtain actual operation information displayed on a panel of a processing machine in accordance with an operation time. The control unit is configured to receive the actual operation information and check the actual operation information with expected operation information. The expected operation information is obtained based on an operation model which is already built up corresponding to a current fabrication process. Deviation information between the actual operation information and the expected operation information is determined and converted into a parameter set. The remote control interface receives the parameter set and converts the parameter set into a control signal set to control the operation of the processing machine.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: February 25, 2020
    Assignee: United Microelectronics Corp.
    Inventors: Neng-Hsing Shen, Chien-Wen Yang, Chun-Man Li, Ji-Fu Kung, Ching-Pei Lin
  • Patent number: 10572697
    Abstract: Computer-implemented methods of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation to process parameter values characterizing the semiconductor device fabrication operation are disclosed. The methods involve generating cost values using a computationally predicted result of the semiconductor device fabrication operation and a metrology result produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under a set of fixed process parameter values. The determination of the parameters of the process simulation model may employ pre-process profiles, via optimization of the resultant post-process profiles of the parameters against profile metrology results. Cost values for, e.g., optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide optimization.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: February 25, 2020
    Assignee: Lam Research Corporation
    Inventors: Ye Feng, Marcus Musselman, Andrew D. Bailey, III, Mehmet Derya Tetiker, Saravanapriyan Sriraman, Yan Zhang, Julien Mailfert
  • Patent number: 10571340
    Abstract: A wavefront measuring device and method obtain wavefront information of an optical system. The method including: irradiating the optical system with a light beam; allowing the light beam passed via the optical system to come into a diffraction grating having periodicity in a first direction; and obtaining the wavefront information based on an interference fringe formed by light beams generated from the diffraction grating. The diffraction grating including: first portions which allow light to pass therethrough; and second portions which shield light, each of the second portions being provided between two of the first portions. A ratio between a width of one of the first portions in the first direction and a width of one of the second portions in the first direction is changed in the first direction, the one of the first portions and the one of the second portions being adjacent to each other.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: February 25, 2020
    Assignee: NIKON CORPORATION
    Inventors: Katsura Otaki, Katsumi Sugisaki, Takashi Gemma
  • Patent number: 10553575
    Abstract: A semiconductor device includes an array of Engineering Change Order (ECO) cells. Each of the ECO cells in the array includes a first metal pattern and a second metal pattern. Each of the ECO cells in the array further includes a plurality of active area patterns isolated from each other and arranged between the first and second metal patterns. Each of the ECO cells in the array further includes a first central metal pattern overlapping the first metal pattern. Each of the ECO cells in the array further includes a via electrically connecting the first central metal pattern to the first metal pattern. The plurality of active area patterns is arranged symmetrically about the first central metal pattern.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: February 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Chun Tien, Ya-Chi Chou, Hui-Zhong Zhuang, Chun-Fu Chen, Ting-Wei Chiang, Hsiang Jen Tseng
  • Patent number: 10545412
    Abstract: A method to collect data and train, validate and deploy statistical models to predict overlay errors using patterned wafer geometry data and other relevant information includes selecting a training wafer set, measuring at multiple lithography steps and calculating geometry differences, applying a plurality of predictive models to the training wafer geometry differences and comparing predicted overlay to the measured overlay on the training wafer set. The most accurate predictive model is identified and the results fed-forward to the lithography scanner tool which can correct for these effects and reduce overlay errors during the wafer scan-and-expose processes.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: January 28, 2020
    Assignee: KLA-Tencor Corporation
    Inventors: Wei Chang, Krishna Rao, Joseph Gutierrez, Ramon Olavarria, Craig MacNaughton, Amir Azordegan, Prasanna Dighe
  • Patent number: 10527929
    Abstract: A method of fabricating a semiconductor device includes designing a layout, performing an optical proximity correction (OPC) process to correct the designed layout, fabricating a first photomask using the corrected designed layout, and forming patterns on a substrate using the first photomask. The OPC process includes generating an OPC model and correcting the designed layout using the generated OPC model. The generation of the OPC model includes rasterizing a planar image of an actual pattern to obtain first label data, rasterizing a simulation image of a simulation pattern to obtain second label data, the simulation pattern being obtained using the OPC model, in which a parameter set including process parameters is set, comparing the first label data with the second label data to obtain comparison data, and correcting the process parameters of the parameter set, based on the comparison data.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: January 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Moon-Gyu Jeong
  • Patent number: 10520831
    Abstract: A technique enabling a stable resist pattern forming process, when substrate processing apparatuses that perform a resist coating process separately from a developing process. A wafer having been heated after a resist coating process in a first substrate processing apparatus is also heated before an exposure process in a second substrate processing apparatus. Thus, even when amine in an atmosphere adheres to the wafer while it is being transported from the first substrate processing apparatus to the second substrate processing apparatus, the amine scatters by the heating process. At least one of a heating time and a heating temperature is adjusted based on a substrate rest time which includes a period of time between a time point at which a FOUP 10 is unloaded from the first substrate processing apparatus and a time point at which the FOUP 10 is loaded into the second substrate processing apparatus.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: December 31, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Masashi Enomoto, Yoshihiro Kondo
  • Patent number: 10520829
    Abstract: Examples of optical proximity correction (OPC) based computational lithography techniques are disclosed herein. An exemplary method includes receiving an IC design layout that includes an IC feature, the IC feature specifying a mask feature for selectively exposing to radiation a portion of a photoresist disposed on a substrate; determining topographical information of an underlying layer disposed on the substrate between the photoresist and the substrate; performing an OPC process on the IC feature to generate a modified IC feature; and providing a modified IC design layout including the modified IC feature for fabricating a mask based on the modified IC design layout. The OPC process may use the topographical information of the underlying layer to compensate for an amount of radiation directed towards the portion of the photoresist so as to expose the portion of the photoresist to a target dosage of radiation.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Chun Wang, Chi-Ping Liu, Cheng Kun Tsai, Wei-Chen Chien, Wen-Chun Huang
  • Patent number: 10504745
    Abstract: In a method according to an embodiment, before etching a target layer of a wafer, a main surface of the target layer is divided into a plurality of areas. A difference value between a groove width of a mask and a reference value of the groove width is calculated for each of the plurality of areas, a temperature of the target layer is adjusted by using correspondence data indicating correspondence between a temperature of the target layer and a film thickness of a formed film. Then, a film is formed on the mask for each atom layer, and a film having a film thickness corresponding to the difference value is formed on the mask to correct the groove width in each of the plurality of areas to the reference value.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: December 10, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yoshihide Kihara, Toru Hisamatsu, Masanobu Honda
  • Patent number: 10493672
    Abstract: The present invention provides an imprint apparatus which forms a pattern of an imprint material onto a substrate by using a mold, the apparatus including a control unit configured to provide a user interface for displaying a first map indicating a supply position of the imprint material to be supplied onto the substrate, an adjustment window for adjusting a value of an apparatus parameter which is set in the imprint apparatus and used to change a supply position of the imprint material, and a second map indicating a supply position of the imprint material after adjustment of the value of the apparatus parameter.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: December 3, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Sentaro Aihara, Yeshwanth Srinivasan, Steven Wayne Burns
  • Patent number: 10489547
    Abstract: A method of designing a layout includes assigning a first color group to a plurality of first routing tracks. The method includes assigning a second color group to a plurality of second routing tracks. A first routing track is between adjacent second routing tracks. The method includes assigning a color from the first color group to each default conductive element along each first routing track. A color of a first default conductive element along each first routing track is different from a color of an adjacent default conductive element along a same first routing track. The method includes assigning a color from the second color group to each default conductive element along each second routing track. A color of a first default conductive element along each second routing track is different from a color of an adjacent default conductive element along a same second routing track.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: November 26, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Hung Lin, Chung-Hsing Wang, Yuan-Te Hou
  • Patent number: 10488760
    Abstract: A parameter acquiring method for dose correction of a charged particle beam includes writing evaluation patterns on a substrate coated with resist; writing, while varying writing condition, a peripheral pattern on a periphery of any different one of the evaluation patterns, after an ignorable time as to influence of resist temperature increase due to writing of an evaluation pattern concerned has passed; and calculating a parameter for defining correlation among a width dimension change amount of the evaluation pattern concerned, a temperature increase amount of the evaluation pattern concerned, and a backscatter dose reaching the evaluation pattern concerned, by using, under each writing condition, a width dimension of the evaluation pattern concerned, the temperature increase amount of the evaluation pattern concerned at each shot time, and the backscatter dose reaching the evaluation pattern concerned from each shot.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: November 26, 2019
    Assignee: NuFlare Technology, Inc.
    Inventor: Haruyuki Nomura
  • Patent number: 10461229
    Abstract: Embodiments of the invention include a light emitting diode including a semiconductor structure including an active layer disposed between an n-type region and a p-type region. The active layer emits UV radiation. A first metal layer is in direct contact with the p-type region. A second metal layer is in direct contact with the n-type region. The first and second metal layers are both formed on a first side of the semiconductor structure. A transparent optic is optically coupled to a major surface of the light emitting diode.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: October 29, 2019
    Assignee: RayVio Corporation
    Inventors: Robert S. West, Yitao Liao, Douglas A. Collins
  • Patent number: 10444629
    Abstract: Methods include inputting an array of pixels, where each pixel in the array of pixels has a pixel dose. The array of pixels represents dosage on a surface to be exposed with a plurality of patterns, each pattern of the plurality of patterns having an edge. A target bias is input. An edge of a pattern in the plurality of patterns is identified. For each pixel which is in a neighborhood of the identified edge, a calculated pixel dose is calculated such that the identified edge is relocated by the target bias. The array of pixels with the calculated pixel doses is output. Systems for performing the methods are also disclosed.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: October 15, 2019
    Assignee: D2S, Inc.
    Inventor: Harold Robert Zable
  • Patent number: 10431718
    Abstract: Embodiments are related to integrated circuit (IC) fabrication and, more particularly, to a fluidic assembly process for the placement of light emitting diodes on a direct-emission display substrate.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: October 1, 2019
    Assignee: eLux Inc.
    Inventors: Mark Albert Crowder, Paul J. Schuele, Changqing Zhan, Kenji Alexander Sasaki, Kurt Michael Ulmer
  • Patent number: 10423076
    Abstract: A method including: obtaining at least a characteristic of deformation of a resist layer in a first direction, as if there were no deformation in any directions perpendicular to the first direction; obtaining at least a characteristic of deformation of the resist layer in a second direction as if there were no deformation in the first direction, the second direction being perpendicular different to from the first direction; and obtaining at least a characteristic of three-dimensional deformation of the resist layer based on the characteristic of the deformation in the first direction and the characteristic of the deformation in the second direction.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: September 24, 2019
    Assignee: ASML Netherlands B.V.
    Inventor: Peng Liu
  • Patent number: 10409168
    Abstract: Measurement data is obtained for calibration fields that have been exposed by a lithographic apparatus using different field layouts and exposure sequences. The measurement data is classified in subsets by scan direction, step direction, field size and other variables. The measurement data is indexed by a time value that varies through each exposure sequence. Time values within different exposure sequences can be related using a normalized time value based on the beginning and end of each exposure sequence. An inter-field performance model is calculated for each subset. An intra-field component of a performance model is calculated with time as a third dimension. The time-indexed performance model is used to determine intra-field corrections for a variety of product exposures having product layouts and product exposure sequences different to the calibration fields, based on time and other a variables of the product layout and product exposure sequence.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: September 10, 2019
    Assignee: ASML Netherlands B.V.
    Inventor: Alexander Alexandrovich Danilin
  • Patent number: 10401279
    Abstract: Systems and methods for prediction and measurement of overlay errors are disclosed. Process-induced overlay errors may be predicted or measured utilizing film force based computational mechanics models. More specifically, information with respect to the distribution of film force is provided to a finite element (FE) model to provide more accurate point-by-point predictions in cases where complex stress patterns are present. Enhanced prediction and measurement of wafer geometry induced overlay errors are also disclosed.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: September 3, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Pradeep Vukkadala, Haiguang Chen, Jaydeep Sinha, Sathish Veeraraghavan
  • Patent number: 10394133
    Abstract: A laser unit management system may include a server configured to hold first information provided with access limitation that allows an access with a first access authorization, second information provided with access limitation that allows an access with a second access authorization, and third information provided with access limitation that allows both an access with the first access authorization and an access with the second access authorization; and a laser unit including a laser output section and a controller, the laser output section being configured to output pulsed laser light toward an exposure unit that is configured to perform wafer exposure, the controller being configured to store the first information, the second information, and the third information in the server. The second information may include wafer-exposure-related information on the exposure unit and laser-control-related information on the laser unit that are in association with each other.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: August 27, 2019
    Assignee: GIGAPHOTON INC.
    Inventors: Yuji Minegishi, Yutaka Igarashi, Takeshi Ohta
  • Patent number: 10381221
    Abstract: A processing method in one embodiment includes: a step that takes an image of the end face of a reference substrate, whose warp amount is known, over the whole periphery thereof using a camera to obtain shape data of the end face of the reference substrate over the whole periphery of the reference substrate; a step that takes an image of the end face of a substrate over the whole periphery thereof using a camera to obtain shape data of the end face of the substrate over the whole periphery of the substrate; a step that calculates warp amount of the substrate based on the obtained shape data; a step that forms a resist film on a surface of the substrate; a step that determines the supply position from which an organic solvent is to be supplied to a peripheral portion of the resist film and dissolves the peripheral portion by the solvent supplied from the supply position to remove the same from the substrate.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: August 13, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Yasuaki Noda, Tadashi Nishiyama
  • Patent number: 10372113
    Abstract: Two or more color data can be combined to form a new data source to enhance sensitivity to defocus signal. Defocus detection can be performed on the newly formed data source. In a setup step, a training wafer can be used to select the best color combination, and obtain defocus detection threshold. This can include applying a segment mask, calculating mean intensities of the segment, determining a color combination that optimizes defocus sensitivity, and generating a second segment mask based on pixels that are above a threshold to sensitivity. In a detection step, the selected color combination is calculated, and the threshold is applied to obtain defocus detection result.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: August 6, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Xuguang Jiang, Shifang Li, Yong Zhang
  • Patent number: 10372043
    Abstract: A method for improving a lithographic process for imaging a portion of a design layout onto a substrate using a lithographic apparatus, the method including: obtaining a relationship of a characteristic of one or more features in the portion with respect to dose; obtaining a value of the characteristic; and obtaining a target dose based on the value of the characteristic and the relationship.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: August 6, 2019
    Assignee: ASML Netherlands B.V.
    Inventors: Gang Chen, Te-Sheng Wang
  • Patent number: 10365085
    Abstract: A method for measuring a thickness of a thin film includes: a step of basing on a training database to establish an artificial neural network, the training database including a plurality of modified spectra and a plurality of film thicknesses corresponding individually to the plurality of modified spectra; a step of measuring a sample having a coated film so as to obtain a spectrum; and, a step of running the artificial neural network already trained by the plurality of modified spectra so as to use the spectrum to estimate a thickness of the coated film on the sample. In addition, a system related to the method for measuring a thickness of a thin film is provided to include a measuring unit, a spectrometer and a processing unit.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: July 30, 2019
    Assignee: INSTITUTE OF NUCLEAR ENERGY RESEARCH, ATOMIC ENERGY COUNCIL, EXECUTIVE YUAN, R.O.C.
    Inventors: Tzong-Daw Wu, Jiun-Shen Chen, Ching-Pei Tseng, Cheng-Chang Hsieh
  • Patent number: 10340196
    Abstract: The selection of metrology targets for use in a focus and dose application includes providing a FEM wafer including a plurality of fields with one or more metrology targets, measuring the one or more metrology targets within each field of the FEM wafer, performing a regression process on measurement results from the one or more selected fields of the FEM wafer to determine one or more DOI values for the one or more metrology targets of the one or more selected fields, calculating one or more diagnostic parameters for the one or more metrology targets of the one or more selected fields based on the regression process performed on the one or more selected fields of the FEM wafer, and identifying a set of candidate metrology targets based on the one or more calculated diagnostic parameters of the one or more selected fields of the FEM wafer.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: July 2, 2019
    Assignee: KLA-Tencor Corporation
    Inventors: Roie Volkovich, Hiroyuki Kurita, Yoel Feler
  • Patent number: 10324369
    Abstract: Embodiments of the present disclosure provide a method of generating mandrel patterns. A mandrel pattern is generated by constructing a boundary box, initiating a plurality of lead mandrels, and extending the lead mandrels across the boundary box. When a pattern region includes holes, portions of mandrels are removed from the holes after extension of the leading mandrels.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: June 18, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Yu Wang, Nian-Fuh Cheng, Chia-Ping Chiang, Ming-Hui Chih, Wen-Chun Huang, Tsai-Sheng Gau
  • Patent number: 10310386
    Abstract: Methods of reducing a pattern displacement error, contrast loss, best focus shift, and/or tilt of a Bossung curve of a portion of a design layout used in a lithographic process for imaging that portion onto a substrate using a lithographic apparatus. The methods include adjusting an illumination source of the lithographic apparatus, placing one or more assist features onto, or adjusting a position and/or shape of one or more existing assist features in, the portion. Adjusting the illumination source and/or the one or more assist features may be by an optimization algorithm.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: June 4, 2019
    Assignee: ASML Netherlands B.V.
    Inventors: Duan-Fu Stephen Hsu, Feng-Liang Liu
  • Patent number: 10311197
    Abstract: Layout design data is seeded with sampling markers. The sampling markers are used to determine patterning scores for patterning clusters in the layout design data, such that a patterning score corresponds to a particular coloring arrangement, and the value of a patterning score corresponds to how many of the sampling markers have a given color. Coloring arrangements are then applied to the patterning clusters based upon the patterning scores.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: June 4, 2019
    Assignee: Mentor Graphics Corporation
    Inventor: Fedor G Pikus
  • Patent number: 10313686
    Abstract: Apparatus and methods for encoding panoramic content, such as by a wide field of view and large image size. In one implementation, a panoramic image may be mapped to a cube, equirectangular or any other projection e.g., icosahedron or octahedron. Projection may be selected adaptively based on evaluation of the panoramic content. Content evaluation may include obtaining rate distortion cost metric for a given projection configuration including projection type, projection arrangement, and projection orientation. Projection configuration with the lowest cost may be selected as target projection for encoding content. As content composition changes (e.g., object motion, texture presence and/or location) projection may be adaptively selected to match changes in the content. Adaptive content selection methodology may provide for a lower encoded bitrate for a given encoded quality and/or higher quality for a given bitrate.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: June 4, 2019
    Assignee: GoPro, Inc.
    Inventor: Adeel Abbas
  • Patent number: 10311186
    Abstract: Methodologies and a device for assessing integrated circuit and pattern for yield risk based on 3D simulation of semiconductor patterns are provided. Embodiments include generating, with a processor, a 3D simulation of semiconductor patterns; obtaining critical dimensions of distances between layers or within a layer of the 3D simulation of semiconductor patterns; comparing the set of critical dimensions with predefined minimum dimensions; and yield scoring each of the semiconductor patterns of the 3D simulation based on the comparing step.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: June 4, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jaime Bravo, Vikrant Chauhan, Piyush Pathak, Shobhit Malik, Uwe Paul Schroeder
  • Patent number: 10297419
    Abstract: The present invention has an object to provide a scanning electron microscope which suppresses a potential gradient produced by preliminary charge without changing lens conditions of an electron microscope. As an aspect to achieve the above object, there is proposed a scanning electron microscope in which a scanning deflector is controlled so that a second beam is scanned to detect electrons released from a sample after scanning a first beam on the sample to charge the surface of the sample and the first beam is scanned so that charge density in a surrounding part within a scanned area by the first beam is increased relatively as compared with a center part within the scanned area by the first beam.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: May 21, 2019
    Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Shahedul Hoque, Hajime Kawano