Including Control Feature Responsive To A Test Or Measurement Patents (Class 430/30)
  • Patent number: 11651936
    Abstract: A charged particle beam apparatus includes: a specimen chamber; a specimen holder that is disposed in the specimen chamber; a specimen exchange chamber that is connected to the specimen chamber; a transporting mechanism that transports a specimen between the specimen chamber and the specimen exchange chamber; a first temperature sensor that measures a temperature of the specimen holder; a second temperature sensor that measures a temperature of the transporting mechanism; and a control unit. The control unit: calculates a temperature difference between the specimen holder and the transporting mechanism based on the temperature of the specimen holder and the temperature of the transporting mechanism when the control unit has received an instruction to transport a specimen; determining whether the temperature difference is a threshold or more; and stopping transportation of a specimen when the control unit has determined that the temperature difference is the threshold or more.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: May 16, 2023
    Assignee: JEOL Ltd.
    Inventors: Naoki Fujimoto, Izuru Chiyo
  • Patent number: 11639901
    Abstract: A test structure for use in metrology measurements of a sample pattern formed by periodicity of unit cells, each formed of pattern features arranged in a spaced-apart relationship along a pattern axis, the test structure having a test pattern, which is formed by a main pattern which includes main pattern features of one or more of the unit cells and has a symmetry plane, and a predetermined auxiliary pattern including at least two spaced apart auxiliary features located within at least some of those features of the main pattern, parameters of which are to be controlled during metrology measurements.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: May 2, 2023
    Assignee: NOVA LTD
    Inventors: Gilad Barak, Oded Cohen, Igor Turovets
  • Patent number: 11635699
    Abstract: Methods for training a process model and determining ranking of simulated patterns (e.g., corresponding to hot spots). A method involves obtaining a training data set including: (i) a simulated pattern associated with a mask pattern to be printed on a substrate, (ii) inspection data of a printed pattern imaged on the substrate using the mask pattern, and (iii) measured values of a parameter of the patterning process applied during imaging of the mask pattern on the substrate; and training a machine learning model for the patterning process based on the training data set to predict a difference in a characteristic of the simulated pattern and the printed pattern. The trained machine learning model can be used for determining a ranking of hot spots. In another method a model is trained based on measurement data to predict ranking of the hot spots.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: April 25, 2023
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Youping Zhang, Maxime Philippe Frederic Genin, Cong Wu, Jing Su, Weixuan Hu, Yi Zou
  • Patent number: 11630394
    Abstract: Disclosed is a method for lithographically producing a target structure on a non-planar initial structure by exposing a photoresist by means of a lithography beam. In the inventive method, the topography of a surface of the non-planar initial structure is detected. A test parameter for the lithography beam is used and an interaction of the lithography beam with the initial structure and the resultant change in the lithography beam and/or the target structure to be produced are determined. A correction parameter for the lithography beam is determined such that the change in the lithography beam and/or the target structure to be produced that is caused by the interaction of the lithography beam with the initial structure is reduced. The desired target structure on the initial structure is produced by exposing the photoresist by means of the lithography beam using the correction parameter.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: April 18, 2023
    Assignee: Karlsruhe Institute of Technology
    Inventors: Christian Koos, Tobias Hoose, Philipp Dietrich, Matthias Blaicher, Maria Laura Gödecke, Nicole Lindenmann
  • Patent number: 11626304
    Abstract: The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: April 11, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzu-Cheng Lin, Y. Y. Peng, Jerry Wang, Kewei Zuo, Chien Rhone Wang
  • Patent number: 11624981
    Abstract: Computer implemented methods and computer program products have instructions for generating transfer functions that relate segments on lithography photomasks to features produced by photolithography and etching using such segments. Such methods may be characterized by the following elements: (a) receiving after development inspection metrology results produced from one or more first test substrates on which resist was applied and patterned using a set of design layout segments; (b) receiving after etch inspection metrology results produced from one or more second test substrates which were etched after resist was applied and patterned using said set of design layout segments; and (c) generating the transfer function using the set of design layout segments together with corresponding after development inspection metrology results and corresponding after etch inspection metrology results.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: April 11, 2023
    Assignee: Lam Research Corporation
    Inventors: Saravanapriyan Sriraman, David M. Fried
  • Patent number: 11618183
    Abstract: A process for the production of a fibre-composite material, the process including the following steps: a) a fibre bundle is conducted over at least one deflection bar having radially circumferential rounded elevations, thus being expanded; b) the expanded fibre bundle is subsequently drawn into an impregnation chamber; c) a melt is applied to the expanded fibre bundle; and d) the fibre bundle impregnated with melt is drawn through a take-off die at the end of the apparatus, and a corresponding device, which achieves very good impregnation quality.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: April 4, 2023
    Assignee: Evonik Operations GmbH
    Inventors: Mark Reinhard Berlin, Udo Sondermann
  • Patent number: 11609506
    Abstract: A method for in-situ wave front detection within an inspection system is disclosed. The method includes generating light with a light source and directing the light to a stage-level reflective mask grating structure disposed on a mask stage. The method includes directing light reflected from the stage-level reflective structure to a detector-level mask structure disposed in a plane of a detector and then collecting, with an optical element, light reflected from the detector-level mask structure. The method includes forming a pupil image on the detector and laterally shifting the stage-level reflective mask, with the mask stage, across a grating period of the stage-level reflective mask grating structure to provide phase reconstruction for lateral shearing interferometry. The method includes selectively impinging light reflected from the optical element on the one or more sensors of the detector.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: March 21, 2023
    Assignee: KLA Corporation
    Inventor: Markus Mengel
  • Patent number: 11579537
    Abstract: According to one embodiment, a pattern inspection method includes detecting a region of a photomask having a pattern that differs from a corresponding design, acquiring an exposure focus shift information including an exposure focus shift amount of a portion of a substrate corresponding to the detected region of the photomask. The exposure focus shift amount for the detected region is acquired from the exposure focus shift information, and then a pass/fail determination for the detected region is performed based on an estimated pattern to be formed on the substrate.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: February 14, 2023
    Assignee: Kioxia Corporation
    Inventors: Keiko Morishita, Kosuke Takai
  • Patent number: 11580289
    Abstract: A method for determining a patterning device pattern. The method includes obtaining (i) an initial patterning device pattern having at least one feature, and (ii) a desired feature size of the at least one feature, obtaining, based on a patterning process model, the initial patterning device pattern and a target pattern for a substrate, a difference value between a predicted pattern of the substrate image by the initial patterning device and the target pattern for the substrate, determining a penalty value related the manufacturability of the at least one feature, wherein the penalty value varies as a function of the size of the at least one feature, and determining the patterning device pattern based on the initial patterning device pattern and the desired feature size such that a sum of the difference value and the penalty value is reduced.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: February 14, 2023
    Assignee: ASML Netherlands B.V.
    Inventors: Roshni Biswas, Rafael C. Howell, Cuiping Zhang, Ningning Jia, Jingjing Liu, Quan Zhang
  • Patent number: 11561481
    Abstract: Techniques for using open frame (E0) exposures for lithographic tool track/cluster monitoring are provided. In one aspect, a method for monitoring a lithographic process includes: performing open frame exposures E0 of at least one wafer coated with a photoresist using a photolithography tool; baking and developing the at least one wafer; performing a defect inspection of the at least one wafer to generate a haze map; grouping haze data from the haze map; and analyzing the haze data to identify a maximum E0 response dose E?.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: January 24, 2023
    Assignee: International Business Machines Corporation
    Inventors: Cody J. Murray, Ekmini Anuja De Silva, Christopher Frederick Robinson, Luciana Meli
  • Patent number: 11561477
    Abstract: A method including: obtaining data based an optical proximity correction for a spatially shifted version of a training design pattern; and training a machine learning model configured to predict optical proximity corrections for design patterns using data regarding the training design pattern and the data based on the optical proximity correction for the spatially shifted version of the training design pattern.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: January 24, 2023
    Assignee: ASML Netherlands B.V.
    Inventors: Jing Su, Yen-Wen Lu, Ya Luo
  • Patent number: 11550228
    Abstract: A lithography apparatus is provided. The lithography apparatus includes a wafer stage configured to secure a semiconductor wafer and having a plurality of electrodes. The lithography apparatus also includes an exposure tool configured to perform an exposure process by projecting an extreme ultraviolet (EUV) light on the semiconductor wafer. The lithography apparatus further includes a controller configured to control power supplied to the electrodes to have a first adjusted voltage during the exposure process for a first group of exposure fields on the semiconductor wafer so as to secure the semiconductor wafer to the wafer stage. The first adjusted voltage is in a range from about 1.6 kV to about 3.2 kV.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: January 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Kuan Wu, Po-Chung Cheng, Li-Jui Chen, Chih-Tsung Shih
  • Patent number: 11531279
    Abstract: A method for correcting misalignments is provided. An alignment for each device of a group of devices mounted on a substrate is determined. An alignment error for the group of devices mounted on the substrate is determined based on the respective alignment for each device. One or more correction factors are calculated based on the alignment error. The alignment error is corrected based on the one or more correction factors.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: December 20, 2022
    Assignee: Onto Innovation Inc.
    Inventors: Elvino da Silveira, Keith F. Best, Wayne Fitzgerald, Jian Lu, Xin Song, J. Casey Donaher, Christopher J. McLaughlin
  • Patent number: 11517941
    Abstract: The substrate processing method includes a hydrophilization step of hydrophilizing a surface of a substrate, a processing liquid supplying step of supplying a processing liquid to the hydrophilized surface of the substrate, a processing film forming step in which the processing liquid supplied to the surface of the substrate is solidified or cured to form a processing film on the surface of the substrate, and a peeling step in which a peeling liquid is supplied to the surface of the substrate to peel the processing film from the surface of the substrate. The peeling step includes a penetrating hole forming step in which the processing film is partially dissolved in the peeling liquid to form a penetrating hole in the processing film.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: December 6, 2022
    Inventors: Katsuya Akiyama, Yukifumi Yoshida
  • Patent number: 11520237
    Abstract: The present disclosure, in some embodiments, relates to a photolithography tool. The photolithography tool includes a source configured to generate electromagnetic radiation. A dynamic focal system is configured to provide the electromagnetic radiation to a plurality of different vertical positions over a substrate stage. The plurality of different vertical positions include a first position having a first depth of focus and a second position having a second depth of focus that is below the first depth of focus and that vertically overlaps the first depth of focus.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: December 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jun-Yih Yu, De-Fang Huang, De-Chen Tseng, Jia-Feng Chang, Li-Fang Hsu
  • Patent number: 11467484
    Abstract: A method for inspecting a reticle including a reflective layer on a reticle substrate is provided. The method may include loading the reticle on a stage, cooling the reticle substrate to a temperature lower than a room temperature, irradiating a laser beam to the reflective layer on the reticle substrate, receiving the laser beam using a photodetector to obtain an image of the reflective layer, and detect a particle defect on the reflective layer or a void defect in the reflective layer based on the image of the reflective layer.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: October 11, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seulgi Kim, Hyonseok Song, Inyong Kang, Kangwon Lee, JuHyoung Lee, Eunsik Jang
  • Patent number: 11468222
    Abstract: A method, includes, in part, defining a continuous signal, defining a threshold value, calibrating the continuous signal and the threshold value from measurements made on edges of one or more patterns on a mask and corresponding edges of the patterns on a wafer, convolving the continuous signal with a kernel to form a corrected signal, and establishing, by a processor, a probability of forming an edge at a point along the corrected signal in accordance with a difference between the value of the corrected signal at the point and the calibrated threshold value. The kernel is calibrated using the same measurements made on the patterns' edges.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: October 11, 2022
    Assignee: Synopsys, Inc.
    Inventors: Yudhishthir Prasad Kandel, Lawrence S. Melvin, III
  • Patent number: 11467509
    Abstract: A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: October 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Jie Lee, Shih-Chun Huang, Shih-Ming Chang, Ken-Hsien Hsieh, Yung-Sung Yen, Ru-Gun Liu
  • Patent number: 11454887
    Abstract: Disclosed is a method and associated inspection apparatus for measuring a characteristic of interest relating to a structure on a substrate. The inspection apparatus uses measurement radiation comprising a plurality of wavelengths. The method comprises performing a plurality of measurement acquisitions of said structure, each measurement acquisition being performed using measurement radiation comprising a different subset of the plurality of wavelengths, to obtain a plurality of multiplexed measurement signals. The plurality of multiplexed measurement signals are subsequently de-multiplexed into signal components according to each of said plurality of wavelengths, to obtain a plurality of de-multiplexed measurement signals which are separated according to wavelength.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: September 27, 2022
    Assignee: ASML Netherlands B.V.
    Inventor: Nitesh Pandey
  • Patent number: 11442366
    Abstract: A device manufacturing method, the method including: obtaining a measurement data time series of a plurality of substrates on which an exposure step and a process step have been performed; obtaining a status data time series relating to conditions prevailing when the process step was performed on at least some of the plurality of substrates; applying a filter to the measurement data time series and the status data time series to obtain filtered data; and determining, using the filtered data, a correction to be applied in an exposure step performed on a subsequent substrate.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: September 13, 2022
    Assignee: ASML Netherlands B.V.
    Inventors: Rizvi Rahman, Hakki Ergün Cekli, Cëdric Dësirë Grouwstra
  • Patent number: 11443420
    Abstract: There is provided a system and method of generating a metrology recipe usable for examining a semiconductor specimen, comprising: obtaining a first image set comprising a plurality of first images captured by an examination tool, obtaining a second image set comprising a plurality of second images, wherein each second image is simulated based on at least one first image, wherein each second image is associated with ground truth data; performing a first test on the first image set and a second test on the second image set in accordance with a metrology recipe configured with a first parameter set, and determining, in response to a predetermined criterion not being met, to select a second parameter set, configure the metrology recipe with the second parameter set, and repeat the first test and the second test in accordance with the metrology recipe configured with the second parameter set.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: September 13, 2022
    Assignee: Applied Materials Israel Ltd.
    Inventors: Roman Kris, Grigory Klebanov, Einat Frishman, Tal Orenstein, Meir Vengrover, Noa Marom, Ilan Ben-Harush, Rafael Bistritzer, Sharon Duvdevani-Bar
  • Patent number: 11435685
    Abstract: An image forming apparatus includes an image forming unit configured to perform a first image forming process and a second image forming process to form an image and a test image on a sheet; a reader, arranged in a conveyance path along which the sheet is conveyed, configured to read the test image on the sheet, the test image being formed by the image forming unit; a member; a controller configured to obtain, from the reader, reading data related to the test image on the sheet.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: September 6, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Akinobu Nishikata, Takashi Yokoya, Toshifumi Oikawa, Yutaka Ando, Koji Yumoto, Riki Fukuhara, Yuichiro Oda
  • Patent number: 11397380
    Abstract: A critical dimension measurement system includes a voltage measurement circuit, a control circuit, and a critical dimension measurement circuit. The voltage measurement circuit may measure potentials of mask patterns of a photomask. The control circuit may include an information storage circuit for storing distribution information on the potentials of the mask patterns, measured by the voltage measurement circuit, and information on layout patterns corresponding to the mask patterns of the photomask. The critical dimension measurement circuit may be operated, by the control circuit, in a first measurement mode and a second measurement mode running for a shorter time than the first measurement mode, and measure critical dimensions of the mask patterns.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: July 26, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won Joo Park, Hyung Joo Lee, Seuk Hwan Choi, Dong Seok Nam, Yoon Taek Han
  • Patent number: 11385436
    Abstract: The invention relates firstly to a method for determining a mechanical deviation on a displacement path of an optical zoom lens (03), in particular on a displacement path of an optical zoom lens (03) of a microscope. The optical zoom lens (03) is arranged in a beam path (01) between an object (19) to be recorded and an electronic image sensor (04). In a first method step, an optical marker is introduced into the beam path (01) at a position of the beam path (01) located between the object (19) to be recorded and the optical zoom lens (03), such that the optical marker passes the optical zoom lens (03) and then is depicted on an image in which a position of the optical marker is detected and determined. This is compared with a reference position of the optical marker in order to determine the mechanical deviation on the displacement path of the optical zoom lens (03).
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: July 12, 2022
    Assignee: CARL ZEISS MICROSCOPY GMBH
    Inventors: Daniel Stegmann, Daniel Harangozo, Peter Schacht, Thomas Milde
  • Patent number: 11379647
    Abstract: A method for optical proximity correction (OPC) comprises creating a semi-physical model of a mask for a current layer in an IC design layout using physical parameters of a lithography process used to create the mask, the semi-physical model specifying contours of the plurality of features of the mask. It is determined from design information whether the current layer is deformed by the one or more reference layers that overlap the current layer near the contours. Responsive to determining that the current layer is deformed by the one or more reference layers, the semi-physical model and the design information of the one or more reference layers are input into a trained machine learning algorithm to generate a contour shift prediction for the current layer, the contour shift prediction estimating a residual error of the semi-physical model. The contour shift prediction is then used for multilayer OPC correction of the current layer.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: July 5, 2022
    Assignee: Intel Corporation
    Inventors: Hyungjin Ma, Gregory Toepperwein, Nabil Laachi, Chihhui Wu, Vasudev Lal
  • Patent number: 11366400
    Abstract: A method of determining information indicating an arrangement of an imprint material in an imprint apparatus, includes repeating, by the imprint apparatus, a process of arranging an imprint material on a substrate in accordance with a provisional arrangement, forming a pattern by curing the imprint material in a state in which a mold is brought into contact with the imprint material, and changing the provisional arrangement based on the pattern, until quality of the pattern satisfies a predetermined condition, and determining, by the imprint apparatus, information indicating the arrangement of the imprint material based on the latest provisional arrangement at a stage where the quality of the pattern satisfies the predetermined condition.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: June 21, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Shinichi Hirano
  • Patent number: 11353364
    Abstract: IR radiation may be used to examine substrates prior to a fabrication operation in order to adjust processing parameters of the fabrication operation, or to determine features of the substrate. A thermographic image may be collected and provided to a transfer function or machine learning model to determine processing parameters or features. The processing parameters may improve the uniformity of the wafer and/or achieve a desired target feature value.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: June 7, 2022
    Assignee: Lam Research Corporation
    Inventor: William Dean Thompson
  • Patent number: 11340523
    Abstract: A method of correcting a designed pattern of a photomask for fabricating a semiconductor device is provided. A substrate is provided. A first mask pattern of the photomask designed to form a first contact pattern on the substrate is conceived. The first mask pattern includes a plurality of mask holes each having a hole size. The first mask pattern is adjusted to expand the hole size along a horizontal direction and rotate the mask holes for conceiving a second mask pattern of the photomask designed to form a second contact pattern having a plurality of contact holes. A plurality of device gaps between the contact holes is verified, and an overlay margin between the second contact pattern and an adjacent pattern in the semiconductor device is verified for determining whether the second contact pattern is the designed pattern of the photomask.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: May 24, 2022
    Assignee: XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.
    Inventors: Siwon Yang, Jiyong Yoo, Byung-In Kwon
  • Patent number: 11322416
    Abstract: A pattern of core material is formed on a wafer to include core features that have a critical dimension. A trim amount indicates an average amount of thickness to be removed from vertically oriented surfaces of the core features. A trim profile indicates how much variation in removal of thickness from vertically oriented surfaces of the core features is to be applied as a function of radial location on the wafer. A first set of data correlates the trim amount to one or more plasma trim process parameters. A second set of data correlates the trim profile to one or more plasma trim process parameters. Based on the trim amount, trim profile, and first and second sets of data, a set of plasma trim process parameters to achieve the trim amount and trim profile on the wafer is determined and a corresponding plasma trim process is performed on the wafer.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: May 3, 2022
    Assignee: Lam Research Corporation
    Inventors: Pulkit Agarwal, Adrien LaVoie, Ravi Kumar, Purushottam Kumar
  • Patent number: 11300886
    Abstract: A method for correcting values of one or more feed-forward parameters used in a process of patterning substrates, the method including: obtaining measured overlay and/or alignment error data of a patterned substrate; and calculating one or more correction values for the one or more feed-forward parameters in dependence on the measured overlay and/or alignment error data.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: April 12, 2022
    Assignee: ASML Netherlands B.V.
    Inventors: Hadi Yagubizade, Ahmet Koray Erdamar, Hakki Ergün Cekli
  • Patent number: 11289376
    Abstract: The present disclosure provides a method for forming interconnect structures. The method includes providing a semiconductor structure including a substrate and a conductive feature formed in a top portion of the substrate; depositing a resist layer over the substrate, wherein the resist layer has an exposure threshold; providing a radiation with an incident exposure dose to the resist layer, wherein the incident exposure dose is configured to be less than the exposure threshold of the resist layer while a sum of the incident exposure dose and a reflected exposure dose from a top surface of the conductive feature is larger than the exposure threshold of the resist layer, thereby forming a latent pattern above the conductive feature; and developing the resist layer to form a patterned resist layer.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: March 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Ru-Gun Liu, Shih-Ming Chang, Hoi-Tou Ng
  • Patent number: 11262657
    Abstract: Described herein are technologies to facilitate device fabrication, especially those that involve spin coatings of a substrate. More particularly, technologies described herein facilitate the planarization (i.e., flatness) of spin coatings during the device fabrication to form a uniformly planar film or layer on the substrate. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: March 1, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Michael Carcasi, Ryan Burns, Mark Somervell
  • Patent number: 11215919
    Abstract: A method of manufacturing a lithographic mask includes performing optical proximity correction (OPC) for correcting an optical proximity effect (OPE) on a design layout, and forming a lithographic mask based on the design layout corrected by performing the OPC, wherein performing the OPC includes generating a plurality of segments. and adjusting a bias of the plurality of segments, and the plurality of dissection positions include global uniform dissection positions defined for each third length based on a global coordinate system that is a coordinate system of the whole design layout.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: January 4, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sanghun Kim, Joobyoung Kim
  • Patent number: 11187994
    Abstract: A method for controlling a manufacturing process for manufacturing semiconductor devices, the method including: obtaining performance data indicative of the performance of the manufacturing process, the performance data including values for a performance parameter across a substrate subject to the manufacturing process; and determining a process correction for the manufacturing process based on the performance data and at least one control characteristic related to a dynamic behavior of one or more control parameters of the manufacturing process, wherein the determining is further based on an expected stability of the manufacturing process when applying the process correction.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: November 30, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Mohammad Reza Kamali, Brennan Peterson
  • Patent number: 11183434
    Abstract: A method where deviations of a characteristic of an image simulated by two different process models or deviations of the characteristic simulated by a process model and measured by a metrology tool, are used for various purposes such as to reduce the calibration time, improve the accuracy of the model, and improve the overall manufacturing process.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: November 23, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Yu Cao, Yi Zou, Chenxi Lin
  • Patent number: 11150561
    Abstract: A method for collecting information in image-error compensation is provided. The method includes providing a reticle having a first image structure and a second image structure; moving a light shading member to control a first exposure field; projecting a light over the first exposure field; recording an image of the first image structure after the light is projected; moving the light shading member to control a second exposure field; projecting the light over the second exposure field; and recording an image of the second image structure after the light is projected.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Wen Cho, Fu-Jye Liang, Chun-Kuang Chen, Chih-Tsung Shih, Li-Jui Chen, Po-Chung Cheng, Chin-Hsiang Lin
  • Patent number: 11143966
    Abstract: Disclosed is a method for lithographically producing a target structure on a non-planar initial structure by exposing a photoresist by means of a lithography beam. In the inventive method, the topography of a surface of the non-planar initial structure is detected. A test parameter for the lithography beam is used and an interaction of the lithography beam with the initial structure and the resultant change in the lithography beam and/or the target structure to be produced are determined. A correction parameter for the lithography beam is determined such that the change in the lithography beam and/or the target structure to be produced that is caused by the interaction of the lithography beam with the initial structure is reduced. The desired target structure on the initial structure is produced by exposing the photoresist by means of the lithography beam using the correction parameter.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: October 12, 2021
    Assignee: Karlsruhe Institute of Technology
    Inventors: Christian Koos, Tobias Hoose, Philipp Dietrich, Matthias Blaicher, Maria Laura Gödecke, Nicole Lindenmann
  • Patent number: 11137694
    Abstract: A lithographic apparatus that includes an illumination system that conditions a radiation beam, a first stationary plate having a first surface, and a reticle stage defining, along with the first stationary plate, a first chamber. The reticle stage supports a reticle in the first chamber, and the reticle stage includes a first surface spaced apart from a second surface of the first stationary plate, thereby defining a first gap configured to suppress an amount of contamination passing from a second chamber to the first chamber. The first stationary plate is between the reticle stage and both the illumination system and a projection system configured to project a pattern imparted to the radiation beam by the patterning device onto a substrate.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: October 5, 2021
    Assignees: ASML Netherlands B.V., ASML Holding N V.
    Inventors: Yang-Shan Huang, Marcel Joseph Louis Boonen, Han-Kwang Nienhuys, Jacob Brinkert, Richard Joseph Bruls, Peter Conrad Kochersperger
  • Patent number: 11131021
    Abstract: A method for the production of a structural die that has die structures for applying microstructures and/or nanostructures on substrates or soft dies, whereby the die structures are coated at least partially with a coating. In addition, the invention relates to a corresponding structural die as well as a device for the production of a structural die that has die structures for applying microstructures and/or nanostructures on substrates or soft dies, whereby the device has coating means for coating the die structures.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: September 28, 2021
    Assignee: EV GROUP E. THALLNER GMBH
    Inventor: Dominik Treiblmayr
  • Patent number: 11126085
    Abstract: Methods include inputting an array of pixels, where each pixel in the array of pixels has a pixel dose. The array of pixels represents dosage on a surface to be exposed with a plurality of patterns, each pattern of the plurality of patterns having an edge. A target bias is input. An edge of a pattern in the plurality of patterns is identified. For each pixel which is in a neighborhood of the identified edge, a calculated pixel dose is calculated such that the identified edge is relocated by the target bias. The array of pixels with the calculated pixel doses is output. Systems for performing the methods are also disclosed.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: September 21, 2021
    Assignee: D2S, Inc.
    Inventor: Harold Robert Zable
  • Patent number: 11106142
    Abstract: A method including evaluating a plurality of substrate measurement recipes for measurement of a metrology target processed using a patterning process, against stack sensitivity and overlay sensitivity, and selecting one or more substrate measurement recipes from the plurality of substrate measurement recipes that have a value of the stack sensitivity that meets or crosses a threshold and that have a value of the overlay sensitivity within a certain finite range from a maximum or minimum value of the overlay sensitivity.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: August 31, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Kaustuve Bhattacharyya, Arie Jeffrey Den Boef, Martin Jacobus Johan Jak
  • Patent number: 11087454
    Abstract: A defect observation device comprising: a defect determination coordinate creation unit by which the coordinates of a plurality of second defect candidates are determined as overlapping defect candidate coordinates, the plurality of second defect candidates respectively having, in a plurality of second imaging visual field regions overlapping a first imaging visual field region, a circuit pattern which partly overlaps a circuit pattern in the first imaging visual field region, in which a first defect candidate for defect determination among a plurality of defect candidates of a sample is present; a pseudo-reference image generation unit which generates a pseudo-reference image including a circuit pattern of the first defect candidate by superimposing a plurality of images respectively captured at the plurality of overlapping defect candidate coordinates; and a defect determination unit which compares an image for defect determination captured at the coordinates of the first defect candidate with the pseudo-re
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: August 10, 2021
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Naoaki Kondo, Minoru Harada, Yuji Takagi, Takehiro Hirai
  • Patent number: 11080458
    Abstract: In a method of optimizing a lithography model in a lithography simulation, a mask is formed in accordance with a given layout, a wafer is printed using the mask, a pattern formed on the printed wafer is measured, a wafer pattern is simulated using a wafer edge bias table and the given mask layout, a difference between the simulated wafer pattern and the measured pattern is obtained, and the wafer edge table is adjusted according to the difference.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fu An Tien, Hsu-Ting Huang, Ru-Gun Liu, Shih-Hsiang Lo
  • Patent number: 11064150
    Abstract: An approach for providing a user interface having a resolution corresponding to a resolution of a high resolution content is provided. The approach allocates at least one partial frame buffer based on a size and a location of a region on a screen of a display on which a user interface (UI) is displayed. The approach displays the UI based on at least one piece of partial graphic data obtained from the allocated at least one partial frame buffer.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: July 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Je-ik Kim, Joo-yoen Lee
  • Patent number: 11061332
    Abstract: A patterning method is provided in which a light-sensitive layer is formed, and a target resolution is defined for a pattern to be formed in a target layer. Based on a reference dose and reference LWR that results from a single patterning exposure at an EUV wavelength, the target resolution and reference dose, the light-sensitive layer is subjected to at least two radiation exposures including an EUV patterning exposure at a dose selected to be less than the reference dose and within 15 mJ/cm2-200 mJ/cm2, and a flood exposure at a wavelength of 200 nm-420 nm and a dose of 0.5 J/cm2-20 J/cm2. The light-sensitive layer is then developed to form a mask pattern, which is used to etch the pattern into the target layer with the target resolution and a LWR less than or approximately equal to the reference LWR and ?5 nm.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: July 13, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Michael A. Carcasi, Mark H. Somervell, Seiji Nagahara
  • Patent number: 11031211
    Abstract: A charged particle beam device capable of easily discriminating the energy of secondary charged particles is realized. The charged particle beam device includes a charged particle source, a sample stage on which a sample is placed, an objective lens that irradiates the sample with a charged particle beam from the charged particle source, a deflector that deflects secondary charged particles released by irradiating the sample with the charged particle beam, a detector that detects the secondary charged particles deflected by the deflector, a sample voltage control unit that applies a positive voltage to the sample or the sample stage, and a deflection intensity control unit that controls the intensity with which the deflector deflects the secondary charged particles.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: June 8, 2021
    Assignee: Hitachi High-Tech Corporation
    Inventors: Naoto Ito, Yu Yamazawa
  • Patent number: 11016391
    Abstract: According to one embodiment, a first test process concerning a light-exposure process is performed by forming a first lower layer and a first upper layer on a first substrate. A second test process concerning a light-exposure process is performed by forming a second lower layer and a second upper layer on a second substrate. A correction model is created on a basis of results obtained in the first test process and the second test process. A manufacturing process is performed by forming a third lower layer and a third upper layer on a third substrate. In the manufacturing process, an overlay estimation correction value is calculated by using the correction model, based on a first pattern position deviation amount, a step processing history in the manufacturing process, a second pattern position deviation amount, and an overlay residual, and the overlay estimation correction value is used in a light-exposure process.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: May 25, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kazuhiro Segawa
  • Patent number: 11003089
    Abstract: The present disclosure, in some embodiments, relates to a method of performing a photolithography process. The method includes forming a photosensitive material over a substantially flat upper surface of a substrate. The substantially flat upper surface of the substrate extends between opposing sides of the substrate. The photosensitive material is exposed to electromagnetic radiation at a plurality of depths of focus that are centered at different heights over the substrate. The photosensitive material is developed to remove a part of the photosensitive material.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jun-Yih Yu, De-Fang Huang, De-Chen Tseng, Jia-Feng Chang, Li-Fang Hsu
  • Patent number: 10997345
    Abstract: Computer-implemented methods of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation to process parameter values characterizing the semiconductor device fabrication operation are disclosed. The methods involve generating cost values using a computationally predicted result of the semiconductor device fabrication operation and a metrology result produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under a set of fixed process parameter values. The determination of the parameters of the process simulation model may employ pre-process profiles, via optimization of the resultant post-process profiles of the parameters against profile metrology results. Cost values for, e.g., optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide optimization.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: May 4, 2021
    Assignee: Lam Research Corporation
    Inventors: Ye Feng, Marcus Musselman, Andrew D. Bailey, III, Mehmet Derya Tetiker, Saravanapriyan Sriraman, Yan Zhang, Julien Mailfert