Including Control Feature Responsive To A Test Or Measurement Patents (Class 430/30)
  • Patent number: 11215919
    Abstract: A method of manufacturing a lithographic mask includes performing optical proximity correction (OPC) for correcting an optical proximity effect (OPE) on a design layout, and forming a lithographic mask based on the design layout corrected by performing the OPC, wherein performing the OPC includes generating a plurality of segments. and adjusting a bias of the plurality of segments, and the plurality of dissection positions include global uniform dissection positions defined for each third length based on a global coordinate system that is a coordinate system of the whole design layout.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: January 4, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sanghun Kim, Joobyoung Kim
  • Patent number: 11187994
    Abstract: A method for controlling a manufacturing process for manufacturing semiconductor devices, the method including: obtaining performance data indicative of the performance of the manufacturing process, the performance data including values for a performance parameter across a substrate subject to the manufacturing process; and determining a process correction for the manufacturing process based on the performance data and at least one control characteristic related to a dynamic behavior of one or more control parameters of the manufacturing process, wherein the determining is further based on an expected stability of the manufacturing process when applying the process correction.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: November 30, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Mohammad Reza Kamali, Brennan Peterson
  • Patent number: 11183434
    Abstract: A method where deviations of a characteristic of an image simulated by two different process models or deviations of the characteristic simulated by a process model and measured by a metrology tool, are used for various purposes such as to reduce the calibration time, improve the accuracy of the model, and improve the overall manufacturing process.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: November 23, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Yu Cao, Yi Zou, Chenxi Lin
  • Patent number: 11150561
    Abstract: A method for collecting information in image-error compensation is provided. The method includes providing a reticle having a first image structure and a second image structure; moving a light shading member to control a first exposure field; projecting a light over the first exposure field; recording an image of the first image structure after the light is projected; moving the light shading member to control a second exposure field; projecting the light over the second exposure field; and recording an image of the second image structure after the light is projected.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Wen Cho, Fu-Jye Liang, Chun-Kuang Chen, Chih-Tsung Shih, Li-Jui Chen, Po-Chung Cheng, Chin-Hsiang Lin
  • Patent number: 11143966
    Abstract: Disclosed is a method for lithographically producing a target structure on a non-planar initial structure by exposing a photoresist by means of a lithography beam. In the inventive method, the topography of a surface of the non-planar initial structure is detected. A test parameter for the lithography beam is used and an interaction of the lithography beam with the initial structure and the resultant change in the lithography beam and/or the target structure to be produced are determined. A correction parameter for the lithography beam is determined such that the change in the lithography beam and/or the target structure to be produced that is caused by the interaction of the lithography beam with the initial structure is reduced. The desired target structure on the initial structure is produced by exposing the photoresist by means of the lithography beam using the correction parameter.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: October 12, 2021
    Assignee: Karlsruhe Institute of Technology
    Inventors: Christian Koos, Tobias Hoose, Philipp Dietrich, Matthias Blaicher, Maria Laura Gödecke, Nicole Lindenmann
  • Patent number: 11137694
    Abstract: A lithographic apparatus that includes an illumination system that conditions a radiation beam, a first stationary plate having a first surface, and a reticle stage defining, along with the first stationary plate, a first chamber. The reticle stage supports a reticle in the first chamber, and the reticle stage includes a first surface spaced apart from a second surface of the first stationary plate, thereby defining a first gap configured to suppress an amount of contamination passing from a second chamber to the first chamber. The first stationary plate is between the reticle stage and both the illumination system and a projection system configured to project a pattern imparted to the radiation beam by the patterning device onto a substrate.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: October 5, 2021
    Assignees: ASML Netherlands B.V., ASML Holding N V.
    Inventors: Yang-Shan Huang, Marcel Joseph Louis Boonen, Han-Kwang Nienhuys, Jacob Brinkert, Richard Joseph Bruls, Peter Conrad Kochersperger
  • Patent number: 11131021
    Abstract: A method for the production of a structural die that has die structures for applying microstructures and/or nanostructures on substrates or soft dies, whereby the die structures are coated at least partially with a coating. In addition, the invention relates to a corresponding structural die as well as a device for the production of a structural die that has die structures for applying microstructures and/or nanostructures on substrates or soft dies, whereby the device has coating means for coating the die structures.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: September 28, 2021
    Assignee: EV GROUP E. THALLNER GMBH
    Inventor: Dominik Treiblmayr
  • Patent number: 11126085
    Abstract: Methods include inputting an array of pixels, where each pixel in the array of pixels has a pixel dose. The array of pixels represents dosage on a surface to be exposed with a plurality of patterns, each pattern of the plurality of patterns having an edge. A target bias is input. An edge of a pattern in the plurality of patterns is identified. For each pixel which is in a neighborhood of the identified edge, a calculated pixel dose is calculated such that the identified edge is relocated by the target bias. The array of pixels with the calculated pixel doses is output. Systems for performing the methods are also disclosed.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: September 21, 2021
    Assignee: D2S, Inc.
    Inventor: Harold Robert Zable
  • Patent number: 11106142
    Abstract: A method including evaluating a plurality of substrate measurement recipes for measurement of a metrology target processed using a patterning process, against stack sensitivity and overlay sensitivity, and selecting one or more substrate measurement recipes from the plurality of substrate measurement recipes that have a value of the stack sensitivity that meets or crosses a threshold and that have a value of the overlay sensitivity within a certain finite range from a maximum or minimum value of the overlay sensitivity.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: August 31, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Kaustuve Bhattacharyya, Arie Jeffrey Den Boef, Martin Jacobus Johan Jak
  • Patent number: 11087454
    Abstract: A defect observation device comprising: a defect determination coordinate creation unit by which the coordinates of a plurality of second defect candidates are determined as overlapping defect candidate coordinates, the plurality of second defect candidates respectively having, in a plurality of second imaging visual field regions overlapping a first imaging visual field region, a circuit pattern which partly overlaps a circuit pattern in the first imaging visual field region, in which a first defect candidate for defect determination among a plurality of defect candidates of a sample is present; a pseudo-reference image generation unit which generates a pseudo-reference image including a circuit pattern of the first defect candidate by superimposing a plurality of images respectively captured at the plurality of overlapping defect candidate coordinates; and a defect determination unit which compares an image for defect determination captured at the coordinates of the first defect candidate with the pseudo-re
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: August 10, 2021
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Naoaki Kondo, Minoru Harada, Yuji Takagi, Takehiro Hirai
  • Patent number: 11080458
    Abstract: In a method of optimizing a lithography model in a lithography simulation, a mask is formed in accordance with a given layout, a wafer is printed using the mask, a pattern formed on the printed wafer is measured, a wafer pattern is simulated using a wafer edge bias table and the given mask layout, a difference between the simulated wafer pattern and the measured pattern is obtained, and the wafer edge table is adjusted according to the difference.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fu An Tien, Hsu-Ting Huang, Ru-Gun Liu, Shih-Hsiang Lo
  • Patent number: 11064150
    Abstract: An approach for providing a user interface having a resolution corresponding to a resolution of a high resolution content is provided. The approach allocates at least one partial frame buffer based on a size and a location of a region on a screen of a display on which a user interface (UI) is displayed. The approach displays the UI based on at least one piece of partial graphic data obtained from the allocated at least one partial frame buffer.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: July 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Je-ik Kim, Joo-yoen Lee
  • Patent number: 11061332
    Abstract: A patterning method is provided in which a light-sensitive layer is formed, and a target resolution is defined for a pattern to be formed in a target layer. Based on a reference dose and reference LWR that results from a single patterning exposure at an EUV wavelength, the target resolution and reference dose, the light-sensitive layer is subjected to at least two radiation exposures including an EUV patterning exposure at a dose selected to be less than the reference dose and within 15 mJ/cm2-200 mJ/cm2, and a flood exposure at a wavelength of 200 nm-420 nm and a dose of 0.5 J/cm2-20 J/cm2. The light-sensitive layer is then developed to form a mask pattern, which is used to etch the pattern into the target layer with the target resolution and a LWR less than or approximately equal to the reference LWR and ?5 nm.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: July 13, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Michael A. Carcasi, Mark H. Somervell, Seiji Nagahara
  • Patent number: 11031211
    Abstract: A charged particle beam device capable of easily discriminating the energy of secondary charged particles is realized. The charged particle beam device includes a charged particle source, a sample stage on which a sample is placed, an objective lens that irradiates the sample with a charged particle beam from the charged particle source, a deflector that deflects secondary charged particles released by irradiating the sample with the charged particle beam, a detector that detects the secondary charged particles deflected by the deflector, a sample voltage control unit that applies a positive voltage to the sample or the sample stage, and a deflection intensity control unit that controls the intensity with which the deflector deflects the secondary charged particles.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: June 8, 2021
    Assignee: Hitachi High-Tech Corporation
    Inventors: Naoto Ito, Yu Yamazawa
  • Patent number: 11016391
    Abstract: According to one embodiment, a first test process concerning a light-exposure process is performed by forming a first lower layer and a first upper layer on a first substrate. A second test process concerning a light-exposure process is performed by forming a second lower layer and a second upper layer on a second substrate. A correction model is created on a basis of results obtained in the first test process and the second test process. A manufacturing process is performed by forming a third lower layer and a third upper layer on a third substrate. In the manufacturing process, an overlay estimation correction value is calculated by using the correction model, based on a first pattern position deviation amount, a step processing history in the manufacturing process, a second pattern position deviation amount, and an overlay residual, and the overlay estimation correction value is used in a light-exposure process.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: May 25, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kazuhiro Segawa
  • Patent number: 11003089
    Abstract: The present disclosure, in some embodiments, relates to a method of performing a photolithography process. The method includes forming a photosensitive material over a substantially flat upper surface of a substrate. The substantially flat upper surface of the substrate extends between opposing sides of the substrate. The photosensitive material is exposed to electromagnetic radiation at a plurality of depths of focus that are centered at different heights over the substrate. The photosensitive material is developed to remove a part of the photosensitive material.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jun-Yih Yu, De-Fang Huang, De-Chen Tseng, Jia-Feng Chang, Li-Fang Hsu
  • Patent number: 10997345
    Abstract: Computer-implemented methods of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation to process parameter values characterizing the semiconductor device fabrication operation are disclosed. The methods involve generating cost values using a computationally predicted result of the semiconductor device fabrication operation and a metrology result produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under a set of fixed process parameter values. The determination of the parameters of the process simulation model may employ pre-process profiles, via optimization of the resultant post-process profiles of the parameters against profile metrology results. Cost values for, e.g., optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide optimization.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: May 4, 2021
    Assignee: Lam Research Corporation
    Inventors: Ye Feng, Marcus Musselman, Andrew D. Bailey, III, Mehmet Derya Tetiker, Saravanapriyan Sriraman, Yan Zhang, Julien Mailfert
  • Patent number: 10990017
    Abstract: A method of fabricating a circuit element, such as a quantum computing circuit element, including obtaining a lithography mask write file that includes mask information characterizing one or more mask features, obtaining a uniformity function that is configured to modify the mask information to compensate for a non-uniform deposition process, applying the uniformity function to the lithography mask write to obtain a modified lithography mask write file, and performing lithography as directed by the modified lithography mask write file.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: April 27, 2021
    Assignee: Google LLC
    Inventors: Brian James Burkett, Rami Barends
  • Patent number: 10976668
    Abstract: An illumination optical unit for EUV projection lithography serves for obliquely illuminating an illumination field, in which an object field of a downstream imaging catoptric optical unit and a reflective object to be imaged can be arranged. A pupil generating device of the illumination optical unit is embodied so that an illumination pupil results, which brings about a dependency of an imaging telecentricity against a structure variable of the object to be imaged. This dependency is such that a dependency of the imaging telecentricity against the structure variable of the object to be imaged on account of interaction of the oblique illumination with structures of the object to be imaged is at least partly compensated for. An optical system for EUV projection lithography also has an imaging catoptric optical unit alongside an illumination optical unit and can additionally have a wavefront manipulation device.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: April 13, 2021
    Assignee: Carl Zeiss SMT GmbH
    Inventor: Joerg Zimmermann
  • Patent number: 10962881
    Abstract: A method for lithography in semiconductor fabrication is provided. The method includes placing a semiconductor wafer having a plurality of exposure fields over a wafer stage. The method further includes projecting an extreme ultraviolet (EUV) light over the semiconductor wafer. The method also includes securing the semiconductor wafer to the wafer stage by applying a first adjusted voltage to an electrode of the wafer stage while the EUV light is projected to a first group of the exposure fields of the semiconductor wafer. The first adjusted voltage is in a range from about 1.6 kV to about 3.2 kV.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Kuan Wu, Po-Chung Cheng, Li-Jui Chen, Chih-Tsung Shih
  • Patent number: 10962892
    Abstract: A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Jie Lee, Shih-Chun Huang, Shih-Ming Chang, Ken-Hsien Hsieh, Yung-Sung Yen, Ru-Gun Liu
  • Patent number: 10955744
    Abstract: A method of determining a parameter of a pattern transfer process and device manufacturing methods are disclosed. In one arrangement, a method includes obtaining a detected representation of radiation redirected by a structure. The structure is a structure formed by applying a pattern processing to a pattern transferred to an earlier formed structure by a pattern transfer process. The pattern processing is such as to remove one or more selected regions in a horizontal plane of the earlier formed structure to form a pattern in the horizontal plane. The pattern is defined by a unit cell that is mirror symmetric with respect to an axis of mirror symmetry. An asymmetry in the detected representation is determined. The determined asymmetry in the detected representation is used to determine a parameter of the pattern transfer process.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: March 23, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Koen Van Witteveen, Wei-Chun Wang, Paul Jonathan Turner, Elliott Gerard McNamara, Giacomo Miceli
  • Patent number: 10955755
    Abstract: Disclosed herein are several methods of reducing one or more pattern displacement errors, contrast loss, best focus shift , tilt of a Bossung curve of a portion of a design layout used in a lithographic process for imaging that portion onto a substrate using a lithographic apparatus. The methods include adjusting an illumination source of the lithographic apparatus, placing assist features onto or adjusting positions and/or shapes existing assist features in the portion. Adjusting the illumination source and/or the assist features may be by an optimization algorithm.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: March 23, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Duan-Fu Stephen Hsu, Feng-Liang Liu
  • Patent number: 10928737
    Abstract: A method of characterizing distortions in a lithographic process, and associated apparatuses. The method includes obtaining measurement data corresponding to a plurality of measurement locations on a substrate, the measurement data comprising measurements performed on a plurality of substrates, and comprising one or more measurements performed on one or more of the substrates for each of the measurement locations. For each of the measurement locations, a first quality value representing a quality metric and a noise value representing a noise metric is determined from the measurements performed at that measurement location. A plurality of distortion parameters is determined, each distortion parameter configured to characterize a systematic distortion in the quality metric and a statistical significance of the distortion parameters from the first quality value and from the noise value is determined. Systematic distortion is parameterized from the distortion parameters determined to be statistically significant.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: February 23, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Everhardus Cornelis Mos, Jochem Sebastiaan Wildenberg, Roy Werkman, Erik Johannes Maria Wallerbos
  • Patent number: 10929177
    Abstract: A computer-implemented method of managing resources for multiple trial distributed processing tasks is presented. The method includes estimating an expected time needed to process each of a set of mask patterns which can be independently processed. The method further includes allocating each of the set of mask patterns to a set of processing cores in accordance with the expected time, and processing the mask patterns in accordance with the allocation, when the computer in invoked to estimate, allocate, and process.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: February 23, 2021
    Assignee: SYNOPSYS, INC.
    Inventor: David Howard Ziger
  • Patent number: 10921714
    Abstract: Embodiments of the present disclosure generally provide improved photolithography systems and methods using a digital micromirror device (DMD). The DMD comprises columns and rows of micromirrors disposed opposite a substrate. Light beams reflect off the micromirrors onto the substrate, resulting in a patterned substrate. Certain subsets of the columns and rows of micromirrors may be positioned to the “off” position, such that they dump light, in order to correct for uniformity errors, i.e., features larger than desired, in the patterned substrate. Similarly, certain subsets of the columns and rows of micromirrors may be defaulted to the “off” position and selectively allowed to return to their programmed position in order to correct for uniformity errors, i.e., features smaller than desired, in the patterned substrate.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: February 16, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Joseph R. Johnson, Thomas L. Laidig, Christopher Dennis Bencher
  • Patent number: 10895813
    Abstract: A lithographic cluster includes a track unit and a lithographic apparatus. The lithographic apparatus includes an alignment sensor and at least one controller. The track unit is configured to process a first lot and a second lot. The lithographic apparatus is operatively coupled to the track unit. The alignment sensor is configured to measure an alignment of at least one alignment mark type of a calibration wafer. At least one controller is configured to determine a correction set for calibrating the lithographic apparatus based on the measured alignment of the at least one alignment mark type and apply first and second weight corrections to the correction set for processing the first and second lots, respectively, such that overlay drifts or jumps during processing the first and second lots are mitigated.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: January 19, 2021
    Assignee: ASML Holding N.V.
    Inventors: Irit Tzemah, Eric Brian Catey, John David Connelly
  • Patent number: 10872996
    Abstract: A UV radiation detector includes: a diode including a substrate having a first side and a second side, the first side and the second side being located on opposing faces of the substrate, an active layer including rocksalt phase crystalline structure CaS disposed on the first side of the substrate, an electrical contact disposed on the second side of the substrate, and a semi-transparent conducting layer disposed on the active layer; and a circuit connecting the semi-transparent conducting layer and the electrical contact. The UV radiation detector detects radiation having a wavelength between 200 and 280 nm.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: December 22, 2020
    Assignee: The Hong Kong University of Science and Technology
    Inventors: Qinglin He, Ying Hoi Lai, Yi Liu, Iam Keong Sou
  • Patent number: 10838824
    Abstract: A media agent is configured to perform substantially autonomously to initiate, continue, and manage information management operations such as a backup job of a certain client's primary data, manage the operations, and generate and store resultant system-level metadata from the operations, etc. The media agent is configured to do this even when out of communication with the storage manager that manages the information management system. When communications are restored, the media agent reports the relevant metadata to the storage manager. The storage manager comprises corresponding enhancements, including specialized logic for identifying the media agent as an intelligent media agent capable of some autonomous functionality, for transmitting management parameters thereto, and for seamlessly integrating the received metadata into the storage manager's associated management infrastructure such as a management database.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: November 17, 2020
    Assignee: Commvault Systems, Inc.
    Inventor: Michael Frank Klose
  • Patent number: 10824081
    Abstract: A method and apparatus is disclosed for monitoring critical dimensions in a pattern of 1-dimensional and/or 2-dimensional features, produced on a substrate in a process step that is part of or related to a manufacturing process for producing a semiconductor device, the process step being performed in accordance with a predefined pattern design, wherein one or more metrology targets (1) are added to the pattern design. The targets comprise one or more versions of an asymmetric metrology mark, each version of the mark comprising a uniform portion (2) and a periodic portion (3), the latter comprising a regular array of parallel line-shaped features or an array of 2-dimensional features. The design width of the features is situated in a range situated around a nominal design width w0. A position-related parameter S is defined that is essentially proportional to the design widths in the range.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: November 3, 2020
    Assignee: IMEC VZW
    Inventors: Christopher Ausschnitt, Vincent Truffert
  • Patent number: 10809627
    Abstract: An exposure mask includes an aligning portion and a boundary portion. The aligning portion may be aligned with pixel areas of a substrate and includes a first exposure member and a second exposure member. The boundary portion includes a first exposure element, a second exposure element, a third exposure element, and a fourth exposure element. The first exposure member, the first exposure element, and the second exposure element are positioned in a first row. The first exposure element is positioned between the first exposure member and the second exposure element and is larger than the second exposure element. The second exposure member, the third exposure element, and the fourth exposure element are positioned in a second row. The third exposure element is positioned between the second exposure member and the fourth exposure element and is smaller than the fourth exposure element. Each exposure member/element includes a light transmitter/blocker.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: October 20, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventor: Inwoo Kim
  • Patent number: 10796067
    Abstract: Systems, methods, media, and other such embodiments described herein relate to critical area analysis (CAA) operations as part of electronic design automation (EDA). One embodiment involves accessing a circuit design having a first layer (which may be a composite layer), sampling the first layer, and performing an initial CAA using the sampled portions of the layer with a set of predetermined defect sizes. The initial CAA is used to automatically generate a model which can be used to accurately select input parameters (e.g., selected defect sizes) for a full analysis. A CAA characteristic is then calculated for the first layer using the input parameters. In various embodiments, different sampling percentages and criteria for selecting input parameters can be used to reduce the computing resources to compute a CAA characteristic, such as theta-bar, while limiting error to a threshold amount (e.g. less than one percent).
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: October 6, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jonathan R. Fales, Frank E. Gennari, Jeffrey E. Nelson, Jeffrey Russell, Ya-Chieh Lai, Jac Paul Condella
  • Patent number: 10777422
    Abstract: In a method according to an embodiment, before etching a target layer of a wafer, a main surface of the target layer is divided into a plurality of areas. A difference value between a groove width of a mask and a reference value of the groove width is calculated for each of the plurality of areas, a temperature of the target layer is adjusted by using correspondence data indicating correspondence between a temperature of the target layer and a film thickness of a formed film. Then, a film is formed on the mask for each atom layer, and a film having a film thickness corresponding to the difference value is formed on the mask to correct the groove width in each of the plurality of areas to the reference value.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: September 15, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yoshihide Kihara, Toru Hisamatsu, Masanobu Honda
  • Patent number: 10755025
    Abstract: Disclosed herein is a computer-implemented method for determining an overlapping process window (OPW) of an area of interest on a portion of a design layout for a device manufacturing process for imaging the portion onto a substrate, the method including: obtaining a plurality of features in the area of interest; obtaining a plurality of values of one or more processing parameters of the device manufacturing process; determining existence of defects, probability of the existence of defects, or both in imaging the plurality of features by the device manufacturing process under each of the plurality of values; and determining the OPW of the area of interest from the existence of defects, the probability of the existence of defects, or both.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: August 25, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Frank Gang Chen, Joseph Werner De Vocht, Yuelin Du, Wanyu Li, Yen-Wen Lu
  • Patent number: 10757423
    Abstract: Apparatus and methods for encoding panoramic content, such as by a wide field of view and large image size. In one implementation, a panoramic image may be mapped to a cube, equirectangular or any other projection e.g., icosahedron or octahedron. Projection may be selected adaptively based on evaluation of the panoramic content. Content evaluation may include obtaining rate distortion cost metric for a given projection configuration including projection type, projection arrangement, and projection orientation. Projection configuration with the lowest cost may be selected as target projection for encoding content. As content composition changes (e.g., object motion, texture presence and/or location) projection may be adaptively selected to match changes in the content. Adaptive content selection methodology may provide for a lower encoded bitrate for a given encoded quality and/or higher quality for a given bitrate.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: August 25, 2020
    Assignee: GoPro, Inc.
    Inventor: Adeel Abbas
  • Patent number: 10739685
    Abstract: Photoresist layers are exposed to an exposure beam by using an exposure tool assembly, wherein the photoresist layers coat semiconductor substrates and wherein for each exposure a current exposure parameter set is used that includes at least a defocus value and an exposure dose. The exposed photoresist layers are developed, wherein resist patterns are formed from the photoresist layers. Feature characteristics in the resist patterns and/or in substrate patterns derived from the resist patterns are measured. The current exposure parameter set is updated in response to deviations of the measured feature characteristics from target feature characteristics. De-corrected feature characteristics of hypothetical resist patterns are estimated, which would be formed without updating the exposure parameter set. In response to information obtained from the de-corrected feature characteristics the measurement strategy for the feature characteristics may be changed or the current exposure parameter set may be updated.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: August 11, 2020
    Assignee: Qoniac GmbH
    Inventors: Stefan Buhl, Boris Habets, Wan-Soo Kim
  • Patent number: 10725383
    Abstract: Methods include inputting an array of pixels, where each pixel in the array of pixels has a pixel dose. The array of pixels represents dosage on a surface to be exposed with a plurality of patterns, each pattern of the plurality of patterns having an edge. A target bias is input. An edge of a pattern in the plurality of patterns is identified. For each pixel which is in a neighborhood of the identified edge, a calculated pixel dose is calculated such that the identified edge is relocated by the target bias. The array of pixels with the calculated pixel doses is output. Systems for performing the methods are also disclosed.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: July 28, 2020
    Assignee: D25, Inc.
    Inventor: Harold Robert Zable
  • Patent number: 10727143
    Abstract: A pattern of core material is formed on a wafer to include core features that have a critical dimension. A trim amount indicates an average amount of thickness to be removed from vertically oriented surfaces of the core features. A trim profile indicates how much variation in removal of thickness from vertically oriented surfaces of the core features is to be applied as a function of radial location on the wafer. A first set of data correlates the trim amount to one or more plasma trim process parameters. A second set of data correlates the trim profile to one or more plasma trim process parameters. Based on the trim amount, trim profile, and first and second sets of data, a set of plasma trim process parameters to achieve the trim amount and trim profile on the wafer is determined and a corresponding plasma trim process is performed on the wafer.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: July 28, 2020
    Assignee: Lam Research Corporation
    Inventors: Pulkit Agarwal, Adrien Lavoie, Ravi Kumar, Purushottam Kumar
  • Patent number: 10710355
    Abstract: A method of slicing printing color 3D object and a color 3D printing system; the method includes following steps: execute a slicing process to a color 3D object for obtaining a plurality of layers of slice objects; analyze one of the pluralities of layers of the slice objects for generating sintering control data and color control data; lay a layer of powder; color the layer of powder according to the color control data; sinter the colored powder according to the sintering control data for completing printing one layer of the slice objects; perform repeatedly above steps until all layers of the slice objects are printed and a color stereoscopic physical model is generated. The method can effectively generate a color stereoscopic physical model. In addition, because of the adoption of laser sintering technology, the color stereoscopic physical model generated by the present disclosed example has great strength.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: July 14, 2020
    Assignees: XYZPRINTING, INC., KINPO ELECTRONICS, INC.
    Inventor: Chung-Ju Chen
  • Patent number: 10691028
    Abstract: Methods and systems for providing overlay corrections are provided. A method may include: selecting an overlay model configured to perform overlay modeling for a wafer; obtaining a first set of modeled results from the overlay model, the first set of modeled results indicating adjustments applicable to a plurality of term coefficients of the overlay model; calculating a significance matrix indicating the significance of the plurality of term coefficients; identifying at least one less significant term coefficient among the plurality of term coefficients based on the calculated significance matrix; obtaining a second set of modeled results from the overlay model, the second set of modeled results indicating adjustments applicable to the plurality of term coefficients except for the identified at least one less significant term coefficient; and providing the second set of modeled results to facilitate overlay correction.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: June 23, 2020
    Assignee: KLA-Tencor Corporation
    Inventors: Hoyoung Heo, William Pierson, Jeremy Nabeth, Sanghuck Jeon, Onur N. Demirer, Miguel Garcia-Medina, Soujanya Vuppala
  • Patent number: 10663870
    Abstract: A method including obtaining a plurality of gauges of a plurality of gauge patterns for a patterning process, each gauge pattern configured for measurement of a parameter of the patterning process when created as part of the patterning process, and creating a selection of one or more gauges from the plurality of gauges, wherein a gauge is included in the selection provided the gauge and all the other gauges, if any, of the same gauge pattern, or all of the one or more gauges of the same gauge pattern linked to the gauge, pass a gauge printability check.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: May 26, 2020
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Jun Chen, Thomas I. Wallow, Bart Laenens, Yi-Hsing Peng
  • Patent number: 10663872
    Abstract: A lithographic apparatus includes a patterning device support to support a patterning device, the patterning device system including a moveable structure movably arranged relative to an object, a patterning device holder movably arranged relative to the movable structure to hold the patterning device, an actuator to move the movable structure relative to the object, and an ultra short stroke actuator to move the patterning device holder with respect to the movable structure; a substrate support to hold a substrate; a projection system to project a patterned radiation beam onto a target portion of the substrate; a transmission image sensor for measuring a position of the patterned radiation beam downstream of the projection system; and a calibrator for determining a relationship between magnitude of an applied control signal to the ultra short stroke actuator and resulting change in position of the patterned radiation beam and/or patterning device holder and/or patterning device.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: May 26, 2020
    Assignee: ASML Netherlands B.V.
    Inventor: Hans Butler
  • Patent number: 10663868
    Abstract: The present disclosure, in some embodiments, relates to a photolithography tool. The photolithography tool includes an illumination source configured to generate electromagnetic radiation and projection optics configured to focus the electromagnetic radiation onto a photosensitive material overlying a substrate according to a pattern on a photomask. A dynamic focal element is configured to dynamically change positions at which the electromagnetic radiation is focused over the substrate during exposure of the photosensitive material. The positions at which the electromagnetic radiation is focused define a plurality of depths of focus. The plurality of depths of focus respectively span a different spatial region within the photosensitive material that is smaller than a thickness of the photosensitive material.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jun-Yih Yu, De-Fang Huang, De-Chen Tseng, Jia-Feng Chang, Li-Fang Hsu
  • Patent number: 10656531
    Abstract: A process of characterizing a process window of a patterning process, the process including: obtaining a set of inspection locations for a pattern, the pattern defining features to be applied to a substrate with a patterning process, the set of inspection locations corresponding to a set of the features, the set of features being selected from among the features according to sensitivity of the respective features to variation in one or more process characteristics of the patterning process; patterning one or more substrates under varying process characteristics of the patterning process; and determining, for each of the variations in the process characteristics, whether at least some of the set of features yield unacceptable patterned structures on the one or more substrates at corresponding inspection locations.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: May 19, 2020
    Assignee: ASML Netherlands B.V.
    Inventors: Te-Sheng Wang, Xiang Wan
  • Patent number: 10656535
    Abstract: A method and apparatus is disclosed for monitoring critical dimensions in a pattern of 1-dimensional and/or 2-dimensional features, produced on a substrate in a process step that is part of or related to a manufacturing process for producing a semiconductor device, the process step being performed in accordance with a predefined pattern design, wherein one or more metrology targets (1) are added to the pattern design. The targets comprise one or more versions of an asymmetric metrology mark, each version of the mark comprising a uniform portion (2) and a periodic portion (3), the latter comprising a regular array of parallel line-shaped features or an array of 2-dimensional features. The design width of the features is situated in a range situated around a nominal design width w0. A position-related parameter S is defined that is essentially proportional to the design widths in the range.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: May 19, 2020
    Assignee: IMEC VZW
    Inventors: Christopher Ausschnitt, Vincent Truffert
  • Patent number: 10649335
    Abstract: A substrate processing method, includes acquiring a height distribution along a radial direction of a substrate in a peripheral edge portion of a front surface of the substrate, forming an underlayer film on the entire front surface of the substrate so as to correct a drop of a height of the peripheral edge portion based on the height distribution, and forming a resist film on the entire surface of the underlayer film.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: May 12, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Teruhiko Kodama, Masashi Enomoto, Masahide Tadokoro, Takafumi Hashimoto
  • Patent number: 10591851
    Abstract: An image forming apparatus, in which an image forming method is performed, includes an image forming device to form an image on a recording medium, a reading device to scan the recording medium having a mark and generate a scanned image, and circuitry to calculate a correction value to adjust a position of the image to be formed on the recording medium, based on the scanned image. The circuitry calculates the correction value to adjust a position of an image to be formed on a second face of the recording medium based on a first scanned image generated from a first face of the recording medium, within a period from when the first scanned image is generated from the first face to when the image starts to be formed on the second face.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: March 17, 2020
    Assignee: Ricoh Company, Ltd.
    Inventor: Yukifumi Kobayashi
  • Patent number: 10585361
    Abstract: A projection exposure apparatus is disclosed, including a focal plane measuring system (8) and an alignment measuring system (9) both disposed between a reticle stage (3) and a substrate stage (4). The alignment measuring system (9) is capable of focusing. The focal plane measuring system (8) measures variation in the surface profile of a substrate (5), and the alignment measuring system (9) effectuates focusing based on data obtained from the measurement performed by the focal plane measuring system (8). After the completion of the focusing, coordinates of various points on the substrate (5) in the alignment measuring system (9) are those of the points that have experienced the profile variation of the substrate (5). A relative positional relationship between the reticle (2) and the substrate (5) that has undergone the profile variation can be computationally derived from the changes in the coordinates of the points, and compensation can be accomplished by moving the substrate stage (4).
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: March 10, 2020
    Assignee: SHANGHAI MICRO ELECTRONICS EQUIPMENT (GROUP) CO., LTD.
    Inventor: Yuefei Chen
  • Patent number: 10570507
    Abstract: An apparatus for controlling an operation of a machine includes an optical recognition system, a control unit, and a remote control interface. The optical recognition system is configured to monitor and obtain actual operation information displayed on a panel of a processing machine in accordance with an operation time. The control unit is configured to receive the actual operation information and check the actual operation information with expected operation information. The expected operation information is obtained based on an operation model which is already built up corresponding to a current fabrication process. Deviation information between the actual operation information and the expected operation information is determined and converted into a parameter set. The remote control interface receives the parameter set and converts the parameter set into a control signal set to control the operation of the processing machine.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: February 25, 2020
    Assignee: United Microelectronics Corp.
    Inventors: Neng-Hsing Shen, Chien-Wen Yang, Chun-Man Li, Ji-Fu Kung, Ching-Pei Lin
  • Patent number: 10571340
    Abstract: A wavefront measuring device and method obtain wavefront information of an optical system. The method including: irradiating the optical system with a light beam; allowing the light beam passed via the optical system to come into a diffraction grating having periodicity in a first direction; and obtaining the wavefront information based on an interference fringe formed by light beams generated from the diffraction grating. The diffraction grating including: first portions which allow light to pass therethrough; and second portions which shield light, each of the second portions being provided between two of the first portions. A ratio between a width of one of the first portions in the first direction and a width of one of the second portions in the first direction is changed in the first direction, the one of the first portions and the one of the second portions being adjacent to each other.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: February 25, 2020
    Assignee: NIKON CORPORATION
    Inventors: Katsura Otaki, Katsumi Sugisaki, Takashi Gemma