Abstract: A method of forming an integrated circuit includes the following steps. A substrate including a plurality of exposure fields is provided, and each of the exposure field includes a target portion and a set of alignment marks. Measure the set of alignment marks of each exposure field by a measuring system to obtain alignment data for the respective exposure field. Determine an exposure parameter corresponding to each exposure field and an exposure location on the target portion from the alignment data for the respective exposure field by a calculating system. Feedback the alignment data to a next substrate.

Abstract: A method of determining exposure dose of a lithographic apparatus used in a lithographic process on a substrate. Using the lithographic process to produce a first structure on the substrate, the first structure having a dose-sensitive feature which has a form that depends on exposure dose of the lithographic apparatus on the substrate. Using the lithographic process to produce a second structure on the substrate, the second structure having a dose-sensitive feature which has a form that depends on the exposure dose of the lithographic apparatus but which has a different sensitivity to the exposure dose than the first structure. Detecting scattered radiation while illuminating the first and second structures with radiation to obtain first and second scatterometer signals. Using the first and second scatterometer signals to determine an exposure dose value used to produce at least one of the first and second structures.

Abstract: Disclosed herein is a computer-implemented method for improving a lithographic process for imaging a portion of a design layout onto a substrate using a lithographic projection apparatus, the method comprising defining a multi-variable cost function, the multi-variable cost function being a function of a stochastic effect of the lithographic process.

Abstract: A substrate can include a feature pattern included in an integrated circuit on the substrate and an in-situ metrology pattern spaced apart from the feature pattern on the substrate, the in-situ metrology pattern and the feature pattern both configured to have equal heights relative to a surface of the substrate.

Abstract: An exposure apparatus transfers a pattern on a wafer by irradiating a reticle with an illumination light, and the pattern is formed on a pattern surface of the reticle. The exposure apparatus is provided with a reticle stage that moves holding the reticle, and a sensor that irradiates a measurement light on the pattern surface of the reticle held by the reticle stage and detects speckles from the pattern.

Abstract: A system and method are presented for use in inspection of patterned structures. The system comprises: data input utility for receiving first type of data indicative of image data on at least a part of the patterned structure, and data processing and analyzing utility configured and operable for analyzing the image data, and determining a geometrical model for at least one feature of a pattern in said structure, and using said geometrical model for determining an optical model for second type of data indicative of optical measurements on a patterned structure.

Abstract: A method of lithography patterning includes forming a resist layer over a substrate and providing a radiation with a first exposure dose to define an opening to be formed in the resist layer. The opening is to have a target critical dimension CD1 after developed by a negativ-tone development (NTD) process. The method further includes exposing the resist layer to the radiation with a second exposure dose less than the first exposure dose and developing the resist layer in a negative-tone development process to remove unexposed portions of the resist layer, resulting in an opening between resist patterns. A critical dimension CD2 of the opening is greater than CD1 by a delta. The method further includes forming an interfacial layer on sidewalls of the resist patterns. The interfacial layer has a thickness that is substantially equal to half of the delta.

Abstract: This exposure method comprises a first step of performing the exposure processing by irradiating a projection optical system (the system) by a first pupil plane illumination distribution (the first distribution) of the system; a second step of performing the exposure processing by irradiating the system by a second pupil plane illumination distribution (the second distribution) that is different from the first distribution, after the first step; a change amount obtaining step of obtaining a change amount of an imaging performance of the system in a condition of the second distribution, with respect to the imaging performance in the first step; and a correction amount obtaining step of obtaining a correction amount for correcting the imaging performance in the second step, by using the change amount, wherein, in the second step, the exposure processing is performed by correcting the imaging performance using the correction amount.

Abstract: A method for measuring a critical dimension of a mask pattern, including generating a mask pattern using an optically proximity-corrected (OPC) mask design including at least one block; measuring a first critical dimension of a target-region of interest (target-ROI) including neighboring blocks having a same critical dimension (CD), in the mask pattern; determining a group region of interest including the target-ROI and at least one neighboring block adjacent to the target-ROI; measuring second CDs of the neighboring blocks of the group region of interest; and correcting a measuring value of the first CD using a measuring value of the second CDs.

Abstract: A projection optical system is constituted by, in order from the reduction side, a first optical system constituted by a plurality of lenses for forming an image displayed by image display elements as an intermediate image, and a second optical system constituted by a plurality of lenses for forming the intermediate image on a magnification side conjugate plane. Conditional Formula (1) below is satisfied. 8.20<Im?·f2/f2<20.

Abstract: Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process.

Abstract: An apparatus and method are used to form patterns on a substrate. The apparatus comprises a projection system, a patterning device, a low-pass filter, and a data manipulation device. The projection system projects a beam of radiation onto the substrate as an array of sub-beams. The patterning device modulates the sub-beams to substantially produce a requested dose pattern on the substrate. The low-pass filter operates on pattern data derived from the requested dose pattern in order to form a frequency-clipped target dose pattern that comprises only spatial frequency components below a selected threshold frequency. The data manipulation device produces a control signal comprising spot exposure intensities to be produced by the patterning device, based on a direct algebraic least-squares fit of the spot exposure intensities to the frequency-clipped target dose pattern. In various examples, filters can also be used.

Abstract: Methods and apparatuses for configuring group constraints of features of cells for a multi-patterning process are provided. The apparatus determines features within a circuit layout, distance constraints for at least one of the features, group constraints for the features based on the distance constraints, the group constraints defining limits on groups assignable to each of the features. In addition, the apparatus receives an integrated circuit layout including a plurality of abutting cells. The apparatus then determines whether group constraints of a second cell conflict with group constraints of a first cell, the second cell abutting with the first cell, and configures a subset of the group constraints of the second cell based on the group constraints of the first cell and based on the group constraints of the second cell that conflict with the group constraints of the first cell.

Abstract: A method of patterning a photoresist layer includes forming a photoresist layer on a substrate, exposing the photoresist layer to light using a first light source so as to induce a chemical change in the photoresist layer, performing a post-exposure bake process on the photoresist layer, the post-exposure bake process including irradiating the photoresist layer with at least two shots of laser light from a second light source such that the photoresist layer is heated to a first temperature, and performing a developing process on the photoresist layer after the post-exposure bake process, the development process selectively removing a portion of the photoresist layer.

Abstract: The invention relates to a method for producing a structure in a lithographic material, wherein the structure in the lithographic material is defined by means of a writing beam of an exposure device, in that a plurality of partial structures are written sequentially, wherein for writing the partial structures a write field of the exposure device is displaced and positioned sequentially and that a partial structure is written in the write field in each case, and wherein for positioning of the write field a reference structure is detected by means of an imaging measuring device.

Abstract: According to measurement results of an encoder system, a stage driving system that is a magnetic levitation type planar motor is controlled to drive and control a wafer stage, and in the case where an abnormality of the driving and control of the wafer stage has been detected, the stage driving system is controlled to apply a thrust in a vertical direction to the wafer stage. With this operation, the pitching of the wafer stage can be avoided, which makes it possible to prevent damage of the wafer stage and structures placed immediately above the stage upper surface.

Abstract: The present invention discloses a method for measuring the concentration of a photoresist in a stripping liquid. In the method for measuring the concentration of a photoresist in a stripping liquid, a plurality of standard photoresist samples are prepared at first, then the spectrum of the standard photoresist samples and the spectrum of the test photoresist sample are collected, and the nth derivative of the spectrum of the standard photoresist samples and the spectrum of the test photoresist sample are taken, wherein n is an integer equal to or greater than 1, a standard curve based on the nth derivative curves and calculating the concentration of the test photoresist sample is established, the concentration of a photoresist in a stripping liquid can be measured accurately according to the standard curve.

Abstract: According to one embodiment, wafer lithography equipment includes an exposure unit transferring a circuit pattern onto a wafer, a measurement unit measuring a dimension of the circuit pattern and a calculator. The calculator includes calculating a first difference. The first difference is the difference between a first dimension and a second dimension. The first dimension is obtained by substituting a first exposure amount and a first focus distance into an approximate response surface function. The second dimension is measured by the measurement unit. The calculator also includes calculating a second difference. The second difference is the sum total of the first difference for all of the circuit patterns. The calculator also includes calculating a second exposure amount and a second focus distance causing the difference between the approximate response surface function and the second difference to be a minimum. The calculator also includes calculating a correction exposure amount.

Abstract: Provided is a method for increasing pattern density of a structure on a substrate using an integration scheme, the method comprising: providing a substrate having a first spacer pattern and an underlying layer, the underlying layer comprising a first underlying layer, a second underlying layer, and a target layer; performing a conformal spacer deposition using an oxide, the deposition creating a conformal layer; performing a spacer RIE process and a pull process, thereby generating a second spacer pattern, the spacer RIE process includes adsorption of N-containing gas on a surface of the substrate which activates the surface to react with an F- and/or an H-containing gas to form fluorosilicates; and wherein the integration targets include selectively etching spacer films within a target spacer etch rate, enhanced simultaneous selectivity to the first underlying layer and the second underlying layer and preventing pattern damage.

Abstract: A method, system, and computer program product for triple patterning technology (TPT) violation detection and visualization within an integrated circuit design layout are disclosed. In a first aspect, the method comprises mapping a plurality of violations of the integrated circuit design layout to a graph, generating a color graph corresponding to the graph, detecting at least one TPT violation from the color graph; and visualizing the at least one TPT violation on a layout canvas. In a second aspect, the system comprises a graph generator module for mapping a plurality of violations of the integrated circuit design layout to a graph and to generate a color graph corresponding to the graph, a detector module for detecting at least one TPT violation from the color graph, and a visualizer module for visualizing the at least one TPT violation on a layout canvas.

Abstract: Methods and systems for determining a configuration for an optical element positioned in a collection aperture during wafer inspection are provided. One system includes a detector configured to detect light from a wafer that passes through an optical element, which includes a set of collection apertures, when the optical element has different configurations thereby generating different images for the different configurations. The system also includes a computer subsystem configured for constructing additional image(s) from two or more of the different images, and the two or more different images used to generate any one of the additional image(s) do not include only different images generated for single collection apertures in the set. The computer subsystem is further configured for selecting one of the different or additional configurations for the optical element based on the different images and the additional image(s).

Abstract: Various systems and methods for detecting design and process defects on a wafer, reviewing defects on a wafer, selecting one or more features within a design for use as process monitoring features, or some combination thereof are provided. One system is configured to detect design defects and process defects at locations on a wafer at which images are acquired by an electron beam review subsystem based on defects in a design, additional defects in the design, which are detected by comparing an image of a die in the design printed on the wafer acquired by the electron beam review subsystem to an image of the die stored in a database, and defects detected on the wafer by a wafer inspection system.

Abstract: Candidate layout patterns can be generated using a generative model trained based on known data, such as historical hot spot data, features extraction, and geometrical primitives. The generative model can be sampled to obtain candidate layouts that can be ranked and repaired using error optimization, design rule checking, optical proximity checking, and other methods to ensure that resulting candidates are manufacturable.

Abstract: Disclosed herein is a method of dividing rectangular plate-shaped workpieces into individual device chips including a detecting step wherein an annular frame to which a plurality of rectangular plate-shaped workpieces are stuck is held on a chuck table and the positions and angles of the projected dicing lines on each of the plate-shaped workpieces are detected, and a dividing step wherein a laser beam having a wavelength which is absorbable by the plate-shaped workpieces is applied from a laser beam applying unit to the plate-shaped workpieces while the chuck table and the laser beam applying unit are being relatively processing-fed and finely adjusted for each of the plate-shaped workpieces on the basis of the positions and angles detected in the detecting step, thereby dividing the plate-shaped workpieces into a plurality of device chips along the projected dicing lines.

Abstract: An analysis system that includes a processor and an memory module; wherein the memory module is arranged to store aerial images of an area of a mask, each aerial image corresponds to focus value out of a set of different focus values; wherein the processor is arranged to find weak points by processing the aerial images using different printability thresholds; and wherein the processor is arranged to determine focus and exposure values for generating a Process Window Qualification (PWQ) wafer to be manufactured using the mask in response to focus and exposure values associated with the weak points.

Abstract: A projection lens for imaging a pattern arranged in an object plane of the projection lens into an image plane of the projection lens via electromagnetic radiation having an operating wavelength ?<260 nm has a multiplicity of optical elements having optical surfaces which are arranged in a projection beam path between the object plane and the image plane. Provision is made of a wavefront manipulation system for dynamically influencing the wavefront of the projection radiation passing from the object plane to the image plane.

Abstract: Disclosed is a projection optical system including a first optical system configured to form a first image conjugate to an object and have an optical axis and a second optical system configured to project a second image conjugate to the first image onto a surface to be projected on, wherein the first image satisfies a condition of: Im×Tr?1.70 wherein Im denotes a length of the first image in a direction of an optical axis of the first optical system, normalized by a focal length of the first optical system, and Tr denotes a throw ratio for the projection optical system.

Abstract: A method of electron-beam lithography by direct writing solves the reliability of design of etched components through rounding of the corners of contiguous patterns, notably in patterns to be etched of critical dimension of the order of 35 nm. The method determines critical patterns, and correction patterns by subtracting patterns of corrections of dimensions and of locations as a function of rounding of external or internal corners to be corrected and etching of the corrected design. The corrections may be by a correction model taking account of the parameters of the critical patterns. A correction of the proximity effects specific to these methods is also performed, by resizing of edges of blocks to be etched in combination optimized by the energy latitude with a modulation of the radiated doses. A rescaling and negation functions and eRIF functions may be used to optimize the parameters and the realization of the extrusion.

Abstract: A lithography metrology method is provided. Focus sensitivity data and dose sensitivity data of sample patterns to be formed on a substrate are acquired. At least one focus pattern selected in descending order of focus sensitivity from among the acquired focus sensitivity data of the sample patterns is determined. At least one low-sensitivity focus pattern in ascending order of the focus sensitivity from among the acquired dose sensitivity data of the sample patterns is selected, and at least one dose pattern selected in descending order of dose sensitivity from among the at least one low-sensitivity focus pattern is determined. A split substrate having a plurality of chip regions is prepared. A plurality of focus split patterns having a shape corresponding to the at least one focus pattern and a plurality of dose split patterns having a shape corresponding to the at least one dose pattern in the plurality of chip regions are formed.

Abstract: The present invention makes the use of measurement of a diffraction spectrum in or near an image plane in order to determine a property of an exposed substrate. In particular, the positive and negative first diffraction orders are separated or diverged, detected and their intensity measured. The intensity of each of the first diffraction orders from the diffraction spectrum are compared to determine overlay (or other properties) of exposed layers on the substrate.

Abstract: A method includes receiving layout data representing a plurality of patterns. The layout data includes a plurality of layers and spaces identified between adjacent patterns. In at least one layer of the plurality of layers, the adjacent patterns violate a G0-rule. The method further includes determining whether each identified space is a critical G0-space. The identified space is determined to be a critical G0-space if a portion of at least one adjacent pattern that is removed merges two adjacent odd-loops of G0-spaces into a single even loop or G0 spaces or alternatively, if a portion of an adjacent pattern that is removed converts one odd-loop of G0-spaces to a non-loop of G0-spaces. The method further includes receiving a modification of at least one adjacent pattern and updating a spacing of a layer that is adjacent to the layers within the adjacent pattern that violate the G0-rule.

Abstract: The present invention makes the use of measurement of a diffraction spectrum in or near an image plane in order to determine a property of an exposed substrate. In particular, the positive and negative first diffraction orders are separated or diverged, detected and their intensity measured. The intensity of each of the first diffraction orders from the diffraction spectrum are compared to determine overlay (or other properties) of exposed layers on the substrate.

Abstract: Embodiments of the present invention describe methods of selecting a subset of test patterns from an initial larger set of test patterns for calibrating a computational lithography model. An example method comprises: generating an information matrix for the initial larger set of test patterns, wherein the terms of the information matrix comprise one or more identified model parameters that represent a lithographic process response; and, executing a selection algorithm using terms of the information matrix to select the subset of test patterns that effectively determines values of the identified model parameters that contribute significantly in the lithographic process response, wherein the subset of test patterns characteristically represents the initial larger set of test patterns. The selection algorithm explores coverage relationships existing in the initial larger set of test patterns.

Abstract: A substrate support device includes a plate portion including a heater plate that includes a heating element provided in the heater plate, and also including a first cooling plate provided on a bottom surface of the heater plate and having a first flow path, and a second cooling plate provided on a top surface of the heater plate and having a second flow path; and a shaft portion supporting the plate portion and including a line connected to the heating element to supply an electric current to the heating element, and a tube supplying a coolant to the first cooling plate and the second cooling plate, the line and the tube being provided inside the shaft portion.

Abstract: In order to provide a semiconductor device that includes a conductive layer on one surface of a semiconductor substrate with an insulating layer therebetween, a bump on the other surface of the semiconductor substrate, and a through-electrode through the semiconductor substrate connecting the conductive layer with the bump, a through-hole is formed from the other surface of the semiconductor substrate to be connected to the conductive layer, a seed metal film is formed on the through-hole and the other surface, a photoresist is formed thereon, a mask layer is formed by processing the photoresist with a pattern larger than the through-hole, a plated film is grown by electrolytic plating so as to integrally form the through-electrode and a part of the bump.

Abstract: Methods are disclosed for measuring target structures formed by a lithographic process on a substrate. A grating or other structure within the target is smaller than an illumination spot and field of view of a measurement optical system. The position of an image of the component structure varies between measurements, and a first type of correction is applied to reduce the influence on the measured intensities, caused by differences in the optical path to and from different positions. A plurality of structures may be imaged simultaneously within the field of view of the optical system, and each corrected for its respective position. The measurements may comprise first and second images of the same target under different modes of illumination and/or imaging, for example in a dark field metrology application.

Abstract: The present disclosure provides a method for pattern correction for electron-beam (e-beam) lithography. In accordance with some embodiments, the method includes splitting a plurality of patterns into a plurality of pattern types; performing model fittings to determine a plurality of models for the plurality of pattern types respectively; and performing a pattern correction to an integrated circuit (IC) layout using the plurality of models.

Abstract: Methods for measuring photosensitizer concentrations in a photo-sensitized chemically-amplified resist (PS-CAR) patterning process are described. Measured photosensitizer concentrations can be used in feedback and feedforward control of the patterning process and subsequent processing steps. Also described is a metrology target formed using PS-CAR resist, and a substrate including a plurality of such metrology targets to facilitate patterning process control.

Abstract: A lithographic mask has a substrate substantially transmissive for radiation of a certain wavelength, the substrate having a radiation absorbing material in an arrangement, the arrangement configured to apply a pattern to a cross-section of a radiation beam of the certain wavelength, wherein the absorbing material has a thickness which is substantially equal to the certain wavelength divided by a refractive index of the absorbing material.

Abstract: Methods and systems are provided for a scanning microscope to rapidly form a partial digital image of an area. The method includes performing an initial scan for the area and using initial scan to identify regions representing features of interest in the area. Then, the method performs additional adaptive scans of the regions representing structures of interest. Such scans adapt the path of the scanning beam to follow the edges of a feature of interest by performing localized scan patterns that intersect the feature edge, and directing the localized scan patterns to follow the feature edge.

Abstract: A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure “shots” are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. A simulation is run on the clusters of shots to estimate the resulting fabrication shapes that the clusters of shots create. The clusters of shots are modified to align the estimated fabrication shapes more closely with desired fabrication shapes. The process of simulating and modifying the shots is iterative, repeating until the estimated fabrication shapes are within a desired error difference of the planned fabrication shape.

Abstract: Provided is an integrated circuit (IC) manufacturing method. The method includes receiving a design layout of an IC, the design layout having a main feature; performing a process correction to the main feature thereby generating a modified main feature; using a computer, generating a simulated contour of the modified main feature, the simulated contour having a plurality of points; generating a plurality of assistant data in computer readable format, wherein each assistant data includes at least one process performance factor associated with one of the points; and keeping the simulated contour and the assistant data for use by a further process stage, such as mask making, mask inspection, mask repairing, wafer direct writing, wafer inspection, and wafer repairing.

Abstract: A recording medium stores a program for causing a computer to execute a method of calculating a resist pattern.

Abstract: A position detector configured to detect a position of an object to be detected. The position detector has an optical system configured to detect a mark on the object to be detected that includes a lens that has a positive refractive power, and a reflection member configured to reflect a light flux that passes through the lens in a convergent state or a divergent state. The reflection member is configured from at least one material of a material that exhibits a refractive index of less than 1.0 and an extinction coefficient of greater than 0.0, and a material that exhibits a refractive index of greater than 1.0 and an extinction coefficient of greater than 0.5.

Abstract: A patterning method may employ a particle beam, such as an electron beam (E-beam) and an exposure system that may include preparing an exposure layout defining a spatial distribution of an E-beam, performing an E-beam exposure process to a mask layer, based on the exposure layout, performing a developing process to the mask layer to form mask patterns including a first pattern. The first pattern may be a single solid pattern, and the exposure layout may include a first data associated with a plurality of E-beam conditions defined for a first region corresponding to the first pattern.

Abstract: Methods of preparing layouts for semiconductor devices and semiconductor devices fabricated using the layouts are provided. Preparing the layouts for semiconductor devices may include disposing assistant patterns near a main gate pattern that is provided on a weak active pattern. The weak active pattern may be, for example, an outermost one of active patterns and may be one expected to have an increased width during a fabrication process.

Abstract: A method for lithography exposing process is provided. The method includes performing a first lithography exposing process to a resist layer using a mask having a focus-sensitive pattern and an energy-sensitive pattern; measuring critical dimensions (CDs) of transferred focus-sensitive pattern and transferred energy-sensitive pattern on the resist layer; extracting Bossung curves from the CDs; and determining slopes of the Bossung curves.

Abstract: A method of processing a substrate is described herein. The method includes positioning a substrate on a stage associated with a maskless direct writing pattern generator. The substrate has an undeveloped, unexposed photoresist layer formed thereon. The photoresist layer has a plurality of writing pixel locations. The method includes delivering predetermined doses of electromagnetic energy from the pattern generator to each writing pixel location. A first predetermined dose is a full tone dose, and the first predetermined dose is delivered to at least one writing pixel location. A second predetermined is a fractional tone dose, and the second predetermined dose is delivered to at least one writing pixel location. A third predetermined dose is either a fractional dose or a zero tone dose. The third predetermined dose is delivered to at least one writing pixel location, and the third predetermined dose is different from the second predetermined dose.

Abstract: Systems and methods are disclosed for describing and tracking edges within the field of view of one or more imaging devices. In one example, the present system defines a row of pixels taken across a width of the edge, and then determines a binary edge descriptor for the edge by comparing at least one of grayscale values and contrast of pixels within respective pixel pairs from the row of pixels, the result of the comparisons setting bits within the binary descriptor.

Abstract: Deformation of a substrate due to one or more processing steps is determined by measuring substrate alignment data at lithographic processing steps before and after the one or more processing steps. Any abnormal pattern in the alignment data differential is identified by comparing the calculated alignment data differential with previous data accumulated in a database. By comparing the abnormal pattern with previously identified tool-specific patterns for alignment data differential, a processing step that introduces the abnormal pattern and/or the nature of the abnormal processing can be identified, and appropriate process control measures can be taken to rectify any anomaly in the identified processing step.