Abstract: There is provided a system and method of generating a metrology recipe usable for examining a semiconductor specimen, comprising: obtaining a first image set comprising a plurality of first images captured by an examination tool, obtaining a second image set comprising a plurality of second images, wherein each second image is simulated based on at least one first image, wherein each second image is associated with ground truth data; performing a first test on the first image set and a second test on the second image set in accordance with a metrology recipe configured with a first parameter set, and determining, in response to a predetermined criterion not being met, to select a second parameter set, configure the metrology recipe with the second parameter set, and repeat the first test and the second test in accordance with the metrology recipe configured with the second parameter set.

Abstract: An image forming apparatus includes an image forming unit configured to perform a first image forming process and a second image forming process to form an image and a test image on a sheet; a reader, arranged in a conveyance path along which the sheet is conveyed, configured to read the test image on the sheet, the test image being formed by the image forming unit; a member; a controller configured to obtain, from the reader, reading data related to the test image on the sheet.

Abstract: A critical dimension measurement system includes a voltage measurement circuit, a control circuit, and a critical dimension measurement circuit. The voltage measurement circuit may measure potentials of mask patterns of a photomask. The control circuit may include an information storage circuit for storing distribution information on the potentials of the mask patterns, measured by the voltage measurement circuit, and information on layout patterns corresponding to the mask patterns of the photomask. The critical dimension measurement circuit may be operated, by the control circuit, in a first measurement mode and a second measurement mode running for a shorter time than the first measurement mode, and measure critical dimensions of the mask patterns.

Abstract: The invention relates firstly to a method for determining a mechanical deviation on a displacement path of an optical zoom lens (03), in particular on a displacement path of an optical zoom lens (03) of a microscope. The optical zoom lens (03) is arranged in a beam path (01) between an object (19) to be recorded and an electronic image sensor (04). In a first method step, an optical marker is introduced into the beam path (01) at a position of the beam path (01) located between the object (19) to be recorded and the optical zoom lens (03), such that the optical marker passes the optical zoom lens (03) and then is depicted on an image in which a position of the optical marker is detected and determined. This is compared with a reference position of the optical marker in order to determine the mechanical deviation on the displacement path of the optical zoom lens (03).

Abstract: A method for optical proximity correction (OPC) comprises creating a semi-physical model of a mask for a current layer in an IC design layout using physical parameters of a lithography process used to create the mask, the semi-physical model specifying contours of the plurality of features of the mask. It is determined from design information whether the current layer is deformed by the one or more reference layers that overlap the current layer near the contours. Responsive to determining that the current layer is deformed by the one or more reference layers, the semi-physical model and the design information of the one or more reference layers are input into a trained machine learning algorithm to generate a contour shift prediction for the current layer, the contour shift prediction estimating a residual error of the semi-physical model. The contour shift prediction is then used for multilayer OPC correction of the current layer.

Abstract: A method of determining information indicating an arrangement of an imprint material in an imprint apparatus, includes repeating, by the imprint apparatus, a process of arranging an imprint material on a substrate in accordance with a provisional arrangement, forming a pattern by curing the imprint material in a state in which a mold is brought into contact with the imprint material, and changing the provisional arrangement based on the pattern, until quality of the pattern satisfies a predetermined condition, and determining, by the imprint apparatus, information indicating the arrangement of the imprint material based on the latest provisional arrangement at a stage where the quality of the pattern satisfies the predetermined condition.

Abstract: IR radiation may be used to examine substrates prior to a fabrication operation in order to adjust processing parameters of the fabrication operation, or to determine features of the substrate. A thermographic image may be collected and provided to a transfer function or machine learning model to determine processing parameters or features. The processing parameters may improve the uniformity of the wafer and/or achieve a desired target feature value.

Abstract: A method of correcting a designed pattern of a photomask for fabricating a semiconductor device is provided. A substrate is provided. A first mask pattern of the photomask designed to form a first contact pattern on the substrate is conceived. The first mask pattern includes a plurality of mask holes each having a hole size. The first mask pattern is adjusted to expand the hole size along a horizontal direction and rotate the mask holes for conceiving a second mask pattern of the photomask designed to form a second contact pattern having a plurality of contact holes. A plurality of device gaps between the contact holes is verified, and an overlay margin between the second contact pattern and an adjacent pattern in the semiconductor device is verified for determining whether the second contact pattern is the designed pattern of the photomask.

Abstract: A pattern of core material is formed on a wafer to include core features that have a critical dimension. A trim amount indicates an average amount of thickness to be removed from vertically oriented surfaces of the core features. A trim profile indicates how much variation in removal of thickness from vertically oriented surfaces of the core features is to be applied as a function of radial location on the wafer. A first set of data correlates the trim amount to one or more plasma trim process parameters. A second set of data correlates the trim profile to one or more plasma trim process parameters. Based on the trim amount, trim profile, and first and second sets of data, a set of plasma trim process parameters to achieve the trim amount and trim profile on the wafer is determined and a corresponding plasma trim process is performed on the wafer.

Abstract: A method for correcting values of one or more feed-forward parameters used in a process of patterning substrates, the method including: obtaining measured overlay and/or alignment error data of a patterned substrate; and calculating one or more correction values for the one or more feed-forward parameters in dependence on the measured overlay and/or alignment error data.

Abstract: The present disclosure provides a method for forming interconnect structures. The method includes providing a semiconductor structure including a substrate and a conductive feature formed in a top portion of the substrate; depositing a resist layer over the substrate, wherein the resist layer has an exposure threshold; providing a radiation with an incident exposure dose to the resist layer, wherein the incident exposure dose is configured to be less than the exposure threshold of the resist layer while a sum of the incident exposure dose and a reflected exposure dose from a top surface of the conductive feature is larger than the exposure threshold of the resist layer, thereby forming a latent pattern above the conductive feature; and developing the resist layer to form a patterned resist layer.

Abstract: Described herein are technologies to facilitate device fabrication, especially those that involve spin coatings of a substrate. More particularly, technologies described herein facilitate the planarization (i.e., flatness) of spin coatings during the device fabrication to form a uniformly planar film or layer on the substrate. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

Abstract: A method of manufacturing a lithographic mask includes performing optical proximity correction (OPC) for correcting an optical proximity effect (OPE) on a design layout, and forming a lithographic mask based on the design layout corrected by performing the OPC, wherein performing the OPC includes generating a plurality of segments. and adjusting a bias of the plurality of segments, and the plurality of dissection positions include global uniform dissection positions defined for each third length based on a global coordinate system that is a coordinate system of the whole design layout.

Abstract: A method for controlling a manufacturing process for manufacturing semiconductor devices, the method including: obtaining performance data indicative of the performance of the manufacturing process, the performance data including values for a performance parameter across a substrate subject to the manufacturing process; and determining a process correction for the manufacturing process based on the performance data and at least one control characteristic related to a dynamic behavior of one or more control parameters of the manufacturing process, wherein the determining is further based on an expected stability of the manufacturing process when applying the process correction.

Abstract: A method where deviations of a characteristic of an image simulated by two different process models or deviations of the characteristic simulated by a process model and measured by a metrology tool, are used for various purposes such as to reduce the calibration time, improve the accuracy of the model, and improve the overall manufacturing process.

Abstract: A method for collecting information in image-error compensation is provided. The method includes providing a reticle having a first image structure and a second image structure; moving a light shading member to control a first exposure field; projecting a light over the first exposure field; recording an image of the first image structure after the light is projected; moving the light shading member to control a second exposure field; projecting the light over the second exposure field; and recording an image of the second image structure after the light is projected.

Abstract: Disclosed is a method for lithographically producing a target structure on a non-planar initial structure by exposing a photoresist by means of a lithography beam. In the inventive method, the topography of a surface of the non-planar initial structure is detected. A test parameter for the lithography beam is used and an interaction of the lithography beam with the initial structure and the resultant change in the lithography beam and/or the target structure to be produced are determined. A correction parameter for the lithography beam is determined such that the change in the lithography beam and/or the target structure to be produced that is caused by the interaction of the lithography beam with the initial structure is reduced. The desired target structure on the initial structure is produced by exposing the photoresist by means of the lithography beam using the correction parameter.

Abstract: A lithographic apparatus that includes an illumination system that conditions a radiation beam, a first stationary plate having a first surface, and a reticle stage defining, along with the first stationary plate, a first chamber. The reticle stage supports a reticle in the first chamber, and the reticle stage includes a first surface spaced apart from a second surface of the first stationary plate, thereby defining a first gap configured to suppress an amount of contamination passing from a second chamber to the first chamber. The first stationary plate is between the reticle stage and both the illumination system and a projection system configured to project a pattern imparted to the radiation beam by the patterning device onto a substrate.

Abstract: A method for the production of a structural die that has die structures for applying microstructures and/or nanostructures on substrates or soft dies, whereby the die structures are coated at least partially with a coating. In addition, the invention relates to a corresponding structural die as well as a device for the production of a structural die that has die structures for applying microstructures and/or nanostructures on substrates or soft dies, whereby the device has coating means for coating the die structures.

Abstract: Methods include inputting an array of pixels, where each pixel in the array of pixels has a pixel dose. The array of pixels represents dosage on a surface to be exposed with a plurality of patterns, each pattern of the plurality of patterns having an edge. A target bias is input. An edge of a pattern in the plurality of patterns is identified. For each pixel which is in a neighborhood of the identified edge, a calculated pixel dose is calculated such that the identified edge is relocated by the target bias. The array of pixels with the calculated pixel doses is output. Systems for performing the methods are also disclosed.

Abstract: A method including evaluating a plurality of substrate measurement recipes for measurement of a metrology target processed using a patterning process, against stack sensitivity and overlay sensitivity, and selecting one or more substrate measurement recipes from the plurality of substrate measurement recipes that have a value of the stack sensitivity that meets or crosses a threshold and that have a value of the overlay sensitivity within a certain finite range from a maximum or minimum value of the overlay sensitivity.

Abstract: A defect observation device comprising: a defect determination coordinate creation unit by which the coordinates of a plurality of second defect candidates are determined as overlapping defect candidate coordinates, the plurality of second defect candidates respectively having, in a plurality of second imaging visual field regions overlapping a first imaging visual field region, a circuit pattern which partly overlaps a circuit pattern in the first imaging visual field region, in which a first defect candidate for defect determination among a plurality of defect candidates of a sample is present; a pseudo-reference image generation unit which generates a pseudo-reference image including a circuit pattern of the first defect candidate by superimposing a plurality of images respectively captured at the plurality of overlapping defect candidate coordinates; and a defect determination unit which compares an image for defect determination captured at the coordinates of the first defect candidate with the pseudo-re

Abstract: In a method of optimizing a lithography model in a lithography simulation, a mask is formed in accordance with a given layout, a wafer is printed using the mask, a pattern formed on the printed wafer is measured, a wafer pattern is simulated using a wafer edge bias table and the given mask layout, a difference between the simulated wafer pattern and the measured pattern is obtained, and the wafer edge table is adjusted according to the difference.

Abstract: An approach for providing a user interface having a resolution corresponding to a resolution of a high resolution content is provided. The approach allocates at least one partial frame buffer based on a size and a location of a region on a screen of a display on which a user interface (UI) is displayed. The approach displays the UI based on at least one piece of partial graphic data obtained from the allocated at least one partial frame buffer.

Abstract: A patterning method is provided in which a light-sensitive layer is formed, and a target resolution is defined for a pattern to be formed in a target layer. Based on a reference dose and reference LWR that results from a single patterning exposure at an EUV wavelength, the target resolution and reference dose, the light-sensitive layer is subjected to at least two radiation exposures including an EUV patterning exposure at a dose selected to be less than the reference dose and within 15 mJ/cm2-200 mJ/cm2, and a flood exposure at a wavelength of 200 nm-420 nm and a dose of 0.5 J/cm2-20 J/cm2. The light-sensitive layer is then developed to form a mask pattern, which is used to etch the pattern into the target layer with the target resolution and a LWR less than or approximately equal to the reference LWR and ?5 nm.

Abstract: A charged particle beam device capable of easily discriminating the energy of secondary charged particles is realized. The charged particle beam device includes a charged particle source, a sample stage on which a sample is placed, an objective lens that irradiates the sample with a charged particle beam from the charged particle source, a deflector that deflects secondary charged particles released by irradiating the sample with the charged particle beam, a detector that detects the secondary charged particles deflected by the deflector, a sample voltage control unit that applies a positive voltage to the sample or the sample stage, and a deflection intensity control unit that controls the intensity with which the deflector deflects the secondary charged particles.

Abstract: According to one embodiment, a first test process concerning a light-exposure process is performed by forming a first lower layer and a first upper layer on a first substrate. A second test process concerning a light-exposure process is performed by forming a second lower layer and a second upper layer on a second substrate. A correction model is created on a basis of results obtained in the first test process and the second test process. A manufacturing process is performed by forming a third lower layer and a third upper layer on a third substrate. In the manufacturing process, an overlay estimation correction value is calculated by using the correction model, based on a first pattern position deviation amount, a step processing history in the manufacturing process, a second pattern position deviation amount, and an overlay residual, and the overlay estimation correction value is used in a light-exposure process.

Abstract: The present disclosure, in some embodiments, relates to a method of performing a photolithography process. The method includes forming a photosensitive material over a substantially flat upper surface of a substrate. The substantially flat upper surface of the substrate extends between opposing sides of the substrate. The photosensitive material is exposed to electromagnetic radiation at a plurality of depths of focus that are centered at different heights over the substrate. The photosensitive material is developed to remove a part of the photosensitive material.

Abstract: Computer-implemented methods of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation to process parameter values characterizing the semiconductor device fabrication operation are disclosed. The methods involve generating cost values using a computationally predicted result of the semiconductor device fabrication operation and a metrology result produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under a set of fixed process parameter values. The determination of the parameters of the process simulation model may employ pre-process profiles, via optimization of the resultant post-process profiles of the parameters against profile metrology results. Cost values for, e.g., optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide optimization.

Abstract: A method of fabricating a circuit element, such as a quantum computing circuit element, including obtaining a lithography mask write file that includes mask information characterizing one or more mask features, obtaining a uniformity function that is configured to modify the mask information to compensate for a non-uniform deposition process, applying the uniformity function to the lithography mask write to obtain a modified lithography mask write file, and performing lithography as directed by the modified lithography mask write file.

Abstract: An illumination optical unit for EUV projection lithography serves for obliquely illuminating an illumination field, in which an object field of a downstream imaging catoptric optical unit and a reflective object to be imaged can be arranged. A pupil generating device of the illumination optical unit is embodied so that an illumination pupil results, which brings about a dependency of an imaging telecentricity against a structure variable of the object to be imaged. This dependency is such that a dependency of the imaging telecentricity against the structure variable of the object to be imaged on account of interaction of the oblique illumination with structures of the object to be imaged is at least partly compensated for. An optical system for EUV projection lithography also has an imaging catoptric optical unit alongside an illumination optical unit and can additionally have a wavefront manipulation device.

Abstract: A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.

Abstract: A method for lithography in semiconductor fabrication is provided. The method includes placing a semiconductor wafer having a plurality of exposure fields over a wafer stage. The method further includes projecting an extreme ultraviolet (EUV) light over the semiconductor wafer. The method also includes securing the semiconductor wafer to the wafer stage by applying a first adjusted voltage to an electrode of the wafer stage while the EUV light is projected to a first group of the exposure fields of the semiconductor wafer. The first adjusted voltage is in a range from about 1.6 kV to about 3.2 kV.

Abstract: A method of determining a parameter of a pattern transfer process and device manufacturing methods are disclosed. In one arrangement, a method includes obtaining a detected representation of radiation redirected by a structure. The structure is a structure formed by applying a pattern processing to a pattern transferred to an earlier formed structure by a pattern transfer process. The pattern processing is such as to remove one or more selected regions in a horizontal plane of the earlier formed structure to form a pattern in the horizontal plane. The pattern is defined by a unit cell that is mirror symmetric with respect to an axis of mirror symmetry. An asymmetry in the detected representation is determined. The determined asymmetry in the detected representation is used to determine a parameter of the pattern transfer process.

Abstract: Disclosed herein are several methods of reducing one or more pattern displacement errors, contrast loss, best focus shift , tilt of a Bossung curve of a portion of a design layout used in a lithographic process for imaging that portion onto a substrate using a lithographic apparatus. The methods include adjusting an illumination source of the lithographic apparatus, placing assist features onto or adjusting positions and/or shapes existing assist features in the portion. Adjusting the illumination source and/or the assist features may be by an optimization algorithm.

Abstract: A method of characterizing distortions in a lithographic process, and associated apparatuses. The method includes obtaining measurement data corresponding to a plurality of measurement locations on a substrate, the measurement data comprising measurements performed on a plurality of substrates, and comprising one or more measurements performed on one or more of the substrates for each of the measurement locations. For each of the measurement locations, a first quality value representing a quality metric and a noise value representing a noise metric is determined from the measurements performed at that measurement location. A plurality of distortion parameters is determined, each distortion parameter configured to characterize a systematic distortion in the quality metric and a statistical significance of the distortion parameters from the first quality value and from the noise value is determined. Systematic distortion is parameterized from the distortion parameters determined to be statistically significant.

Abstract: A computer-implemented method of managing resources for multiple trial distributed processing tasks is presented. The method includes estimating an expected time needed to process each of a set of mask patterns which can be independently processed. The method further includes allocating each of the set of mask patterns to a set of processing cores in accordance with the expected time, and processing the mask patterns in accordance with the allocation, when the computer in invoked to estimate, allocate, and process.

Abstract: Embodiments of the present disclosure generally provide improved photolithography systems and methods using a digital micromirror device (DMD). The DMD comprises columns and rows of micromirrors disposed opposite a substrate. Light beams reflect off the micromirrors onto the substrate, resulting in a patterned substrate. Certain subsets of the columns and rows of micromirrors may be positioned to the “off” position, such that they dump light, in order to correct for uniformity errors, i.e., features larger than desired, in the patterned substrate. Similarly, certain subsets of the columns and rows of micromirrors may be defaulted to the “off” position and selectively allowed to return to their programmed position in order to correct for uniformity errors, i.e., features smaller than desired, in the patterned substrate.

Abstract: A lithographic cluster includes a track unit and a lithographic apparatus. The lithographic apparatus includes an alignment sensor and at least one controller. The track unit is configured to process a first lot and a second lot. The lithographic apparatus is operatively coupled to the track unit. The alignment sensor is configured to measure an alignment of at least one alignment mark type of a calibration wafer. At least one controller is configured to determine a correction set for calibrating the lithographic apparatus based on the measured alignment of the at least one alignment mark type and apply first and second weight corrections to the correction set for processing the first and second lots, respectively, such that overlay drifts or jumps during processing the first and second lots are mitigated.

Abstract: A UV radiation detector includes: a diode including a substrate having a first side and a second side, the first side and the second side being located on opposing faces of the substrate, an active layer including rocksalt phase crystalline structure CaS disposed on the first side of the substrate, an electrical contact disposed on the second side of the substrate, and a semi-transparent conducting layer disposed on the active layer; and a circuit connecting the semi-transparent conducting layer and the electrical contact. The UV radiation detector detects radiation having a wavelength between 200 and 280 nm.

Abstract: A media agent is configured to perform substantially autonomously to initiate, continue, and manage information management operations such as a backup job of a certain client's primary data, manage the operations, and generate and store resultant system-level metadata from the operations, etc. The media agent is configured to do this even when out of communication with the storage manager that manages the information management system. When communications are restored, the media agent reports the relevant metadata to the storage manager. The storage manager comprises corresponding enhancements, including specialized logic for identifying the media agent as an intelligent media agent capable of some autonomous functionality, for transmitting management parameters thereto, and for seamlessly integrating the received metadata into the storage manager's associated management infrastructure such as a management database.

Abstract: A method and apparatus is disclosed for monitoring critical dimensions in a pattern of 1-dimensional and/or 2-dimensional features, produced on a substrate in a process step that is part of or related to a manufacturing process for producing a semiconductor device, the process step being performed in accordance with a predefined pattern design, wherein one or more metrology targets (1) are added to the pattern design. The targets comprise one or more versions of an asymmetric metrology mark, each version of the mark comprising a uniform portion (2) and a periodic portion (3), the latter comprising a regular array of parallel line-shaped features or an array of 2-dimensional features. The design width of the features is situated in a range situated around a nominal design width w0. A position-related parameter S is defined that is essentially proportional to the design widths in the range.

Abstract: An exposure mask includes an aligning portion and a boundary portion. The aligning portion may be aligned with pixel areas of a substrate and includes a first exposure member and a second exposure member. The boundary portion includes a first exposure element, a second exposure element, a third exposure element, and a fourth exposure element. The first exposure member, the first exposure element, and the second exposure element are positioned in a first row. The first exposure element is positioned between the first exposure member and the second exposure element and is larger than the second exposure element. The second exposure member, the third exposure element, and the fourth exposure element are positioned in a second row. The third exposure element is positioned between the second exposure member and the fourth exposure element and is smaller than the fourth exposure element. Each exposure member/element includes a light transmitter/blocker.

Abstract: Systems, methods, media, and other such embodiments described herein relate to critical area analysis (CAA) operations as part of electronic design automation (EDA). One embodiment involves accessing a circuit design having a first layer (which may be a composite layer), sampling the first layer, and performing an initial CAA using the sampled portions of the layer with a set of predetermined defect sizes. The initial CAA is used to automatically generate a model which can be used to accurately select input parameters (e.g., selected defect sizes) for a full analysis. A CAA characteristic is then calculated for the first layer using the input parameters. In various embodiments, different sampling percentages and criteria for selecting input parameters can be used to reduce the computing resources to compute a CAA characteristic, such as theta-bar, while limiting error to a threshold amount (e.g. less than one percent).

Abstract: In a method according to an embodiment, before etching a target layer of a wafer, a main surface of the target layer is divided into a plurality of areas. A difference value between a groove width of a mask and a reference value of the groove width is calculated for each of the plurality of areas, a temperature of the target layer is adjusted by using correspondence data indicating correspondence between a temperature of the target layer and a film thickness of a formed film. Then, a film is formed on the mask for each atom layer, and a film having a film thickness corresponding to the difference value is formed on the mask to correct the groove width in each of the plurality of areas to the reference value.

Abstract: Disclosed herein is a computer-implemented method for determining an overlapping process window (OPW) of an area of interest on a portion of a design layout for a device manufacturing process for imaging the portion onto a substrate, the method including: obtaining a plurality of features in the area of interest; obtaining a plurality of values of one or more processing parameters of the device manufacturing process; determining existence of defects, probability of the existence of defects, or both in imaging the plurality of features by the device manufacturing process under each of the plurality of values; and determining the OPW of the area of interest from the existence of defects, the probability of the existence of defects, or both.

Abstract: Apparatus and methods for encoding panoramic content, such as by a wide field of view and large image size. In one implementation, a panoramic image may be mapped to a cube, equirectangular or any other projection e.g., icosahedron or octahedron. Projection may be selected adaptively based on evaluation of the panoramic content. Content evaluation may include obtaining rate distortion cost metric for a given projection configuration including projection type, projection arrangement, and projection orientation. Projection configuration with the lowest cost may be selected as target projection for encoding content. As content composition changes (e.g., object motion, texture presence and/or location) projection may be adaptively selected to match changes in the content. Adaptive content selection methodology may provide for a lower encoded bitrate for a given encoded quality and/or higher quality for a given bitrate.

Abstract: Photoresist layers are exposed to an exposure beam by using an exposure tool assembly, wherein the photoresist layers coat semiconductor substrates and wherein for each exposure a current exposure parameter set is used that includes at least a defocus value and an exposure dose. The exposed photoresist layers are developed, wherein resist patterns are formed from the photoresist layers. Feature characteristics in the resist patterns and/or in substrate patterns derived from the resist patterns are measured. The current exposure parameter set is updated in response to deviations of the measured feature characteristics from target feature characteristics. De-corrected feature characteristics of hypothetical resist patterns are estimated, which would be formed without updating the exposure parameter set. In response to information obtained from the de-corrected feature characteristics the measurement strategy for the feature characteristics may be changed or the current exposure parameter set may be updated.

Abstract: Methods include inputting an array of pixels, where each pixel in the array of pixels has a pixel dose. The array of pixels represents dosage on a surface to be exposed with a plurality of patterns, each pattern of the plurality of patterns having an edge. A target bias is input. An edge of a pattern in the plurality of patterns is identified. For each pixel which is in a neighborhood of the identified edge, a calculated pixel dose is calculated such that the identified edge is relocated by the target bias. The array of pixels with the calculated pixel doses is output. Systems for performing the methods are also disclosed.

Abstract: A pattern of core material is formed on a wafer to include core features that have a critical dimension. A trim amount indicates an average amount of thickness to be removed from vertically oriented surfaces of the core features. A trim profile indicates how much variation in removal of thickness from vertically oriented surfaces of the core features is to be applied as a function of radial location on the wafer. A first set of data correlates the trim amount to one or more plasma trim process parameters. A second set of data correlates the trim profile to one or more plasma trim process parameters. Based on the trim amount, trim profile, and first and second sets of data, a set of plasma trim process parameters to achieve the trim amount and trim profile on the wafer is determined and a corresponding plasma trim process is performed on the wafer.