Abstract: A charged particle beam writing apparatus, includes a unit to input information about a stripe region height, and to judge, when a write region is divided into stripe regions in a thin rectangular shape by the stripe region height, whether a height of a last stripe region is narrower than the stripe region height; and a unit to divide the write region into stripe regions in the thin rectangular shape in such a way that the last stripe region and a stripe region prior to the last stripe region are combined to create one stripe region and stripe regions at least two stripe regions prior to the last stripe region are each created as stripe regions of the stripe region height if the height of the last stripe region is narrower than the stripe region height.

Abstract: A mask and methods for making the mask and monitoring mask haze using the mask are provided. The mask includes chip areas that are separated by scribe lanes. A scribe lane includes a monitoring area that contains a primary pattern and an associated assist feature. The assist feature includes two parallel scattering bars. Regions in the monitoring area other than the primary pattern and the associated assist feature are covered with a phase shift layer having a transmittance smaller than that of the primary pattern and the assist feature. When the mask is exposed to a light source, the assist feature is not transferred onto a wafer but cooperates with the primary pattern to generate a primary transferred pattern on the wafer. When a region between the two scattering bars has mask haze thereon, a defect identification pattern is generated on the wafer near the primary transferred pattern following exposure.

Abstract: The present disclosure provides a dithering method of increasing wafer throughput by an electron beam lithography system. The dithering method generates an edge map from a vertex map. The vertex map is generated from an integrated circuit design layout (such as an original pattern bitmap). A gray map (also referred to as a pattern gray map) is also generated from the integrated circuit design layout. By combining the edge map with the gray map, a modified integrated circuit design layout (modified pattern bitmap) is generated for use by the electron beam lithography system.

Abstract: A manufacturing method of a photomask by which a resist pattern corresponding to a pattern with designed values can be formed, a method for optical proximity correction, and a manufacturing method of a semiconductor device are provided. Proximity design features that are close to each other and estimated to violate a mask rule check are extracted. In the proximity design features, correction prohibited regions where optical proximity correction is not carried out are set based on the distance between the features obtained from the extracted proximity design features and the resolution of an exposure device. Optical proximity correction is carried out on the proximity design features with the correction prohibited regions excluded to obtain corrected proximity patterns. A predetermined mask material is patterned by carrying out electron beam lithography based on the corrected proximity pattern data.

Abstract: According to embodiments, an image forming apparatus has a sensor that scans a sheet to detect an identifier on the sheet, which indicates the presence, and orientation, of a form on the sheet, a memory that holds a reference pattern of the identifier, a control section that is configured to compare the identifier detected by the sensor and the reference pattern and determine the orientation of the form, and an image forming unit that form an image on the sheet. The image forming unit is configured to form the image so that the orientation of the image conforms to the orientation of the form.

Abstract: A document reading device (1) comprises a mounting surface (5) on which a page to be read (9) of a passport (7) is placed, a camera (13) for taking an image of the page to be read (9), an illumination light source (15) for radiating illumination light that will be reflected on the page to be read (9), and an ultraviolet light source (41) for radiating ultraviolet light to activate a fluorescent material on the page to be read (9). The illumination light source (15) is located at a position corresponding to a first edge (73) perpendicular to a binding edge (71) on the page to be read (9) and radiates illumination light in the direction intersecting with the first edge (73). The ultraviolet light source (41) is located at a position corresponding to a second edge (75) parallel to the binding edge (71) and arranged to radiate ultraviolet light in the direction intersecting with the second edge (75). The illumination light source (15) includes an infrared light source (21) and a white light source (31).

Abstract: The invention provides a method for patterning a resist coated substrate carried on a stage, where the patterning utilizes a charged particle beam. The method comprises the steps of: moving the stage at a nominally constant velocity in a first direction; while the stage is moving, deflecting the charged particle beam in the first direction to compensate for the movement of the stage, the deflecting including: (a) compensating for an average velocity of the stage; and (b) separately compensating for the difference between an instantaneous position of the stage and a calculated position based on the average velocity. The separately compensating step uses a bandwidth of less than 10 MHz. The invention also provides a deflector control circuit for implementing the separate compensation functions.

Abstract: Methods, systems, and tool sets involving reticles and photolithography processing. Several embodiments include obtaining qualitative data from within the pattern area of a reticle indicative of the physical characteristics of the pattern area. Additional embodiments include obtaining qualitative data indicative of the physical characteristics of the reticle remotely from a photolithography tool. In further embodiments qualitative data is obtained from within the pattern area of a reticle in a tool that is located remotely from the photolithography tool. Several embodiments provide data taken from within the pattern area to more accurately reflect the contour of the pattern area of the reticle without using the photolithography tool to obtain such measurements. This is expected to provide accurate data for correcting the photolithography tool to compensate for variances in the pattern area, and to increase throughput because the photolithography tool is not used to measure the reticle.

Abstract: Movements of a lithographic apparatus include dynamic positioning errors on one or more axes which cause corresponding errors which can be measured in the applied pattern. A test method includes operating the apparatus several times while deliberately imposing a relatively large dynamic positioning error at different specific frequencies and axes. Variations in the error in the applied pattern are measured for different frequencies and amplitudes of the injected error across a frequency band of interest for a given axis or axes. Calculation using said measurements and knowledge of the frequencies injected allows analysis of dynamic positioning error variations in frequency bands correlated with each injected error frequency.

Abstract: In view of realizing a lithographic process which makes it possible to estimate and correct flare with an extremely high accuracy, and causes only an extremely small dimensional variation in width, over the entire portion not only of a single shot region, but also of a single chip region, a mask pattern correction device of the present invention has a numerical aperture calculation unit calculating, for every single shot region, flare energy for a mask pattern corresponding to a transferred pattern, based on an exposure layout of a plurality of shot regions, or more specifically, while considering flare from a plurality of shot regions located around every single shot region.

Abstract: A method of making a mask includes receiving an IC design layout from a designer, applying an logic operation (LOP) correction, performing an OPC correction, fracturing the modified data into a plurality of main features in an electron beam format, and sending the electron beam format data to a mask writer for a mask fabrication. An XOR operation is implemented into the method to check and verify if a pattern is lost during OPC modification and/or data fracture. A BACKBONE XOR operation is also implemented into the method for a plurality of main features with a critical dimension (CD) size smaller than the max OPC correction to check and verify if a small pattern feature is lost during OPC modification and/or data fracture for 45 nm and beyond semiconductor technologies.

Abstract: Correction of critical dimension variation is accomplished with a second exposure, e.g. using a second reticle. Embodiments include exposing a first wafer with a first dose using a first reticle, having a pattern corresponding to a target pattern for a wafer, identifying CD variations between the exposed wafer and the target pattern for different features in the target pattern, exposing a second wafer with the first reticle using a second dose, less than or equal to the first dose, and correcting the CD variations by applying an additional exposure of the second wafer. Embodiments further include using one or more additional exposures to prevent printing unwanted structures on the reticle or to deliberately vary the sizes of selected structures on the wafer for development purposes.

Abstract: A method of manufacturing a semiconductor device in which the alignment accuracy of an immersion exposure device is maintained even when exposure steps are carried out intermittently. In the method, a substrate is placed on a stage of an exposure device (substrate placing step). Then, a first liquid is supplied to between the substrate and the optics system of the exposure device to expose the substrate through the first liquid (exposure step). A second liquid is supplied from a different place from the first liquid to a drainage groove provided around the stage at least in a period other than when the first liquid is supplied onto the stage, in order to suppress change in the temperature of the exposure device.

Abstract: An inspection method for inspecting a device mounted on a substrate, includes generating a shape template of the device, acquiring height information of each pixel by projecting grating pattern light onto the substrate through a projecting section, generating a contrast map corresponding to the height information of each pixel, and comparing the contrast map with the shape template. Thus, a measurement object may be exactly extracted.

Abstract: A multi charged particle beam writing apparatus according to one aspect of the present invention includes a plurality of first blankers to respectively perform blanking deflection of a corresponding beam in multiple beams having passed through the plurality of openings of the aperture member, a plurality of second blankers to deflect a defective beam in the multiple beams having passed through the plurality of openings of the aperture member to be in a direction orthogonal to a deflection direction of the plurality of first blankers, a blanking aperture member to block each of beams which were deflected to be in a beam off state by at least one of the plurality of first blankers and the plurality of second blankers, and a detection processing unit to detect a defective beam in the multiple beams having passed through the plurality of openings of the aperture member.

Abstract: A projection exposure tool for microlithography for imaging mask structures of an image-providing substrate onto a substrate to be structured includes a measuring apparatus configured to determine a relative position of measurement structures disposed on a surface of one of the substrates in relation to one another in at least one lateral direction with respect to the substrate surface and to thereby simultaneously measure a number of measurement structures disposed laterally offset in relation to one another.

Abstract: A ladder type stage apparatus that transports a film-shaped substrate includes a plurality of rods whose longitudinal directions are aligned in a direction that is orthogonal to the moving direction of the film-shaped substrate in order to support the film-shaped substrate; chains that join the rods along a closed-loop trajectory; and a drive motor that moves the rods along this loop-shaped trajectory via the chains.

Abstract: System and method of selective optical pattern enhancement for semiconductor manufacturing. A method for performing a photolithography process includes providing a reticle pattern for a photomask, the reticle pattern including one or more active areas, the photomask including at least a first active area and a first insulation area. The method also includes identifying a first structure pattern defined by the reticle pattern. Additionally, the method includes defining a block area covering the first structure, the block area being positioned within the active area. The method further includes applying at least a first optical proximity correction to the reticle pattern to form a corrected pattern, the first optical proximity correction being restricted to the block area. Also, the method includes transferring the corrected pattern to a wafer.

Abstract: After performing a pretreatment step of coating an organic solvent mixed with a polymeric organic compound over a substrate having a tungsten film formed on the surface of the substrate, a chemically amplified resist is coated to form a resist pattern. Further, a ratio of a C1s peak intensity to a W4d peak intensity measured by XPS is 0.1 or mote at the surface of the tungsten film after the pretreatment step and before coating the chemically amplified resist.

Abstract: A method for creating double patterning compliant integrated circuit layouts is disclosed. The method allows patterns to be assigned to different masks and stitched together during lithography. The method also allows portions of the pattern to be removed after the process.

Abstract: Aspects of the invention relate to techniques for determining edge fragment correlation information. With various implementations of the invention, image intensity slope information for edge fragments in a layout design is determined. The image intensity slope information comprises information describing how image intensity for each of the edge fragments changes with its position. Image amplitude sensitivity information for the edge fragments is also determined. The image amplitude sensitivity information comprises information describing how image amplitude for each of the edge fragments changes with positions of neighboring edge fragments. Based on the image intensity slope information and the image amplitude sensitivity information, edge fragment correlation information for the edge fragments is determined. Using the edge fragment correlation information, the layout design may be processed by using, for example, OPC techniques.

Abstract: A method for patterning a second layer of a work piece in a direct write machine in the manufacturing of a multilayer system-in-package stack. The work piece having a first layer with a plurality of electrical components in the form of dies arbitrarily placed. Each component having connection points where some need to be connected between the components. A first pattern wherein different zones comprising connection points of dies distributed in the first layer are associated with different requirements on alignment. The method comprising the steps of: a. Detecting sacred zones in first pattern that have a high requirement on alignment to selected features of the system-in-package stack or to the placed components; b. Detecting stretch zones of the first pattern that are allowed to have a lower requirement on alignment to other features of the system-in-package stack; c.

Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary method includes receiving an integrated circuit (IC) layout design including a target pattern on a grid. The method further includes receiving a multiple-grid structure. The multiple-grid structure includes a number of exposure grid segments offset one from the other by an offset amount in a first direction. The method further includes performing a multiple-grid exposure to expose the target pattern on a substrate and thereby form a circuit feature pattern on the substrate. Performing the multiple-grid exposure includes scanning the substrate with the multiple-grid structure in a second direction such that a sub-pixel shift of the exposed target pattern occurs in the first direction, and using a delta time (?t) such that a sub-pixel shift of the exposed target pattern occurs in the second direction.

Abstract: On a film where an exposure material coating has been formed in a exposure pattern formation region on a film base material, a colored firing material, colored light-curable material, or colored ink is applied to at least one of two widthwise side edges to form a side part application coating, which is irradiated with laser light by an alignment mark formation unit to form an alignment mark. The alignment mark is then used to detect film meandering and adjust the positions of masks. This makes it easy to form the alignment mark and detect the alignment mark thus formed and makes it possible to accurately correct for meandering of a film and stably expose the film in the process of continuous exposure of a film where an exposure material coating has been formed in a exposure pattern formation region on a film base material.

Abstract: A substrate is loaded onto a substrate support of a lithographic apparatus, after which the apparatus measures locations of substrate alignment marks. These measurements define first correction information allowing the apparatus to apply a pattern at one or more desired locations on the substrate. Additional second correction information is used to enhance accuracy of pattern positioning, in particular to correct higher order distortions of a nominal alignment grid. The second correction information may be based on measurements of locations of alignment marks made when applying a previous pattern to the same substrate. The second correction information may alternatively or in addition be based on measurements made on similar substrates that have been patterned prior to the current substrate.

Abstract: A detection apparatus, which detects a mark formed on a lower surface of a target object, includes: a first detector which illuminates the mark from an upper surface side of the target object to detect an image of the illuminated mark; a second detector which detects an upper surface position of the target object; and a processor which obtains information indicating a focus position to focus on the mark in the first detector, based on the upper surface position detected by the second detector.

Abstract: An electron beam lithography method and apparatus for improving throughput is disclosed. An exemplary lithography method includes receiving a pattern layout having a pattern layout dimension; shrinking the pattern layout dimension; and overexposing a material layer to the shrunk pattern layout dimension, thereby forming the pattern layout having the pattern layout dimension on the material layer.

Abstract: A method for correcting a position error of a lithography apparatus comprises inputting position data of exposure pattern, irradiating laser light onto a position reference mask from a position measurement laser system, calculating actual position data of the laser light irradiated onto the position reference mask, and comparing the position data of the exposure pattern with the actual position data of the laser light irradiated onto the position reference mask. With this method, circuit patterns can be accurately formed at predetermined positions on a photomask, and the circuit patterns on the photomask can be accurately formed at predetermined positions on a wafer.

Abstract: According to one embodiment, a mask pattern creation method includes extracting an area, in which a DSA material is directed self-assembled to form a DSA pattern, from a design pattern area based on a design pattern and information on the DSA material. The method also includes creating a guide pattern that causes the DSA pattern to be formed in the area based on the design pattern, the information on the DSA material, the area, and a design constraint when forming the guide pattern. The method further includes creating a mask pattern of the guide pattern using the guide pattern.

Abstract: A peripheral exposure method for performing an exposure treatment by illuminating light to a periphery of a resist film formed on a substrate to be processed is discussed. The method includes rotating the substrate to be processed on a horizontal plane, bringing a coolant gas into contact with the periphery of the resist film of the substrate to be processed which is being rotated, and cooling the substrate to be processed. Further, the method also includes measuring a temperature of the substrate to be processed, wherein when the temperature of the substrate to be processed is equal to or less than a predetermined temperature, the exposure treatment is performed.

Abstract: An apparatus for detecting a position of a mark from a mark signal obtained by capturing an image of the mark includes a signal processor. The signal processor is configured to set a processing window with respect to each of a plurality of positions relative to the mark signal, to calculate an even function intensity of the mark signal in the processing window with respect to each of the plurality of positions, and to detect the positions of the marks based on the even function intensity calculated with respect to each of the plurality of positions.

Abstract: A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a double patterning technology-compliant logical design for the integrated circuit, the logical design including a plurality of elements; scoring the design of one or more of the plurality of elements to produce a design score; modifying the design based at least in part on the design score; generating a mask set implementing the modified logical design; and employing the mask set to implement the logical design in and on a semiconductor substrate.

Abstract: Techniques for forming a first electronic circuit including a plurality of instances of a repeatable circuit element include the steps of: obtaining a total number of instances of the repeatable circuit element in a design of an IC including the first electronic circuit and at least a second electronic circuit; and configuring at least one functional parameter of the first electronic circuit as a function of the total number of instances of the repeatable circuit element in the IC to thereby satisfy a prescribed minimum composite manufacturing yield of the IC and/or at least one specification of the IC under prescribed operating conditions.

Abstract: The present disclosure provides for many different embodiments of a charged particle beam data storage system and method. In an example, a method includes dividing a design layout into a plurality of units; creating a lookup table that maps each of the plurality of units to its position within the design layout and a data set, wherein the lookup table associates any repeating units in the plurality of units to a same data set; and exposing an energy sensitive layer to a charged particle beam based on the lookup table.

Abstract: Masks for patterning material layers of semiconductor devices, methods of patterning and methods of manufacturing semiconductor devices, and lithography systems are disclosed. A lithography mask includes a pattern of alternating lines and spaces, wherein the lines and spaces comprise different widths. When the lithography mask is used to pattern a material layer of a semiconductor device, the pattern of the material layer comprises alternating lines and spaces having substantially the same width.

Abstract: According to one embodiment, a flare prediction method in photolithography includes determining a pattern density distribution of a pattern layout, determining an inclination of a variation in the pattern density distribution, and performing a flare calculation in a plurality of partition sizes based on the inclination of a variation in the pattern density distribution.

Abstract: In the field of semiconductor production using shaped charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, in which a plurality of shaped beam shots is determined which will form a target pattern on a surface, within a predetermined tolerance, where the plurality of shaped beam shots includes a plurality of circular or nearly-circular character projection (CP) shots plus one or more non-circular shot, and where at least two shots in the plurality of circular or nearly-circular shots overlap. Methods for manufacturing a surface and for manufacturing a semiconductor device on a substrate are also disclosed.

Abstract: A pattern is formed on a mask substrate. Positional deviation information between an actual position of the pattern formed on the mask substrate and a design position decided at the time of designing the pattern is calculated. A heterogeneous layer of which a volume expands more greatly than that of surrounding mask substrate region is formed in a predetermined position within the mask substrate so that volume expansion of the heterogeneous layer according to the positional deviation information is achieved.

Abstract: A method for performing a photolithography process includes providing a reticle on a projection apparatus, the reticle having a test pattern defined thereon, the test pattern including a plurality of one-dimensional structures and a plurality of two-dimensional structures. The test pattern defined on the reticle is transferred to at least one area on a wafer. The projection apparatus is focused on the test pattern transferred on the wafer during a photolithography process to perform a process monitoring.

Abstract: According to one embodiment, generating virtual data by mirroring data based on a dimension measurement result in a measurement region on an inner side of a shot region to a non-shot region on an outer side of a shot edge, and calculating dose data of the measurement region and a non-measurement region based on data in the measurement region and the virtual data are included.

Abstract: In the field of semiconductor production using charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed. Base dosages for a plurality of exposure passes are set and a multiplicity of shots for the plurality of exposure passes is exposed. The multiplicity of shots comprises two groups: a first group of shots for at least two exposures passes, wherein the union of shots for each exposure pass covers the same area, and where shots within an exposure pass are disjoint; and a second group of shots, where each shot in the second group of shots overlaps a shot in the first group of shots. Each shot in the second group is in one of the plurality of exposure passes. A method for forming a set of patterns on a surface is also disclosed.

Abstract: The energy distribution of exposure light directed passing through the slit of an exposure apparatus is determined. A photoresist layer on a substrate is exposed over a plurality of shots while changing the intensity of the exposure light for each shot. Then the photoresist layer is developed to form a sample photoresist layer. An image of the developed sample photoresist layer is analyzed for color intensity. Values of the color intensity across a selected one of the shots are correlated with values of the intensity of the exposure light to produce an energy distribution of the exposure light along the length of the slit. The energy distribution is used to change the slit so that a more desirable energy distribution may be realized when the slit is used in a process of manufacturing a semiconductor device.

Abstract: A method of generating a mask having optical proximity correction features.

Abstract: A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.

Abstract: Methods of making flexible circuit films include providing a polymer film or other flexible substrate having a plurality of alignment marks and a photosensitive material thereon. The substrate passes around a suitable roller, belt, or other inelastic conveyor such that the substrate and the conveyor move together at least from a first location to a second location. Positions of a first set of the alignment marks on a first portion of the substrate are measured when such portion is at the first location, and the measured positions can be used to calculate a distortion of the substrate. The photosensitive material is then patternwise exposed when the first portion of the substrate has moved to the second location. The patternwise exposing is based on the measured positions of the first set of alignment marks, and may include exposing the web with a distortion-adjusted pattern. Related systems and articles are also disclosed.

Abstract: A method of splitting a lithographic pattern into two sub-patterns, includes generating test structures corresponding to structures of interest in the lithographic pattern, varying the test structures through a selected range of dimensions, simulating an image of the test structures, determining an image quality metric for the simulated image, analyzing the determined image quality metric to determine pitch ranges for which split improves the image quality metric and ranges for which split does not improve the image quality metric, and generating the two sub-patterns in accordance with the determined pitch ranges.

Abstract: A method for correcting a layout pattern includes the following steps. A first layout pattern, a second layout pattern, and a mis-alignment value are provided. The first layout pattern includes a first conducting line pattern, and the second layout pattern includes at least one contact via pattern. The contact via pattern at least partially overlaps the first conducting line pattern. The layout pattern is verified whether spacing between the contact via pattern and the first conducting line pattern is smaller than the mis-alignment value by a computing system. A first modified contact via pattern is then obtained by expanding the contact via pattern along a direction away from the spacing smaller than the mis-alignment value.

Abstract: A charged particle beam drawing apparatus has a drawing chamber including a movable stage which supports a mask, the mask being formed by applying a resist to an upper surface of a mask substrate, an optical column for applying a charged particle beam to draw patterns in the resist, a charged particle beam dose correction portion for correcting a dose of the charged particle beam applied from the optical column to the resist on the basis of proximity effect and fogging effect, and a conversion coefficient changing portion for changing a conversion coefficient on the basis of pattern density in the resist and a position in the resist, wherein the conversion coefficient is a ratio of an accumulation energy of the charged particle beam accumulated in the resist, to an accumulation dose of the charged particle beam accumulated in the resist.

Abstract: At least one pattern of a photomask is identified that has a likelihood of causing collapse of a microelectronic device feature that is formed using the photomask, due to surface tension of a solution that is applied to the feature during manufacture of the microelectronic device. The patterns of the photomask are then modified to reduce the likelihood of the collapse. The photomask may be formed and the photomask may be used to manufacture microelectronic devices. Related methods, systems, devices and computer program products are described.

Abstract: A method of forming a semiconductor device can include determining a shot set including a plurality of shots, based on a final pattern used to form a mask. Shots included in the plurality shots can be classified as being in a first pass shot set or in a second pass shot set, where each can include a plurality of non-directly neighboring shots. A first pass exposure can be performed to radiate a reticle to provide the first pass shot set and a second pass exposure can be performed to radiate the reticle to provide the second pass shot set.