Abstract: An electron beam lithography method and apparatus for improving throughput is disclosed. An exemplary lithography method includes receiving a pattern layout having a pattern layout dimension; shrinking the pattern layout dimension; and overexposing a material layer to the shrunk pattern layout dimension, thereby forming the pattern layout having the pattern layout dimension on the material layer.

Abstract: One or more techniques or systems for determining double patterning technology (DPT) layout routing compliance are provided herein. For example, a layout routing component of a system is configured to assign a pin loop value to a pin loop. In some embodiments, the pin loop value is assigned based on a mask assignment of a pin of the pin loop. In some embodiments, the pin loop value is assigned based on a number of nodes associated with the pin loop. DPT compliance or a DPT violation is determined for the pin loop based on the pin loop value. In this manner, odd loop detection associated with DPT layout routing is provided because a DPT violation results in generation of an additional instance of a net, for example. Detecting an odd loop allows a design to be redesigned before fabrication, where the odd loop would present undesired issues.

Abstract: An electron beam lithography method and apparatus for improving throughput is disclosed. An exemplary lithography method includes receiving a pattern layout having a pattern layout dimension; shrinking the pattern layout dimension; and overexposing a material layer to the shrunk pattern layout dimension, thereby forming the pattern layout having the pattern layout dimension on the material layer.

Abstract: According to one embodiment, an exposure tolerance estimation method is disclosed. The method can include setting a plurality of regions along a first surface of a substrate. The method can form a plurality of patterns for estimation by performing exposure on each of the regions using at least three levels of exposure condition using an exposure mask. The method can measure dimensions of the patterns for estimation and find relationships between the exposure condition and the dimensions. The method can select a first region from the regions. In the first region, a first dimension of a first pattern for estimation formed by exposure using a first exposure condition of an intermediate level out of the at least three levels falls within a previously set range. In addition, the method can calculate an exposure tolerance from a relationship between the first exposure condition and the first dimension.

Abstract: The present disclosure provides for many different embodiments of a charged particle beam data storage system and method. In an example, a method includes dividing a design layout into a plurality of units; creating a lookup table that maps each of the plurality of units to its position within the design layout and a data set, wherein the lookup table associates any repeating units in the plurality of units to a same data set; and exposing an energy sensitive layer to a charged particle beam based on the lookup table.

Abstract: A manufacturing method of a photomask by which a resist pattern corresponding to a pattern with designed values can be formed, a method for optical proximity correction, and a manufacturing method of a semiconductor device are provided. Proximity design features that are close to each other and estimated to violate a mask rule check are extracted. In the proximity design features, correction prohibited regions where optical proximity correction is not carried out are set based on the distance between the features obtained from the extracted proximity design features and the resolution of an exposure device. Optical proximity correction is carried out on the proximity design features with the correction prohibited regions excluded to obtain corrected proximity patterns. A predetermined mask material is patterned by carrying out electron beam lithography based on the corrected proximity pattern data.

Abstract: A writing area of a sample is divided into a plurality of stripes having a width corresponding to an area density of a pattern to be written on the sample with a charged-particle beam. The writing is stopped when writing of at least one stripe is terminated, and a drift amount is measured. An irradiation position of the charged-particle beam is corrected with the use of the drift amount. When the average value of the area density is more than a predetermined value, a stripe has a width smaller than the reference width, and when the average value of the area density is less than the predetermined value, the stripe has a width larger than the reference width. The width of the stripe is preferably a width corresponding to the variation of a drift from the beginning of irradiation with the charged-particle beam.

Abstract: The present disclosure provides a method for electron-beam (e-beam) lithography patterning. The method includes forming a resist layer on a substrate; performing a first e-beam exposure process to the resist layer according to a first pattern; performing a second e-beam exposure process to the resist layer according to a second pattern, wherein the second patterned is overlapped to the first pattern on the resist layer; and developing the resist layer.

Abstract: In a method and a device for operating a drive unit, a first output variable of the drive unit is restricted; a setpoint value of a second output variable of the drive unit is specified; and an actual value of the second output variable of the drive unit is determined. The setpoint value is compared with the actual value, and if it is determined that the actual value does not exceed the setpoint value, then the first output variable is restricted to a first value. If it is determined that the actual value exceeds the setpoint value, then the first output variable is restricted to a second value smaller than the first value.

Abstract: The present invention is directed to an electrophoretic display comprising: (a) microcups comprising partition walls and top-openings; (b) an organic-based electrophoretic fluid filled in the microcups, wherein said fluid comprises charged pigment particles dispersed in a solvent; and (c) a top-sealing layer formed from a sealing composition to enclose the electrophoretic fluid within the microcups. The sealing composition comprises: (i) a water soluble polymer, (ii) a water-based suspension, a water-based dispersion, a water-based emulsion, or a water-based latex, each comprising a polymer; and (iii) water.

Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary method includes receiving an integrated circuit (IC) layout design including a target pattern on a grid. The method further includes receiving a multiple-grid structure. The multiple-grid structure includes a number of exposure grid segments offset one from the other by an offset amount in a first direction. The method further includes performing a multiple-grid exposure to expose the target pattern on a substrate and thereby form a circuit feature pattern on the substrate. Performing the multiple-grid exposure includes scanning the substrate with the multiple-grid structure in a second direction such that a sub-pixel shift of the exposed target pattern occurs in the first direction, and using a delta time (?t) such that a sub-pixel shift of the exposed target pattern occurs in the second direction.

Abstract: A method for optical proximity correction (OPC) is disclosed, in which a set of VSB shots is determined, where the set of shots can approximately form a target reticle pattern that is an OPC-compensated version of an input pattern. The set of shots is simulated to create a simulated reticle pattern. A substrate image is calculated, based on using the simulated reticle pattern in an optical lithographic process to form the substrate image. A system for OPC is also disclosed.

Abstract: A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identifies a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout.

Abstract: The present disclosure provides an embodiment of a method, for a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel size S1 to generate an alternating data grid having a second pixel size S2 that is <S1, wherein the pattern generator includes multiple grid segments configured to offset from each other in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each subsequent segment of the grid segments is controlled to have a time delay relative to a preceding segment of the grid segments.

Abstract: The present disclosure provide one embodiment of a method of a lithography process for reducing a critical dimension (CD) by a factor n wherein n<1. The method includes providing a pattern generator having a first pixel area S1 to generate a data grid having a second pixel area S2 that is equal to n2*S1, wherein the pattern generator includes a multi-segment structure having multiple grid segments, wherein the grid segments includes a first set of grid segments and a second set of grid segments, each of the first set of grid segments being configured to have an offset in a first direction; and scanning the pattern generator in a second direction perpendicular to the first direction during the lithography process such that each of the second set of grid segments is controlled to have a time delay.

Abstract: A method comprises: (a) transforming a layout of a layer of an integrated circuit (IC) or micro electro-mechanical system (MEMS) to a curvilinear mask layout; (b) replacing at least one pattern of the curvilinear mask layout with a previously stored fracturing template having approximately the same shape as the pattern, to form a fractured IC or MEMS layout; and (c) storing, in a non-transitory storage medium, an e-beam generation file including a representation of the fractured IC or MEMS layout, to be used for fabricating a photomask.

Abstract: Described herein is a method for obtaining a preferred layout for a lithographic process, the method comprising: identifying an initial layout including a plurality of features; and reconfiguring the features until a termination condition is satisfied, thereby obtaining the preferred layout; wherein the reconfiguring comprises evaluating a cost function that measures how a lithographic metric is affected by a set of changes to the features for a plurality of lithographic process conditions, and expanding the cost function into a series of terms at least some of which are functions of characteristics of the features.

Abstract: A method for verifying stitching accuracy of a stitched chip on a wafer is disclosed. Initially, a set of test structures are inserted within a reticle layout. An exposure program is executed to control a photolithography equipment having a stepper to perform multiple exposures of the reticle on a wafer to generate a stitched chip on the wafer. Electrical measurements are then performed on the test structures at actual stitch boundaries of the stitched chip to evaluate stitching accuracy of the stitched chip.

Abstract: Disclosed is a method, system, and computer program product for performing predictions for an electronic design. Embodiments of the invention allow the ability to efficiently update the model predictions at a later time once previously incomplete blocks are completed. Predictions can be efficiently updated after block designs are updated (e.g. after correcting problems detected from model predictions).

Abstract: Systems and methods for process simulation are described. The methods may use a reference model identifying sensitivity of a reference scanner to a set of tunable parameters. Chip fabrication from a chip design may be simulated using the reference model, wherein the chip design is expressed as one or more masks. An iterative retuning and simulation process may be used to optimize critical dimension in the simulated chip and to obtain convergence of the simulated chip with an expected chip. Additionally, a designer may be provided with a set of results from which an updated chip design is created.

Abstract: Described herein is a method of processing a pattern layout for a lithographic process, the method comprising: identifying a feature from a plurality of features of the layout, the feature violating a pattern layout requirement; and reconfiguring the feature, wherein the reconfigured feature still violates the pattern layout requirement, the reconfiguring including evaluating a cost function that measures a lithographic metric affected by a change to the feature and a parameter characteristic of relaxation of the pattern layout requirement.

Abstract: Among other things, one or more techniques and systems for performing design layout are provided. An initial design layout is associated with an electrical component, such as a standard cell. The initial design layout comprises a first pattern, such as a mandrel pattern, and a second pattern, such as a passive fill pattern. An initial cut pattern is generated for the initial design layout. Responsive to identifying a design rule violation associated with the initial cut pattern, the initial design layout is modified to generate a modified initial design layout. An updated cut pattern, not resulting in the design rule violation, is generated based upon the modified initial design layout. The updated cut pattern is applied to the modified initial design layout to generate a final design layout. The final design layout can be verified as self-aligned multiple patterning (SAMP) compliant.

Abstract: A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.

Abstract: A method of determining calibration test patterns to be utilized to calibrate a model for simulating the imaging performance of an optical imaging system. The method includes the steps of defining a model equation representing the imaging performance of the optical imaging system; transforming the model equation into a plurality of discrete functions; identifying a calibration pattern for each of the plurality of discrete functions, where each calibration pattern corresponding to one of the plurality of discrete functions being operative for manipulating the one of the plurality of discrete functions during a calibration process; and storing the calibration test patterns identified as corresponding to the plurality of discrete functions. The calibration test patterns are then utilized to calibrate the model for simulating the imaging performance of an optical imaging system.

Abstract: In a method and apparatus for quantitatively evaluating two-dimensional patterns, a reference coordinate system is set in order to convert pattern edge information (one-dimensional data) acquired by measurement using an existing critical dimension machine into coordinate data. Thus, a pattern is converted into coordinate information. Next, a function formula is determined from this coordinate information by approximate calculation and a pattern is represented by the mathematical expression y=f(x). Integrating y=f(x) in the reference coordinate used when calculating the coordinate data gives the area of the pattern, whereby it is possible to convert the coordinate data to two-dimensional data.

Abstract: Correction of reticle defects, such as EUV reticle defects, is accomplished with a second exposure. Embodiments include obtaining a reticle with a first pattern corresponding to a design for a wafer pattern, detecting dark defects and/or design/OPC weak spots in the first pattern, exposing a resist covered wafer using the reticle, and exposing the wafer using a second reticle with a second pattern or a second image field with openings corresponding to the dark defects, with a repair pattern on the reticle or on another reticle, or with a programmed e-beam or laser writer.

Abstract: One embodiment relates to a method of measuring overlay errors for a programmable pattern, area-imaging electron beam lithography apparatus. Patterned cells of an overlay measurement target array may be printed in swaths such that they are superposed on patterned cells of a first (base) array. In addition, the overlay array may have controlled-exposure areas distributed within the swaths. The superposed cells of the overlay and base arrays are imaged. The overlay errors are then measured based on distortions between the two arrays in the image data. Alternatively, non-imaging methods, such as using scatterometry, may be used. Another embodiment relates to a method for correcting overlay errors for an electron beam lithography apparatus. Overlay errors for a pattern to be printed are determined based on within-swath exposure conditions. The pattern is then pre-distorted to compensate for the overlay errors. Other embodiments, aspects and features are also disclosed.

Abstract: In the field of semiconductor production using charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, in which the union of shots from one of a plurality of exposure passes is different than the union of shots from a different exposure pass. Methods for manufacturing a reticle and manufacturing an integrated circuit are also disclosed, in which the union of shots from one of a plurality of charged particle beam exposure passes is different than the union of shots from a different exposure pass.

Abstract: The present invention provides an exposure apparatus which exposes a substrate, the apparatus including an adjustment unit configured to adjust an oxygen concentration in a space between the projection optical system and the substrate, a measuring unit configured to measure an illuminance of light applied to the substrate, and a control unit configured to control the measuring unit so as to measure illuminances of light applied to the substrate a plurality of times during irradiation of the substrate with light from the projection optical system, configured to calculate, based on each of the illuminances measured the plurality of times, an oxygen concentration value corresponding to the measured illuminance on each time and configured to control the adjustment unit so as to set the oxygen concentration in the space to the calculated oxygen concentration value.

Abstract: Systems and methods are provided for extracting parasitics in a design of an integrated circuit with multi-patterning requirements. The method includes determining resistance solutions and capacitance solutions. The method further includes performing parasitic extraction of the resistance solutions and the capacitance solutions to generate mean values for the resistance solutions and the capacitance solutions. The method further includes capturing a multi-patterning source of variation for each of the resistance solutions and the capacitance solutions during the parasitic extraction. The method further includes determining a sensitivity for each captured source of variation to a respective vector of parameters. The method further includes determining statistical parasitics by multiplying each of the resistance solutions and the capacitance solutions by the determined sensitivity for each respective captured source of variation.

Abstract: A method and system arrangement for controlling and determining mask operation activities. Upon obtaining chip physical layout design data and running resolution enhancement technology on the chip physical layout design to generate mask features which may include any sub-resolution assist features, a placement sensitivity metric is determined for each of the generated mask features or edge fragments. In one alternative embodiment an edge placement sensitivity metric is determined for each edge of the generated mask features or edge fragments. The determined sensitivity metrics for each feature are classified and applied to subsequent mask operational activities such as post processing, write exposure and mask repair.

Abstract: A method of forming a pattern of doped region includes the following steps. At first, a device layout pattern including a gate layout pattern and a doped region layout pattern is provided to a computer system. Subsequently, the device layout pattern is split into a plurality of sub regions, and the sub regions have different pattern densities of the gate layout pattern. Then, at least an optical proximity correction (OPC) calculation is respectively performed on the doped region layout pattern in each of the sub regions to respectively form a corrected sub doped region layout pattern in each of the sub regions. Afterwards, the corrected sub doped region layout patterns are combined to form a corrected doped region layout pattern, and the corrected doped region layout pattern is outputted onto a mask through the computer system.

Abstract: A method for forming an integrated circuit (IC) is presented. The method includes providing a wafer having a substrate prepared with a photoresist layer. The photoresist layer is processed by passing a radiation from an exposure source of a lithography tool through a mask having a pattern. The process parameters of the lithography tool are determined by performing a pattern matching process. The photoresist layer is developed to transfer the pattern on the mask to the photoresist layer.

Abstract: An integrated circuit with standard cells with top and bottom metal-1 and metal-2 power rails and with lateral standard cell borders that lie between an outermost vertical dummy poly lead from one standard cell and an adjacent standard cell. A DPT compatible standard cell design rule set. A method of forming an integrated circuit with standard cells constructed using a DPT compatible standard cell design rule set. A method of forming DPT compatible standard cells.

Abstract: An apparatus includes a probe tip configured to contact the mask, a cantilever configured to mount the probe tip wherein the cantilever includes a mirror, an optical unit having a light source projecting a light beam on the mirror and a light detector receiving a reflected light beam from the mirror, and an electrical power supply configured to connect the probe tip. The apparatus further includes a computer system configured to connect the optical unit, the electrical power supply, and the stage. The electrical power supply provides an electrical current to the probe tip and heats the probe tip to a predetermined temperature. The heated probe tip repairs a defect by smoothing and reducing a dimension of the defect, and inducing structural deformations of multilayer that cancel out the distortion (of multilayer) caused by buried defects using the heated probe tip as a thermal source canning the defect.

Abstract: A method includes determining model parameters for forming an integrated circuit, and generating a techfile using the model parameters. The techfile includes at least two of a C_worst table, a C_best table, and a C_nominal table. The C_worst table stores greatest parasitic capacitances between layout patterns of the integrated circuit when lithography masks comprising the layout patterns shift relative to each other. The C_best table stores smallest parasitic capacitances between the layout patterns when the lithography masks shift relative to each other. The C_nominal table stores nominal parasitic capacitances between the layout patterns when the lithography masks do not shift relative to each other. The techfile is embodied on a tangible non-transitory storage medium.

Abstract: A charged particle beam drawing method according to an embodiment is a method including forming a first measurement pattern in a first measurement pattern area; in succession with processing of forming the first measurement pattern, forming a second measurement pattern in a second measurement pattern area located farthest from the first measurement pattern area in the same column as the first measurement pattern area; and in moving a charged particle beam from the second measurement pattern area to a third measurement pattern area located adjacent to the first measurement pattern area in the same column as the first and second measurement patterns to form a third measurement pattern, moving the charged particle beam to the third measurement pattern area while taking tiny shots approximately equivalent to a data resolution at the adjacent measurement pattern areas to be drawn in the same column one after another from the second measurement pattern.

Abstract: Methods and structures for extreme ultraviolet (EUV) lithography are disclosed. A method includes determining a phase error correction for a defect in an EUV mask, determining an amplitude error correction for the EUV mask based on both the defect in the EUV mask and the phase error correction, and modifying the EUV mask with the determined phase error correction and the determined amplitude error correction.

Abstract: A method for forming an integrated circuit (IC) is presented. The method includes providing a wafer having a substrate prepared with a photoresist layer. The photoresist layer is processed by passing a radiation from an exposure source of a lithography tool through a mask having a pattern. The process parameters of the lithography tool are determined by performing a pattern matching process. The photoresist layer is developed to transfer the pattern on the mask to the photoresist layer.

Abstract: A mask overlay method, and a mask and a semiconductor device using the same are disclosed. According to the disclosed mask overlay technique, test marks and front layer overlay marks corresponding to a plurality of overlay mark designs are generated in a first layer of a semiconductor device. The test patterns generating the test marks each include a first sub pattern and a second sub pattern. Note that the first sub pattern has the same design as a front layer overlay pattern (which generates the front layer overlay mark corresponding thereto). Based on the test marks, performances of the plurality of overlay mark designs are graded. The front layer overlay mark corresponding to the overlay mark design having the best performance is regarded as an overlay reference for a mask of a second layer of the semiconductor device.

Abstract: The present invention provides a mask and a repairing method therefor. A reference area is selected in a configuration pattern of a mask template, the reference area is corresponding to a to-be-shaded area of a mask; a repair area is formed on a drillable member according to the reference area; a hollow area is formed in the repair area of the drillable member, the hollow area is corresponding to the to-be-shaded area; the drillable member is attached to the mask, the hollow area is corresponding to the to-be-shaded area; and shading material is coated on the drillable member, so as to form a shaded layer on the to-be-shaded layer.

Abstract: In a case where a substrate is exposed to exposure light of a first wavelength band, an exposure coefficient, which is defined as an amount of fluctuation of an imaging characteristic of a projection optical system per unit of exposure energy, for the first wavelength band is calculated using data of the amount of fluctuation of the optical characteristic of the projection optical system. An exposure coefficient for a second wavelength band that is different from the first wavelength band is calculated using the exposure coefficient for the first wavelength band. In a case where the substrate is exposed to exposure light of the second wavelength band, the amount of fluctuation of the imaging characteristic of the projection optical system is calculated using the exposure coefficient for the second wavelength band.

Abstract: A method for fracturing or mask data preparation or proximity effect correction or optical proximity correction or mask process correction is disclosed in which a set of charged particle beam shots is determined that is capable of forming a pattern on a surface, wherein critical dimension (CD) split is reduced through the use of overlapping shots.

Abstract: Exposure apparatus is equipped with an illumination optical device which illuminates a mask with an exposure beam, a mask table which holds a periphery of a pattern area of the mask from above so that a pattern surface of the mask becomes substantially parallel to an XY plane and makes a force at least parallel to an XY plane and on the mask, and a wafer stage which moves along the XY plane, holding a wafer substantially parallel to the XY plane. Therefore, an overlay with high precision of a pattern of a mask and an underlying pattern on the substrate can be realized, even though the exposure apparatus employs a proximity method, that is, the exposure apparatus does not use a projection optical system.

Abstract: Disclosed is a method of modifying of a surface of a substrate of a photolithographic mask for extreme ultraviolet radiation comprising the step of focusing femtosecond light pulses of a laser system onto the substrate so that a plurality of color centers is generated inside the substrate, wherein the color centers are distributed to cause a modification of the substrate surface.

Abstract: A method for fabricating an anti-fuse memory cell having a semiconductor structure with a minimized area. The method includes providing a reference pattern for the semiconductor structure, and applying a reverse OPC technique that includes inverting selected corners of the reference pattern. The reverse OPC technique uses photolithographic distortions to provide a resulting fabricated pattern that is intentionally distorted relative to the reference pattern. By inverting corners of a geometric reference pattern, the resulting distorted pattern will have an area that is reduced relative to the original reference pattern. This technique is advantageous for reducing the area of a selected region of a semiconductor structure which may otherwise not be possible through normal design parameters.

Abstract: A layout decomposition method and a method for manufacturing a semiconductor device applying the same are provided. According to the layout decomposition method, a design layout is received by the logic processer of a computing system. A design rule for layout decomposition is then identified by the logic processer, including identifying the loose areas (areas with loosely distributed features) and dense areas (areas with densely distributed features) on a substrate, and identifying first areas with odd-numbered features and second areas with even-numbered features on the substrate. Next, a first mask with a first pattern and a second mask with a second pattern are generated corresponding to results of design rule identification by the computing system.

Abstract: The present disclosure describes methods of forming a mask. In an example, the method includes receiving an integrated circuit (IC) design layout, modifying the IC design layout data using an optical proximity correction (OPC) process, thereby providing an OPCed IC design layout, and modifying the OPCed IC design layout data using a mask rule check (MRC) process, wherein the MRC process corrects rule violations of the OPCed IC design layout data using a mask error enhancement factor (MEEF) index, thereby providing a MRC/OPCed IC design layout.

Abstract: A method comprises: selecting a circuit pattern or network of circuit patterns in a layout of an integrated circuit (IC) to be fabricating using double patterning technology (DPT). Circuit patterns near the selected circuit pattern or network are grouped into one or more groups. For each group, a respective expected resistance-capacitance (RC) extraction error cost is calculated, which is associated with a mask alignment error, for two different sets of mask assignments. The circuit patterns in the one or more groups are assigned to be patterned by respective photomasks, so as to minimize a total of the expected RC extraction error costs.

Abstract: After a cassette is mounted on a cassette mounting part, a control unit instructs a substrate treatment apparatus to start treatment on substrates in the cassette. Thereafter, the control unit indicates, to the substrate treatment apparatus, a cassette on the cassette mounting part to which a substrate is transferred at completion of the treatment. If the transfer destination cassette for the substrate at the completion of treatment has not been indicated when a number of remaining treatment steps for the substrate reaches a predetermined set number, an alarm is given from the substrate treatment apparatus. This alarm is sent from the substrate treatment apparatus to the control unit, and the control unit indicates a transfer destination cassette for the substrate.