Etching Of Substrate And Material Deposition Patents (Class 430/314)
  • Patent number: 10248023
    Abstract: A method of manufacturing a semiconductor device includes: coating a first resist containing a photoacid generator or a thermal acid generator on a semiconductor substrate; forming a first opening portion in the first resist by optical exposure; subjecting a shrink agent containing an acid to a crosslinking reaction by the heat treatment to form a thermoset layer on an overall surface of the first resist; coating a second resist on the semiconductor substrate and the thermoset layer; and forming a second opening portion located above the first opening portion and larger than the first opening portion in the second resist by optical exposure.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: April 2, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yasuki Aihara, Kazuyuki Onoe, Takahiro Ueno
  • Patent number: 10164184
    Abstract: A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fu-Ting Sung, Ching-Pei Hsieh, Chia-Shiung Tsai, Chern-Yow Hsu, Shih-Chang Liu
  • Patent number: 10114288
    Abstract: Wet-strippable underlayer compositions comprising one or more silicon-containing polymers comprising a backbone comprising Si—O linkages, one or more organic blend polymers, and a cure catalyst are provided. These compositions are useful in the manufacture of various electronic devices.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: October 30, 2018
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: Charlotte A. Cutler, Suzanne M. Coley, Owendi Ongayi, Christopher P. Sullivan, Paul J. LaBeaume, Li Cui, Shintaro Yamada, Mingqi Li, James F. Cameron
  • Patent number: 10049892
    Abstract: Techniques herein include methods of processing photoresist patterns and photoresist materials for successful use in multi-patterning operations. Techniques include combinations of targeted deposition, curing, and trimming to provide a post-processed resist that effectively enables multi-patterning using photoresist materials to function as mandrels. Photoresist patterns and mandrels are hardened, strengthened, and/or dimensionally adjusted to provide desired dimensions and/or mandrels enabling straight sidewall spacers. Polymer is deposited with tapered profile to compensate for compressive stresses of various conformal or subsequent films to result in a vertical profile despite any compression.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: August 14, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Nihar Mohanty, Eric Chih-Fang Liu, Elliott Franke
  • Patent number: 10043851
    Abstract: A process flow for forming magnetic tunnel junction (MTJ) nanopillars with minimal sidewall residue and damage is disclosed wherein a pattern is first formed in a hard mask or uppermost MTJ layer. Thereafter, the hard mask sidewall is etch transferred through the remaining MTJ layers with a RIE process comprising main etch and over etch portions, and a cleaning step. The RIE process features noble gas and an oxidant that is one or more of CH3OH, C2H5OH, NH3, N2O, H2O2, H2O, O2, and CO. Noble gas/oxidant flow rate ratio during over etch may be greater than during main etch to avoid chemical damage to MTJ sidewalls. The cleaning step may comprise plasma or ion beam etch with the noble gas and oxidant mixture. Highest values for magnetoresistive ratio and coercivity (Hc) are observed for noble gas/oxidant ratios from 75:25 to 90:10, especially for MTJ nanopillar sizes ?100 nm.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: August 7, 2018
    Assignee: Headway Technologies, Inc.
    Inventors: Dongna Shen, Yu-Jen Wang
  • Patent number: 10020377
    Abstract: A method of manufacturing an electronic device comprising a first terminal (e.g. a source terminal), a second terminal (e.g. a drain terminal), a semiconductor channel connecting the first and second terminals and a gate terminal to which a potential may be applied to control a conductivity of the channel. The method comprises a first exposure of a photoresist from above the substrate using a mask and a second exposure from below, wherein in the second exposure the first and second terminals shield a part of the photoresist from exposure. An intermediate step reduces the solubility of the photoresist exposed in the first exposure. A window is formed in the photoresist at the location which was shielded by the mask, but exposed to radiation from below. Semiconductor material, dielectric material and conductor material are deposited inside the window to form a semiconductor channel, gate dielectric, and a gate terminal, respectively.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: July 10, 2018
    Assignee: Pragmatic Printing Limited
    Inventors: John James Gregory, Richard David Price
  • Patent number: 9982339
    Abstract: A mask comprises a mask substrate having a protruding section in an opening end surface of an opening, having an acute angle defined by ?1 and ?2 of no more than 43°, and having a height from a film-formation surface on the substrate to a tip section of the protruding section greater than the thickness of the film to be formed on the film-formation surface.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: May 29, 2018
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tetsuya Okamoto, Takeshi Hirase, Tohru Senoo, Tohru Sonoda, Daichi Nishikawa, Mamoru Ishida
  • Patent number: 9941384
    Abstract: A semiconductor device includes a first III-V compound layer on a substrate, a second III-V compound layer on the first III-V compound layer, in which a material of the first III-V compound layer is different from that of the second III-V compound layer, a gate metal stack disposed on the second III-V compound layer, a source contact and a drain contact disposed at opposite sides of the gate metal stack, a gate field plate disposed between the gate metal stack and the drain contact, an anti-reflective coating (ARC) layer formed on the source contact and the drain contact, and an etch stop layer formed on the ARC layer.
    Type: Grant
    Filed: August 29, 2015
    Date of Patent: April 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jheng-Sheng You, Hsin-Chih Lin, Kun-Ming Huang, Lieh-Chuan Chen, Po-Tao Chu, Shen-Ping Wang, Chien-Li Kuo
  • Patent number: 9859208
    Abstract: A method for an interconnect structure including: forming a hard mask layer on a semiconductor substrate having a wiring line; patterning the hard mask layer to form a patterned hard mask layer having a hard mask layer opening; depositing a dielectric stack on the patterned hard mask layer and in the hard mask layer opening; patterning the dielectric stack to form a via opening aligned with the hard mask layer opening and to expose the wiring line through the via opening and the hard mask layer opening, a bottom of the via opening defined by the hard mask layer having the hard mask layer opening; and filling the via opening and the hard mask layer opening with a metal to form a via in contact with the wiring line.
    Type: Grant
    Filed: September 18, 2016
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Matthew S. Angyal, Naftali E. Lustig, Rasit O. Topaloglu
  • Patent number: 9659811
    Abstract: A method of forming a semiconductor device includes forming a low-k dielectric layer over a substrate and forming a first dielectric layer on the low-k dielectric layer. A first metal hard mask layer is formed on the first dielectric layer, and a second dielectric layer is formed on the first metal hard mask layer. A second metal hard mask layer is formed on the second dielectric layer, and a first trench opening is formed in the second metal hard mask layer and the second dielectric layer exposing the first metal hard mask layer. A first via opening is formed in the exposed first metal hard mask layer in the first trench opening, and the first trench opening and first via opening are extended into the low-k dielectric layer to form a first trench and a first via.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: May 23, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Yun Peng, Chung-Chi Ko, Shing-Chyang Pan
  • Patent number: 9634191
    Abstract: A wire-bond free semiconductor device with two electrodes both of which are accessible from the bottom side of the device. The device is fabricated with two electrodes that are electrically connected to the oppositely doped epitaxial layers, each of these electrodes having leads with bottom-side access points. This structure allows the device to be biased with an external voltage/current source, obviating the need for wire-bonds or other such connection mechanisms that must be formed at the packaging level. Thus, features that are traditionally added to the device at the packaging level (e.g., phosphor layers or encapsulants) may be included in the wafer level fabrication process. Additionally, the bottom-side electrodes are thick enough to provide primary structural support to the device, eliminating the need to leave the growth substrate as part of the finished device.
    Type: Grant
    Filed: November 14, 2007
    Date of Patent: April 25, 2017
    Assignee: CREE, INC.
    Inventors: Bernd Keller, Ashay Chitnis, Nicholas W. Medendorp, Jr., James Ibbetson, Max Batres
  • Patent number: 9548201
    Abstract: The present disclosure provides forming nanostructures with precision dimension control and minimum lithographic related errors for features with dimension under 14 nanometers and beyond. A self-aligned multiple spacer patterning (SAMSP) process is provided herein and the process utilizes minimum lithographic exposure process, but rather multiple deposition/etching process to incrementally reduce feature sizes formed in the mask along the manufacturing process, until a desired extreme small dimension nanostructures are formed in a mask layer.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: January 17, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Ying Zhang, Uday Mitra, Praburam Gopalraja, Srinivas D. Nemani, Hua Chung
  • Patent number: 9543606
    Abstract: The present invention pertains to a fuel cell with a storage unit (4) for storing hydrogen (Hx), with a proton conductive layer, which covers a surface of the storage unit (4), and with a cathode (7) on a side of the proton conductive layer, which side is located opposite, wherein the storage unit (4) is directly coupled with an anode and/or the storage unit (4) is incorporated in a substrate (1) of a semiconductor. The storage unit (4) is preferably connected to the substrate (1) at least via a stress compensation layer (3).
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: January 10, 2017
    Assignee: Micronas GmbH
    Inventors: Mirko Lehmann, Claas Mueller, Holger Reinecke, Mirko Frank, Gilbert Erdler
  • Patent number: 9536966
    Abstract: A semiconductor device includes a III-N layer, a plurality of parallel conductive fingers on the III-N layer, an insulator layer over the III-N layer, and a gate. The plurality of parallel conductive fingers includes a source and drain bus, a plurality of source fingers coupled to the source bus and extending from the source bus towards the drain bus to respective source finger ends, and a plurality of drain fingers coupled to the drain bus and extending from the drain bus towards the source bus to respective drain finger ends, the drain fingers being interdigitated between the source fingers. The gate comprises a plurality of straight and a plurality of connecting sections, each straight section between a source finger and adjacent drain finger, and the connecting sections each joining two adjacent straight sections and curving around a respective source or drain finger end.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: January 3, 2017
    Assignee: Transphorm Inc.
    Inventor: Tsutomu Ogino
  • Patent number: 9530689
    Abstract: Methods for fabricating integrated circuits are provided. One method includes decomposing a master pattern layout for a semiconductor device layer that includes a target metal line with a target interconnecting via/contact into a first sub-pattern and a second sub-pattern. The target metal line is decomposed into a first line feature pattern that is part of the first sub-pattern and a second line feature pattern that is part of the second sub-pattern such that the first and second line feature patterns have overlapping portions defining a stitch that corresponds to the target interconnecting via/contact. A first photomask is generated that corresponds to the first sub-pattern. A second photomask is generated that corresponds to the second sub-pattern.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: December 27, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Deniz Elizabeth Civay, Jason Eugene Stephens, Jiong Li, Guillaume Bouche, Richard A. Farrell
  • Patent number: 9502447
    Abstract: An array substrate comprises a base substrate, a gate line, a data line and a thin film transistor arranged in an array on the base substrate, a pixel electrode and a passivation layer, the thin film transistor include a gate electrode, an active layer, a source electrode and a drain electrode, and the pixel electrode and the active layer, the drain are disposed in a same layer and formed integrally. A display device comprising the array substrate and a manufacturing method of the array substrate are further disclosed.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: November 22, 2016
    Assignee: BOE Technology Co., Ltd.
    Inventor: Hongfei Cheng
  • Patent number: 9466486
    Abstract: A method of forming a target pattern includes forming a first trench in a substrate with a cut mask; forming a first plurality of lines over the substrate with a first main mask, wherein the first main mask includes at least one line that overlaps the first trench and is thereby cut into at least two lines by the first trench; forming a spacer layer over the substrate and the first plurality of lines and over sidewalls of the first plurality of lines; forming a patterned material layer over the spacer layer with a second main mask thereby the patterned material layer and the spacer layer collectively define a second plurality of trenches; removing at least a portion of the spacer layer to expose the first plurality of lines; and removing the first plurality of lines thereby resulting a patterned spacer layer over the substrate.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: October 11, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Feng Shieh, Ru-Gun Liu, Hung-Chang Hsieh, Tien-I Bao, Chung-Ju Lee, Shau-Lin Shue
  • Patent number: 9454081
    Abstract: Disclosed is a method and apparatus for mitigation of photoresist line pattern collapse in a photolithography process by applying a gap-fill material treatment after the post-development line pattern rinse step. The gap-fill material dries into a solid layer filling the inter-line spaces of the line pattern, thereby preventing line pattern collapse due to capillary forces during the post-rinse line pattern drying step. Once dried, the gap-fill material is depolymerized, volatilized, and removed from the line pattern by heating, illumination with ultraviolet light, by application of a catalyst chemistry, or by plasma etching.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: September 27, 2016
    Assignee: Tokyo Electron Limited
    Inventors: Mark H Somervell, Benjamen M Rathsack, Ian J Brown, Steven Scheer, Joshua S Hooge
  • Patent number: 9433115
    Abstract: A photostructurable ceramic is processed using photostructuring process steps for embedding devices within a photostructurable ceramic volume, the devices may include one or more of chemical, mechanical, electronic, electromagnetic, optical, and acoustic devices, all made in part by creating device material within the ceramic or by disposing a device material through surface ports of the ceramic volume, with the devices being interconnected using internal connections and surface interfaces.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: August 30, 2016
    Assignee: The Aerospace Corporation
    Inventor: Henry Helvajian
  • Patent number: 9425133
    Abstract: An integrated circuit includes circuitry, a first conductor coupled to the circuitry, a conductive pad coupled to the first conductor, and a second conductor coupled to the conductive pad. The second conductor would be floating but for its coupling to the conductive pad. The second conductor may be spaced apart from the first conductor by a distance that is substantially equal to a width of a merged spacer that was formed from a merging of single sidewall spacers over a conductive material from which the first and second conductors were formed.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: August 23, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Roger W Lindsay
  • Patent number: 9418862
    Abstract: A method includes forming a resist over a substrate, resulting in a layer of resist scum between the resist and the substrate. The method further includes forming trenches in the resist, wherein at least a portion of the layer of resist scum remains between the trenches and the substrate. The method further includes forming a first material layer in the trenches, wherein the first material layer has a higher etch resistance than the resist in an etching process. The method further includes performing the etching process to the first material layer, the resist, and the layer of resist scum, thereby forming a patterned first material layer over a patterned layer of resist scum over the substrate.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: August 16, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Min Huang, Chieh-Han Wu, Chung-Ju Lee, Chih-Tsung Shih, Jeng-Horng Chen, Shinn-Sheng Yu
  • Patent number: 9397266
    Abstract: Light emitting diodes include a diode region having first and second opposing faces that include therein an n-type layer and a p-type layer, an anode contact that ohmically contacts the p-type layer and extends on the first face, and a cathode contact that ohmically contacts the n-type layer and also extends on the first face. The anode and cathode contacts extend on the first face to collectively cover substantially all of the first face. A small gap may be provided between the contacts.
    Type: Grant
    Filed: January 20, 2014
    Date of Patent: July 19, 2016
    Assignee: CREE, INC.
    Inventors: Matthew Donofrio, James Ibbetson, Zhimin James Yao
  • Patent number: 9338898
    Abstract: A method-of producing a printed wiring board comprises: forming a via-hole for interlayer connection in a laminate in which a copper foil for laser processing comprises a copper foil and an easily soluble laser absorption layer provided on a surface of the copper foil which has a higher etching rate to a copper etchant than the copper foil and absorbs an infrared laser beam and another conductor layer is laminated through an insulating layer, directly irradiating the infrared laser beam on the easily soluble laser absorption layer; and removing the easily soluble laser absorption layer from the surface of the copper foil in a desmear step of removing a smear in a via-hole and/or a microetching step as a pretreatment of an electroless plating step is adopted.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: May 10, 2016
    Assignee: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Joji Fujii, Hiroaki Tsuyoshi, Hiroto Iida, Kazuhiro Yoshikawa, Mitsuyoshi Matsuda
  • Patent number: 9287161
    Abstract: A method of manufacturing a wiring includes sequentially forming a first insulation layer, a first layer, and a second layer on a substrate, etching an upper portion of the second layer a plurality of times to form a second layer pattern including a first recess having a shape of a staircase, etching a portion of the second layer pattern and a portion of the first layer under the first recess to form a first layer pattern including a second recess having a shape of a staircase similar to the first recess, etching a portion of the first layer pattern under the second recess to form a first opening exposing a portion of a top surface of the first insulation layer, etching the exposed portion of the first insulation layer to form a second opening through the first insulation layer, and forming a wiring filling the second opening.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: March 15, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Hyun Lee, Myeong-Cheol Kim, Yoo-Jung Lee, Il-Sup Kim, Seung-Ju Park
  • Patent number: 9279925
    Abstract: An interference filter includes a first substrate, a second substrate opposed to the first substrate, a first optical film provided to the first substrate, and a second optical film provided to the second substrate and opposed to the first optical film, at least one of the first and second optical films has a metal film having a reflecting property and a transmitting property with respect to light in a desired wavelength band, a surface and an edge portion of the metal film are covered by a barrier film, and the barrier film is formed of a material having conductivity.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: March 8, 2016
    Assignee: Seiko Epson Corporation
    Inventor: Susumu Shinto
  • Patent number: 9269659
    Abstract: An interposer for a packaged semiconductor device is formed by applying an encapsulant to (e.g., by overmolding or applying lamination of tapes to) a perforated metal foil having vertical metal tabs that form the vertical metal vias in the interposer. A solid metal foil can be stamped using a micro-stamping tool to form the perforated foil and vertical tabs. Bump pads and/or re-distribution layer (RDL) traces are formed (e.g., using wafer fabrication processes or by applying flexible tape RDL layers) on the top and back sides of the foil to complete the manufacturing process. Such interposers can be cheaper to manufacture than conventional interposers having silicon or glass substrates with through-silicon vias (TSVs) formed using wafer fabrication processes.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: February 23, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Chee Seng Foong, Lan Chu Tan
  • Patent number: 9229318
    Abstract: In various embodiments of the present invention a circuit apparatus having a rounded trace, a method to manufacture the circuit apparatus, and a design structure used in the design, testing, or manufacturing of the circuit apparatus are described. An artwork layer having an adaptable-mask section allows a graded amount of light to pass into an underlying photoresist layer. Subsequent to developing the photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least a portion of a rounded trace. The photoresist layer is removed resulting in a circuit apparatus having a rounded trace.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: January 5, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Matthew S. Doyle, Joseph Kuczynski, Kevin A. Splittstoesser, Timothy J. Tofil
  • Patent number: 9224773
    Abstract: A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed at a surface of the semiconductor substrate, wherein the photo-sensitive device is configured to receive a light signal from the backside of the semiconductor substrate, and convert the light signal to an electrical signal. An amorphous-like adhesion layer is disposed on the backside of the semiconductor substrate. The amorphous-like adhesion layer includes a compound of nitrogen and a metal. A metal shielding layer is disposed on the backside of the semiconductor substrate and contacting the amorphous-like adhesion layer.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: December 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chieh Chang, Jian-Shin Tsai, Chih-Chang Huang, Ing-Ju Lee, Ching-Yao Sun, Jyun-Ru Wu, Ching-Che Huang, Szu-An Wu, Ying-Lang Wang
  • Patent number: 9219253
    Abstract: A method for manufacturing an organic EL display device is provided in which an organic compound layer is formed by vapor deposition after a layer used for patterning the organic compound layer has been formed, so that the organic compound layer is formed without being affected by the surface tension of the sides of the layer for the patterning.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: December 22, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Nozomu Izumi, Kenji Ookubo, Tomoyuki Hiroki, Nobuhiko Sato
  • Patent number: 9171703
    Abstract: Provided herein is an apparatus, including a patterned resist overlying a substrate; a number of features of the patterned resist, wherein the number of features respectively includes a number of sidewalls; and a sidewall-protecting material disposed about the number of sidewalls, wherein the sidewall-protecting material is characteristic of a conformal, thin-film deposition, and wherein the sidewall-protecting material facilitates a high-fidelity pattern transfer of the patterned resist to the substrate during etching.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: October 27, 2015
    Assignee: Seagate Technology LLC
    Inventors: Shuaigang Xiao, David Kuo, Kim Y. Lee, XiaoMin Yang, Justin Hwu
  • Patent number: 9142558
    Abstract: A semiconductor device includes a plurality of lower electrodes having a vertical length greater than a horizontal width on a substrate, a supporter disposed between the lower electrodes, an upper electrode disposed on the lower electrodes, and a capacitor dielectric layer disposed between the lower electrodes and the upper electrode. The supporter includes a first element, a second element, and oxygen, an oxide of the second element has a higher band gap energy than an oxide of the first element, and the content of the second element in the supporter is from about 10 at % to 90 at %.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: September 22, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Jeong Yang, Soon-Wook Jung, Bong-Jin Kuh, Wan-Don Kim, Byung-Hong Chung, Yong-Suk Tak
  • Patent number: 9111880
    Abstract: A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: August 18, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Choong-Ryul Ryou, Hee-Sung Kang
  • Patent number: 9081285
    Abstract: A method for fabricating a circuit, by defining a first set of resist features on a substrate and corresponding to a first mask layout, followed by defining a second set of resist features on the substrate corresponding to a second mask layout, wherein the second set adds to the first set for rectifying an error in either mask layout. In another aspect, the method is by defining a first set of resist features on a substrate and corresponding to a first mask layout that has an error, etching the substrate while the first set protects selected regions, defining a second set of resist features on the substrate and corresponding to a second mask layout, followed by etching the substrate to selectively remove portions of the selected regions for rectifying the error.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: July 14, 2015
    Assignee: III Holdings 1, LLC
    Inventor: Krishnakumar Mani
  • Patent number: 9076715
    Abstract: A structure includes a first chip having a first substrate, and first dielectric layers underlying the first substrate, with a first metal pad in the first dielectric layers. A second chip includes a second substrate, second dielectric layers over the second substrate and bonded to the first dielectric layers, and a second metal pad in the second dielectric layers. A conductive plug includes a first portion extending from a top surface of the first substrate to a top surface of the first metal pad, and a second portion extending from the top surface of the first metal pad to a top surface of the second metal pad. An edge of the second portion is in physical contact with a sidewall of the first metal pad. A dielectric layer spaces the first portion of the conductive plug from the first plurality of dielectric layers.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: July 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Shih Pei Chou, U-Ting Chen, Chia-Chieh Lin
  • Patent number: 9070557
    Abstract: A semiconductor structure including a double patterned structure and a method for forming the semiconductor structure are provided. A negative photoresist layer is formed on a positive photoresist layer, which is formed over a substrate. An exposure process is performed to form a first exposure region in the positive photoresist layer and to form a second exposure region in the negative photoresist layer in response to a first and a second intensity thresholds of the exposure energy. A negative-tone development process is performed to remove portions of the negative photoresist layer to form first opening(s). The positive photoresist layer is then etched along the first opening(s) to form second opening(s) therein. A positive-tone development process is performed to remove the first exposure region therefrom to form a double patterned positive photoresist layer.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: June 30, 2015
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP.
    Inventors: Daniel Hu, Ken Wu, Yiming Gu
  • Patent number: 9070559
    Abstract: According to one embodiment, first, a core pattern is formed above a hard mask layer that is formed above a process object. Then, a spacer film is formed above the hard mask layer. Next, the spacer film is etch-backed. Subsequently, an embedded layer is embedded between the core patterns whose peripheral areas are surrounded by the spacer film. Then, the core pattern and the embedded layer are removed simultaneously. Subsequently, using the spacer pattern as a mask, the hard mask layer and the process object are processed.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: June 30, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiro Miyoshi, Maki Miyazaki, Kentaro Matsunaga
  • Patent number: 9069249
    Abstract: A method for using self aligned multiple patterning with multiple resist layers includes forming a first patterned resist layer onto a substrate, forming a spacer layer on top of the first patterned resist layer such that spacer forms on side walls of features of the first resist layer, and forming a second patterned resist layer over the spacer layer and depositing a masking layer. The method further includes performing a planarizing process to expose the first patterned resist layer, removing the first resist layer, removing the second resist layer, and exposing the substrate.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: June 30, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Feng Shieh, Ken-Hsien Hsieh, Shih-Ming Chang, Chih-Ming Lai, Ru-Gun Liu
  • Patent number: 9063430
    Abstract: A coating agent for forming a fine pattern and a method for forming a fine pattern using the coating agent, in which the coating agent allows a resist pattern to be favorably fined, and can form a fined pattern having a suppressed deviation of CD. A coating agent for forming a fine pattern including (A) a water-soluble polymer is combined with a compound in which the compound has an alkyl group having 8 or more carbon atoms bound to a nitrogen atom, and is combined with 4 moles or more of ethylene oxide and/or propylene oxide with respect to 1 mole of a nitrogen atom bound with the alkyl group as (B) a nitrogen-containing compound.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: June 23, 2015
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Tomoya Kumagai, Takumi Namiki
  • Patent number: 9058997
    Abstract: Methods of multiple exposure in the fields of deep ultraviolet photolithography, next generation lithography, and semiconductor fabrication comprise a spin-castable methodology for enabling multiple patterning by completing a standard lithography process for the first exposure, followed by spin casting an etch selective overcoat layer, applying a second photoresist, and subsequent lithography. Utilizing the etch selectivity of each layer, provides a cost-effective, high resolution patterning technique. The invention comprises a number of double or multiple patterning techniques, some aimed at achieving resolution benefits, as well as others that achieve cost savings, or both resolution and cost savings. These techniques include, but are not limited to, pitch splitting techniques, pattern decomposition techniques, and dual damascene structures.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Martin Burkhardt, Sean D. Burns, Matthew E. Colburn
  • Patent number: 9054045
    Abstract: According to one embodiment, the invention relates to a method for the anisotropic etching of patterns in at least one layer to be etched through a hard mask comprising carbon in an inductive-coupling plasma etching reactor (ICP), the method being characterized in that the hard mask is made from boron doped with carbon (B:C), and in that, prior to the anisotropic etching of the patterns in said layer to be etched through the hard mask of carbon-doped boron (B:C), the following steps are performed: realization of an intermediate hard mask situated on a layer of carbon-doped boron intended to form the hard mask made from carbon-doped boron (B:C), etching of the layer of carbon-doped boron (B:C) through the intermediate hard mask in order to form the hard mask made from carbon-doped boron (B:C), the realization of the intermediate hard mask and the etching of the hard mask made from carbon-doped boron (B:C) being done in said inductive coupling plasma etching reactor (ICP).
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: June 9, 2015
    Assignees: Commissariat a l'energie atomique et aux energies alternatives, Applied Materials, Inc.
    Inventors: Nicolas Posseme, Gene Lee
  • Patent number: 9034570
    Abstract: Some embodiments include methods of forming patterns of openings. The methods may include forming spaced features over a substrate. The features may have tops and may have sidewalls extending downwardly from the tops. A first material may be formed along the tops and sidewalls of the features. The first material may be formed by spin-casting a conformal layer of the first material across the features, or by selective deposition along the features relative to the substrate. After the first material is formed, fill material may be provided between the features while leaving regions of the first material exposed. The exposed regions of the first material may then be selectively removed relative to both the fill material and the features to create the pattern of openings.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: May 19, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Gurtej S. Sandhu, John Smythe, Ming Zhang
  • Patent number: 9029071
    Abstract: The present invention provides a silicon oxynitride film formation method capable of reducing energy cost, and also provides a substrate equipped with a silicon oxynitride film formed thereby. This method comprises the steps of: casting a film-formable coating composition containing a polysilazane compound on a substrate surface to form a coat; drying the coat to remove excess of the solvent therein; and then irradiating the dried coat with UV light at a temperature lower than 150° C.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: May 12, 2015
    Assignee: Merck Patent GmbH
    Inventors: Ninad Shinde, Tatsuro Nagahara, Yusuke Takano
  • Publication number: 20150125674
    Abstract: A conductive pattern is prepared in a polymeric layer that has (a) a reactive polymer comprising pendant tertiary alkyl ester groups, (b) a compound that provides an acid upon exposure to radiation having a ?max of at least 150 nm and up to and including 450 nm, and (c) a crosslinking agent. The polymeric layer is patternwise exposed to provide a polymeric layer comprising non-exposed regions and exposed regions comprising a polymer comprising carboxylic acid groups. The exposed regions are contacted with electroless seed metal ions to form a pattern of electroless seed metal ions. The pattern of electroless seed metal ions is then reduced to provide a pattern of corresponding electroless seed metal nuclei. The corresponding electroless seed metal nuclei are then electrolessly plated with a conductive metal.
    Type: Application
    Filed: November 5, 2013
    Publication date: May 7, 2015
    Inventors: Thomas B. Brust, Mark Edward Irving, Catherine A. Falkner, Anne Troxell Wyand
  • Publication number: 20150119673
    Abstract: A neural probe comprising an array of stimulation and/or recording electrodes supported on a tape spring-type carrier is described. The neural probe comprising the tape spring-type carrier is used to insert flexible electrode arrays straight into tissue, or to insert them off-axis from the initial penetration of a guide tube. Importantly, the neural probe is not rigid, but has a degree of stiffness provided by the tape spring-type carrier that maintains a desired trajectory into body tissue, but will subsequently allow the probe to flex and move in unison with movement of the body tissue.
    Type: Application
    Filed: October 21, 2014
    Publication date: April 30, 2015
    Inventors: David S. Pellinen, Bencharong Suwarato, Rio J. Vetter, Jamille Farraye Hetke, Daryl R. Kipke
  • Patent number: 9005877
    Abstract: A method for patterning a layered structure is provided that includes performing photolithography to provide a developed prepattern layer on a horizontal surface of an underlying substrate, modifying the prepattern layer to form spaced apart inorganic material guides, casting and annealing a layer of a self-assembling block copolymer to form laterally-spaced cylindrical features, forming a pattern by selectively removing at least a portion of one block of the self-assembling block copolymer, and transferring the pattern to the underlying substrate. The method is suitable for making sub-50 nm patterned layered structures.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: April 14, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Benjamen M. Rathsack, Mark H. Somervell, Meenakshisundaram Gandhi
  • Patent number: 9005883
    Abstract: The invention provides a patterning process comprises the steps of: (1) forming a positive chemically amplifying type photoresist film on a substrate to be processed followed by photo-exposure and development thereof by using an organic solvent to obtain a negatively developed pattern, (2) forming a silicon-containing film by applying a silicon-containing film composition comprising a solvent and a silicon-containing compound capable of becoming insoluble in a solvent by a heat, an acid, or both, (3) insolubilizing in a solvent the silicon-containing film in the vicinity of surface of the negatively developed pattern, (4) removing the non-insolubilized part of the silicon-containing film to obtain an insolubilized part as a silicon-containing film pattern, (5) etching the upper part of the silicon-containing film pattern thereby exposing the negatively developed pattern, (6) removing the negatively developed pattern, and (7) transferring the silicon-containing film pattern to the substrate to be processed.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: April 14, 2015
    Assignee: Shin-Estu Chemical Co., Ltd.
    Inventors: Tsutomu Ogihara, Takafumi Ueda
  • Patent number: 9005875
    Abstract: A method of fabricating a substrate including coating a first resist onto a hardmask, exposing regions of the first resist to electromagnetic radiation at a dose of 10.0 mJ/cm2 or greater and removing a portion of said the and forming guiding features. The method also includes etching the hardmask to form isolating features in the hardmask, applying a second resist within the isolating features forming regions of the second resist in the hardmask, and exposing regions of the second resist to electromagnetic radiation having a dose of less than 10.0 mJ/cm2 and forming elements.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 14, 2015
    Assignee: Intel Corporation
    Inventors: Robert L. Bristol, Paul A. Nyhus, Charles H. Wallace
  • Patent number: 8999627
    Abstract: The present application discloses methods, systems and devices for using charged particle beam tools to pattern and inspect a substrate. The inventors have discovered that it is highly advantageous to use write and inspection tools that share the same or substantially the same stage and the same or substantially the same designs for respective arrays of multiple charged particle beam columns, and that access the same design layout database to target and pattern or inspect features. By using design-matched charged particle beam tools, correlation of defectivity is preserved between inspection imaging and the design layout database. As a result, image-based defect identification and maskless design correction, of random and systematic errors, can be performed directly in the design layout database, enabling a fast yield ramp.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: April 7, 2015
    Assignee: Multibeam Corporation
    Inventors: David K. Lam, Kevin M. Monahan, Theodore A. Prescop, Cong Tran
  • Patent number: 8999628
    Abstract: The present application discloses methods, systems and devices for using charged particle beam tools to pattern and inspect a substrate. The inventors have discovered that it is highly advantageous to use write and inspection tools that share the same or substantially the same stage and the same or substantially the same designs for respective arrays of multiple charged particle beam columns, and that access the same design layout database to target and pattern or inspect features. By using design-matched charged particle beam tools, correlation of defectivity is preserved between inspection imaging and the design layout database. As a result, image-based defect identification and maskless design correction, of random and systematic errors, can be performed directly in the design layout database, enabling a fast yield ramp.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: April 7, 2015
    Assignee: Multibeam Corporation
    Inventors: David K. Lam, Kevin M. Monahan, Theodore A. Prescop, Cong Tran
  • Patent number: 8993218
    Abstract: One or more techniques or systems for controlling a profile for photo resist (PR) are provided herein. In some embodiments, a first shield layer is formed on a first PR layer and a second PR layer is formed on the first shield layer. A first window is formed within the second PR layer during a first exposure with a mask. A second window is formed within the first shield layer based on the first window. A third window is formed within the first PR layer during a second exposure without a mask. Because, the third window is formed while the first shield layer and the second PR layer are on the first PR layer, a profile associated with the first PR layer is controlled. Contamination during ion bombardment is mitigated due to the controlled profile.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Li Huai Yang, Chien-Mao Chen