Abstract: The present invention includes a method of creating high Q empty substrate integrated waveguide devices and/or system with low loss, mechanically and thermally stabilized in photodefinable glass ceramic substrate. The photodefinable glass ceramic process enables high performance, high quality, and/or low-cost structures. Compact low loss RF empty substrate integrated waveguide devices are a cornerstone technological requirement for RF systems, in particular, for portable systems.

Abstract: Apparatus for and method of removing a contaminant from a working surface of a lithography support such as a reticle or wafer stage in an EUV or a DUV photolithography system in which a cleaning substrate provided with a coating made a selected material and configuration is pressed against the working surface so that the contaminant is transferred from the working surface to the coating.

Abstract: A method of cleaning a semiconductor wafer includes: loading a semiconductor wafer into a cell having an annular trough; moving a plurality of nozzles into operational orientations for spraying a cleaning solution onto a top surface of the loaded semiconductor wafer; spraying the cleaning solution from each nozzle onto the top surface of the loaded semiconductor wafer in a direction defined by each nozzle's operational orientation such that a patterned flow of cleaning solution is formed on the top surface of the loaded semiconductor wafer; and collecting the cleaning solution in the annular trough of the cell as it flows off the top surface of the loaded semiconductor wafer.

Abstract: A circuit board with anti-corrosion properties, a method for manufacturing the circuit board, and an electronic device are provided. The circuit board includes a circuit substrate, a first protective layer, and a second protective layer. The circuit substrate includes a base layer and an outer wiring layer formed on the base layer. The circuit substrate further defines a via hole connected to the outer wiring layer. The first protective layer is formed on the outer wiring layer and an inner sidewall of the via hole, and is made of a white oil. The second protective layer is formed on the first protective layer.

Abstract: Embodiments of systems and methods for dicing a bonded structure are provided. A method for dicing a bonded structure includes thinning a top surface and a bottom surface of a bonded structure. The bonded structure may have a first wafer and a second wafer bonded with a bonding interface. The method may also include forming a series of ablation structures in the first wafer and the second wafer. The series of ablation structures may be between a first part and a second part of the bonded structure. The method may also include separating the first part and the second part of the bonded structure along the series of ablation structures.

Abstract: Spatial light modulators (SLMs) and systems using same are described. Generally, the system includes a laser, a fixture holding a workpiece to be processed using the laser, illumination optics to illuminate the SLM with laser light, imaging optics to focus modulated light from the SLM onto the workpiece, and a controller to control the laser, the SLM, imaging optics and the fixture to scan the modulated light across a workpiece surface. The SLM includes an array of microelectromechanical system based diffractors, each including an electrostatically deflectable member coupled to a first light reflective surface and to bring light reflected from the first light reflective surface into interference with light reflected from a second light reflective surface in the SLM. The controller is operable to provide analog gray-scale control of an intensity of modulated light reflected from each diffractor by controlling an electrostatic force generated by a driver coupled thereto.

Abstract: A method of manufacturing a printed circuit board a includes preparing an insulating substrate on which a first metal layer is formed, stacking a resist laminate having a plurality of layers on the first metal layer, forming an opening exposing a portion of the first metal layer by patterning the stacked resist laminate having the plurality of layers, forming a second metal layer on the exposed portion of the first metal layer, removing the patterned resist laminate having the plurality of layers, and etching at least another portion of the first metal layer.

Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.

Abstract: A substrate processing apparatus includes a photoresist coater applying a photoresist film on a substrate, a humidifier increasing an amount of moisture in an ambient to which the photoresist film on the substrate is exposed, and an exposer irradiating the photoresist film exposed to the ambient having the increased amount of moisture with light. The humidifier is disposed between the photoresist coater and the exposer.

Abstract: A method includes forming a semiconductor fin on a substrate; forming a dielectric layer over the semiconductor fin; forming a metal gate electrode in the dielectric layer and extending across the semiconductor fin; forming a source/drain regions on the semiconductor fin and on opposite sides of the metal gate electrode; performing a first non-zero bias plasma etching process to the metal gate electrode; after performing the first non-zero bias plasma etching process, performing a first zero bias plasma etching process to the metal gate electrode.

Abstract: Methods incorporate variable side wall angle (VSA) into calculated patterns, using a mask 3D (M3D) effect. Embodiments include inputting a mask exposure information, calculating a mask 2D (M2D) effect from the mask exposure information, and determining the M3D effect from the M2D effect. Determining the M3D effect may include determining the VSA, such as by using a neural network. Embodiments may include determining a dose margin from mask exposure information; calculating a VSA using the dose margin; and calculating a pattern on a substrate using the calculated VSA, wherein calculating the pattern on the substrate includes a mask 3D effect.

Abstract: A method for fabricating a semiconductor device is described that includes forming a base layer over a top layer of a substrate, the base layer includes a silicon based dielectric having a thickness less than or equal to 5 nm and greater than or equal to 0.5 nm; forming a photoresist layer over the base layer, the photoresist including a first side and an opposite second side; exposing a first portion of the photoresist layer to a pattern of extreme ultraviolet (EUV) radiation from the first side; exposing a second portion of the photoresist layer with a pattern of electron flux from the second side, the electron flux being directed into the photoresist layer from the base layer in response to the EUV radiation; developing the exposed photoresist layer to form a patterned photoresist layer; and transferring the pattern of the patterned photoresist layer to the base layer and the top layer.

Abstract: A system of measuring an image of a pattern in a scanning type EUV mask may include a high-power laser output unit including a flat mirror and a spherical mirror, which are used to focus a high-power femto-second laser on a gas cell; a coherent EUV light generating portion generating a coherent EUV light; a pin-hole, a graphene filter, and a zirconium (Zr) filter; a stage; an x-ray spherical mirror configured to focus a coherent EUV light; a zone-plate lens placed between the stage and the x-ray spherical mirror; an x-ray flat mirror placed between the zone-plate lens and the x-ray spherical mirror; an order sorting aperture (OSA) placed on the stage and configured to transmit only a first-order diffraction light of the focused coherent EUV light; and a detector portion placed on the stage.

Abstract: A display device includes a rollable display panel and a discharger. The rollable display panel with a first portion and a second portion includes a displaying side and a non-displaying side opposite to the displaying side. The discharger is disposed on one of the displaying side and the non-displaying side, wherein the discharger is positioned between the first portion and the second portion when the rollable display panel is rolled and the first portion and the second portion move close to each other.

Abstract: A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a plurality of first mask patterns over the target layer. The method also includes forming a lining layer conformally covering the first mask patterns and the target layer. A first opening is formed over the lining layer and between the first mask patterns. The method further includes filling the first opening with a second mask pattern, and performing an etching process on the lining layer and the target layer using the first mask patterns and the second mask pattern as a mask such that a plurality of second openings are formed in the target layer.

Abstract: The coumarin compounds are antibacterial agents. The emergence of drug-resistant bacteria calls for constant development of new antibacterial agents with the aim of generating medicaments that are potent against drug sensitive and resistant bacteria and are well tolerated. The present compounds are not only new, but have very valuable antimicrobial properties. These compounds showed a broad spectrum of activity against gram-positive and gram-negative bacteria, as well tuberculosis mycobacteria. They also showed potent activity against drug-resistant bacteria, such as MRSA and VRSA. The molecular target of these compounds was identified as DNA Gyrase B. Based on their pharmacological profiles, the present compounds may find important clinical applications for severe infectious diseases and tuberculosis.

Abstract: An etching method for forming a vertical structure is provided. The etching method may include: positioning a mask on a substrate, wherein the mask includes an opening pattern and a compensation pattern, and the compensation pattern is disposed at a corner of two adjacent sides of the opening pattern and includes a concave compensation pattern that is indented from one of the two adjacent sides; and forming the vertical structure on the substrate through the opening pattern of the mask by a dry etching process.

Abstract: A method includes forming a polymer layer on a patterned photo resist. The polymer layer extends into an opening in the patterned photo resist. The polymer layer is etched to expose the patterned photo resist. The polymer layer and a top Bottom Anti-Reflective Coating (BARC) are etched to pattern the top BARC, in which the patterned photo resist is used as an etching mask. The top BARC is used as an etching mask to etching an underlying layer.

Abstract: A method includes the following steps. A photoresist is exposed to a first light-exposure through a first mask, wherein the first mask includes a first stitching region, and a portion of the photoresist corresponding to a portion of the first stitching region is unexposed during the first light-exposure. The photoresist is exposed to a second light-exposure through a second mask, wherein the second mask includes a second stitching region and a functional feature in the second stitching region, and the portion of the photoresist is exposed by the functional feature during the second light-exposure.

Abstract: Disclosed here is a method for making a three-dimensional micro-architected aerogel, comprising: (a) curing a reaction mixture comprising a co-sol-gel material (e.g., graphene oxide (GO)) and at least one catalyst to obtain a crosslinked co-sol-gel (e.g., GO hydrogel); (b) providing a photoresin comprising a solvent, a photoinitiator, a crosslinkable polymer precursor, and a dispersion of the crosslinked co-sol-gel (e.g., GO hydrogel); (c) curing the photoresin using projection microstereolithography layer-by-layer to produce a wet gel having a pre-designed three-dimensional structure; (d) drying the wet gel to produce a dry gel; and (e) pyrolyzing the dry gel to produce a three-dimensional micro-architected aerogel (e.g., graphene aerogel). Also disclosed is a photoresin for projection microstereolithography, comprising a solvent, a photoinitiator, a crosslinkable polymer precursor, and a dispersion of a crosslinked co-sol-gel.

Abstract: A method of forming a patterned photoresist layer includes the following operations: (i) forming a patterned photoresist on a substrate; (ii) forming a molding layer covering the patterned photoresist; (iii) reflowing the patterned photoresist in the molding layer; and (iv) removing the molding layer from the reflowed patterned photoresist. In some embodiments, the molding layer has a glass transition temperature that is greater than or equal to the glass transition temperature of the patterned photoresist. In yet some embodiments, the molding layer has a glass transition temperature that is 3° C.-30° C. less than the glass transition temperature of the patterned photoresist.

Abstract: Some embodiments include a reticle which includes first pattern features and second pattern features. A first optimal dose of actinic radiation is associated with the first pattern features and a second optimal dose of the actinic radiation is associated with the second pattern features. The second pattern features are larger than the first pattern features. Each of the second pattern features has a configuration which includes a central region laterally surrounded by an outer region, with the central region being of different opacity than the outer region. The configurations of the second pattern features balance the second optimal dose of the actinic radiation to be within about 5% of the first optimal dose of the actinic radiation. Some embodiments include photo-processing methods.

Abstract: A substrate cleaning method includes: arranging a substrate within a processing container; spraying gas from a spray port of a gas nozzle arranged within the processing container; causing vertical shock waves, generated by spraying the gas from the gas nozzle, to collide with a main surface of the substrate; and removing particles adhering to the main surface of the substrate, by causing the vertical shock waves to collide with the main surface of the substrate.

Abstract: A method for forming a target substrate is provided. The method includes providing a mask substrate. The method also includes providing a second base with a material layer. The method further includes arranging the mask substrate and the second base correspondingly. In addition, the method includes performing exposure and development processes on the material layer to form the target substrate and removing the mask substrate.

Abstract: Disclosed is a stamp (14) for an imprint lithography process, the stamp comprising an elastomer stamp body including a polysiloxane bulk portion (110) and a patterned surface comprising a feature pattern (16) for imprinting an imprinting composition (12) wherein the elastomer stamp body comprises a basic organic amine in an amount of at least 0.1% by weight based on the total weight of the elastomer stamp body. Also disclosed are methods of manufacturing such a stamp, and a method of forming a patterned layer on a substrate using such a stamp.

Abstract: Methods of processing a feature on a semiconductor workpiece are disclosed. The method is performed after features have been created on the workpiece. An etching species may be directed toward the workpiece at a non-zero tilt angle. In certain embodiments, the tilt angle may be 30° or more. Further, the etching species may also be directed with a non-zero twist angle. In certain embodiments, the etching species may sputter material from the features, while in other embodiments, the etching species may be a chemically reactive species. By adjusting the tilt and twist angles, as well as the flow rate of the etching species and the exposure time, the LER and LWR of a feature may be reduced with minimal impact of the CD of the feature.

Abstract: A diffraction pattern guided source mask optimization (SMO) method that includes determining a source variable region from a diffraction pattern. The source variable region corresponds to one or more areas of a diffraction pattern in a pupil for which one or more pupil variables are to be adjusted. The source variable region in the diffraction pattern includes a plurality of pixels in an image of a selected region of interest in the diffraction pattern. Determining the source variable region can include binarization of the plurality of pixels in the image such that individual pixels are either included in the source variable region or excluded from the source variable region. The method can include adjusting the one or more pupil variables for the one or more areas of the pupil that correspond to the source variable region; and rendering a final pupil based on the adjusted one or more pupil variables.

Abstract: A method of forming a pattern on a substrate is provided. The method includes forming a first layer on an underlying layer of the substrate, where the first layer is patterned to have a first structure. The method also includes depositing a grafting material on side surfaces of the first structure, where the grafting material includes a solubility-shifting material. The method further includes diffusing the solubility-shifting material by a predetermined distance into a neighboring structure that abuts the solubility-shifting material, where the solubility-shifting material changes solubility of the neighboring structure in a developer, and removing soluble portions of the neighboring structure using the developer to form a second structure.

Abstract: A mask blank glass substrate having a maximum value of a circularly averaged power spectral density of 1,000 nm4 or less at a spatial frequency of 0.1 ?m?1 or more and 20 ?m?1 or less, the maximum value being obtained by measuring a surface morphology of a region of 10 ?m×10 ?m with an atomic force microscope.

Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for placing self-aligned top vias at line ends of an interconnect structure. In a non-limiting embodiment of the invention, a line feature is formed in a metallization layer of an interconnect structure. The line feature can include a line hard mask. A trench is formed in the line feature to expose line ends of the line feature. The trench is filled with a host material and a growth inhibitor is formed over a first line end of the line feature. A via mask is formed over a second line end of the line feature. The via mask can be selectively grown on an exposed surface of the host material. Portions of the line feature that are not covered by the via mask are recessed to define a self-aligned top via at the second line end.

Abstract: A wafer edge exposure apparatus includes a wafer carrying module, a reticle, a reticle driving module, an alignment module, an exposure module, and a control module; the wafer carrying module is configured to carry the wafer and drive the wafer to rotate; the wafer includes a valid region and an edge region surrounding the valid region; the reticle driving module is configured to drive the reticle to rotate; the alignment unit is configured to detect the alignment state of the reticle with the wafer; and the control module is configured to control the movement state of the wafer carrying module and the reticle driving module and configured to control the exposure module to perform wafer edge exposure on the wafer.

Abstract: A display substrate is described that comprises: a display area, a retaining wall surrounding the display area, and a thin film encapsulation layer comprising a first inorganic barrier layer, an organic barrier layer, and a second inorganic barrier layer. The display area has a corner portion being a portion of the display area surrounded by the retaining wall. Convex dams are provided at a position on the substrate corresponding to the corner portion. A portion of the first inorganic barrier layer corresponding to the corner portion covers the convex dams, and a portion of the first inorganic barrier layer between the two adjacent convex dams forms a diversion trench. The organic barrier layer comprises cured organic material, and the organic material is provided on the portion of the first inorganic barrier layer at the corner portion under a capillary action of the diversion trench before curing.

Abstract: An embodiment of the disclosure provides a heater package including a substrate, a first barrier layer, at least one heater, and a second barrier layer. The first barrier layer is disposed on a surface of the substrate and has a first treatment layer on a side away from the substrate. The heater is disposed on the substrate and includes a heating layer and at least one electrode. The at least one electrode and the heating layer contact with each other. The second barrier layer covers an upper surface and a sidewall of the heater and has a second treatment layer on an opposite side or the side away from the substrate. A ratio of a thickness of the first treatment layer to a thickness of the first barrier layer and a ratio of a thickness of the second treatment layer to a thickness of the second barrier layer range from 0.03 to 0.2.

Abstract: According to an embodiment, a wafer (W) includes a layer (EL) to be etched, an organic film (OL), an antireflection film (AL), and a mask (MK1), and a method (MT) according to an embodiment includes a step of performing an etching process on the antireflection film (AL) by using the mask (MK1) with plasma generated in a processing container (12), in the processing container (12) of a plasma processing apparatus (10) in which the wafer (W) is accommodated, and the step includes steps ST3a to ST4 of conformally forming a protective film (SX) on the surface of the mask (MK1), and steps ST6a to ST7 of etching the antireflection film (AL) by removing the antireflection film (AL) for each atomic layer by using the mask (MK1) on which the protective film (SX) is formed.

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.

Abstract: A resist composition comprising a base polymer and a quencher in the form of a heterocyclic amine compound having a tertiary ester structure offers a high sensitivity and minimal LWR or improved CDU, independent of whether it is of positive or negative tone.

Abstract: Predictive multi-planar semiconductor manufacturing systems and methods are provided including a processor, an artificial intelligence unit in communication with the processor, and a computer readable memory with processing instructions in communication with the processor. The manufacturing system receives and analyzes semiconductor design and manufacturing process rules and data and dimensions for a user's desired semiconductor. The artificial intelligence unit is configured to run simulations trying multiple three-dimensional, multi-planar shapes and analyzing for highest surface area yield based on the design and manufacturing process rules and data and the dimensions. The artificial intelligence unit is further configured to determine a three-dimensional, multi-planar shape for the desired semiconductor to optimize surface area based on the simulations and to construct the three-dimensional, multi-planar shape that optimizes surface area.

Abstract: A spin dispenser module and methods for using the same is disclosed. The spin dispenser module includes a cup having a basin with sidewalls and an exhaust, a rotatable platform situated inside the cup adapted for holding and rotating a substrate, a liquid dispenser disposed over the rotatable platform for dispensing a liquid coating material on top of the substrate, one or more ejector inlets disposed over the rotatable platform, the one or more ejectors connected to a negative pressure source, and a motor coupled to the rotatable platform to rate the rotatable platform at different rotational speeds. The one or more ejector inlets may be translatable and/or rotatable with optionally adjustable suction pressure. The ejector inlets operate after a liquid coating material is dispensed to avoid deposition of suspended organic compounds after a coating is formed.

Abstract: A method and associated apparatuses for controlling a process of manufacturing semiconductor devices on a substrate. The method includes obtaining process data relating to the process and determining a correction for the process based on the process data and a first control objective associated with the devices on the substrate. A first probability of the first control objective being achievable is determined and the correction adjusted based on the probability and at least a second control objective having a second probability of being achievable compared to the first control objective.

Abstract: A die layout calculation method is provided. The method includes: selecting, based on a distribution array of a plurality of dies in a wafer, one die as a reference die; making first movements of a wafer center to determine a first coverage region for each first movement, and determining a feasible region based on a number of complete dies in each first coverage region; making a plurality of second movements of the wafer center in the feasible region to determine a second coverage region for each second movement, and determining a relative position of the wafer center in the reference die corresponding to a maximum number of complete dies in the second coverage region; and determining a die layout comprising a location of each die in the wafer. This method improves the accuracy and efficiency of determining the maximum number of dies.

Abstract: A single-substrate electroless (EL) plating apparatus including a workpiece chuck that is rotatable about rotation axis and inclinable about an axis of inclination. The chuck inclination may be controlled to a non-zero inclination angle during a dispense of plating solution to improve uniformity in the surface wetting and/or plating solution residence time across the a surface of a workpiece supported by the chuck. The angle of inclination may be only a few degrees off-level with the plating solution dispensed from a nozzle that scans over a high-side of the chuck along a radius of the workpiece while the chuck rotates. The angle of inclination may be actively controlled during dispense of the plating solution. The inclination angle may be larger at commencement of the plating solution dispense than at cessation of the dispense.

Abstract: A method of forming a resist pattern, including forming a resist composition using a resist film; exposing the resist film; and alkali-developing the exposed resist film to form a positive-tone resist pattern, wherein the resist composition includes a first resin component and a second resin component which satisfies a specific relationship DRMIX<DRP1 and DRMIX<DRP2, wherein DRP1 is the dissolution rate of the first resin component (P1) in an alkali developing solution, DRP2 is the dissolution rate of the second resin component (P2) in an alkali developing solution, and DRMIX is the dissolution rate of a mixed resin of the first resin component (P1) and the second resin component (P2).

Abstract: A method for producing a film includes: coating a surface of a substrate with a composition containing a polymer having a structural unit represented by formula (1) and having a number average molecular weight of 13000 or more and a solvent, heating a coating film formed by the coating, and removing, with a rinsing liquid, a part of the coating film after the heating, wherein the rinsing liquid to be used contains a basic compound. In the formula (1), Y1 is a single bond, —CO—NR2—, a divalent aromatic ring group, a divalent group containing —O—, or a divalent group containing —CO—NR2—. A1 is a single bond, —O—, —S—, or —NR3—. R1 is a hydrogen atom, a monovalent hydrocarbon group, a monovalent halogenated hydrocarbon group, or a monovalent group having a heterocyclic structure.

Abstract: Systems and methods for selectively etching features in an electronic substrate via a precision dispense apparatus and precision etchant dispense tool are disclosed. The method includes creating a toolpath instruction for etching at least one feature in the substrate, programming the precision dispense apparatus to execute the created toolpath instruction, and causing the precision dispense tool to deposit etchant material onto the surface of the substrate to etch the substrate surface to produce the at least one feature according to the created toolpath instruction. The capabilities of the systems and methods disclosed herein extend to 3D substrates and post-build processing, among others.

Abstract: An exposure apparatus includes an illumination optical system for illuminating an original including a periodic pattern, a projection optical system for forming an image of the original on a substrate, a controller configured to cause light from the illumination optical system to be obliquely incident on the original such that a light intensity distribution which is line-symmetric with respect to a line, passing through an origin of a pupil region of the projection optical system and orthogonal to a periodic direction of the periodic pattern, is formed in the pupil region by diffracted light beams including diffracted light of not lower than 2nd-order from the periodic pattern, and to control exposure of the substrate such that each point in a shot region of the substrate is exposed in not less than two focus states.

Abstract: According to one embodiment, a proximity effect correcting method includes acquiring drawing information for drawing a pattern on a substrate with irradiation of an electron beam. The method further includes acquiring surface profile information related to a surface profile of the substrate. The method further includes calculating an energy distribution of a backscattered beam to be produced by backscattering of the electron beam in the substrate on a basis of the acquired drawing information and surface profile information. The method further includes calculating a required energy amount of the electron beam on a basis of the calculated energy distribution.

Abstract: A method for manufacturing a dual conductor laminated substrate includes providing a first laminate including a first insulating layer and a first conductive layer; defining a first trace pattern including one or more traces in the first laminate; providing a second laminate including a second insulating layer and a second conductive layer; defining a second trace pattern including one or more traces in the second laminate; defining access holes in the second insulating layer; at least one of depositing and stenciling a conductive material in the access holes of the second insulating layer; and aligning and attaching the first laminate to the second laminate to create a laminated substrate.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes performing an optical proximity correction (OPC) on design patterns of a layout to generate a corrected layout, and forming a photoresist pattern on a substrate using a photomask manufactured based on the corrected layout. The OPC comprises generating develop targets for the design patterns, respectively, choosing first object patterns based on distances between the develop targets, performing a first OPC operation on the design patterns based on a mask rule to generate first correction patterns, choosing second object patterns by considering distances between the first correction patterns and a target error of each of the first correction patterns, and performing a second OPC operation on the first and second object patterns to generate second correction patterns, the performing the second OPC not based on the mask rule.

Abstract: Provided is a resist compound, a method for forming a pattern using the same, and a method for manufacturing a semiconductor device. According to the present disclosure, the compound may be represented by Formula 1.

Abstract: This disclosure describes a process of generating a planarizing polyimide based dielectric film on a substrate with conducting metal pattern, wherein the process comprised steps of: (a) providing a dielectric film forming composition comprising at least one fully imidized polyimide polymer and at least one solvent; and (b) depositing the dielectric film forming composition onto a substrate with conducting metal pattern to form a dielectric film, wherein the difference in the highest and lowest points on a top surface of the dielectric film is less than about 2 microns.