Making Electrical Device Patents (Class 430/311)
  • Patent number: 9767244
    Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: September 19, 2017
    Assignee: Infineon Technologies AG
    Inventors: Henning Haffner, Manfred Eller, Richard Lindsay
  • Patent number: 9733574
    Abstract: Manufacturing of semiconductor devices often involves performed photolithography to pattern and etch the various features of those devices. Such photolithography involves masking and focusing light onto a surface of the semiconductor device for exposing and etching the features of the semiconductor devices. However, due to design specifications and other causes, the semiconductor devices may not have a perfectly flat light-incident surface. Rather, some areas of the semiconductor device may be raised or lowered relative to other areas of the semiconductor device. Therefore, focusing the light on one area causes another to become unfocused. By carefully designing a photomask to cause phase shifts of the light transmitted therethrough, focus across all areas of the semiconductor device can be achieved during photolithography, which results in sharp and accurate patterns formed on the semiconductor device.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: August 15, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Gong Chen, Frank Tsai
  • Patent number: 9721754
    Abstract: The invention relates to a method for processing a substrate with a focussed particle beam which incidents on the substrate, the method comprising the steps of: (a) generating at least one reference mark on the substrate using the focused particle beam and at least one processing gas, (b) determining a reference position of the at least one reference mark, (c) processing the substrate using the reference position of the reference mark, and (d) removing the at least one reference mark from the substrate.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: August 1, 2017
    Assignee: Carl Zeiss SMT GmbH
    Inventors: Tristan Bret, Petra Spies, Thorsten Hofmann
  • Patent number: 9711344
    Abstract: To improve the manufacturing yield of a semiconductor device, there is to provide a method of manufacturing a semiconductor device using a multilayer resist, in which before performing water repelling processing for immersion exposure on a wafer, an anti-reflection film, an underlayer film, and an intermediate film applied to a wafer edge portion are eliminated through rinse processing.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: July 18, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Toshifumi Suganaga
  • Patent number: 9686869
    Abstract: A write wiring trace is formed over insulating layer. A coating layer, being directly in contact with at least a first portion of a surface of the write wiring trace, is formed over the insulating layer to cover the write wiring trace. A connection terminal is formed over the insulating layer to be electrically connected to the write wiring trace and exposed from the coating layer.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: June 20, 2017
    Assignee: NITTO DENKO CORPORATION
    Inventors: Hiroyuki Tanabe, Hitoki Kanagawa
  • Patent number: 9685765
    Abstract: A new monolithic resonator metasurface design achieves ultra-high Q-factors while using only one resonator per unit cell. The metasurface relies on breaking the symmetry of otherwise highly symmetric resonators to induce intra-resonator mixing of bright and dark modes (rather than inter-resonator couplings), and is scalable from the near-infrared to radio frequencies and can be easily implemented in dielectric materials. The resulting high-quality-factor Fano metasurface can be used in many sensing, spectral filtering, and modulation applications.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: June 20, 2017
    Assignee: Sandia Corporation
    Inventors: Michael B. Sinclair, Larry K. Warne, Lorena I. Basilio, William L. Langston, Salvatore Campione, Igal Brener, Sheng Liu
  • Patent number: 9671689
    Abstract: New photoacid generator compounds (“PAGs”) are provided that comprise a cholate moiety and photoresist compositions that comprise such PAG compounds.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: June 6, 2017
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: Emad Aqad, Mingqi Li, Joseph Mattia, Cheng-Bai Xu
  • Patent number: 9666450
    Abstract: An interconnection substrate includes a plurality of electrically conductive elements of at least one wiring layer defining first and second lateral directions. Electrically conductive projections for bonding to electrically conductive contacts of at least one component external to the substrate, extend from the conductive elements above the at least one wiring layer. The conductive projections have end portions remote from the conductive elements and neck portions between the conductive elements and the end portions. The end portions have lower surfaces extending outwardly from the neck portions in at least one of the lateral directions. The substrate further includes a dielectric layer overlying the conductive elements and extending upwardly along the neck portions at least to the lower surfaces. At least portions of the dielectric layer between the conductive projections are recessed below a height of the lower surfaces.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: May 30, 2017
    Assignee: Tessera, Inc.
    Inventors: Kazuo Sakuma, Philip Damberg, Belgacem Haba
  • Patent number: 9653396
    Abstract: A coil CL1 is formed on a semiconductor substrate SB via a first insulation film, a second insulation film is formed so as to cover the first insulation film and the coil CL1, and a pad PD1 is formed on the second insulation film. A laminated film LF having an opening OP1 from which the pad PD1 is partially exposed is formed on the second insulation film, and a coil CL2 is formed on the laminated insulation film. The coil CL2 is disposed above the coil CL1, and the coil CL2 and the coil CL1 are magnetically coupled to each other. The laminated film LF is composed of a silicon oxide film LF1, a silicon nitride film LF2 thereon, and a resin film LF3 thereon.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: May 16, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Takuo Funaya, Takayuki Igarashi
  • Patent number: 9645390
    Abstract: The spatial light modulator is provided with: a substrate; a fixed electrode disposed on a surface of the substrate; a connecting section, which has one end of the connecting section connected to the surface of the substrate; a movable section, which is connected to another end of the connecting section; a supporting post section, which extends in the thickness direction of the substrate with one end of the supporting post section connected to the movable section; a reflecting member, which is connected to another end of the supporting post section; a movable electrode, which is disposed on a surface of the reflecting member, the surface of the reflecting member facing the fixed electrode; and a conductive layer, which is disposed on the supporting post section with a film thickness larger than that of the movable electrode, and which electrically connects between the movable section and the movable electrode.
    Type: Grant
    Filed: January 2, 2015
    Date of Patent: May 9, 2017
    Assignee: Nikon Corporation
    Inventors: Junji Suzuki, Yoshihiko Suzuki
  • Patent number: 9638999
    Abstract: The present invention provides methods of fabricating microelectronics structures and the resulting structures formed thereby using a dual-layer, light-sensitive, wet-developable bottom anti-reflective coating stack to reduce reflectance from the substrate during exposure. The invention provides dye-filled and dye-attached compositions for use in the anti-reflective coatings. The anti-reflective coatings are thermally crosslinkable and photochemically decrosslinkable. The bottom anti-reflective coating stack has gradient optical properties and develops at the same time as the photoresist. The method and structure are particularly suited to high-NA lithography processes.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: May 2, 2017
    Assignee: Brewer Science Inc.
    Inventors: Jim D. Meador, Douglas J. Guerrero, Ramil-Marcelo L. Mercado
  • Patent number: 9632415
    Abstract: A negative pattern is formed by applying a resist composition onto a substrate, exposing the resist film, and developing the exposed resist film in an organic solvent developer. The process further involves coating the negative pattern with a shrink agent solution of a polymer comprising recurring units capable of forming lactone under the action of acid in a C7-C16 ester or C8-C16 ketone solvent, baking the coating, and removing the excessive shrink agent via organic solvent development for thereby shrinking the size of spaces in the pattern.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: April 25, 2017
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Jun Hatakeyama, Kazuhiro Katayama, Koji Hasegawa, Masayoshi Sagehashi
  • Patent number: 9618850
    Abstract: A negative pattern is formed by applying a resist composition onto a substrate, exposing the resist film, and developing the exposed resist film in an organic solvent developer. The process further involves coating the negative pattern with a shrink agent solution of a polymer comprising recurring units having an acid labile group-substituted hydroxyl and/or carboxyl group in a C7-C16 ester or C8-C16 ketone solvent, baking the coating, and removing the excessive shrink agent via organic solvent development for thereby shrinking the size of spaces in the pattern.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: April 11, 2017
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Jun Hatakeyama, Kazuhiro Katayama, Koji Hasegawa, Kenji Funatsu
  • Patent number: 9618842
    Abstract: A resist composition including a base component that exhibits changed solubility in an alkali developing solution under the action of acid, an acid-generator component that generates acid upon exposure, and a nitrogen-containing organic compound, the acid generator component including an acid generator represented by general formula (b0), the nitrogen-containing organic compound including a compound represented by general formula (d1) or general formula (d2) in which each of R1 and R2 represents an aryl group or an alkyl group, Rf represents a fluorinated alkyl group, X?represents a counter anion, each of R3 and R4 represents an aliphatic hydrocarbon group, R5 represents a hydrocarbon group having 5 or more carbon atoms, and each of R6 and R7 independently represents a hydrogen atom, an aliphatic hydrocarbon group, or —C(?O)—O—R5.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: April 11, 2017
    Assignee: TOKYO OHKA KOGYO CO., LTD.
    Inventors: Yoshiyuki Utsumi, Makiko Irie
  • Patent number: 9599890
    Abstract: The invention concerns a manufacturing method for nanolithography masks from a PS-b-PMMA block copolymer film deposited on a surface to be etched, said copolymer film comprising PMMA nanodomains orientated perpendicularly to the surface to be etched, said method being characterized in that it comprises the following steps: partially irradiating said copolymer film to form a first irradiated area and a second non-irradiated area in said copolymer film, then treating said copolymer film in a developer solvent to selectively remove at least said PMMA nanodomains of said first irradiated area of said copolymer film.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: March 21, 2017
    Assignees: ARKEMA FRANCE, COMMISSARIAT A L' ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Christophe Navarro, Maxime Argoud, Xavier Chevalier, Raluca Tiron, Ahmed Gharbi
  • Patent number: 9593414
    Abstract: Amorphous silicon (a-Si) is hydrogenated for use as a dielectric (e.g., an interlayer dielectric) for superconducting electronics. A hydrogenated a-Si layer is formed on a substrate by CVD or sputtering. The hydrogen may be integrated during or after the a-Si deposition. After the layer is formed, it is first annealed in an environment of high hydrogen chemical potential and subsequently annealed in an environment of low hydrogen chemical potential. Optionally, the a-Si (or an H-permeable overlayer, if added) may be capped with a hydrogen barrier before removing the substrate from the environment of low hydrogen chemical potential.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: March 14, 2017
    Assignees: Intermolecular, Inc., Northrop Grumman Systems Corporation
    Inventors: Sergey Barabash, Chris Kirby, Dipankar Pramanik, Andrew Steinbach
  • Patent number: 9588414
    Abstract: Various embodiments provide photomask patterns and methods for forming the same. In an exemplary method, a to-be-etched pattern can be provided. The to-be-etched pattern can be divided into a first mask pattern and an initial second mask pattern. The first mask pattern can include one or more first patterns and the initial second mask pattern can include one or more second patterns. A second print scattering pattern can be formed and added to the initial second mask pattern. A position of the second print scattering pattern can be separated from a position of the one or more first patterns of the first mask pattern.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: March 7, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Tiezhu Wang
  • Patent number: 9581894
    Abstract: A system and method for repairing a photolithographic mask is provided. An embodiment comprises forming a shielding layer over an absorbance layer on a substrate. Once the shielding layer is in place, the absorbance layer may be repaired using, e.g., an e-beam process to initiate a reaction to repair a defect in the absorbance layer, with the shielding layer being used to shield the remainder of the absorbance layer from undesirable etching during the repair process.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: February 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chiang Tu, Chun-Lang Chen, Jong-Yuh Chang, Boming Hsu, Tran-Hui Shen
  • Patent number: 9583368
    Abstract: A flip chip package and a manufacturing method thereof are disclosed. The flip chip package in accordance with an embodiment of the present invention includes: a substrate; a plurality of pads formed on the substrate; a solder resist covering the substrate in such a way that the pads are exposed; a chip mounted on the substrate in such a way that the chip is electrically connected with the pads; a plurality of bumps formed, respectively, on the pads in such a way that the bumps are interposed between the pads and the chip; an under-fill flowing between the substrate and the chip and being filled in between the substrate and the chip; and an opening placed in between the plurality of bumps in such a way that a flowing space of the under-fill is provided in between the plurality of bumps.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: February 28, 2017
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Seok Yoon Hong
  • Patent number: 9570304
    Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming an anti-reflection layer on a lower layer, forming photoresist patterns on the anti-reflection layer, forming protection patterns to cover the photoresist patterns, respectively, etching the anti-reflection layer using the photoresist patterns covered with the protection patterns as an etch mask to form anti-reflection patterns, forming spacers to cover sidewalls of the anti-reflection patterns, and removing the anti-reflection patterns.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: February 14, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min Ju Park, Haisub Na, Hyojin Yun, Kyoungseon Kim, Su Min Kim, Hyunwoo Kim, Su-min Park, So-Ra Han
  • Patent number: 9570343
    Abstract: The present invention is a new formulation and process for treating TiN semiconductor devices having a high aspect ratio structure formed thereon. The new composition is designed to be used in the chip making process between cleaning a wet etched memory device and its final rinse/drying process. It is intended to include the treatment in order to prevent collapse of the high aspect ratio TiN structure found on the semiconductor device.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: February 14, 2017
    Assignee: AVANTOR PERFORMANCE MATERIALS, LLC
    Inventor: Glenn Westwood
  • Patent number: 9548209
    Abstract: Provided is an integrated circuit (IC) fabrication method. The method includes receiving a mask, the mask having a plurality of dies and receiving a wafer, the wafer having a resist layer. The method further includes exposing the resist layer using the mask with a fraction radiation dose thereby forming a first plurality of images; re-positioning the mask relative to the wafer; and exposing the resist layer using the mask with another fraction radiation dose. A second plurality of images is formed, wherein a portion of the second plurality of images is superimposed over another portion of the first plurality of images.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: January 17, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Fang Yu, Chia-Ching Huang, Ting-Hao Hsu
  • Patent number: 9530688
    Abstract: A method of an aspect includes forming an interconnect line etch opening in a hardmask layer. The hardmask layer is over a dielectric layer that has an interconnect line disposed therein. The interconnect line etch opening is formed aligned over the interconnect line. A block copolymer is introduced into the interconnect line etch opening. The block copolymer is assembled to form a plurality of assembled structures that are spaced along a length of the interconnect line etch opening. An assembled structure is directly aligned over the interconnect line that is disposed within the dielectric layer.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: December 27, 2016
    Assignee: Intel Corporation
    Inventors: Paul A. Nyhus, Swaminathan Sivakumar, Robert Bristol
  • Patent number: 9523911
    Abstract: The present invention provides a radiation-sensitive resin composition that contains a polymer having a structural unit that includes an acid-labile group; and an acid generator, wherein the acid generator includes a compound including a sulfonate anion having SO3?, wherein a hydrogen atom or an electron-donating group bonds to an ? carbon atom with respect to SO3?, and an electron-withdrawing group bonds to a ? carbon atom with respect to SO3?; and a radiation-degradable onium cation. The compound preferably has a group represented by the following formula (1-1) or (1-2). In the following formulae (1-1) and (1-2), R1 and R2 each independently represent a hydrogen atom or a monovalent electron-donating group. R3 represent a monovalent electron-withdrawing group. R4 represents a hydrogen atom or a monovalent hydrocarbon group.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: December 20, 2016
    Assignee: JSR CORPORATION
    Inventors: Hiroshi Tomioka, Takakazu Kimoto, Yusuke Asano
  • Patent number: 9520258
    Abstract: A method of forming nanotubes may include applying a photoresist to a metal substrate, selectively exposing a first portion of the photoresist to electromagnetic radiation while not exposing a second portion to the electromagnetic radiation, removing the second portion of the photoresist from the metal substrate exposing a first portion of the metal substrate, exposing the first portion of the metal substrate to an etchant removing the first portion of the photoresist exposing a second portion of the metal substrate, and growing carbon nanotubes on the second portion of the metal substrate.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: December 13, 2016
    Assignees: ELORET CORPORATION
    Inventor: Michael Mikio Oye
  • Patent number: 9514958
    Abstract: An etching method containing the step of processing a substrate having a first layer containing titanium nitride (TiN) and a second layer containing a transition metal by bringing an etching liquid into contact with the substrate and thereby removing the first layer, wherein the first layer has a surface oxygen content from 0.1 to 10% by mole, and wherein the etching liquid comprises an ammonia compound and an oxidizing agent, and has a pH of from 7 to 14.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: December 6, 2016
    Assignee: FUJIFILM Corporation
    Inventors: Yoshinori Nishiwaki, Tetsuya Kamimura, Tadashi Inaba, Atsushi Mizutani
  • Patent number: 9500952
    Abstract: An orthogonal process for photolithographic patterning organic structures is disclosed. The disclosed process utilizes fluorinated solvents or supercritical CO2 as the solvent so that the performance of the organic conductors and semiconductors would not be adversely affected by other aggressive solvent. One disclosed method may also utilize a fluorinated photoresist together with the HFE solvent, but other fluorinated solvents can be used. In one embodiment, the fluorinated photoresist is a resorcinarene, but various fluorinated polymer photoresists and fluorinated molecular glass photoresists can be used as well. For example, a copolymer perfluorodecyl methacrylate (FDMA) and 2-nitrobenzyl methacrylate (NBMA) is a suitable orthogonal fluorinated photoresist for use with fluorinated solvents and supercritical carbon dioxide in a photolithography process.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: November 22, 2016
    Assignee: Cornell University
    Inventors: Christopher K. Ober, George Malliaras, Jin-Kyun Lee, Alexander Zakhidov, Margarita Chatzichristidi, Priscilla Dodson
  • Patent number: 9466796
    Abstract: According to one embodiment, there is provided a manufacturing method of an electronic device including a lower electrode, a source electrode and a drain electrode made of a nanoparticulate conductive material on a substrate, an organic semiconductor layer between the source and drain electrodes, and a gate electrode on the organic semiconductor layer via a gate insulating layer. The manufacturing method includes forming a nonphotosensitive resin layer as the gate insulating layer on the organic semiconductor layer and on the lower electrode, forming a photosensitive resin layer as the gate insulating layer on the nonphotosensitive resin layer, and forming a through hole in the photosensitive resin layer on the lower electrode.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: October 11, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Masahiko Akiyama
  • Patent number: 9460260
    Abstract: A method for processing exposure data (40) for exposing a pattern on a target (30) using a plurality of charged particle beams (24), the exposure data comprising pattern data (42) representing one or more features (60) to be written on the target (30) and exposure dose data (52) describing exposure dose of the charged particle beams.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: October 4, 2016
    Assignee: MAPPER LITHOGRAPHY IP B.V.
    Inventor: Marco Jan-Jaco Wieland
  • Patent number: 9458343
    Abstract: A method of forming patterns includes (a) coating a substrate with a resist composition for negative development to form a resist film, wherein the resist composition contains a resin capable of increasing the polarity by the action of the acid and becomes more soluble in a positive developer and less soluble in a negative developer upon irradiation with an actinic ray or radiation, (b) forming a protective film on the resist film with a protective film composition after forming the resist film and before exposing the resist film, (c) exposing the resist film via an immersion medium, and (d) performing development with a negative developer.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: October 4, 2016
    Assignee: FUJIFILM Corporation
    Inventor: Hideaki Tsubaki
  • Patent number: 9459534
    Abstract: Provided are photoresist overcoat compositions, substrates coated with the overcoat compositions and methods of forming electronic devices by a negative tone development process. The compositions, coated substrates and methods find particular applicability in the manufacture of semiconductor devices.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: October 4, 2016
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: Young Cheol Bae, Rosemary Bell, Jong Keun Park, Seung-Hyun Lee
  • Patent number: 9455186
    Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: September 27, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew S. Angyal, Junjing Bao, Griselda Bonilla, Samuel S. Choi, James A. Culp, Thomas W. Dyer, Ronald G. Filippi, Stephen E. Greco, Naftali E. Lustig, Andrew H. Simon
  • Patent number: 9451704
    Abstract: A plurality of suspension boards and an inspection substrate are integrally supported by a support frame. In each suspension board, a line is formed on a conductive first support substrate via a first insulating layer. The first support substrate and the line are electrically connected by a first via in the first insulating layer. In the inspection substrate, a conductor layer is formed on a conductive second support substrate with a second insulating layer sandwiched therebetween. The second support substrate and the conductor layer are electrically connected by a second via in the second insulating layer. The first via and the second via have the same configuration.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: September 20, 2016
    Assignee: NITTO DENKO CORPORATION
    Inventors: Terukazu Ihara, Jun Ishii, Naohiro Terada
  • Patent number: 9405199
    Abstract: A method of forming a resist pattern, and a film including a metal-containing compound formed on the resist pattern while developing the resist pattern. The method uses an organic solvent developer liquid, in which a metal compound capable of generating a hydroxyl group upon hydrolysis is dissolved in an organic solvent that does not have a functional group that reacts with the metal compound.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: August 2, 2016
    Assignee: TOKYO OHKA KOGYO CO., LTD.
    Inventors: Mai Sugawara, Kiyoshi Ishikawa
  • Patent number: 9400953
    Abstract: Methods, algorithms, processes, circuits, and/or structures for laser patterning suitable for customized RFID designs are disclosed. In one embodiment, a method of laser patterning of an identification device can include the steps of: (i) depositing a patternable resist formulation on a substrate having configurable elements and/or materials thereon; (ii) irradiating the resist formulation with a laser tool sufficiently to change the solubility characteristics of the resist in a developer; and (iii) developing exposed areas of the resist using the developer. Embodiments of the present invention can advantageously provide a relatively low cost and high throughput approach for customized RFID devices.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: July 26, 2016
    Assignee: Thin Film Electronics ASA
    Inventors: Criswell Choi, Joerg Rockenberger, Christopher Gudeman, J. Devin Mackenzie, Partick Smith, James Montague Cleeves
  • Patent number: 9396958
    Abstract: Techniques herein provide methods for self-aligned etching that use existing features for patterning or registering a pattern, without damaging existing features. Existing substrate structures are used to create a surface that enables directed self-assembly (DSA) of block copolymers (BCP) without a separate lithographic patterning layer. Methods herein include recessing at least one existing material or structure on a substrate, and adding a film that remains on the recessed material only. This film can be selected to have a preferential surface energy that enables controlled self-assembly of block copolymers. The substrate can then be etched using both existing structures and one polymer material as an etching mask. One example advantage is that self-assembled polymer material can be located to protect exposed corners of existing features, which reduces a burden of selective etch chemistry, increases precision of subsequent etching, and reduces sputter yield.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: July 19, 2016
    Assignee: Tokyo Electron Limited
    Inventors: Andrew W. Metz, Anton J. deVilliers
  • Patent number: 9389516
    Abstract: A process and composition for negative tone development comprises providing a photoresist film that generates acidic sites. Irradiating the photoresist film patternwise provides an irradiated film having exposed and unexposed regions where the exposed regions comprise imaged sites. Baking the irradiated film at elevated temperatures produces a baked-irradiated film comprising the imaged sites which after irradiating, baking, or both irradiating and baking comprise acidic imaged sites. Treating the baked-irradiated film with a liquid, gaseous or vaporous weakly basic compound converts the acidic imaged sites to a base treated film having chemically modified acidic imaged sites. Applying a solvent developer substantially dissolves regions of the film that have not been exposed to the radiant energy, where the solvent developer comprises a substantial non-solvent for the chemically modified acidic imaged sites.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: July 12, 2016
    Assignee: International Business Machines Corporation
    Inventors: Luisa D. Bozano, Dario L. Goldfarb, Linda K. Sundberg, Hoa D. Truong, Hsinyu Tsai, Gregory M. Walraff
  • Patent number: 9341939
    Abstract: Implementations described and claimed herein include photolithography technology to alleviate the imbalance of transmission intensity induced. In one implementation, a method comprises exposing an alternating phase shift mask (Alt-PSM) and a trim mask, wherein an exposure placement of the trim mask is shifted relative to an exposure placement of the Alt-PSM.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: May 17, 2016
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Dan Yu, Aaron Bowser, Yi Liu
  • Patent number: 9341469
    Abstract: A continuous scan type measuring apparatus includes a continuous scan type optical application measuring instrument, a single-axis measuring instrument scanning stage and two carrier stages. The continuous scan type optical application measuring instrument performs a surface shape measurement of a measuring object. The single-axis measuring instrument scanning stage carries the optical application measuring instrument and causes the optical application measuring instrument to perform continuous scanning along a predetermined direction. The two carrier stages are detachably mount respective measuring objects thereon and move independently of each other. The two carrier stages are positioned independently at one of a measurement position within a scanning range of the optical application measuring instrument and a replacement position of the measuring objects.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: May 17, 2016
    Assignee: TAKAOKA TOKO CO., LTD.
    Inventor: Mitsuhiro Ishihara
  • Patent number: 9304399
    Abstract: A resist composition includes: a crosslinking material that is crosslinked in the presence of an acid; an acid amplifier; and a solvent.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: April 5, 2016
    Assignee: SONY CORPORATION
    Inventors: Nobuyuki Matsuzawa, Isao Mita, Koji Arimitsu
  • Patent number: 9295162
    Abstract: A non-deleterious method for producing a continuous conductive circuit upon a non-conductive substrate can begin with the application of a metallic base layer upon a surface of a non-conductive substrate. A circuit pattern can be created within the metallic base layer based upon a circuit design. The metallic base layer comprising the circuit pattern can be physically separated from the remainder of the metallic base layer on the non-conductive substrate. The region of the non-conductive substrate surface that encloses the circuit pattern can be called the plating region. The remainder of the non-conductive substrate surface can be called the non-plating region. A first metal layer can be added upon the metallic base layer. A second metal layer can be added upon the first metal layer of the plating region. The second metal layer can be electrically conductive and restricted from forming on the first metal layer of the non-plating region.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: March 22, 2016
    Assignee: Taiwan Green Point Enterprises Co., Ltd.
    Inventors: Sheng-Hung Yi, Pen-Yi Liao
  • Patent number: 9291754
    Abstract: A method for producing a mold includes: applying a block copolymer solution made of first and second polymers on a base member; performing a first annealing process at a temperature higher than Tg of the block copolymer after drying the coating film; forming a concavity and convexity structure on the base member by removing the second polymer by an etching process; performing a second annealing process of the concavity and convexity structure at a temperature higher than Tg of the first polymer; forming a seed layer on the structure; laminating or stacking a metal layer on the seed layer by an electroforming; and peeling off the metal layer from the base member. The second annealing process enables satisfactory transfer of a concavity and convexity structure on the base member onto the metal layer.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: March 22, 2016
    Assignees: JX NIPPON OIL & ENERGY CORPORATION, TOKYO INSTITUTE OF TECHNOLOGY
    Inventors: Satoshi Masuyama, Madoka Takahashi, Suzushi Nishimura, Maki Fukuda, Takashi Seki
  • Patent number: 9281191
    Abstract: To improve the performance of a semiconductor device, a semiconductor device manufacturing method includes an exposing process of performing pattern exposure of a resist film formed on a substrate by using EUV light reflected from a front surface of an EUV mask as a reflective mask. In this exposing process, the resist film is subjected to pattern exposure by repeating a process of irradiating the resist film with the EUV light by changing a focal position of the EUV light with which the resist film is irradiated, along a film thickness direction of the resist film. After this exposing process, the resist film subjected to pattern exposure is developed to form a resist pattern.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: March 8, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Toshihiko Tanaka
  • Patent number: 9263285
    Abstract: There is provided a composition for forming a resist underlayer film having heat resistance for use in a lithography process in semiconductor device production. A composition for forming a resist underlayer film, comprising a polymer that contains a unit structure of formula (1) and a unit structure of formula (2) in a proportion of 3 to 97:97 to 3 in molar ratio: A method for producing a semiconductor device, including the steps of: forming an underlayer film using the composition for forming a resist underlayer film on a semiconductor substrate; forming a hard mask on the underlayer film; further forming a resist film on the hard mask; forming a patterned resist film and developing; etching the hard mask according to the patterned resist film; etching the underlayer film according to the patterned hard mask; and processing the semiconductor substrate according to the patterned underlayer film.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: February 16, 2016
    Assignee: NISSAN CHEMICAL INDUSTRIES, LTD.
    Inventors: Tetsuya Shinjo, Hiroaki Okuyama, Keisuke Hashimoto, Yasunobu Someya, Ryo Karasawa, Masakazu Kato
  • Patent number: 9245789
    Abstract: The present invention addresses the problem of inhibiting the evolution of a poisoning gas to eliminate wiring-pattern resolution failures and thereby forming a desired wiring layer structure to provide functional elements having an improved property yield. This method for forming multi-layered copper interconnect on a semiconductor substrate comprises: forming a multilayer resist structure to form a given resist pattern on a substrate including an interlayer dielectric film that has via holes which have been formed in part thereof and filled with an SOC layer, the multilayer resist structure comprising an SOC layer, an SOG layer, an SiO2 layer, and a chemical amplification type resist superposed in this order from the substrate side; conducting etching using the resist pattern as a mask to form a pattern for a wiring layer and via plugs; and forming the wiring layer and the via plugs in the pattern.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: January 26, 2016
    Assignee: NEC CORPORATION
    Inventors: Koichiro Okamoto, Munehiro Tada, Hiromitsu Hada, Toshitsugu Sakamoto
  • Patent number: 9239498
    Abstract: The present invention provides a liquid crystal display device, which includes a plurality of pixel units. Each of the pixel units further includes a liquid crystal layer, a pixel electrode and a corresponding electrode. The pixel electrode and the corresponding electrode are disposed on two opposite sides of liquid crystal layer. The corresponding electrode further includes a first electrode pattern disposed oppositely to the pixel electrode, and a second electrode pattern connected to the first electrode pattern for applying an external voltage to the first electrode pattern so as to form an alignment electric field for the liquid crystal layer between the first electrode pattern and the pixel electrode. The present invention changes the way in which the external voltage is applied, and introduces the external voltage from one side of the color filter substrate to improve success rate of liquid crystal alignment, reduce energy-consumption and reduce waste.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: January 19, 2016
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventors: Bing-jei Liao, Chialiang Lin
  • Patent number: 9213238
    Abstract: An orthogonal process for photolithographic patterning organic structures is disclosed. The disclosed process utilizes fluorinated solvents or supercritical CO2 as the solvent so that the performance of the organic conductors and semiconductors would not be adversely affected by other aggressive solvent. One disclosed method may also utilize a fluorinated photoresist together with the HFE solvent, but other fluorinated solvents can be used. In one embodiment, the fluorinated photoresist is a resorcinarene, but various fluorinated polymer photoresists and fluorinated molecular glass photoresists can be used as well. For example, a copolymer perfluorodecyl methacrylate (FDMA) and 2-nitrobenzyl methacrylate (NBMA) is a suitable orthogonal fluorinated photoresist for use with fluorinated solvents and supercritical carbon dioxide in a photolithography process.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: December 15, 2015
    Assignee: Cornell University
    Inventors: Christopher K. Ober, George Malliaras, Jin-Kyun Lee, Alexander Zakhidov, Margarita Chatzichristidi, Priscilla Dodson
  • Patent number: 9212293
    Abstract: Provided are photoresist overcoat compositions, substrates coated with the overcoat compositions and methods of forming electronic devices by a negative tone development process. The compositions, coated substrates and methods find particular applicability in the manufacture of semiconductor devices.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: December 15, 2015
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: Young Cheol Bae, Rosemary Bell, Jong Keun Park, Seung-Hyun Lee
  • Patent number: 9207531
    Abstract: According to one embodiment, a pattern including first and second block phases is formed by self-assembling a block copolymer onto a film to be processed. The entire block copolymer present in a first region is removed under a first condition by carrying out energy beam irradiation and development, thereby leaving a pattern including the first and second block phases in a region other than the first region. The first block phase present in a second region is selectively removed under a second condition by carrying out energy beam irradiation and development, thereby leaving a pattern including the first and second block phases in an overlap region between a region other than the first region and a region other than the second region, and leaving a pattern of second block phase in the second region excluding the overlap region. The film is etched with the left patterns as masks.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: December 8, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroko Nakamura, Koji Asakawa, Shigeki Hattori, Satoshi Tanaka, Toshiya Kotani
  • Patent number: 9202702
    Abstract: A semiconductor device having a substrate, and at least one contact, situated on and/or above a surface of the substrate, having at least one layer made of a conductive material, the conductive material including at least one metal. The layer made of the conductive material is sputtered on, and has tear-off marks on at least one outer side area between an outer base area facing the surface and an outer contact area facing away from the surface. A manufacturing method for a semiconductor device having at least one contact is also described.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: December 1, 2015
    Assignee: ROBERT BOSCH GMBH
    Inventors: Frederik Schrey, Achim Trautmann, Joachim Rudhard