Making Electrical Device Patents (Class 430/311)
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Patent number: 12386251Abstract: A first bright field reticle and a second bright field reticle are utilized for a double exposure EUV photolithography process in which exposure areas of the first and second bright field reticles overlap. The first and second reticles each include, respectively, a substrate, a reflective multilayer on the substrate, a main pattern of absorption material on the reflective multilayer, a black border area, and an additional absorption area of the absorption material between the black border and the main pattern.Type: GrantFiled: May 5, 2023Date of Patent: August 12, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sheng-Min Wang, Ken-Hsien Hsieh, Manuel Alejandro Fernandez Lopez, Yu-Tse Lai
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Patent number: 12386262Abstract: A resist lower layer film formation composition that exhibits a high etching resistance and a good dry-etching rate ratio and optical constant, exhibits good coating performance even on a so-called stepped substrate, produces a small film thickness difference after embedding, and enables a flat film to be formed. Also a method for manufacturing a polymer suitable for the resist lower layer film formation composition, a resist lower layer film in which the formation composition is used, and a method for manufacturing a semiconductor device. A resist lower layer film formation composition containing: a solvent; and a reaction product between an aromatic compound having 6-60 carbon atoms and a carbon-oxygen double bond of an oxygen-containing compound having 3-60 carbon atoms. The oxygen-containing compound has, in one molecule, one partial structure: —CON< or —COO—. In the reaction product, one carbon atom of the oxygen-containing compound links two of the aromatic compounds.Type: GrantFiled: May 21, 2019Date of Patent: August 12, 2025Assignee: NISSAN CHEMICAL CORPORATIONInventors: Hikaru Tokunaga, Hiroto Ogata, Keisuke Hashimoto, Makoto Nakajima
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Patent number: 12374655Abstract: A method includes attaching a wafer to a wafer chuck having a curved surface. The method further includes placing a device die on the wafer, such that a first dielectric layer of the device die is in contact with a second dielectric layer of the wafer, and performing an annealing process to bond the first dielectric layer to the second dielectric layer. The method further includes encapsulating the device die with an encapsulating material, forming redistribution lines overlapping the encapsulating material and the device die, and sawing the encapsulating material to form a plurality of packages.Type: GrantFiled: June 13, 2022Date of Patent: July 29, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chih Chiou, Yung-Chi Lin, Yen-Ming Chen
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Patent number: 12353143Abstract: A reticle includes a border section surrounding a pattern section, and gas openings arranged in and passing through the border section. The gas openings are coupled to a gas supply. Each gas opening extends in a first direction inclined to and forming an angle with a reticle center axis that extends perpendicularly away from a front surface of the reticle, and is configured to blow a pressurized gas in the first direction away from the front surface to create an air wall adjacent to and surrounding the front surface, thereby advantageously preventing particles from falling on the front surface of the reticle.Type: GrantFiled: April 21, 2023Date of Patent: July 8, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yao-Tang Lin, Tzu-Wen Chen, Jian-Yuan Su, Ming-Hsin Chen
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Patent number: 12354857Abstract: The present disclosure provides embodiments of a system and method for detecting processing chamber condition. The embodiments include performing a wafer-less processing step in a processing chamber to determine the condition of the chamber walls. Based on an analysis of the residual gas resulting from the wafer-less processing step, an operator or a process controller can determine whether the chamber walls have deteriorated to such an extent as to be cleaned.Type: GrantFiled: July 28, 2023Date of Patent: July 8, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Yen-Liang Chen
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Patent number: 12347911Abstract: A manufacturing method of a filter, including the following steps: defining an adhesive layer on a surface of a substrate according to a filter pattern; covering the surface of the substrate by a conductive layer, wherein the conductive layer comprises a first covering part and a second covering part, wherein the first covering part and the second covering part are non-overlapping. In an aspect, the first covering part of the conductive layer is attached to the adhesive layer according to the filter pattern and the second covering part is not attached to the adhesive layer. In an aspect, the second covering part of the conductive layer is attached to the surface of the substrate to form the filter pattern.Type: GrantFiled: December 16, 2022Date of Patent: July 1, 2025Assignee: National Tsing Hua UniversityInventors: Shang-Hua Yang, Yi-Chun Hung
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Patent number: 12346029Abstract: Collection reflectors with multiple reflector elements defined on a curved surface are used to collect EUV optical radiation from an EUV emitting area. Each of the reflector elements can image the emitting area at or near a corresponding reflective element of a second multi-element reflector that overlaps radiation from each of the multiple reflector element of the collection reflector to illuminate a grating reticle. Systems with such a collection reflector can use fewer optical elements. In addition, grating reticles are defined on a curve substrate an include a plurality of grating phase steps so that the grating reticle provides phase curvature along two axes but with physical curvature along a single axis. Methods of producing varying duty cycle 1D patterns are also disclosed.Type: GrantFiled: May 4, 2022Date of Patent: July 1, 2025Assignee: Nikon CorporationInventors: Donis G. Flagello, Daniel Gene Smith, Michael Birk Binnard, Stephen Paul Renwick
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Patent number: 12332576Abstract: A method for maintaining a projection exposure apparatus comprising at least two modules and a reference element, wherein the modules are referenced to the reference element, comprises: removing a module; attaching a service module to or in the vicinity of the projection exposure apparatus; referencing the service module to the reference element of the projection exposure apparatus; and implementing a maintenance measure with the aid of the service module.Type: GrantFiled: November 14, 2022Date of Patent: June 17, 2025Assignee: Carl Zeiss SMT GmbHInventors: Dirk Heinrich Ehm, Jens Kugler, Benjahman Julius Modeste, Marwene Nefzi
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Patent number: 12334342Abstract: The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes forming a hard mask layer over a substrate, the substrate having one or more regions to receive a treatment process, forming a resist layer over the hard mask layer, patterning the resist layer to form a plurality of openings in the resist layer, each of the openings free of concave corners, performing an opening expanding process to enlarge at least one of the openings in the resist layer, transferring the openings in the resist layer to the hard mask layer, and performing the treatment process to the one or more regions in the substrate through the openings in the hard mask layer.Type: GrantFiled: July 30, 2023Date of Patent: June 17, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Tien Shen, Ya-Wen Yeh, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Wei-Hao Wu, Li-Te Lin, Ru-Gun Liu, Kuei-Shun Chen
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Patent number: 12327656Abstract: The present invention relates to the technical field of conductivity measurement electrode preparation, and specifically discloses a method for manufacturing a high-precision marine conductivity measurement electrode based on screen printing. The method of the present invention can realize the preparation of a conductivity measurement electrode with high precision, short preparation time and less drop-out of the electrode, thereby meeting the requirements of the current marine observation network for the high-volume and high-precision application of the conductivity sensor.Type: GrantFiled: February 23, 2023Date of Patent: June 10, 2025Assignee: INSTITUTE OF OCEANOGRAPHIC INSTRUMENTATION, SHANDONG ACADEMY OF SCIENCESInventors: Zhigang Gai, Fengxiang Guo, Shousheng Liu, Xueyu Zhang, Yibao Wang, Lili Zhang, Guangsen Xia, Xiaoling Sun, Wei Sun
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Patent number: 12326401Abstract: Refractive index distribution standard in the form of a three-dimensional object which contains in its volume a base medium and regions of variable size and distance with a refractive index other than that of the base medium, characterised in that the difference between the refractive index of said regions and the refractive index of the base medium is not greater than 0.04, at least one of the regions is a set of at least two prisms or cylinders or coaxial rings of variable size and distance, having a dimension in at least one direction similar to the resolving power of the measurement system under assessment and at least one of the regions is sphere-like or ellipsoid-like in shape.Type: GrantFiled: May 20, 2020Date of Patent: June 10, 2025Assignee: POLITECHNIKA WARSZAWSKAInventors: Michal Ziemczonok, Arkadiusz Kus, Małgorzata Kujawinska
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Patent number: 12300609Abstract: A semiconductor structure includes: a first gate structure and a second gate structure extending in a first direction; a first base level metal interconnect (M0) pattern extending in a second direction perpendicular to the first direction; a second M0 pattern extending in the second direction; a third M0 pattern located between the first and second gate structures and extending in the first direction, two ends of the third M0 pattern connected to the first M0 pattern and the second M0 pattern, respectively; a fourth M0 pattern and a fifth M0 pattern located between the first and second M0 patterns and extending in the second direction. A distance between the fourth M0 pattern and the first M0 pattern in the first direction is equal to a minimum M0 pattern pitch, and a distance between the fourth M0 pattern and the second M0 pattern is equal to the minimum M0 pattern pitch.Type: GrantFiled: August 10, 2023Date of Patent: May 13, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Wei Peng, Jiann-Tyng Tzeng, Ken-Hsien Hsieh
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Patent number: 12287567Abstract: Methods incorporate variable side wall angle (VSA) into calculated patterns, using a mask 3D (M3D) effect. Embodiments include inputting a mask exposure information and determining the M3D effect. Determining the M3D effect may include determining the VSA. Embodiments may include calculating a VSA; and calculating a pattern on a substrate using the calculated VSA, wherein calculating the pattern on the substrate includes a mask 3D effect.Type: GrantFiled: January 30, 2024Date of Patent: April 29, 2025Assignee: D2S, Inc.Inventors: Akira Fujimura, Nagesh Shirali, Ajay Baranwal
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Patent number: 12288751Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate including a dielectric material having a first surface and an opposing second surface, a first material on at least a portion of the second surface, and a second material on at least a portion of the first material, wherein the second material has a different material composition than the first material.Type: GrantFiled: August 17, 2023Date of Patent: April 29, 2025Assignee: Intel CorporationInventors: Aleksandar Aleksov, Johanna M. Swan
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Patent number: 12275184Abstract: Implanted medical devices need a mechanism of immobilization to surrounding tissues, which minimizes tissue damage while providing reliable long-term anchoring. This disclosure relates to techniques for patterning arbitrarily shaped 3D objects and to patterned balloon devices having micro- or nano-patterning on an outer surface of an inflatable balloon. The external pattern can provide enhanced friction and anchoring in an aqueous environment. Examples of these types of patterns are hexagonal arrays inspired by tree frogs, corrugated patterns, and microneedle patterns. The patterned balloon devices can be disposed between an implant and surrounding tissues to facilitate anchoring of the implant.Type: GrantFiled: April 3, 2023Date of Patent: April 15, 2025Assignee: Cornell UniversityInventors: Seyedhamidreza Alaie, Simon Dunham, Bobak Mosadegh, James K. Min, Amir Ali Amiri Moghadam
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Patent number: 12276907Abstract: According to example embodiments, there is provided a photoresist inspection method. The photoresist inspection method includes: providing a photoresist on a substrate; irradiating the photoresist with an electron beam and an excitation beam; detecting fluorescent light generated by the photoresist in response to the excitation beam; and evaluating the photoresist based on the fluorescent light.Type: GrantFiled: February 24, 2022Date of Patent: April 15, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sukjong Bae, Johan Hofkens, Haifeng Yuan, Flip de Jong
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Patent number: 12279368Abstract: A printed wiring board includes a resin insulating layer including resin and particles, and a conductor layer formed on a surface of the resin insulating layer. The particles in the resin insulating layer include first particles and second particles such that the first particles are partially embedded in the resin and the second particles are completely embedded in the resin, and the resin insulating layer is formed such that the first particles has exposed surfaces exposed from the resin and covered surfaces covered by the resin, respectively, the surface of the resin insulating layer includes the first exposed surfaces, and a ratio of a second area to a first area is in a range of 0.1 to 0.25 where the first area is an area of the surface of the resin insulating layer, and the second area is obtained by summing areas of the exposed surfaces of the first particles.Type: GrantFiled: August 30, 2022Date of Patent: April 15, 2025Assignee: IBIDEN CO., LTD.Inventors: Satoru Kawai, Katsuhiko Tanno, Susumu Kagohashi, Kentaro Wada
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Patent number: 12276918Abstract: A method for calculating a spatial map associated with a component, the spatial map indicating spatial variations of thermal expansion parameters in the component, the method comprising: providing or determining a temperature distribution in the component as a function of time; calculating the spatial map associated with the component using the provided or determined temperature distribution in the component and optical measurements of a radiation beam that has interacted directly or indirectly with the component, the optical measurements being time synchronized with the provided or determined temperature distribution in the component.Type: GrantFiled: June 17, 2021Date of Patent: April 15, 2025Assignee: ASML Netherlands B.V.Inventors: Mauritius Gerardus Elisabeth Schneiders, Koos Van Berkel, Wenjie Jin
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Patent number: 12276820Abstract: Provided are novel energy-efficient signal-transparent window assemblies and methods of fabricating thereof. These window assemblies are specifically configured to allow selective penetration of millimeter waves, representing current and future wireless signal spectrum. This signal penetration is provided while IR blocking properties are retained. Furthermore, the windows assemblies remain substantially transparent within the visible spectrum with no specific features detectable to the naked eye. This unique performance is achieved by patterning conductive layers such that the conductive layer edges remain protected during most fabrication steps and the fabrication. As such, the conductive layers are encapsulated and being separated from the environment while retaining separation between individual disjoined structures of these layers. For example, a barrier layer and/or a dielectric layer may extend over the conductive layer edge.Type: GrantFiled: January 6, 2022Date of Patent: April 15, 2025Assignee: LabForInventionInventor: Guowen Ding
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Patent number: 12273993Abstract: The invention relates to a carrier arrangement (100; 500; 600; 700; 800; 900; 1000), and a method for producing a carrier arrangement. The method comprises: producing a layer (130; 530; 630; 730; 830; 930; 1030) on a surface (120; 520; 620; 720; 820; 920; 1020) of a carrier (110; 510; 610; 710; 810; 910; 1010), the layer comprising a first region (131; 531; 631; 731; 831; 931; 1031) and a second region (132; 532; 632; 732; 832; 932; 1032) connected to the first region, the first region covering a first surface region (121; 521; 621; 721; 821; 921; 1021) of the carrier and the second region covering a second surface region (122; 722; 922) of the carrier, detaching the second region of the layer from the carrier, the first region of the layer remaining on the first surface region of the carrier and not being separated from the second region, the layer being flexible in the detached second region.Type: GrantFiled: March 13, 2024Date of Patent: April 8, 2025Assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.Inventors: Mathias Bottcher, Frank Windrich, Kai Zoschke, M. Jürgen Wolf
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Patent number: 12272650Abstract: Embodiments may relate to a microelectronic package that includes a substrate with a cavity therein. A component may be positioned within the substrate, and exposed by the cavity. A solder bump may be positioned within the cavity and coupled with the component, and a bridge die may be coupled with the solder bump. Other embodiments may be described or claimed.Type: GrantFiled: February 28, 2020Date of Patent: April 8, 2025Assignee: Intel CorporationInventors: Omkar G. Karhade, Debendra Mallik, Nitin A. Deshpande, Amruthavalli Pallavi Alur
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Patent number: 12269125Abstract: A laser processing device includes: a laser irradiation unit; and a control unit. The control unit is configured to execute a first control to control the laser irradiation unit to form modified regions for division along each of lines extending in an X direction and cracks extending from the modified regions in a direction of a surface, a second control to control the laser irradiation unit to form modified regions for division along each of a plurality of lines in a Y direction and cracks extending from the modified regions in the direction of the surface, and a third control to control the laser irradiation unit to form cracks extending from a plurality of modified regions for suppressing warpage before the second control, the cracks being formed to reach a back surface and not to be continuous with the cracks extending from the modified regions for division.Type: GrantFiled: January 25, 2022Date of Patent: April 8, 2025Assignee: HAMAMATSU PHOTONICS K.K.Inventors: Takafumi Ogiwara, Hayate Joan
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Patent number: 12272577Abstract: An inspection device includes a laser irradiation unit irradiating a wafer with laser light, a display displaying information, and a control unit. The control unit is constituted to execute deriving of an estimated processing result including information a modified region and a crack extending from the modified region formed on the wafer when the wafer is irradiated with the laser light by the laser irradiation unit on the basis of set recipes (processing conditions), and controlling the display so as to display an estimated processing result image depicting both a graphic image of the wafer and a graphic image of the modified region and the crack in the wafer in consideration of positions of the modified region and the crack in the wafer derived as the estimated processing result.Type: GrantFiled: March 3, 2021Date of Patent: April 8, 2025Assignee: HAMAMATSU PHOTONICS K.K.Inventors: Takeshi Sakamoto, Takafumi Ogiwara, Iku Sano
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Patent number: 12267963Abstract: A circuit board with anti-corrosion properties, a method for manufacturing the circuit board, and an electronic device are provided. The circuit board includes a circuit substrate, a first protective layer, and a second protective layer. The circuit substrate includes a base layer and an outer wiring layer formed on the base layer. The circuit substrate further defines a via hole connected to the outer wiring layer. The first protective layer is formed on the outer wiring layer and an inner sidewall of the via hole, and is made of a white oil. The second protective layer is formed on the first protective layer.Type: GrantFiled: January 31, 2024Date of Patent: April 1, 2025Assignee: CHAMP TECH OPTICAL (FOSHAN) CORPORATIONInventors: Li-Ping Wang, Yung-Ping Lin, Yong-Kang Zhang, Qiu-Ri Zhang, You-Zhi Lu
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Patent number: 12259664Abstract: A method of configuring a mark having a trench to be etched into a substrate, the method including: obtaining a relation between an extent of height variation across a surface of a probationary layer deposited on a probationary trench of a probationary depth and a thickness of the probationary layer; determining an extent of height variation across the surface of a layer deposited on the mark allowing a metrology system to determine a position of the mark; and configuring the mark by determining a depth of the trench based on the relation, the extent of height variation and the thickness of a process layer to be deposited on the mark.Type: GrantFiled: August 17, 2020Date of Patent: March 25, 2025Assignee: ASML NETHERLANDS B.V.Inventors: Jigang Ma, Hua Li
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Patent number: 12261085Abstract: The present disclosure relates to a method for forming a semiconductor structure includes depositing a dielectric layer on a substrate and depositing a patterning layer on the dielectric layer. The method also includes performing a first etching process on the patterning layer to form a first region including a first plurality of blocks at a first pattern density and a second region including a second plurality of blocks at a second pattern density that is lower than the first pattern density. The method also includes performing a second etching process on the second plurality of blocks to decrease a width of each block of the second plurality of blocks and etching the dielectric layer and the substrate using the first and second pluralities of blocks to form a plurality of fin structures.Type: GrantFiled: July 26, 2023Date of Patent: March 25, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Lun Chen, Li-Te Lin, Chao-Hsien Huang
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Patent number: 12259662Abstract: A method for manufacturing a semiconductor device may include: forming a first layer comprising a plurality of patterns, each pattern having a different respective pitch; performing exposure and development to form a second layer at a layer different from the first layer; determining whether a pitch shift of a part of exposure patterns formed is within a tolerance range, using a Moiré pattern; and performing etching for the second layer when the pitch shift of the part of exposure patterns is determined to be within the tolerance range. Performing the exposure and the development may include forming a first exposure pattern corresponding to a key pattern having a first pitch, forming a second exposure pattern corresponding to a cell pattern having a second pitch, and forming a third exposure pattern corresponding to a middle pitch pattern having a third pitch between the first pitch and the second pitch.Type: GrantFiled: November 8, 2022Date of Patent: March 25, 2025Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Woohyeok Jeong, Donghwan Kim, Inchul Shin, Wonhyeok Jo, Hyein Cho, Seulgi Han
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Patent number: 12240760Abstract: Methods of forming carbon nanotubes and structures and devices including carbon nanotubes are disclosed. Methods of forming the carbon nanotubes include patterning a surface of a substrate with polymeric material, removing portions of the polymeric material to form exposed substrate surface sections, and forming the carbon nanotubes on the exposed substrate sections.Type: GrantFiled: May 29, 2019Date of Patent: March 4, 2025Assignee: ASM IP Holding B.V.Inventor: Suvi Haukka
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Patent number: 12235224Abstract: Process window qualification (PWQ) layouts can be used to determine a presence of a pattern anomaly associated with the pattern, patterning process, or patterning apparatus. For example, a modulated die or field can be compared to a slightly lower offset modulated die or field. In another example, the high to low corners for a particular condition or combination of conditions are compared. In yet another example, process modulation parameters can be used to estimate criticality of particular weak points of interest.Type: GrantFiled: April 26, 2022Date of Patent: February 25, 2025Assignee: KLA CORPORATIONInventors: Andrew Cross, Kaushik Sah, Martin Plihal
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Patent number: 12235579Abstract: A method for producing an actinic ray-sensitive or radiation-sensitive resin composition of an embodiment of the present invention is a method for producing an actinic ray-sensitive or radiation-sensitive resin composition including at least a resin having a polarity that increases due to decomposition by the action of an acid, a compound that generates an acid upon irradiation with actinic rays or radiation, and a solvent, in which the compound that generates an acid upon irradiation with actinic rays or radiation includes one or more compounds selected from the group consisting of a compound (I) to (III) below, and the actinic ray-sensitive or radiation-sensitive resin composition is produced by mixing a first solution including the resin having a polarity that increases by the action of an acid and a first solvent with the one or more compounds selected from the group consisting of the compound (I) to (III).Type: GrantFiled: December 13, 2021Date of Patent: February 25, 2025Assignee: FUJIFILM CorporationInventors: Keiyu Ou, Naohiro Tango, Kei Yamamoto, Kazuhiro Marumo
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Patent number: 12228857Abstract: An object of the present invention is to provide a solution which contains an organic solvent as a main component (content: equal to or greater than 98% by mass) and has an excellent defect inhibition ability. Another object of the present invention is to provide a solution storage body storing the solution, an actinic ray-sensitive or radiation-sensitive resin composition containing the solution, and a pattern forming method and a manufacturing method of a semiconductor device using the solution. The solution of the present invention is a solution containing at least one kind of organic solvent having a boiling point lower than 200° C. and an organic impurity having a boiling point equal to or higher than 250° C., in which a content of the organic solvent with respect to a total mass of the solution is equal to or greater than 98% by mass, and a content of the organic impurity with respect to the total mass of the solution is equal to or greater than 0.1 mass ppm and less than 100 mass ppm.Type: GrantFiled: December 28, 2022Date of Patent: February 18, 2025Assignee: FUJIFILM CorporationInventor: Tetsuya Kamimura
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Patent number: 12232312Abstract: The present application provides a memory device and a method of manufacturing the memory device.Type: GrantFiled: March 3, 2022Date of Patent: February 18, 2025Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Liang-Pin Chou
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Patent number: 12222654Abstract: A method includes illuminating radiation to a resist layer over a substrate to pattern the resist layer. The patterned resist layer is developed by using a positive tone developer. The patterned resist layer is rinsed using a basic aqueous rinse solution. A pH value of the basic aqueous rinse solution is lower than a pH value of the developer, and a rinse temperature of rinsing the patterned resist layer is in a range of about 20° C. to about 40° C.Type: GrantFiled: July 16, 2021Date of Patent: February 11, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ming-Hui Weng, Chen-Yu Liu, Cheng-Han Wu, Ching-Yu Chang, Chin-Hsiang Lin
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Patent number: 12210279Abstract: An electroconductive-film-coated substrate includes a glass substrate and an electroconductive film disposed on one main surface of the glass substrate. The electroconductive film has an inclined portion in a peripheral edge. A distance from a position in the inclined portion where a thickness of the electroconductive film is 10% of a film thickness of a center of the electroconductive film to an edge end of the glass substrate is 3.00 mm or less. A distance from an end of the inclined portion to the edge end of the glass substrate is longer than 0.00 mm.Type: GrantFiled: May 24, 2022Date of Patent: January 28, 2025Assignee: AGC Inc.Inventors: Sotaro Nakamura, Masayoshi Mizoguchi, Takeshi Tomizawa, Takahira Miyagi, Ryusuke Morita
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Patent number: 12204248Abstract: In semiconductor manufacturing, deionized (DI) water or another process fluid is flowed through a nonmetallic pipe and onto a semiconductor wafer. Static electric charge is discharged from the DI water or other process fluid flowing through the nonmetallic pipe via an electrically conductive material disposed on an outside of the nonmetallic pipe. The electrically conductive material disposed on the outside of the nonmetallic pipe is electrically grounded. The nonmetallic pipe may comprise fluoropolymer (PFA) based tubing. In some embodiments, the nonmetallic pipe includes: a PFA-NE pipe connected with a chamber or housing containing the wafer, and a second pipe connected with the PFA-NE pipe by a pipe connector, in which the second pipe is more electrically insulating than the PFA-NE pipe.Type: GrantFiled: August 24, 2021Date of Patent: January 21, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Ling Tseng, Kai-Lun Tseng, Yuan-Yen Lo, Pei-Kao Li, Cheng Yu Wu
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Patent number: 12189309Abstract: A clamp assembly is disclose, the clamp assembly comprising a clamp (50) configurable to clamp a support member (110) to a lower base surface (49) of the clamp by electrostatic adhesion, and an arrangement configurable to direct a gas to the lower base surface (49) of the clamp. The arrangement is configurable to humidify the gas by exposing the gas to a liquid. Also disclosed is a method of discharging a lower base surface of a clamp, The method comprises the steps of humidifying a gas by exposing the gas to a liquid, and directing the humidified gas to a lower base surface of the clamp.Type: GrantFiled: November 2, 2020Date of Patent: January 7, 2025Assignee: ASML Netherlands B.V.Inventors: Ronald Van Der Wilk, Tiannan Guan
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Patent number: 12183609Abstract: A wafer carrier assembly comprising a wafer carrier having a first and second side, the first side including: a circular recess configured to receive a semiconductor device wafer, and at least one cut-out arranged along the circumference of the circular recess. The first side also includes a carrier cover having a top and bottom side, the top side including: a plurality of gridlines extending to edges of the carrier cover, and a plurality of reticles extending from the top side to the bottom side where subsets of reticles are arranged to have a common center and each subset of reticles is arranged at each intersection of the plurality of gridlines.Type: GrantFiled: March 3, 2022Date of Patent: December 31, 2024Assignee: Micron Technology, Inc.Inventor: Gabe Glass
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Patent number: 12183226Abstract: A chip on film (COF) package in which a predetermined driving integrated circuit (IC) is mounted includes a wiring structure connected to the driving IC, and a test pad connected to the wiring structure, wherein the test pad includes a base film divided into a first region and a second region, and a conductive layer located in the first region, and the second region is surrounded by the first region in a plan view.Type: GrantFiled: July 6, 2022Date of Patent: December 31, 2024Assignee: LX SEMICON CO., LTD.Inventors: Seung Hoon Jin, Young Min Choi
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Patent number: 12182978Abstract: A projector includes a projection section that projects a first image on a projection surface, a control section that causes the projection section to project a pattern image for installation including a first pattern that is located at an end of the first image, which overlaps with a second image, and a second pattern that is so disposed that a first straight line section is located in a position separate from the end by a distance, and a correction section that corrects the first image based on a captured image containing an image of a first area of the second image, and the first area is an area that overlaps with an area having a width corresponding to the distance measured from the end of the first image in a state in which the first image and the second image overlap with each other.Type: GrantFiled: June 8, 2022Date of Patent: December 31, 2024Assignee: SEIKO EPSON CORPORATIONInventors: Yusuke Kudo, Hirohiko Kihara, Hiroto Yomo, Takaaki Akie, Takaaki Ozawa, Shiki Furui
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Patent number: 12181494Abstract: Disclosed are a probe sheet with a multi-layer contact tip and a method of manufacturing the same capable of improving the design freedom of a contact tip formed on a probe sheet of a probe card for testing a semiconductor device to come in contact with a pad of the semiconductor device. According to the present invention, the design freedom of a contact tip formed on a probe sheet of a probe card for testing a semiconductor device to come in contact with a pad of the semiconductor device can be improved, and since the shape of a contact surface of a contact tip is maintained the same and contact resistance is maintained in an allowable range even when a protective layer coated on the contact tip to increase durability of the contact tip is worn, test reliability of the probe card can be improved.Type: GrantFiled: March 27, 2024Date of Patent: December 31, 2024Assignee: PROTEC MEMS TECHNOLOGY INCInventors: Yong Ho Cho, Tae Kyun Kim
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Patent number: 12169358Abstract: A template and a template blank are used for imprint lithography transferring a transfer pattern in a concave and convex structure to a resin on a transfer substrate, in which a first step structure is formed on a main surface of a base, a second step structure is formed on the first step structure, and an outside region of the second step structure on an upper surface of the first step structure is covered with a light shielding film to solve the above problem.Type: GrantFiled: April 18, 2022Date of Patent: December 17, 2024Assignee: DAI NIPPON PRINTING CO., LTD.Inventors: Takaharu Nagai, Katsutoshi Suzuki, Koji Ichimura, Kouji Yoshida
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Patent number: 12169361Abstract: A substrate processing method and apparatus to create a sacrificial masking layer is disclosed. The layer is created by providing a first precursor selected to react with one of a radiation modified and unmodified layer portion and to not react with the other one of the radiation modified and unmodified layer portion on a substrate in a reaction chamber to selectively grow the sacrificial masking layer.Type: GrantFiled: July 16, 2020Date of Patent: December 17, 2024Assignee: ASM IP Holding B.V.Inventors: Ivo Raaijmakers, Daniele Piumi, Ivan Zyulkov, David Kurt de Roest, Michael Eugene Givens
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Patent number: 12165549Abstract: An electronic device includes a rollable panel and a metal layer. The rollable panel includes a first portion and a second portion. The rollable panel has a first side and a second side opposite to the first side. The rollable panel includes a substrate, a circuit layer disposed on the substrate and a cover layer disposed on the circuit layer. The metal layer is disposed on one of the first side and the second side of the rollable panel and outside the rollable panel. In a rolled mode, at least a part of the metal layer is positioned between the first portion and the second portion of the rollable panel.Type: GrantFiled: January 15, 2024Date of Patent: December 10, 2024Assignee: InnoLux CorporationInventors: Yuan-Lin Wu, Tsung-Han Tsai
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Patent number: 12153032Abstract: An interconnected corrugated carbon-based network comprising a plurality of expanded and interconnected carbon layers is disclosed. In one embodiment, each of the expanded and interconnected carbon layers is made up of at least one corrugated carbon sheet that is one atom thick. In another embodiment, each of the expanded and interconnected carbon layers is made up of a plurality of corrugated carbon sheets that are each one atom thick. The interconnected corrugated carbon-based network is characterized by a high surface area with highly tunable electrical conductivity and electrochemical properties.Type: GrantFiled: July 25, 2022Date of Patent: November 26, 2024Assignee: The Regents of the University of CaliforniaInventors: Veronica Strong, Maher F. El-Kady, Richard B. Kaner
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Patent number: 12139628Abstract: The electroconductive inkjet ink disclosed herein contains at least inorganic powder containing high melting point metal particles, a dispersant, an organic solvent, and a poly(vinyl acetal) resin. In the electroconductive ink, the inorganic powder has an average primary particle diameter of 500 nm or less, a volume ratio of the inorganic powder is 7.5% by volume or lower, the ratio (SI/VD) of the specific surface area of the inorganic powder with respect to the volume of the dispersant is 0.25 or higher and 10 or lower, the poly(vinyl acetal) resin has an average molecular weight of 2.5×104 or larger and 6.4×104 or smaller, and the ratio (WPA/WS) of the weight of the poly(vinyl acetal) resin with respect to the weight of the organic solvent is 0.5% by weight or higher and 3% by weight or lower.Type: GrantFiled: February 19, 2020Date of Patent: November 12, 2024Assignee: NORITAKE CO., LIMITEDInventors: Hiromichi Hayashi, Ayumi Murakami
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Patent number: 12135501Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.Type: GrantFiled: August 3, 2023Date of Patent: November 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Hui Weng, Chen-Yu Liu, Chih-Cheng Liu, Yi-Chen Kuo, Jia-Lin Wei, Yen-Yu Chen, Jr-Hung Li, Yahru Cheng, Chi-Ming Yang, Tze-Liang Lee, Ching-Yu Chang
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Patent number: 12130559Abstract: The present application discloses a method for measuring critical dimension. The method for measuring critical dimension includes providing a substrate; forming a resist layer over the substrate; monitoring a volatile byproduct evolved from the resist layer to obtain a first amount of the volatile byproduct; exposing the resist layer to a radiation source; heating the resist layer; monitoring the volatile byproduct evolved from the resist layer to obtain a second amount of the volatile byproduct; and deducting the critical dimension according to a difference between the first amount of the volatile byproduct and the second amount of the volatile byproduct.Type: GrantFiled: January 26, 2022Date of Patent: October 29, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Chia-Chung Lin
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Patent number: 12117733Abstract: The present application discloses a method for measuring critical dimension. The method for measuring critical dimension includes providing a substrate; forming a resist layer over the substrate; monitoring a volatile byproduct evolved from the resist layer to obtain a first amount of the volatile byproduct; exposing the resist layer to a radiation source; heating the resist layer; monitoring the volatile byproduct evolved from the resist layer to obtain a second amount of the volatile byproduct; and deducting the critical dimension according to a difference between the first amount of the volatile byproduct and the second amount of the volatile byproduct.Type: GrantFiled: January 26, 2022Date of Patent: October 15, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Chia-Chung Lin
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Patent number: 12112948Abstract: In a method of manufacturing an integrated circuit device, a photoresist layer is formed by coating a photoresist composition on a substrate having a main surface and an edge portion surrounding the main surface. A portion of the photoresist layer is removed from the edge portion of the substrate. After the portion of the photoresist layer is removed, the substrate is processed using a main treatment composition including an organic solvent, acid, and water.Type: GrantFiled: August 18, 2020Date of Patent: October 8, 2024Assignees: Samsung Electronics Co., Ltd., Inpria Corporation, Tokyo Ohka Kogyo Co., Ltd.Inventors: Chawon Koh, Soyeon Yoo, Sooyoung Choi, Tsunehiro Nishi, Kwangsub Yoon, Brian Cardineau, Kumagai Tomoya
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Patent number: 12103107Abstract: A method of aligning at least one laser beam of an additive manufacturing arrangement. The method includes measuring a surface of the calibration plate at a plurality of measurement points using the coordinate measuring machine. The method further includes generating a correction field based on the plurality of measurement points using the coordinate measuring machine. The method further includes writing at least one fiducial mark on the surface of the calibration plate using the at least one laser beam. The method further includes generating calibration data for the surface of the calibration plate using the calibration system. The method also includes aligning the laser beam within the additive manufacturing system based on the calibration data and the correction field using the computing device by comparing a position of the fiducial mark from the calibration data with the correction field to determine a corrected position of the laser beam.Type: GrantFiled: July 18, 2019Date of Patent: October 1, 2024Assignee: General Electric CompanyInventors: Brian Scott McCarthy, Eric Edward Halla, Thomas Charles Adcock, Michael Evans Graham, Andrea Marie Schmitz, Mark Samuel Bailey