Making Electrical Device Patents (Class 430/311)
  • Patent number: 10663854
    Abstract: A method of fabricating a photomask comprising providing a photomask blank including a phase shifting layer, a first light blocking layer, a first resist layer, a second light blocking layer and a second resist layer stacked sequentially in this order on a substrate, forming second resist patterns, forming second light blocking patterns, forming first resist patterns, forming first light blocking patterns and phase shifting patterns, removing the first resist patterns, and selectively removing at least one of the first light blocking patterns, wherein the second resist layer has a thickness such that all of the second resist layer is removed while the first resist layer is patterned for exposing the second light blocking layer.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: May 26, 2020
    Assignee: SK hynix Inc.
    Inventor: Dong Sik Jang
  • Patent number: 10658521
    Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least a first channel region and a second channel region. The first channel region and the second channel region each include metal gate structures surrounding a different nanosheet channel layer. The metal gate structures of the first and second channel regions are respectively separated from each other by an unfilled gap. The method includes forming a gap fill layer between and in contact with gate structures surrounding nanosheet channel layers in multiple channel regions. Then, after the gap fill layer has been formed for each nanosheet stack, a masking layer is formed over the gate structures and the gap fill layer in at least a first channel region. The gate structures and the gap fill layer in at least a second channel region remain exposed.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Indira Seshadri, Ekmini Anuja De Silva, Jing Guo, Ruqiang Bao, Muthumanickam Sankarapandian, Nelson Felix
  • Patent number: 10636682
    Abstract: In a substrate processing apparatus, the inner peripheral edge of a second-cup canopy part radially opposes an outer peripheral surface of an opposing-member side wall part. This suppresses dispersion of processing liquids to above a cup part. A second-cup gap distance that is a radial distance between the outer peripheral surface of the opposing-member side wall part and the inner peripheral edge of the second-cup canopy part is greater than a holder gap distance that is a radial distance between the inner peripheral surface of the opposing-member side wall part and the outer peripheral surface of the substrate holder. This prevents or suppresses the possibility that, when a second processing liquid dispersed from a substrate is received by a second cup, the second processing liquid may be pushed downward by a downward airflow. Accordingly, a plurality of types of processing liquids will be separately received by a plurality of cups.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: April 28, 2020
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Noriyuki Kikumoto, Masahiro Kimura, Shuichi Yasuda, Kazuhiro Fujita
  • Patent number: 10622339
    Abstract: A micro-LED macro transfer method, a micro-LED display device, and a method for fabricating the same are provided. In the micro-LED macro transfer method, the LED chips on an array are divided into a first plurality of LED chips and a second plurality of LED chips. An LED chip includes a first surface and a second surface. The first plurality of LED chips are configured so that their first surfaces are coupled to the first transfer substrate. The second plurality of LED chips are configured so that their second surfaces are coupled to the second transfer substrate. Accordingly, the first transfer substrate transfers the first plurality of LED chips to the first transfer substrate while the second transfer substrate transfers the second plurality of LED chips to the second transfer substrate.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: April 14, 2020
    Assignee: Xiamen Changelight Co., Ltd.
    Inventors: Zhiwei Lin, Qunxiong Deng, Kaixuan Chen, Zhijie Ke, Xiangjing Zhuo
  • Patent number: 10619019
    Abstract: A film is described comprises a (meth)acrylic polymer and a polyvinyl acetal (e.g. butyral) resin. The film has a tensile elastic modulus of at least 1 MPa at 25° C. and 1 hertz and a glass transition temperature (i.e. Tg) less than 30 C. The film typically comprises photoinitiator as a result of the method by which the film was made. In one embodiment, the film is heat bondable and further comprising a backing.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: April 14, 2020
    Assignee: 3M Innovative Properties Company
    Inventors: Corinne E. Lipscomb, Mary M. Caruso Dailey, Jonathan E. Janoski, Anthony F. Schultz
  • Patent number: 10615042
    Abstract: A method of manufacturing a semiconductor apparatus comprises forming a first photoresist on each of a first portion and a second portion of a member, exposing the first photoresist on the first portion using a first photomask, exposing the first photoresist on the second portion using a second photomask, forming a first resist pattern by developing the first photoresist on the first portion and the second portion, etching the first portion and the second portion using the first resist pattern as a mask, forming a second photoresist on a third portion of the member, exposing the second photoresist on the third portion using a third photomask, forming a second resist pattern by developing the second photoresist on the third portion, and etching the third portion using the second resist pattern as a mask.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: April 7, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Nobuyuki Endo
  • Patent number: 10586695
    Abstract: Method for performing cleaning treatment on a substrate having a fine pattern provided with a film formed on the surface, comprises: a silylating step of supplying a silylating agent to the surface of the substrate and silylating the surface of the substrate; and a liquid-chemical cleaning step of supplying a cleaning liquid chemical to the surface of the substrate and cleaning the surface of the substrate after, or simultaneously with, the silylating step.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: March 10, 2020
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Takashi Ota, Taiki Hinode
  • Patent number: 10564546
    Abstract: A resist pattern-forming method includes applying a photoresist composition directly or indirectly on a front face of a substrate to form a photoresist film. A topcoat layer is laminated directly or indirectly on a front face of the photoresist film. The photoresist film is subjected to liquid immersion lithography in a presence of a liquid immersion liquid on a front face of the topcoat layer. Part of the topcoat layer is removed after subjecting the photoresist film to the liquid immersion lithography. The photoresist film is developed after the part of the topcoat layer is removed.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: February 18, 2020
    Assignee: JSR CORPORATION
    Inventors: Tomohiko Sakurai, Sousuke Oosawa, Hiromitsu Nakashima, Kousuke Terayama
  • Patent number: 10553769
    Abstract: A light transmissive first insulating film having light transmissive property to visible light, a second insulating film arranged opposite to the first insulating film, a plurality of conductor patterns formed of, for example, mesh patterns having the light transmissive property to the visible light and formed on a surface of at least one of the first insulating film and the second insulating film, a plurality of first light-emitting devices connected to any two conductor patterns of the plurality of conductor patterns, and a resin layer arranged between the first insulating film and the second insulating film to hold the first light-emitting devices are included.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: February 4, 2020
    Assignee: Toshiba Hokuto Electronics Corporation
    Inventor: Keiichi Maki
  • Patent number: 10545404
    Abstract: To provide a production method of a pattern-formed body, which can simply provide a pattern with surface free energy differences. A cured resin layer, to which a pattern of a master (20) has been transferred, is formed on a base (11), by applying a resin composition (12) containing a first compound exhibiting low surface free energy, and a second compound exhibiting surface free energy higher than the surface free energy of the first compound, on the base (11), and curing the resin composition (12) with bringing the resin composition into contact with a master (20), to which a pattern has been formed with surface free energy differences.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: January 28, 2020
    Assignee: DEXERIALS CORPORATION
    Inventors: Makiya Ito, Ryosuke Endo, KyungSung Yun, Hirofumi Kondo
  • Patent number: 10527931
    Abstract: A mask blank is provided, by which an alignment mark can be formed between a transparent substrate and a laminated structure of a light semitransmissive film, etching stopper film, and light shielding film during manufacture of a transfer mask.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: January 7, 2020
    Assignee: HOYA CORPORATION
    Inventors: Osamu Nozawa, Ryo Ohkubo, Hiroaki Shishido, Yasushi Okubo
  • Patent number: 10514613
    Abstract: A pattern modification method and a patterning process are provided. The method includes extracting a first pattern and a second pattern to be respectively transferred to a first target portion and a second target portion of a resist layer. The method also includes obtaining regional information of the first target portion and the second target portion. The method includes determining a first desired focus position for transferring the first pattern based on the regional information. In addition, the method includes determining a second desired focus position for transferring the second pattern based on the regional information. The method includes modifying one or both of the first pattern and the second pattern. As a result, focus positions of the first pattern and the second pattern are shifted to be substantially and respectively positioned at the first desired focus position and the second desired focus position during an exposure operation.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Ming Chang, Ru-Gun Liu, Shuo-Yen Chou, Chien-Wen Lai, Zengqin Zhao
  • Patent number: 10514605
    Abstract: The present invention provides a resist multilayer film-attached substrate, including a substrate and a resist multilayer film formed on the substrate, in which the resist multilayer film has an organic resist underlayer film difficultly soluble in ammonia hydrogen peroxide water, an organic film soluble in ammonia hydrogen peroxide water, a silicon-containing resist middle layer film, and a resist upper layer film laminated on the substrate in the stated order. There can be provided a resist multilayer film-attached substrate that enables a silicon residue modified by dry etching to be easily removed in a wet manner with a removing liquid harmless to a semiconductor apparatus substrate and an organic resist underlayer film required in the patterning process, for example, an ammonia aqueous solution containing hydrogen peroxide called SC1, which is commonly used in the semiconductor manufacturing process.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: December 24, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Seiichiro Tachibana, Tsutomu Ogihara, Hiroko Nagai, Romain Lallement, Karen E. Petrillo
  • Patent number: 10495970
    Abstract: The present disclosure describes a method for improving post-photolithography critical dimension (CD) uniformity for features printed on a photoresist. A layer can be formed on one or more printed features and subsequently etched to improve overall CD uniformity across the features. For example the method includes a material layer disposed over a substrate and a photoresist over the material layer. The photoresist is patterned to form a first feature with a first critical dimension (CD) and a second feature with a second CD that is larger than the first CD. Further, a layer is formed with one or more deposition/etch cycles in the second feature to form a modified second CD that is nominally equal to the first CD.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: December 3, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Xi-Zong Chen, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Chih-Hsuan Lin
  • Patent number: 10471537
    Abstract: A direct diode laser processing apparatus includes a laser oscillator that emits a multiple-wavelength laser beam, a transmission fiber that transmits the multiple-wavelength laser beam emitted from the laser oscillator, and a laser processing machine that condenses the multiple-wavelength laser beam transmitted through the transmission fiber and processes a workpiece. According to chromatic aberrations of the multiple-wavelength laser beam and the wavelength dependence of emissivity of the workpiece, a light intensity distribution of the multiple-wavelength laser beam in a thickness direction of the workpiece is provided with a plurality of peaks.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: November 12, 2019
    Assignee: AMADA HOLDINGS CO., LTD.
    Inventor: Kaori Usuda
  • Patent number: 10474034
    Abstract: A phase shift mask includes a substrate, a second phase shift pattern on the substrate, the second phase shift pattern extending to an outermost perimeter of the substrate, the second phase shift pattern being formed of a material that is semi-transmissive to light of a first wavelength and the substrate being substantially transparent to the light of the first wavelength such that the mask transmits about 2 to about 10% of the light of the first wavelength at the second phase shift pattern, and a first phase shift pattern on the substrate, the second phase shift pattern being disposed between the outermost perimeter of the substrate and the first phase shift pattern.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: November 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Il-yong Jang, Hyung-ho Ko, Jin-sang Yoon
  • Patent number: 10468184
    Abstract: In a coil component 1 and a method for manufacturing the same, a winding part of a coil is grown by plating so as to extend between resin walls of a resin body provided before the coil is grown by plating. The resin wall is interposed between adjacent turns of the winding part of the coil during the plating growth, and therefore contact between adjacent turns of the winding part of the coil cannot occur.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: November 5, 2019
    Assignee: TDK CORPORATION
    Inventors: Hitoshi Ohkubo, Masazumi Arata, Manabu Ohta, Shou Kawadahara, Yoshihiro Maeda, Takahiro Kawahara, Hokuto Eda, Shigeki Sato
  • Patent number: 10431457
    Abstract: A method for forming a patterned structure includes following steps. First lines elongated in a first direction and second lines elongated in a second direction in a layout pattern are decomposed into two masks. A first mask includes first line patterns and a first block pattern. A second mask includes second line patterns and a second block pattern. Two photolithography processes with the first mask and the second mask are performed for forming a patterned structure including first line structures and second line structures. Each first line structure is elongated in the first direction. The first line structures are defined by a region where the first line patterns and the second block pattern overlap with one another. Each second line structure is elongated in the second direction. The second line structures are defined by a region where the second line patterns and the first block pattern overlap with one another.
    Type: Grant
    Filed: November 25, 2016
    Date of Patent: October 1, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 10423070
    Abstract: A substrate treating method includes a determining step for determining a treating condition for hydrophobizing a surface of a substrate, based on a target regarding a dissolved area size in a resist pattern, and a treating step for hydrophobizing the surface of the substrate with the treating condition determined in the determining step before forming resist film on the surface of the substrate.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: September 24, 2019
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Masashi Kanaoka, Masanori Imamura, Taiji Matsu, Hidetoshi Sagawa, Atsushi Tanaka, Kazuhiro Tadokoro, Kazuya Ono, Shinichi Takada, Tsuyoshi Mitsuhashi
  • Patent number: 10388721
    Abstract: A capacitor structure is provided that includes conformal layers of a lower electrode, a high-k metal oxide dielectric, and an upper electrode. The capacitor structure is formed by a single process which enables the in-situ conformal deposition of the electrode and dielectric layers of the capacitor structure. The single process includes atomic layer deposition in which a metal-containing precursor is selected to provide each of the layers of the capacitor structure. The lower electrode layer is formed by utilizing the metal-containing precursor and a first reactive gas, the high-k metal oxide dielectric layer is provided by switching the first reactive gas to a second reactive gas, and the upper electrode layer is provided by switching the second reactive gas back to the first reactive gas.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten
  • Patent number: 10359609
    Abstract: A spacer wafer for a wafer-level camera, a wafer-level camera including the spacer wafer and a method of manufacturing a spacer wafer include a layer of photoresist being formed over a substrate, the layer of photoresist being exposed to radiation through a mask that defines a spacer geometry for at least one wafer-level camera element. The layer photoresist is developed, such that the layer of photoresist is the spacer wafer for the wafer-level camera.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: July 23, 2019
    Assignee: OmniVision Technologies, Inc.
    Inventors: George Barnes, Goran Rauker
  • Patent number: 10354950
    Abstract: A magnetic polymer for use in microelectronic fabrication includes a polymer matrix and a plurality of ferromagnetic particles disposed in the polymer matrix. The magnetic polymer can be part of an insulation layer in an inductor formed in one or more backend wiring layers of an integrated device. The magnetic polymer can also be in the form of a magnetic epoxy layer for mounting contacts of the integrated device to a package substrate.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: July 16, 2019
    Assignee: Ferric Inc.
    Inventors: Noah Sturcken, Ryan Davies
  • Patent number: 10340178
    Abstract: A method includes forming a dielectric layer, forming a photo resist over the dielectric layer, forming a first mask layer over the photo resist, and forming a second mask layer over the first mask layer. A first-photo-first-etching is performed to form a first via pattern in the second mask layer, wherein the first-photo-first-etching stops on a top surface of the first mask layer. A second-photo-second-etching is performed to form a second via pattern in the second mask layer, wherein the second-photo-second-etching stops on the top surface of the first mask layer. The first mask layer is etched using the second mask layer as an etching mask. The photo resist and the dielectric layer are etched to simultaneously transfer the first via pattern and the second via pattern into the dielectric layer.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Hau Shiu, Chung-Chi Ko, Tze-Liang Lee, Wen-Kuo Hsieh, Yu-Yun Peng
  • Patent number: 10317791
    Abstract: A photomask blank includes a substrate, a phase shifting layer disposed on the substrate, a first light blocking layer disposed on the phase shifting layer, a first resist layer disposed on the first light blocking layer, a second light blocking layer disposed on the first resist layer, and a second resist layer disposed on the second light blocking layer.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: June 11, 2019
    Assignee: SK hynix Inc.
    Inventor: Dong Sik Jang
  • Patent number: 10312298
    Abstract: Disclosed are an organic light emitting display, which may achieve weight reduction and slimming, and a method of fabricating the same. An encapsulation part of the organic light emitting display includes a plurality of inorganic encapsulation layers and at least one organic encapsulation layer disposed between the inorganic encapsulation layers, and a plurality of touch electrodes disposed on one of the inorganic encapsulation layers and the at least one organic encapsulation layer of the encapsulation part, each touch electrode having electrically independent self capacitance, thereby achieving weight reduction and slimming of the organic light emitting display.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: June 4, 2019
    Assignee: LG Display Co., Ltd.
    Inventor: Jae-Young Oh
  • Patent number: 10296703
    Abstract: The present disclosure relates to a system and method for visualization of fixing of design rule violations in an electronic circuit design. Embodiments may include displaying at a graphical user interface at least a portion of an electronic design having at least one shape associated therewith and identifying one or more electronic design rules associated with the at least one shape. In response to identifying, embodiments may include determining a proposed shape based upon, at least in part, the one or more electronic design rules associated with the at least one shape, wherein the proposed shape is at least one of a trim shape, a bridge shape, and a patch shape and displaying the proposed shape at the graphical user interface.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: May 21, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Pardeep Juneja, Jean-Marc Bourguet, Joyjeet Bose, Sachin Shrivastava, Yashu Gupta, Ankur Chaplot
  • Patent number: 10287455
    Abstract: Disclosed herein is an article comprising a substrate; upon which is disposed a composition comprising: a first block copolymer that comprises a first block and a second block; where the first block has a higher surface energy than the second block; a second block copolymer that comprises a first block and a second block; where the first block of the first block copolymer is chemically the same as or similar to the first block of the second block copolymer and the second block of the first block copolymer is chemically the same as or similar to the second block of the second block copolymer; where the first and the second block copolymer have a chi parameter greater than 0.04 at a temperature of 200° C.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: May 14, 2019
    Assignees: DOW GLOBAL TECHNOLOGIES LLC, ROHM AND HAAS ELECTRONIC MATERIALS LLC
    Inventors: Jieqian Zhang, Phillip D. Hustad, Peter Trefonas, III, Mingqi Li, Valeriy V. Ginzburg, Jeffrey D. Weinhold
  • Patent number: 10274817
    Abstract: A mask includes a transparent substrate, a first pattern, a second pattern, and a sub-resolution auxiliary feature. The first pattern and the second pattern are over the transparent substrate. The first pattern has an area of 0.16 ?m2 to 60000 ?m2. The second pattern has an area of 0.16 ?m2 to 60000 ?m2. The sub-resolution auxiliary feature is over the transparent substrate and connects the first pattern and the second pattern.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Hung Lai, Chih-Chung Huang, Chih-Chiang Tu, Chung-Hung Lin, Chi-Ming Tsai, Ming-Ho Tsai
  • Patent number: 10272663
    Abstract: Thermally cross-linkable photo-hydrolyzable inkjet printable polymers are used to print microfluidic channels layer-by-layer on a substrate. In one embodiment, for each layer, an inkjet head deposits droplets of a mixture of hydrophobic polymer and cross-linking agent in a pattern lying outside a two-dimensional layout of the channels, and another inkjet head deposits droplets of a mixture of poly(tetrahydropyranyl methacrylate) PTHPMA (or another hydrophobic polymer which hydrolyzes to form a hydrophilic material), cross-linking agent, and a photoacid generator (PAG) in a pattern lying inside the two-dimensional layout of the channels. After all layers are printed, flood exposure of the entire substrate to UV radiation releases acid from the PAG which hydrolyzes PTHPMA to form hydrophilic poly(methacrylic acid) PMAA, thereby rendering the PTHPMA regions hydrophilic. The layers of these now-hydrophilic patterned regions together define the microfluidic channels. The cross-linking agent (e.g.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Dylan J. Boday, Joseph Kuczynski, Robert E. Meyer, III
  • Patent number: 10273314
    Abstract: SET-LRP polymerization of acrylic monomers under acidic conditions is described. The source of the acidity may be the solvent (e.g., an acetic acid-containing solvent) or in the monomer content (e.g., acrylic acid or methacrylic acid, optionally in combination with other monomers such as methyl methacrylate).
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: April 30, 2019
    Assignees: ROHM AND HAAS COMPANY, THE TRUSTEES OF THE UNIVERSITY OF PENNSYLVANIA
    Inventors: Antony K. Van Dyk, Susan J. Fitzwater, Sven Fleischmann, Virgil Percec
  • Patent number: 10269623
    Abstract: Image tone-reversal with a dielectric using bottom-up cross-linking for back end of line (BEOL) interconnects is described. In an example, a semiconductor structure including a metallization layer includes a plurality of trenches in an interlayer dielectric (ILD) layer above a substrate. A pre-catalyst layer is on sidewalls of one or more, but not all, of the plurality of trenches. Cross-linked portions of a dielectric material are proximate the pre-catalyst layer, in the one or more of the plurality of trenches. Conductive structures are in remaining ones of the trenches.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: Robert L. Bristol, James M. Blackwell, Rami Hourani
  • Patent number: 10269645
    Abstract: Fin field-effect transistors (FinFETs) and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate having a plurality of fins; forming gate structures over the base substrate; forming a photoresist film having a plurality of exposure regions and non-exposure regions over the base substrate, the fins and the gate structures, wherein the exposure regions have first regions above the top surfaces of the gate structures and second regions below the top surfaces of the gate structures; performing an exposure process to the photoresist film; performing a post-baking process to cause photoacid in the second regions of the exposure regions to diffuse into portions of the photoresist film below the top surfaces of the gate structures in the non-exposure regions; developing exposed photoresist film to form photoresist layers; and performing a function doping process to the fins using the photoresist layers as a mask.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: April 23, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Xu Dong Yi
  • Patent number: 10263206
    Abstract: An organic semiconductor crystalline film and weak oriented epitaxy growth preparation method thereof. The organic semiconductor crystalline film is a n-type semiconductor or a p-type semiconductor, and organic semiconductor crystal molecules in the organic semiconductor crystalline film are oriented in a stand-up manner on the ordered substrate, and have an oriented relationship with the ordered substrate. The organic semiconductor crystalline film prepared by the present invention is useful for organic transistor and organic phototransistor devices. The method of the present invention can control the high carrier mobility direction of organic semiconductor crystals to have ordered orientation in the film, enhance contacts between crystals, improve mechanical strength and micro-machining property of the film, and give a high carrier mobility. The carrier mobility of weak oriented epitaxially grown film of the present invention is 0.
    Type: Grant
    Filed: April 21, 2007
    Date of Patent: April 16, 2019
    Assignee: Changchun Institute of Applied Chemistry Chinese Academy of Sciences
    Inventors: Donghang Yan, Haibo Wang, Feng Zhu, Jianwu Shi, De Song
  • Patent number: 10261421
    Abstract: An exposure method for exposing a mask pattern, which includes plural types of patterns, with a high throughput and optimal illumination conditions for each type of pattern. The method includes guiding light from a first spatial light modulator illuminated with pulse lights of illumination light to a second spatial light modulator and exposing a wafer with light from the second spatial light modulator, accompanied by: controlling a conversion state of the second spatial light modulator including a plurality of second mirror elements; and controlling a conversion state of the first spatial light modulator including a plurality of first mirror elements to control intensity distribution of the illumination light on a predetermined plane between the first spatial light modulator and the second spatial light modulator.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: April 16, 2019
    Assignee: Nikon Corporation
    Inventor: Soichi Owa
  • Patent number: 10240250
    Abstract: A graphoepitaxy template to align a self-assembled block polymer adapted to self-assemble into a 2-D array having parallel rows of discontinuous first domains extending parallel to a first axis, mutually spaced along an orthogonal second axis, and separated by a continuous second domain. The graphoepitaxy template has first and second substantially parallel side walls extending parallel to and defining the first axis and mutually spaced along the second axis to provide a compartment to hold at least one row of discontinuous first domains of the self-assembled block copolymer on the substrate between and parallel to the side walls, and separated therefrom by a continuous second domain. The compartment has a graphoepitaxial nucleation feature arranged to locate at least one of the discontinuous first domains at a specific position within the compartment. Methods for forming the graphoepitaxy template and its use for device lithography are also disclosed.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: March 26, 2019
    Assignee: ASML Netherlands B.V.
    Inventors: Thanh Trung Nguyen, Jozef Maria Finders, Wilhelmus Sebastianus Marcus Maria Ketelaars, Sander Frederik Wuister, Eddy Cornelis Antonius Van der Heijden, Hieronymus Johannus Christiaan Meessen, Roelof Koole, Emiel Peeters, Christianus Martinus Van Heesch, Aurelie Marie Andree Brizard, Henri Marie Joseph Boots, Tamara Druzhinina, Jessica Margaretha De Ruiter
  • Patent number: 10227463
    Abstract: Biodegradable, cross-linked polymer films and methods of making the same are described. The polymer films can be used for preventing adhesions following surgery and/or delivering therapeutic agents.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: March 12, 2019
    Assignee: MicroVention, Inc.
    Inventors: Gregory M. Cruise, Gloria Hincapie, Clayton Harris, Yue Wu
  • Patent number: 10211061
    Abstract: A method for manufacturing a semiconductor structure includes forming a target layer, a lower hard mask layer, a middle hard mask layer, and an upper hard mask layer in sequence on a substrate. A first mask layer is then formed on the upper hard mask layer. A first patterned upper hard mask layer having at least one recess and at least one remained portion under the recess is formed, wherein the remained portion remains a thickness that is less than a depth of the recess. A patterned organic layer is then formed on the recess. A second patterned upper hard mask layer is form by etching the first patterned upper hard mask layer. A patterned target layer is then formed by etching the middle hard mask layer, the lower hard mask layer, and the target layer by using the second patterned upper hard mask layer as a mask.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: February 19, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • Patent number: 10199500
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: February 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Jen Chang, Chih-Chien Chi, Chen-Yuan Kao, Hung-Wen Su, Kai-Shiang Kuo, Po-Cheng Shih, Jun-Yi Ruan
  • Patent number: 10191390
    Abstract: A method including: providing a reference substrate with a first mark pattern; providing the reference substrate with a first resist layer on the reference substrate, wherein the first resist layer has a minimal radiation dose needed for development of the first resist; using a reference patterning device to impart a radiation beam with a second mark pattern in its cross-section to form a patterned radiation beam; and exposing a target portion of the first resist layer of the reference substrate n times to said patterned radiation beam to create exposed areas in the target portion of the first resist layer in accordance with the second mark pattern that have been subjected to an accumulated radiation dose above the minimal radiation dose of the first resist layer, wherein n is an integer with a value of at least two.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: January 29, 2019
    Assignee: ASML Netherlands B.V.
    Inventors: Paul Cornelis Hubertus Aben, Sanjaysingh Lalbahadoersing, Jurgen Johannes Henderikus Maria Schoonus, David Frans Simon Deckers
  • Patent number: 10151973
    Abstract: An imprint lithography method includes disposing a mask layer on a base substrate in first and in second areas, reducing a thickness of the mask layer in the first area, disposing a first planarization layer on the mask layer in the first and second areas, forming a first imprint pattern on the first planarization layer, forming a first planarization layer pattern by etching the first planarization layer using the first imprint pattern, forming a first mask pattern in the first area by etching the mask layer using the first planarization layer pattern, diposing a second planarization layer on the first mask pattern and the mask layer in the first and second areas, forming a second imprint pattern on the second planarization layer, forming a second planarization layer pattern by etching the planarization layer using the second imprint pattern, and forming a second mask pattern in the second area.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: December 11, 2018
    Assignee: Samsung Display Co., Ltd
    Inventors: Yun-Jong Yeo, Jung-Ha Son, Joo-Hyung Lee, Dae-Young Lee
  • Patent number: 10147607
    Abstract: A semiconductor pitch patterning can include a method comprising directionally forming a mask material on a first set of spacers. The first set of spacers can be formed on a substrate. The method can include directionally forming a mask material on a surface of the substrate. The method can include selectively forming a second set of spacers on side surfaces of the first set of spacers and a portion of the surface of the substrate. The top portion of each of the second set of spacers remains unetched subsequent to removing portions of the mask material from the top portions of the first set of spacers.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: December 4, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Patent number: 10108030
    Abstract: A display device includes a window layer, a first display panel, and a second display panel. The window layer has at least one bent area adjacent a non-bent area. The first display panel is on a first side of the window layer at a position corresponding to the at least one bent area. The second display panel is on the first side of the window layer at a position corresponding to the non-bent area. The first display panel is in a first display area to display an image, and a first non-display area is adjacent the non-bent area and between the first display area and the non-bent area.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: October 23, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Hae-Kwan Seo
  • Patent number: 10085346
    Abstract: Provided is a method for producing a conductive member including: forming a first silver halide emulsion layer, a light absorption layer, and a second silver halide emulsion layer on a transparent support in this order; performing pattern exposure on the first silver halide emulsion layer; and the second silver halide emulsion layer and applying a development treatment thereto to obtain a conductive layer comprising a thin metal wire, in which the light absorption layer absorbs at least some of the wavelengths of light to which the first silver halide emulsion layer or the second silver halide emulsion layer is exposed.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: September 25, 2018
    Assignee: FUJIFILM Corporation
    Inventors: Kenichi Yamamoto, Naoharu Kiyoto, Kenji Naoi
  • Patent number: 10073344
    Abstract: Provided is a negative resist pattern-forming method that enables a resist pattern with fewer development defects to be formed while favorable water repellency of the surface of the upper layer film is maintained. A negative resist pattern-forming method includes the steps of: forming a resist film using a radiation-sensitive resin composition; forming an upper layer film on one face of the resist film using a composition for upper layer film formation; subjecting the resist film having the upper layer film formed thereon to liquid immersion lithography; and developing the resist film subjected to the liquid immersion lithography with a developer solution containing an organic solvent, wherein at least one of the radiation-sensitive resin composition and the composition for upper layer film formation contains a fluorine atom.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: September 11, 2018
    Assignee: JSR CORPORATION
    Inventors: Taiichi Furukawa, Sosuke Osawa
  • Patent number: 10062584
    Abstract: A method for forming a semiconductor structure is disclosed. The method includes the following steps. A first pattern structure and a second pattern structure are formed on a substrate. The second pattern structure is wider than the first pattern structure. Spacers are formed on sidewall surfaces of the first pattern structure and the second pattern structure. An oxidizing treatment step is performed to the spacers having a width gradually increased from tops of the spacers. A pattern defined with the spacers is transferred into the substrate after the oxidizing treatment step.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: August 28, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuan-Lin Chen, An-Chi Liu, Kun-Yuan Liao, Cheng-Pu Chiu
  • Patent number: 10050193
    Abstract: In one aspect, a magnetoresistance structure includes a magnetoresistance stack that includes a plurality of layers that includes a first set of one or more magnetoresistance layers and a second set of one or more magnetoresistance layers. The magnetoresistance structure also includes side walls attached to the sides of the first set of one or more magnetoresistance layers and disposed on the second set of one or more magnetoresistance layers.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: August 14, 2018
    Assignee: Allegro MicroSystems, LLC
    Inventors: Maxim Klebanov, Paolo Campiglio, Yu-Ming Wang
  • Patent number: 10049903
    Abstract: Methods of manufacturing a heater are provided that generally include forming a laminate having a dielectric layer, a first double-sided adhesive dielectric layer, and a conductive layer. Next, a circuit pattern is created into the conductive layer, and then the circuit pattern is covered with a second double-sided adhesive dielectric layer. The second double-sided adhesive dielectric layer is covered with a sacrificial layer, and then the heater is formed, the heater comprising the dielectric layer, the first double-sided adhesive dielectric layer, the conductive layer, and the second double-sided adhesive dielectric layer. Subsequently, the sacrificial layer is removed.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: August 14, 2018
    Assignee: Watlow Electric Manufacturing Company
    Inventors: Kevin Ptasienski, Allen Norman Boldt, Janet Lea Smith, Cal Thomas Swanson, Mohammad Nosrati, Kevin Robert Smith
  • Patent number: 10034384
    Abstract: A method for manufacturing a structure containing a conductor circuit according to the present invention can provide openings in various shapes by patterning a first photosensitive resin layer in a first patterning process according to shapes of openings formed in a heat-curable resin layer. Further, in the method for manufacturing a structure containing a conductor circuit, a plurality of openings can be formed at the same time and a residue of the resin around the opening can be reduced, unlike a case in which openings are formed with a laser. Therefore, it is possible to sufficiently efficiently manufacture the structure having excellent reliability even when the number of pins of a semiconductor element increases and it is necessary to provide a great number of fine openings.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: July 24, 2018
    Assignee: HITACHI CHEMICAL COMPANY, LTD.
    Inventors: Kazuhiko Kurafuchi, Daisuke Fujimoto, Kunpei Yamada, Toshimasa Nagoshi
  • Patent number: 10025197
    Abstract: A method forms a pattern of metallic nanofeatures that generates by plasmonic resonance a desired image having a distribution of colors. The method includes providing a substrate having a layer of photosensitive material, exposing the layer to a high-resolution periodic pattern of dose distribution, and determining a low-resolution pattern of dose distribution such that the sum of the low-resolution pattern and the high-resolution periodic pattern of dose distribution is suitable for forming the pattern of metallic nanofeatures. The lateral dimensions of the metallic nano-features have a spatial variation across the pattern that corresponds to the distribution of colors in the desired image. The layer of photosensitive material is exposed to the low-resolution pattern of dose distribution. The layer of photosensitive material is developed to produce a pattern of nanostructures in the developed photosensitive material.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: July 17, 2018
    Assignee: Eulitha A.G.
    Inventors: Harun H. Solak, Christian Dais, Francis Clube
  • Patent number: 10026801
    Abstract: A semiconductor device includes an inductor disposed on a surface of an intermetallic dielectric layer at a location below which no virtual interconnect members are present. Thus, parasitic capacitance is reduced or eliminated and the Q value of the inductor is high.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: July 17, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, NINGBO SEMICONDUCTOR INTERNATIONAL CORPORATION
    Inventors: Herb He Huang, Hongtao Ge, Haiting Li