Making Electrical Device Patents (Class 430/311)
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Patent number: 11835853Abstract: A mask blank glass substrate having a maximum value of a circularly averaged power spectral density of 1,000 nm4 or less at a spatial frequency of 0.1 ?m?1 or more and 20 ?m?1 or less, the maximum value being obtained by measuring a surface morphology of a region of 10 ?m×10 ?m with an atomic force microscope.Type: GrantFiled: May 28, 2021Date of Patent: December 5, 2023Assignee: SHIN-ETSU CHEMICAL CO., LTD.Inventors: Naoki Yarita, Daijitsu Harada, Masaki Takeuchi
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Patent number: 11830807Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for placing self-aligned top vias at line ends of an interconnect structure. In a non-limiting embodiment of the invention, a line feature is formed in a metallization layer of an interconnect structure. The line feature can include a line hard mask. A trench is formed in the line feature to expose line ends of the line feature. The trench is filled with a host material and a growth inhibitor is formed over a first line end of the line feature. A via mask is formed over a second line end of the line feature. The via mask can be selectively grown on an exposed surface of the host material. Portions of the line feature that are not covered by the via mask are recessed to define a self-aligned top via at the second line end.Type: GrantFiled: October 12, 2021Date of Patent: November 28, 2023Assignee: International Business Machines CorporationInventors: Ashim Dutta, Ekmini Anuja De Silva, Dominik Metzler, John Arnold
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Patent number: 11822239Abstract: A resist composition comprising a base polymer and a quencher in the form of a heterocyclic amine compound having a tertiary ester structure offers a high sensitivity and minimal LWR or improved CDU, independent of whether it is of positive or negative tone.Type: GrantFiled: February 26, 2020Date of Patent: November 21, 2023Assignee: SHIN-ETSU CHEMICAL CO., LTD.Inventors: Jun Hatakeyama, Masaki Ohashi, Takayuki Fujiwara
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Patent number: 11825698Abstract: A display substrate is described that comprises: a display area, a retaining wall surrounding the display area, and a thin film encapsulation layer comprising a first inorganic barrier layer, an organic barrier layer, and a second inorganic barrier layer. The display area has a corner portion being a portion of the display area surrounded by the retaining wall. Convex dams are provided at a position on the substrate corresponding to the corner portion. A portion of the first inorganic barrier layer corresponding to the corner portion covers the convex dams, and a portion of the first inorganic barrier layer between the two adjacent convex dams forms a diversion trench. The organic barrier layer comprises cured organic material, and the organic material is provided on the portion of the first inorganic barrier layer at the corner portion under a capillary action of the diversion trench before curing.Type: GrantFiled: April 27, 2020Date of Patent: November 21, 2023Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Yangyang Zhang, Jing Li, Dawei Wang
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Patent number: 11822237Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.Type: GrantFiled: October 15, 2020Date of Patent: November 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Hui Weng, Chen-Yu Liu, Chih-Cheng Liu, Yi-Chen Kuo, Jia-Lin Wei, Yen-Yu Chen, Jr-Hung Li, Yahru Cheng, Chi-Ming Yang, Tze-Liang Lee, Ching-Yu Chang
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Patent number: 11822261Abstract: A wafer edge exposure apparatus includes a wafer carrying module, a reticle, a reticle driving module, an alignment module, an exposure module, and a control module; the wafer carrying module is configured to carry the wafer and drive the wafer to rotate; the wafer includes a valid region and an edge region surrounding the valid region; the reticle driving module is configured to drive the reticle to rotate; the alignment unit is configured to detect the alignment state of the reticle with the wafer; and the control module is configured to control the movement state of the wafer carrying module and the reticle driving module and configured to control the exposure module to perform wafer edge exposure on the wafer.Type: GrantFiled: April 30, 2021Date of Patent: November 21, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Xueyu Liang
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Patent number: 11825570Abstract: An embodiment of the disclosure provides a heater package including a substrate, a first barrier layer, at least one heater, and a second barrier layer. The first barrier layer is disposed on a surface of the substrate and has a first treatment layer on a side away from the substrate. The heater is disposed on the substrate and includes a heating layer and at least one electrode. The at least one electrode and the heating layer contact with each other. The second barrier layer covers an upper surface and a sidewall of the heater and has a second treatment layer on an opposite side or the side away from the substrate. A ratio of a thickness of the first treatment layer to a thickness of the first barrier layer and a ratio of a thickness of the second treatment layer to a thickness of the second barrier layer range from 0.03 to 0.2.Type: GrantFiled: November 15, 2019Date of Patent: November 21, 2023Assignee: Industrial Technology Research InstituteInventors: Yen-Ching Kuo, Chien-Chang Hung, Hong-Ming Dai, Jane-Hway Liao, Hung-Yi Chen, Shu-Tang Yeh
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Patent number: 11823903Abstract: According to an embodiment, a wafer (W) includes a layer (EL) to be etched, an organic film (OL), an antireflection film (AL), and a mask (MK1), and a method (MT) according to an embodiment includes a step of performing an etching process on the antireflection film (AL) by using the mask (MK1) with plasma generated in a processing container (12), in the processing container (12) of a plasma processing apparatus (10) in which the wafer (W) is accommodated, and the step includes steps ST3a to ST4 of conformally forming a protective film (SX) on the surface of the mask (MK1), and steps ST6a to ST7 of etching the antireflection film (AL) by removing the antireflection film (AL) for each atomic layer by using the mask (MK1) on which the protective film (SX) is formed.Type: GrantFiled: December 22, 2021Date of Patent: November 21, 2023Assignee: Tokyo Electron LimitedInventors: Yoshihide Kihara, Toru Hisamatsu, Tomoyuki Oishi
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Patent number: 11806743Abstract: A spin dispenser module and methods for using the same is disclosed. The spin dispenser module includes a cup having a basin with sidewalls and an exhaust, a rotatable platform situated inside the cup adapted for holding and rotating a substrate, a liquid dispenser disposed over the rotatable platform for dispensing a liquid coating material on top of the substrate, one or more ejector inlets disposed over the rotatable platform, the one or more ejectors connected to a negative pressure source, and a motor coupled to the rotatable platform to rate the rotatable platform at different rotational speeds. The one or more ejector inlets may be translatable and/or rotatable with optionally adjustable suction pressure. The ejector inlets operate after a liquid coating material is dispensed to avoid deposition of suspended organic compounds after a coating is formed.Type: GrantFiled: May 27, 2022Date of Patent: November 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Ching-Hai Yang, Yao-Hwan Kao, Shang-Sheng Li, Kuo-Pin Chen, Hsiang-Kai Tseng, Chuan-Wei Chen
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Patent number: 11809797Abstract: Predictive multi-planar semiconductor manufacturing systems and methods are provided including a processor, an artificial intelligence unit in communication with the processor, and a computer readable memory with processing instructions in communication with the processor. The manufacturing system receives and analyzes semiconductor design and manufacturing process rules and data and dimensions for a user's desired semiconductor. The artificial intelligence unit is configured to run simulations trying multiple three-dimensional, multi-planar shapes and analyzing for highest surface area yield based on the design and manufacturing process rules and data and the dimensions. The artificial intelligence unit is further configured to determine a three-dimensional, multi-planar shape for the desired semiconductor to optimize surface area based on the simulations and to construct the three-dimensional, multi-planar shape that optimizes surface area.Type: GrantFiled: January 18, 2023Date of Patent: November 7, 2023Assignee: GBT Technologies Inc.Inventors: Danny Rittman, Mo Jacob
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Patent number: 11796920Abstract: A method and associated apparatuses for controlling a process of manufacturing semiconductor devices on a substrate. The method includes obtaining process data relating to the process and determining a correction for the process based on the process data and a first control objective associated with the devices on the substrate. A first probability of the first control objective being achievable is determined and the correction adjusted based on the probability and at least a second control objective having a second probability of being achievable compared to the first control objective.Type: GrantFiled: January 14, 2021Date of Patent: October 24, 2023Assignee: ASML NETHERLANDS B.V.Inventors: Jochem Sebastiaan Wildenberg, Hermanus Adrianus Dillen, Fan Feng, Ronald Van Ittersum, Willem Louis Van Mierlo, Koen Thuijs
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Patent number: 11784455Abstract: A die layout calculation method is provided. The method includes: selecting, based on a distribution array of a plurality of dies in a wafer, one die as a reference die; making first movements of a wafer center to determine a first coverage region for each first movement, and determining a feasible region based on a number of complete dies in each first coverage region; making a plurality of second movements of the wafer center in the feasible region to determine a second coverage region for each second movement, and determining a relative position of the wafer center in the reference die corresponding to a maximum number of complete dies in the second coverage region; and determining a die layout comprising a location of each die in the wafer. This method improves the accuracy and efficiency of determining the maximum number of dies.Type: GrantFiled: August 12, 2021Date of Patent: October 10, 2023Assignee: Changxin Memory Technologies, Inc.Inventors: Li-ming Hsiao, Chen Chen
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Patent number: 11769686Abstract: A single-substrate electroless (EL) plating apparatus including a workpiece chuck that is rotatable about rotation axis and inclinable about an axis of inclination. The chuck inclination may be controlled to a non-zero inclination angle during a dispense of plating solution to improve uniformity in the surface wetting and/or plating solution residence time across the a surface of a workpiece supported by the chuck. The angle of inclination may be only a few degrees off-level with the plating solution dispensed from a nozzle that scans over a high-side of the chuck along a radius of the workpiece while the chuck rotates. The angle of inclination may be actively controlled during dispense of the plating solution. The inclination angle may be larger at commencement of the plating solution dispense than at cessation of the dispense.Type: GrantFiled: September 29, 2016Date of Patent: September 26, 2023Assignee: Intel CorporationInventors: Harinath Reddy, Harsono S. Simka, Christopher D. Thomas
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Patent number: 11754926Abstract: A method of forming a resist pattern, including forming a resist composition using a resist film; exposing the resist film; and alkali-developing the exposed resist film to form a positive-tone resist pattern, wherein the resist composition includes a first resin component and a second resin component which satisfies a specific relationship DRMIX<DRP1 and DRMIX<DRP2, wherein DRP1 is the dissolution rate of the first resin component (P1) in an alkali developing solution, DRP2 is the dissolution rate of the second resin component (P2) in an alkali developing solution, and DRMIX is the dissolution rate of a mixed resin of the first resin component (P1) and the second resin component (P2).Type: GrantFiled: November 8, 2019Date of Patent: September 12, 2023Assignee: Tokyo Ohka Kogyo Co., Ltd.Inventor: Eiichi Shimura
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Patent number: 11745216Abstract: A method for producing a film includes: coating a surface of a substrate with a composition containing a polymer having a structural unit represented by formula (1) and having a number average molecular weight of 13000 or more and a solvent, heating a coating film formed by the coating, and removing, with a rinsing liquid, a part of the coating film after the heating, wherein the rinsing liquid to be used contains a basic compound. In the formula (1), Y1 is a single bond, —CO—NR2—, a divalent aromatic ring group, a divalent group containing —O—, or a divalent group containing —CO—NR2—. A1 is a single bond, —O—, —S—, or —NR3—. R1 is a hydrogen atom, a monovalent hydrocarbon group, a monovalent halogenated hydrocarbon group, or a monovalent group having a heterocyclic structure.Type: GrantFiled: June 23, 2022Date of Patent: September 5, 2023Assignee: JSR CORPORATIONInventors: Ryo Kumegawa, Sosuke Osawa, Miki Tamada, Ken Maruyama, Motohiro Shiratani
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Patent number: 11749539Abstract: Systems and methods for selectively etching features in an electronic substrate via a precision dispense apparatus and precision etchant dispense tool are disclosed. The method includes creating a toolpath instruction for etching at least one feature in the substrate, programming the precision dispense apparatus to execute the created toolpath instruction, and causing the precision dispense tool to deposit etchant material onto the surface of the substrate to etch the substrate surface to produce the at least one feature according to the created toolpath instruction. The capabilities of the systems and methods disclosed herein extend to 3D substrates and post-build processing, among others.Type: GrantFiled: August 26, 2020Date of Patent: September 5, 2023Assignee: Rockwell Collins, Inc.Inventors: Richard Korneisel, Nathaniel P. Wyckoff, Brandon C. Hamilton, Kyle B. Snyder, Jenny Calubayan
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Patent number: 11747737Abstract: An exposure apparatus includes an illumination optical system for illuminating an original including a periodic pattern, a projection optical system for forming an image of the original on a substrate, a controller configured to cause light from the illumination optical system to be obliquely incident on the original such that a light intensity distribution which is line-symmetric with respect to a line, passing through an origin of a pupil region of the projection optical system and orthogonal to a periodic direction of the periodic pattern, is formed in the pupil region by diffracted light beams including diffracted light of not lower than 2nd-order from the periodic pattern, and to control exposure of the substrate such that each point in a shot region of the substrate is exposed in not less than two focus states.Type: GrantFiled: August 31, 2021Date of Patent: September 5, 2023Assignee: CANON KABUSHIKI KAISHAInventor: Kazuhiro Takahashi
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Patent number: 11744023Abstract: A method for manufacturing a dual conductor laminated substrate includes providing a first laminate including a first insulating layer and a first conductive layer; defining a first trace pattern including one or more traces in the first laminate; providing a second laminate including a second insulating layer and a second conductive layer; defining a second trace pattern including one or more traces in the second laminate; defining access holes in the second insulating layer; at least one of depositing and stenciling a conductive material in the access holes of the second insulating layer; and aligning and attaching the first laminate to the second laminate to create a laminated substrate.Type: GrantFiled: January 15, 2021Date of Patent: August 29, 2023Assignee: Gentherm GmbHInventor: Timothy Hughes
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Patent number: 11742179Abstract: According to one embodiment, a proximity effect correcting method includes acquiring drawing information for drawing a pattern on a substrate with irradiation of an electron beam. The method further includes acquiring surface profile information related to a surface profile of the substrate. The method further includes calculating an energy distribution of a backscattered beam to be produced by backscattering of the electron beam in the substrate on a basis of the acquired drawing information and surface profile information. The method further includes calculating a required energy amount of the electron beam on a basis of the calculated energy distribution.Type: GrantFiled: September 14, 2021Date of Patent: August 29, 2023Assignee: Kioxia CorporationInventors: Yoshinori Kagawa, Shunko Magoshi
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Patent number: 11733604Abstract: A method of fabricating a semiconductor device is disclosed. The method includes performing an optical proximity correction (OPC) on design patterns of a layout to generate a corrected layout, and forming a photoresist pattern on a substrate using a photomask manufactured based on the corrected layout. The OPC comprises generating develop targets for the design patterns, respectively, choosing first object patterns based on distances between the develop targets, performing a first OPC operation on the design patterns based on a mask rule to generate first correction patterns, choosing second object patterns by considering distances between the first correction patterns and a target error of each of the first correction patterns, and performing a second OPC operation on the first and second object patterns to generate second correction patterns, the performing the second OPC not based on the mask rule.Type: GrantFiled: April 21, 2021Date of Patent: August 22, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Gyeong Seop Kim, Noyoung Chung
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Patent number: 11721553Abstract: A method for forming a semiconductor device includes providing a to-be-etched layer, forming a first mask layer on the to-be-etched layer, forming a patterned core layer on the first mask layer of a first region, forming a sidewall spacer material layer on the core layer and the first mask layer, removing the sidewall spacer material layer on a top surface of the core layer, removing the core layer and the first mask layer at a bottom of the core layer to form a first trench, removing the sidewall spacer material layer on the first mask layer of a second region, forming a first patterned layer exposing the first mask layer of the second region, and using the first patterned layer as a mask to remove the first mask layer of the second region to form a second trench.Type: GrantFiled: March 2, 2021Date of Patent: August 8, 2023Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Jisong Jin
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Patent number: 11721543Abstract: This disclosure describes a process of generating a planarizing polyimide based dielectric film on a substrate with conducting metal pattern, wherein the process comprised steps of: (a) providing a dielectric film forming composition comprising at least one fully imidized polyimide polymer and at least one solvent; and (b) depositing the dielectric film forming composition onto a substrate with conducting metal pattern to form a dielectric film, wherein the difference in the highest and lowest points on a top surface of the dielectric film is less than about 2 microns.Type: GrantFiled: October 1, 2020Date of Patent: August 8, 2023Assignee: Fujifilm Electronic Materials U.S.A., Inc.Inventors: Raj Sakamuri, Ognian Dimov, Sanjay Malik, Michaela Connell, Ahmad A. Naiini, Stephanie Dilocker
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Patent number: 11720022Abstract: Provided is a resist compound, a method for forming a pattern using the same, and a method for manufacturing a semiconductor device. According to the present disclosure, the compound may be represented by Formula 1.Type: GrantFiled: February 12, 2020Date of Patent: August 8, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jin-Kyun Lee, Hyun-Taek Oh, Seok-Heon Jung, Jeong-Seok Mun
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Patent number: 11713243Abstract: In one example, a method comprises forming a first layer on a substrate surface, forming an opening in the first layer, forming a second layer on the first layer and in the opening, and forming a photoresist layer on the second layer, in which the photoresist layer has a first curved surface over a first part of the first layer and over the opening. The method further comprises etching the photoresist layer and a second part of the second layer over the first part of the first layer to form a second curved surface on the second part of the second layer, and forming a mirror element and a support structure in the second layer, including by etching a third part of the second layer and removing the first layer.Type: GrantFiled: August 30, 2022Date of Patent: August 1, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Patrick Ian Oden, James Norman Hall
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Patent number: 11711963Abstract: The present invention provides a mask, a display panel, a method for manufacturing a display panel, and a display device. The display panel has a hollow region and a display region surrounding the hollow region. The display panel includes a plurality of organic light-emitting devices arranged only in the display region. Each of the plurality of organic light-emitting devices includes an anode layer, a cathode layer, a light-emitting layer and a functional layer. The functional layer includes a plurality of uneven portions.Type: GrantFiled: December 31, 2020Date of Patent: July 25, 2023Assignees: WUHAN TIANMA MICROELECTRONICS CO., LTD., WUHAN TIANMA MICROELECTRONICS CO., LTD. SHANGHAI BRANCHInventors: Liyuan Liu, Zhiyong Xiong, Di Zhu, Yawei Zhong
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Patent number: 11707815Abstract: A method for creating a three-dimensional (3D) mark in a protective coating including at least one of a TBC and a bond coating over a metal part, is provided. The method may include positioning a mask over the protective coating, the mask including an opening pattern therein; and performing an abrasive waterjet process on the protective coating using the mask. The abrasive waterjet erodes a first portion of the protective coating exposed through the first opening pattern to create the 3D mark. The mask is removed, leaving the 3D mark in the protective coating. The 3D mark only partially penetrates through the protective coating. A metal part may include a metal body, a protective coating over the metal body, and the 3D mark in the protective coating, is also provided. The 3D mark in the protective coating may include an opening having a width of between 30 and 300 micrometers.Type: GrantFiled: July 9, 2019Date of Patent: July 25, 2023Assignee: General Electric CompanyInventors: Roland Richard Moser, Sophie Betty Claire Duval
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Patent number: 11705332Abstract: A method of forming a pattern in a photoresist layer includes forming a photoresist layer over a substrate, and reducing moisture or oxygen absorption characteristics of the photoresist layer. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.Type: GrantFiled: January 15, 2021Date of Patent: July 18, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Chen Kuo, Chih-Cheng Liu, Ming-Hui Weng, Jia-Lin Wei, Yen-Yu Chen, Jr-Hung Li, Yahru Cheng, Chi-Ming Yang, Tze-Liang Lee, Ching-Yu Chang
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Patent number: 11694902Abstract: Aspects generally relate to methods, systems, and apparatus for processing substrates using one or more amorphous carbon hardmask layers. In one aspect, film stress is altered while facilitating enhanced etch selectivity. In one implementation, a method of processing a substrate includes depositing one or more amorphous carbon hardmask layers onto the substrate, and conducting a rapid thermal anneal operation on the substrate after depositing the one or more amorphous carbon hardmask layers. The rapid thermal anneal operation lasts for an anneal time that is 60 seconds or less. The rapid thermal anneal operation includes heating the substrate to an anneal temperature that is within a range of 600 degrees Celsius to 1,000 degrees Celsius. The method includes etching the substrate after conducting the rapid thermal anneal operation.Type: GrantFiled: February 18, 2021Date of Patent: July 4, 2023Assignee: Applied Materials, Inc.Inventors: Krishna Nittala, Sarah Michelle Bobek, Kwangduk Douglas Lee, Ratsamee Limdulpaiboon, Dimitri Kioussis, Karthik Janakiraman
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Patent number: 11693316Abstract: A resist composition including a resin component having a constitutional unit derived from a compound represented by General Formula (a01-1) and a constitutional unit derived from a compound represented by General Formula (a02-1), and an acid generator component composed of an anion moiety and a cation moiety. In General Formula (a01-1), W1 represents a polymerizable group-containing group, Ct represents a tertiary carbon atom, R11 represents an unsaturated hydrocarbon group which may have a substituent, R12 and R13 represent a chain saturated hydrocarbon group which may have a substituent, and a carbon atom at an ?-position of Ct constitutes a carbon-carbon unsaturated bond.Type: GrantFiled: December 14, 2020Date of Patent: July 4, 2023Assignee: TOKYO OHKA KOGYO CO., LTD.Inventors: KhanhTin Nguyen, Masatoshi Arai, Nobuhiro Michibayashi
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Patent number: 11680792Abstract: A mark field, having at least two location marks with information for the location of the respective location mark in the mark field, and at least one position mark, which is or can be assigned to one of the location marks. Furthermore, the invention relates to a device for determining X-Y positions of structural features of structures arranged on a substrate, wherein the X-Y positions relative to the mark field, which is fixed with respect to the substrate, can be determined. Furthermore, the invention relates to a corresponding method.Type: GrantFiled: February 27, 2018Date of Patent: June 20, 2023Assignee: EV Group E. Thallner GmbHInventors: Thomas Wagenleitner, Frank Bogelsack
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Patent number: 11681233Abstract: A system having a sub-system that is configured to change a thermal condition of a physical component from a set-point to a new set-point, wherein the sub-system includes: a mixer operative to receive a first conditioning fluid having a first temperature and a second conditioning fluid having a second temperature different from the first temperature, and operative to supply to the physical component a mix of the first conditioning fluid and the second conditioning fluid; and a controller configured to control the mixer in dependence on the new set-point. Also a method of operating a lithographic apparatus as well as a device manufactured using the system described herein or according to methods described herein.Type: GrantFiled: September 26, 2019Date of Patent: June 20, 2023Assignee: ASML NETHERLANDS B.V.Inventors: Joost De Hoogh, Alain Louis Claude Leroux, Alexander Marinus Arnoldus Huijberts, Christiaan Louis Valentin, Robert Coenraad Wit, Dries Vaast Paul Hemschoote, Frits Van Der Meulen, Johannes Franciscus Martinus Van Santvoort, Radu Donose
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Patent number: 11683248Abstract: Systems, methods, and related technologies for increasing data availability. The determining of one or more recommendations to improve classification may include accessing network traffic from a network and selecting an entity. One or more values associated with one or more properties associated with the entity may be determined. The one or more values may be accessed from the network traffic. The entity may be classified and in response to the classification meeting a condition, one or more properties that are unavailable in the network traffic may be determined. A data source associated with the one or more properties for which a value is not present in the network traffic may be determined and the data source associated with the one or more properties that are unavailable in the network traffic may be stored.Type: GrantFiled: December 20, 2019Date of Patent: June 20, 2023Assignee: FORESCOUT TECHNOLOGIES, INC.Inventors: Arun Raghuramu, Aveek Kumar Das, Yang Zhang
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Patent number: 11681215Abstract: A method for forming a photomask includes receiving a mask substrate including a protecting layer and a shielding layer formed thereon, removing portions of the shielding layer to form a patterned shielding layer, and providing a BSE detector to monitor the removing of the portions of the shielding layer. When a difference in BSE intensities obtained from the BSE detector is greater than approximately 30%, the removing of the portions of the shielding layer is stopped. The BSE intensity in following etching loops becomes stable.Type: GrantFiled: November 24, 2020Date of Patent: June 20, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hsuan-Wen Wang, Hao-Ming Chang
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Patent number: 11676908Abstract: A method for manufacturing semiconductor devices include steps of depositing a first photoresist over a first dielectric layer, first exposing the first photoresist to a first light-exposure using a first lithographic mask, and second exposing the first photoresist to a second light-exposure using a second lithographic mask. An overlap region of the first photoresist is exposed to both the first light-exposure and the second light-exposure. The first dielectric layer is thereafter patterned to form a mask overlay alignment mark in the overlap region. The patterning includes etching the first dielectric layer form a trench, and filling the trench with a conductive material to produce the alignment mark. A second dielectric layer is deposited over the alignment mark, and a second photoresist is deposited over the second dielectric layer. A third lithographic mask is aligned to the second photoresist using the underlying mask overlay alignment mark for registration.Type: GrantFiled: December 16, 2019Date of Patent: June 13, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Chia Hu, Chang-Ching Yu, Ming-Fa Chen
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Patent number: 11655381Abstract: The present invention provides a solvent composition for use in an ink for producing an electronic device using a printing method, the solvent composition being capable of improving the printing accuracy of the ink, being fired at low temperatures, and suppressing the amount of ash remaining after firing to a very low amount. The solvent composition for electronic device production of the present invention is for use in an ink for producing an electronic device by a printing method, and contains a miscible product of: a solvent and a compound represented by Formula (1) below. In Formula (1), R represents the same or different aliphatic hydrocarbon groups having 1 or more carbon atoms.Type: GrantFiled: April 25, 2018Date of Patent: May 23, 2023Assignee: DAICEL CORPORATIONInventors: Hiroyuki Fujii, Yasuyuki Akai, Youji Suzuki
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Patent number: 11656550Abstract: In certain embodiments, a method for processing a semiconductor substrate includes depositing a resin film on a substrate that has microfabricated structures defining recesses. The resin film fills the recesses and covers the microfabricated structures. The method includes performing, using a photoacid generator (PAG)-based process, a localized removal of the resin film to remove the resin film to respective first depths in the recesses, at least two depths of the respective first depths being different depths. The method includes repeatedly performing, using a thermal acid generator (TAG)-based process and until a predetermined condition is met, a uniform removal of a remaining portion of the resin film to remove a substantially uniform depth of the resin film in the recesses.Type: GrantFiled: December 17, 2020Date of Patent: May 23, 2023Assignee: Tokyo Electron LimitedInventors: Daniel Fulford, Michael Murphy, Jodi Grzeskowiak, Jeffrey Smith
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Patent number: 11658039Abstract: Disclosed are plasma etching apparatuses, plasma etching methods, and semiconductor device fabrication methods. The plasma etching apparatus comprises a chamber, an electrostatic chuck in a lower portion of the chamber, a radio-frequency power supply that has a connection with the electrostatic chuck and provides the electrostatic chuck with a radio-frequency power to generate a plasma in the chamber, and a controller that has a connection with the radio-frequency power supply and controls the radio-frequency power.Type: GrantFiled: July 8, 2021Date of Patent: May 23, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyuho Kim, Nam Kyun Kim, Sungjun Ann, Myungsun Choi, Dougyong Sung, Seungbo Shim
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Patent number: 11649312Abstract: Provided herein are methods of making (meth)acrylate blocked polyurethanes with zirconium catalysts, dual cure resins containing (meth)acrylate blocked polyurethanes and zirconium catalysts, methods of using the same in additive manufacturing, and products made therefrom.Type: GrantFiled: September 7, 2022Date of Patent: May 16, 2023Assignee: Carbon, Inc.Inventor: Andrew Gordon Wright
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Patent number: 11644745Abstract: A photolithography method is provided. The photolithography method includes forming a photoresist layer on a wafer, exposing a portion of the photoresist layer by using an exposure device and a mask, and forming a photoresist pattern by removing a non-exposed portion of the photoresist layer. The mask includes a substrate having a main pattern area and a blocking area outside the main pattern area, a main pattern on the main pattern area of the substrate, and a blocking pattern on the blocking area of the substrate. An external circumference of the blocking pattern extends to the maximum area of the mask that may be illuminated by the exposure device or to the outside of the maximum area of the mask.Type: GrantFiled: June 19, 2020Date of Patent: May 9, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yongwook Lee, Yongwoo Kim, Seunggu Baek, Woojae Shin
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Patent number: 11637033Abstract: A manufacturing method of a protective film agent for laser dicing that includes a solution preparation step of preparing a solution in which at least a water-soluble resin, an organic solvent, and an ultraviolet absorber are mixed; and an ion-exchange treatment step of carrying out ion exchange of sodium ions in the solution by using a cation-exchange resin.Type: GrantFiled: January 14, 2022Date of Patent: April 25, 2023Assignee: DISCO CORPORATIONInventors: Senichi Ryo, Yukinobu Ohura, Hiroto Yoshida, Tomoaki Endo
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Patent number: 11635686Abstract: A resist composition containing a base material component (A) of which solubility in a developing solution is changed due to an action of an acid and a compound represented by Formula (bd1); in the formula, Rbd1 to Rbd3 each independently represent an aryl group which may have a substituent, provided that at least two of Rbd1 to Rbd3 are aryl groups having one or more fluorine atoms as substituents, and at least one of the fluorine atoms of the aryl group is bonded to a carbon atom adjacent to a carbon atom that is bonded to the sulfur atom in the formula, and the total number of the fluorine atoms is 4 or more; X? represents a counter anion.Type: GrantFiled: December 2, 2019Date of Patent: April 25, 2023Assignee: TOKYO OHKA KOGYO CO., LTD.Inventors: Takuya Ikeda, Junichi Miyakawa
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Patent number: 11610810Abstract: A method for fabricating an integrated circuit comprises forming one or more conductive features supported by pillars of a first insulating layer in a first metal layer. One or more vias are formed in a via layer, the one or more vias over and on the first metal layer and in electrical connection with ones of the one or more conductive features. Subsequent to via formation, air gaps are between adjacent ones of the one or more conductive features in the first metal layer to separate the one or more conductive features. A second insulating layer is formed over the one or more conductive features and over the one or more vias, such that the second insulating layer covers the first metal layer and the via layer while bridging over the air gaps, wherein tops the air gaps are substantially coplanar with tops of the one or more conductive features.Type: GrantFiled: December 21, 2018Date of Patent: March 21, 2023Assignee: Intel CorporationInventors: Miriam R. Reshotko, Richard E. Schenker, Nafees Kabir
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Patent number: 11607769Abstract: A CMP polishing apparatus for flattening a quadrate substrate is provided. A polishing apparatus for polishing a quadrate substrate is provided. The polishing apparatus includes a substrate holding portion configured to hold the quadrate substrate. The substrate holding portion includes a quadrate substrate supporting surface that supports the substrate, and an attachment mechanism that attaches a retainer member to be disposed at an outside of at least one corner portion of the substrate supporting surface.Type: GrantFiled: April 23, 2018Date of Patent: March 21, 2023Assignee: EBARA CORPORATIONInventors: Tetsuji Togawa, Hiroshi Sobukawa, Masahiro Hatakeyama
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Patent number: 11605003Abstract: A method includes inputting defect data of a source domain, to which a first mask is applied/unapplied to a reconstruction algorithm. The algorithm is trained to generate defect data of the source domain, to which the first mask is reconstructed. Normal data of the source domain is input to the algorithm, and includes data to which a second mask is applied, and data to which the second mask is not applied. The algorithm is trained to generate normal data of the source domain, to which the second mask is reconstructed. Normal data of a target domain is input to the algorithm, and the normal data of the target domain includes data to which the second mask is applied, and data to which the second mask is not applied. The algorithm is trained to generate normal data of the target domain, to which the second mask is reconstructed.Type: GrantFiled: July 30, 2018Date of Patent: March 14, 2023Assignee: SUALAB CO., LTD.Inventors: Hongdo Ki, Hyunjun Kim
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Patent number: 11599025Abstract: Provided is a resin material for forming an underlayer film which is used to form a resist underlayer film used in a multi-layer resist process, the resin material including a cyclic olefin polymer (I), in which a temperature at an intersection between a storage modulus (G?) curve and a loss modulus (G?) curve in a solid viscoelasticity of the resin material for forming an underlayer film which is as measured under conditions of a measurement temperature range of 30° C. to 300° C., a heating rate of 3° C./min, and a frequency of 1 Hz in a nitrogen atmosphere in a shear mode using a rheometer is higher than or equal to 40° C. and lower than or equal to 200°.Type: GrantFiled: May 30, 2018Date of Patent: March 7, 2023Assignee: MITSUI CHEMICALS, INC.Inventors: Keisuke Kawashima, Takashi Oda, Koji Inoue
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Patent number: 11594457Abstract: The present invention includes a method for creating a system in a package with integrated lumped element devices and active devices on a single chip/substrate for heterogeneous integration system-on-chip (HiSoC) in photo-definable glass, comprising: masking a design layout comprising one or more electrical passive and active components on or in a photosensitive glass substrate; activating the photosensitive glass substrate, heating and cooling to make the crystalline material to form a glass-crystalline substrate; etching the glass-crystalline substrate; and depositing, growing, or selectively etching a seed layer on a surface of the glass-crystalline substrate on the surface of the photodefinable glass.Type: GrantFiled: December 26, 2019Date of Patent: February 28, 2023Assignee: 3D Glass Solutions, Inc.Inventors: Jeb H. Flemming, Kyle McWethy
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Patent number: 11585964Abstract: An electro-plasmonic array is disclosed. The electro-plasmonic array includes a substrate and a plurality of nanoantennas disposed on a surface of the substrate, each of the electro-plasmonic nanoantennas including a conductive nanodisk and a conforming biocompatible electrochromic polymer layer.Type: GrantFiled: August 10, 2020Date of Patent: February 21, 2023Assignee: The Regents of the University of CaliforniaInventors: Ahmet Ali Yanik, Ahsan Habib, Xiangchao Zhu
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Patent number: 11586107Abstract: A phase shift mask suitable for forming a via pattern on a transferred object is provided. The phase shift mask has a first pattern region and a second pattern region. The phase shift mask includes a substrate and a phase shift pattern layer. The phase shift pattern layer is located on the substrate and is disposed corresponding to one of the first pattern region and the second pattern region. An optical phase difference corresponding to the first pattern region and the second pattern region is basically 180 degrees. The first pattern region has a via region away from the second pattern region. The second pattern region includes a plurality of strip patterns surrounding the via region.Type: GrantFiled: December 14, 2020Date of Patent: February 21, 2023Assignee: Powerchip Semiconductor Manufacturing CorporationInventor: Yi-Kai Lai
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Patent number: 11578150Abstract: Embossing resins, methods of manufacturing such resins, and electrokinetic display system, which includes display cells containing such resins. The resins include a fluoropolymer in weight percentage 5%-60%, a difunctional diluent in weight percentage 0-30%, a monofunctional diluent in weight percentage 0-40%, a urethane diacrylate or functionalized nanoscale material, e.g., a functionalized urethane material, in weight percentage 5-50%, a photoinitiator in weight percentage 0.5-5%, and a surfactant in weight percentage less than 0.5%. The difunctional diluent may be Hexanediol Diacrylate, and the monofunctional diluent may be a monofunctional hydrocarbon. The resins are made by identifying a target index of refraction for a cured state thereof, and combining together, by weight percentage, the constituent components to produce the liquid state version of the embossing resin having a desired composite index of refraction.Type: GrantFiled: October 11, 2021Date of Patent: February 14, 2023Inventors: James E. Abbott, Jr., Timothy Koch, Cassady Roop, Palitha Wickramanayake
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Patent number: 11573494Abstract: A photoresist film is patterned into an array of island shapes with improved critical dimension uniformity and no phase edges by using two alternating phase shifting masks (AltPSMs) and one post expose bake (PEB). The photoresist layer is exposed with a first AltPSM having a line/space (L/S) pattern where light through alternating clear regions on each side of an opaque line is 180° phase shifted. Thereafter, there is a second exposure with a second AltPSM having a L/S pattern where opaque lines are aligned orthogonal to the lengthwise dimension of opaque lines in the first exposure, and with alternating 0° and 180° clear regions. Then, a PEB and subsequent development process are used to form an array of island shapes. The double exposure method enables smaller island shapes than conventional photolithography and uses relatively simple AltPSM designs that are easier to implement in production than other optical enhancement techniques.Type: GrantFiled: November 9, 2020Date of Patent: February 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jesmin Haq, Tom Zhong, Zhongjian Teng