Abstract: A method of configuring a mark having a trench to be etched into a substrate, the method including: obtaining a relation between an extent of height variation across a surface of a probationary layer deposited on a probationary trench of a probationary depth and a thickness of the probationary layer; determining an extent of height variation across the surface of a layer deposited on the mark allowing a metrology system to determine a position of the mark; and configuring the mark by determining a depth of the trench based on the relation, the extent of height variation and the thickness of a process layer to be deposited on the mark.

Abstract: A method for manufacturing a semiconductor device may include: forming a first layer comprising a plurality of patterns, each pattern having a different respective pitch; performing exposure and development to form a second layer at a layer different from the first layer; determining whether a pitch shift of a part of exposure patterns formed is within a tolerance range, using a Moiré pattern; and performing etching for the second layer when the pitch shift of the part of exposure patterns is determined to be within the tolerance range. Performing the exposure and the development may include forming a first exposure pattern corresponding to a key pattern having a first pitch, forming a second exposure pattern corresponding to a cell pattern having a second pitch, and forming a third exposure pattern corresponding to a middle pitch pattern having a third pitch between the first pitch and the second pitch.

Abstract: The present disclosure relates to a method for forming a semiconductor structure includes depositing a dielectric layer on a substrate and depositing a patterning layer on the dielectric layer. The method also includes performing a first etching process on the patterning layer to form a first region including a first plurality of blocks at a first pattern density and a second region including a second plurality of blocks at a second pattern density that is lower than the first pattern density. The method also includes performing a second etching process on the second plurality of blocks to decrease a width of each block of the second plurality of blocks and etching the dielectric layer and the substrate using the first and second pluralities of blocks to form a plurality of fin structures.

Abstract: Methods of forming carbon nanotubes and structures and devices including carbon nanotubes are disclosed. Methods of forming the carbon nanotubes include patterning a surface of a substrate with polymeric material, removing portions of the polymeric material to form exposed substrate surface sections, and forming the carbon nanotubes on the exposed substrate sections.

Abstract: A method for producing an actinic ray-sensitive or radiation-sensitive resin composition of an embodiment of the present invention is a method for producing an actinic ray-sensitive or radiation-sensitive resin composition including at least a resin having a polarity that increases due to decomposition by the action of an acid, a compound that generates an acid upon irradiation with actinic rays or radiation, and a solvent, in which the compound that generates an acid upon irradiation with actinic rays or radiation includes one or more compounds selected from the group consisting of a compound (I) to (III) below, and the actinic ray-sensitive or radiation-sensitive resin composition is produced by mixing a first solution including the resin having a polarity that increases by the action of an acid and a first solvent with the one or more compounds selected from the group consisting of the compound (I) to (III).

Abstract: Process window qualification (PWQ) layouts can be used to determine a presence of a pattern anomaly associated with the pattern, patterning process, or patterning apparatus. For example, a modulated die or field can be compared to a slightly lower offset modulated die or field. In another example, the high to low corners for a particular condition or combination of conditions are compared. In yet another example, process modulation parameters can be used to estimate criticality of particular weak points of interest.

Abstract: The present application provides a memory device and a method of manufacturing the memory device.

Abstract: An object of the present invention is to provide a solution which contains an organic solvent as a main component (content: equal to or greater than 98% by mass) and has an excellent defect inhibition ability. Another object of the present invention is to provide a solution storage body storing the solution, an actinic ray-sensitive or radiation-sensitive resin composition containing the solution, and a pattern forming method and a manufacturing method of a semiconductor device using the solution. The solution of the present invention is a solution containing at least one kind of organic solvent having a boiling point lower than 200° C. and an organic impurity having a boiling point equal to or higher than 250° C., in which a content of the organic solvent with respect to a total mass of the solution is equal to or greater than 98% by mass, and a content of the organic impurity with respect to the total mass of the solution is equal to or greater than 0.1 mass ppm and less than 100 mass ppm.

Abstract: A method includes illuminating radiation to a resist layer over a substrate to pattern the resist layer. The patterned resist layer is developed by using a positive tone developer. The patterned resist layer is rinsed using a basic aqueous rinse solution. A pH value of the basic aqueous rinse solution is lower than a pH value of the developer, and a rinse temperature of rinsing the patterned resist layer is in a range of about 20° C. to about 40° C.

Abstract: An electroconductive-film-coated substrate includes a glass substrate and an electroconductive film disposed on one main surface of the glass substrate. The electroconductive film has an inclined portion in a peripheral edge. A distance from a position in the inclined portion where a thickness of the electroconductive film is 10% of a film thickness of a center of the electroconductive film to an edge end of the glass substrate is 3.00 mm or less. A distance from an end of the inclined portion to the edge end of the glass substrate is longer than 0.00 mm.

Abstract: In semiconductor manufacturing, deionized (DI) water or another process fluid is flowed through a nonmetallic pipe and onto a semiconductor wafer. Static electric charge is discharged from the DI water or other process fluid flowing through the nonmetallic pipe via an electrically conductive material disposed on an outside of the nonmetallic pipe. The electrically conductive material disposed on the outside of the nonmetallic pipe is electrically grounded. The nonmetallic pipe may comprise fluoropolymer (PFA) based tubing. In some embodiments, the nonmetallic pipe includes: a PFA-NE pipe connected with a chamber or housing containing the wafer, and a second pipe connected with the PFA-NE pipe by a pipe connector, in which the second pipe is more electrically insulating than the PFA-NE pipe.

Abstract: A clamp assembly is disclose, the clamp assembly comprising a clamp (50) configurable to clamp a support member (110) to a lower base surface (49) of the clamp by electrostatic adhesion, and an arrangement configurable to direct a gas to the lower base surface (49) of the clamp. The arrangement is configurable to humidify the gas by exposing the gas to a liquid. Also disclosed is a method of discharging a lower base surface of a clamp, The method comprises the steps of humidifying a gas by exposing the gas to a liquid, and directing the humidified gas to a lower base surface of the clamp.

Abstract: A wafer carrier assembly comprising a wafer carrier having a first and second side, the first side including: a circular recess configured to receive a semiconductor device wafer, and at least one cut-out arranged along the circumference of the circular recess. The first side also includes a carrier cover having a top and bottom side, the top side including: a plurality of gridlines extending to edges of the carrier cover, and a plurality of reticles extending from the top side to the bottom side where subsets of reticles are arranged to have a common center and each subset of reticles is arranged at each intersection of the plurality of gridlines.

Abstract: A chip on film (COF) package in which a predetermined driving integrated circuit (IC) is mounted includes a wiring structure connected to the driving IC, and a test pad connected to the wiring structure, wherein the test pad includes a base film divided into a first region and a second region, and a conductive layer located in the first region, and the second region is surrounded by the first region in a plan view.

Abstract: Disclosed are a probe sheet with a multi-layer contact tip and a method of manufacturing the same capable of improving the design freedom of a contact tip formed on a probe sheet of a probe card for testing a semiconductor device to come in contact with a pad of the semiconductor device. According to the present invention, the design freedom of a contact tip formed on a probe sheet of a probe card for testing a semiconductor device to come in contact with a pad of the semiconductor device can be improved, and since the shape of a contact surface of a contact tip is maintained the same and contact resistance is maintained in an allowable range even when a protective layer coated on the contact tip to increase durability of the contact tip is worn, test reliability of the probe card can be improved.

Abstract: A projector includes a projection section that projects a first image on a projection surface, a control section that causes the projection section to project a pattern image for installation including a first pattern that is located at an end of the first image, which overlaps with a second image, and a second pattern that is so disposed that a first straight line section is located in a position separate from the end by a distance, and a correction section that corrects the first image based on a captured image containing an image of a first area of the second image, and the first area is an area that overlaps with an area having a width corresponding to the distance measured from the end of the first image in a state in which the first image and the second image overlap with each other.

Abstract: A substrate processing method and apparatus to create a sacrificial masking layer is disclosed. The layer is created by providing a first precursor selected to react with one of a radiation modified and unmodified layer portion and to not react with the other one of the radiation modified and unmodified layer portion on a substrate in a reaction chamber to selectively grow the sacrificial masking layer.

Abstract: A template and a template blank are used for imprint lithography transferring a transfer pattern in a concave and convex structure to a resin on a transfer substrate, in which a first step structure is formed on a main surface of a base, a second step structure is formed on the first step structure, and an outside region of the second step structure on an upper surface of the first step structure is covered with a light shielding film to solve the above problem.

Abstract: An electronic device includes a rollable panel and a metal layer. The rollable panel includes a first portion and a second portion. The rollable panel has a first side and a second side opposite to the first side. The rollable panel includes a substrate, a circuit layer disposed on the substrate and a cover layer disposed on the circuit layer. The metal layer is disposed on one of the first side and the second side of the rollable panel and outside the rollable panel. In a rolled mode, at least a part of the metal layer is positioned between the first portion and the second portion of the rollable panel.

Abstract: An interconnected corrugated carbon-based network comprising a plurality of expanded and interconnected carbon layers is disclosed. In one embodiment, each of the expanded and interconnected carbon layers is made up of at least one corrugated carbon sheet that is one atom thick. In another embodiment, each of the expanded and interconnected carbon layers is made up of a plurality of corrugated carbon sheets that are each one atom thick. The interconnected corrugated carbon-based network is characterized by a high surface area with highly tunable electrical conductivity and electrochemical properties.

Abstract: The electroconductive inkjet ink disclosed herein contains at least inorganic powder containing high melting point metal particles, a dispersant, an organic solvent, and a poly(vinyl acetal) resin. In the electroconductive ink, the inorganic powder has an average primary particle diameter of 500 nm or less, a volume ratio of the inorganic powder is 7.5% by volume or lower, the ratio (SI/VD) of the specific surface area of the inorganic powder with respect to the volume of the dispersant is 0.25 or higher and 10 or lower, the poly(vinyl acetal) resin has an average molecular weight of 2.5×104 or larger and 6.4×104 or smaller, and the ratio (WPA/WS) of the weight of the poly(vinyl acetal) resin with respect to the weight of the organic solvent is 0.5% by weight or higher and 3% by weight or lower.

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.

Abstract: The present application discloses a method for measuring critical dimension. The method for measuring critical dimension includes providing a substrate; forming a resist layer over the substrate; monitoring a volatile byproduct evolved from the resist layer to obtain a first amount of the volatile byproduct; exposing the resist layer to a radiation source; heating the resist layer; monitoring the volatile byproduct evolved from the resist layer to obtain a second amount of the volatile byproduct; and deducting the critical dimension according to a difference between the first amount of the volatile byproduct and the second amount of the volatile byproduct.

Abstract: The present application discloses a method for measuring critical dimension. The method for measuring critical dimension includes providing a substrate; forming a resist layer over the substrate; monitoring a volatile byproduct evolved from the resist layer to obtain a first amount of the volatile byproduct; exposing the resist layer to a radiation source; heating the resist layer; monitoring the volatile byproduct evolved from the resist layer to obtain a second amount of the volatile byproduct; and deducting the critical dimension according to a difference between the first amount of the volatile byproduct and the second amount of the volatile byproduct.

Abstract: In a method of manufacturing an integrated circuit device, a photoresist layer is formed by coating a photoresist composition on a substrate having a main surface and an edge portion surrounding the main surface. A portion of the photoresist layer is removed from the edge portion of the substrate. After the portion of the photoresist layer is removed, the substrate is processed using a main treatment composition including an organic solvent, acid, and water.

Abstract: A method of aligning at least one laser beam of an additive manufacturing arrangement. The method includes measuring a surface of the calibration plate at a plurality of measurement points using the coordinate measuring machine. The method further includes generating a correction field based on the plurality of measurement points using the coordinate measuring machine. The method further includes writing at least one fiducial mark on the surface of the calibration plate using the at least one laser beam. The method further includes generating calibration data for the surface of the calibration plate using the calibration system. The method also includes aligning the laser beam within the additive manufacturing system based on the calibration data and the correction field using the computing device by comparing a position of the fiducial mark from the calibration data with the correction field to determine a corrected position of the laser beam.

Abstract: Embodiments include a substrate and a method of forming the substrate. A substrate includes an interlayer dielectric and conductive traces in the interlayer dielectric (ILD). The conductive traces may include a first conductive trace surrounded by a second and third conductive traces. The substrate also includes a photoresist block in a region of the ILD. The region may be directly surrounded by the ILD and first conductive trace, and the photoresist block may be between the first conductive trace. The photoresist block may have a top surface that is substantially coplanar to top surfaces of the ILD and conductive traces. The photoresist block may have a width substantially equal to a width of the conductive traces. The photoresist block may be in the first conductive trace and between the second and third conductive traces. The photoresist block may include a metal oxide core embedded with organic ligands.

Abstract: The embodiments of the disclosure provide a patterning method, which includes the following processes. A target layer is formed on a substrate. A hard mask layer is formed over the target layer. A first patterning process is performed on the hard mask layer by using a photomask having a first pattern with a first pitch. The photomask is shifted along a first direction by a first distance. A second patterning process is performed on the hard mask layer by using the photomask that has been shifted, so as to form a patterned hard mask. The target layer is patterned using the patterned hard mask to form a patterned target layer. The target layer has a second pattern with a second pitch less than the first pitch.

Abstract: A method for identifying a relief precursor or a relief comprising a carrier and a relief-forming layer, having the steps: a) providing a relief precursor comprising a carrier and a relief-forming layer; b) providing data which identifies the type of relief precursor and, if appropriate, contains process-relevant data for processing it, in the form of at least one two-dimensional code; c) introducing the at least one two-dimensional code into the relief-forming layer as a relief.

Abstract: A plasma processing apparatus in the present disclosure includes a plasma processing chamber, a gas supply, a power supply, and a controller. The controller causes (a) forming a first film on side walls of an opening of a processing target using the plasma so that the first film has different thicknesses along a spacing between pairs of side walls facing each other, and (b) forming a second film by performing a film forming cycle one or more times after (a) so that the second film has different thicknesses along the spacing between the pairs of side walls facing each other.

Abstract: The present invention provides a poly(phenylene ether) which retains low-dielectric characteristics and is soluble in various solvents. The poly(phenylene ether) is characterized by being obtained from one or more raw-material phenols including a phenol satisfying at least Requirement 1 (to have hydrogen atoms in the ortho and para positions) and by having a slope calculated from a conformational plot of less than 0.6.

Abstract: Processing methods may be performed to form a pixel isolation structure on a semiconductor substrate. The method may include forming a pixel isolation bilayer on the semiconductor substrate. The pixel isolation bilayer may include a high-k layer overlying a stopping layer. The method may include forming a lithographic mask on a first region of the pixel isolation bilayer. The method may also include etching the pixel isolation bilayer external to the first region. The etching may reveal the semiconductor substrate. The etching may form the pixel isolation structure.

Abstract: A method for manufacturing a printed wiring board includes forming through holes in a double-sided copper-clad laminated plate such that a high-density region of the through holes and a low-density region of the through holes are formed, forming an electrolytic plating film on a copper foil of the plate in the high-density and low-density regions, forming a masking resist to mask the plating film in the high-density region, etching the plating film in the low-density region exposed from the resist such that the plating film in the low-density region is thinned, peeling off the resist from the plating film in the high-density region, and forming a conductor circuit including the copper foil and the plating film in the high-density and low-density regions. The forming of the plating film on the copper foil of the plate includes forming the plating film in the through holes in the high-density and low-density regions.

Abstract: Systems and methods for tracking the position of one or more objects, such as components of a head-mounted display (HMD) system. One or more objects may carry a plurality of angle sensitive optical detectors. Each of the optical detectors may include an optical subsystem that is configured to vary at least one of phase or intensity of light imparted on the optical detector. The optical subsystem may include one or more of diffractive optical elements, lens arrays, intensity masks, phase masks, or the like. The optical detectors may include a photodetector that includes a plurality of optically active areas, such as a quadrant cell photodetector, an image sensor with an array of photodiodes, etc. Control circuitry may cause light sources to emit light, and may receive sensor data from the plurality of optical detectors. Control circuitry may process the sensor data to track a position of one or more objects.

Abstract: A semiconductor cell culture device for three-dimensional cell culture comprises: a semiconductor material layer in which a cell culture portion of semiconductor material is defined, wherein the cell culture portion defines an area within the semiconductor material layer surrounded by semiconductor material, wherein the cell culture portion comprises a mesh structure having island structures being interconnected by bridge structures and defining through-pores between the island structures allowing for selective transport of cell constructs, cellular components, proteins or other large molecules through the semiconductor material layer and on opposite sides of the cell culture portion in the semiconductor material layer, and a supporting structure connected to the cell culture portion.

Abstract: An etch stop layer is located on top of a first dielectric layer. A conductive line is located on top of the etch stop layer. A second dielectric layer is located above the first dielectric layer. The second dialect layer is in contact with the first dielectric layer.

Abstract: A printed circuit board according to an embodiment includes an insulating layer; a first pad disposed on an upper surface of the insulating layer; a second pad disposed on a lower surface of the insulating layer; a first device mounted on the first pad; a second device mounted on the second pad; a first molding layer disposed on the insulating layer and molding the first device; and a second molding layer disposed on the lower surface of the insulating layer and molding the second device, wherein a lower surface of the second molding layer is positioned on the same plane as a lower surface of the second device.

Abstract: A mark for overlay error measurement and overlay error measurement is provided. The mark includes a first pattern and a second pattern. The first pattern is disposed on a first surface of a substrate. The second pattern is disposed on a second surface of the substrate. The second surface of the substrate is opposite to the first surface of the substrate. The first pattern overlaps at least a portion of the second pattern, and the first pattern and the second pattern collaboratively define a first overlay error.

Abstract: An illumination apparatus comprises a plurality of LEDs aligned to an array of directional optical elements wherein the LEDs are substantially at the input aperture of respective optical elements. An electrode array is formed on the array of optical elements to provide at least a first electrical connection to the array of LED elements. Advantageously such an arrangement provides low cost and high efficiency from the directional LED array.

Abstract: Provided is a formation method of a semiconductor structure, including: providing a substrate having a first region and a second region, a plurality of discrete through holes being formed in the substrate, an arrangement density of the through holes in the first region being greater than that in the second region; forming a sacrificial layer filling the through holes; etching some thickness of the substrate around the sacrificial layer to form openings, the openings surrounding the sacrificial layer, a depth of the opening being less than a depth of the through hole in a direction perpendicular to a surface of the substrate; and removing the sacrificial layer, the openings communicating with the corresponding through holes to form trenches.

Abstract: A pattern decomposition method including following steps is provided. A target pattern is provided, wherein the target pattern includes first patterns and second patterns alternately arranged, and the width of the second pattern is greater than the width of the first pattern. Each of the second patterns is decomposed into a third pattern and a fourth pattern, wherein the third pattern and the fourth pattern have an overlapping portion, and a pattern formed by overlapping the third pattern and the fourth pattern is the same as the second pattern. The third patterns and the first pattern adjacent to the fourth pattern are designated as first photomask patterns of a first photomask. The fourth patterns and the first pattern adjacent to the third pattern are designated as second photomask patterns of a second photomask.

Abstract: The present document describes a lithographic patterning method for creating features on a surface of a substrate. The patterning method includes the steps of applying a resist material to the substrate surface for providing a resist material layer, selectively exposing, dependent on a location and based on patterning data, the resist material layer to a surface treatment step for chemically modifying the resist material of the resist material layer, and developing, based on the chemical modification of the resist material, the resist material layer such as to selectively remove the resist material. In particular, prior to the step of developing, the method comprises a step of scanning at least a part of the surface using an acoustic scanning probe microscopy method for determining a local contact stiffness of the substrate surface at a plurality of locations, for measuring one or more critical dimensions of the features to be formed on the surface.

Abstract: The present invention includes a method of creating high Q empty substrate integrated waveguide devices and/or system with low loss, mechanically and thermally stabilized in photodefinable glass ceramic substrate. The photodefinable glass ceramic process enables high performance, high quality, and/or low-cost structures. Compact low loss RF empty substrate integrated waveguide devices are a cornerstone technological requirement for RF systems, in particular, for portable systems.

Abstract: Apparatus for and method of removing a contaminant from a working surface of a lithography support such as a reticle or wafer stage in an EUV or a DUV photolithography system in which a cleaning substrate provided with a coating made a selected material and configuration is pressed against the working surface so that the contaminant is transferred from the working surface to the coating.

Abstract: A method of cleaning a semiconductor wafer includes: loading a semiconductor wafer into a cell having an annular trough; moving a plurality of nozzles into operational orientations for spraying a cleaning solution onto a top surface of the loaded semiconductor wafer; spraying the cleaning solution from each nozzle onto the top surface of the loaded semiconductor wafer in a direction defined by each nozzle's operational orientation such that a patterned flow of cleaning solution is formed on the top surface of the loaded semiconductor wafer; and collecting the cleaning solution in the annular trough of the cell as it flows off the top surface of the loaded semiconductor wafer.

Abstract: Embodiments of systems and methods for dicing a bonded structure are provided. A method for dicing a bonded structure includes thinning a top surface and a bottom surface of a bonded structure. The bonded structure may have a first wafer and a second wafer bonded with a bonding interface. The method may also include forming a series of ablation structures in the first wafer and the second wafer. The series of ablation structures may be between a first part and a second part of the bonded structure. The method may also include separating the first part and the second part of the bonded structure along the series of ablation structures.

Abstract: A circuit board with anti-corrosion properties, a method for manufacturing the circuit board, and an electronic device are provided. The circuit board includes a circuit substrate, a first protective layer, and a second protective layer. The circuit substrate includes a base layer and an outer wiring layer formed on the base layer. The circuit substrate further defines a via hole connected to the outer wiring layer. The first protective layer is formed on the outer wiring layer and an inner sidewall of the via hole, and is made of a white oil. The second protective layer is formed on the first protective layer.

Abstract: A method of manufacturing a printed circuit board a includes preparing an insulating substrate on which a first metal layer is formed, stacking a resist laminate having a plurality of layers on the first metal layer, forming an opening exposing a portion of the first metal layer by patterning the stacked resist laminate having the plurality of layers, forming a second metal layer on the exposed portion of the first metal layer, removing the patterned resist laminate having the plurality of layers, and etching at least another portion of the first metal layer.

Abstract: Spatial light modulators (SLMs) and systems using same are described. Generally, the system includes a laser, a fixture holding a workpiece to be processed using the laser, illumination optics to illuminate the SLM with laser light, imaging optics to focus modulated light from the SLM onto the workpiece, and a controller to control the laser, the SLM, imaging optics and the fixture to scan the modulated light across a workpiece surface. The SLM includes an array of microelectromechanical system based diffractors, each including an electrostatically deflectable member coupled to a first light reflective surface and to bring light reflected from the first light reflective surface into interference with light reflected from a second light reflective surface in the SLM. The controller is operable to provide analog gray-scale control of an intensity of modulated light reflected from each diffractor by controlling an electrostatic force generated by a driver coupled thereto.

Abstract: A substrate processing apparatus includes a photoresist coater applying a photoresist film on a substrate, a humidifier increasing an amount of moisture in an ambient to which the photoresist film on the substrate is exposed, and an exposer irradiating the photoresist film exposed to the ambient having the increased amount of moisture with light. The humidifier is disposed between the photoresist coater and the exposer.