Abstract: A photoresist includes a core group that contains metal, and one or more first ligands or one or more second ligands attached to the core group. The first ligands each have a following structure: The second ligands each have a following structure: {circle around (M)} represents the core group. L? represents a chemical that includes 0-2 carbon atoms saturated by Hydrogen (H) or Fluorine (F). L represents a chemical that includes 1-6 carbon atoms saturated by H or F. L? represents a chemical that includes 1-6 carbon atoms saturated by H. L?? represents a chemical that includes 1-6 carbon atoms saturated by H or F. Linker represents a chemical that links L? and L?? together.

Abstract: The present photosensitive resin composition includes a polymer (A) having a structural unit (a1) represented by a formula (a1), a structural unit (a2) represented by a formula (a2), and a structural unit (a3) represented by a formula (a3), and a photoacid generator (B). In the formulae (a1) to (a3), R12, R22, and R32 each independently represent an organic group having 1 to 10 carbon atoms; R21 represents a substituted or non-substituted alkyl group having 1 to 10 carbon atoms; R31 represents a hydrogen atom, a substituted or non-substituted alkyl group having 1 to 10 carbon atoms, or a halogen atom; R13 and R23 each independently represent an acid dissociable group; R33 represents a hydroxyaryl group; and l, m and n independently represent an integer from 0 to 10.

Abstract: A compound represented by the following formula (1). The compound can be used as a film forming material for lithography or an optical component forming material. A resin may also be obtained using this compound as a monomer, a composition, a method for forming a resist pattern, a method for forming an insulating film, a method for forming a circuit pattern, and a method for purifying the above compound or resin.

Abstract: As deposited, hard mask thin films have internal stress components which are an artifact of the material, thickness, deposition process of the mask layer as well as of the underlying materials and topography. This internal stress can cause distortion and twisting of the mask layer when it is patterned, especially when sub-micron critical dimensions are being patterned. A stress-compensating process is employed to reduce the impact of this internal stress. Heat treatment can be employed to relax the stress, as an example. In another example, a second mask layer with an opposite internal stress component is employed to offset the internal stress component in the hard mask layer.

Abstract: In one exemplary aspect, the present disclosure is directed to a method for lithography patterning. The method includes providing a substrate and forming a target layer over the substrate. A patterning layer is formed by depositing a first layer having an organic composition; depositing a second layer including over 50 atomic percent of silicon; and depositing a photosensitive layer on the second layer. In some implementations, the second layer is deposited by ALD, CVD, or PVD processes.

Abstract: A composition for forming an organic film contains a polymer having a partial structure shown by the following general formula (1A) or (1B), and an organic solvent, where Ar1 and Ar2 represent a benzene ring or naphthalene ring which optionally have a substituent; X represents a single bond or methylene group; a broken line represents a bonding arm; R represents a hydrogen atom or a monovalent organic group having 1 to 20 carbon atoms; and W1 represents a hydroxyl group, an alkyloxy group having 1 to 10 carbon atoms, or an organic group having at least one aromatic ring optionally having a substituent. A composition for forming an organic film, the composition containing a polymer with high carbon content and thermosetting property as to enable high etching resistance and excellent twisting resistance; a patterning process using the composition; and a polymer suitable for the composition for forming an organic film.

Abstract: A method for preparing a neutral alcoholic malt base is disclosed. The method includes the steps of combining malt extract, which can be derived from malted grains containing gluten, or from those that are gluten-free, fermentable sugar in liquid or solid form, and water to form a fermentable medium having a density of greater than 20° Plato, wherein a ratio of the malt extract to the fermentable sugar in the fermentable medium is from 5:95 to 0.1:99.9; and fermenting the fermentable medium with a yeast that can tolerate an alcohol concentration of at least 10% by volume thereby preparing the neutral alcoholic malt base. A flavored malt beverage can include the neutral alcoholic malt base, water, at least one flavoring, a food grade acid, a sweetening agent, and carbon dioxide.

Abstract: A display device is disclosed. The display device includes a first substrate, a frame positioned in the rear of the first substrate, a second substrate opposite the first substrate and positioned between the first substrate and the frame, the second substrate having an area less than an area of the first substrate, and a member layer electrically connected to the first substrate and extended toward the frame.

Abstract: The present disclosure, in some embodiments, relates to a method of performing an etch process. The method is performed by forming a first plurality of openings defined by first sidewalls of a mask disposed over a substrate. A cut layer is between two of the first plurality of openings. A spacer is formed onto the first sidewalls of the mask and a second plurality of openings are formed. The second plurality of openings are defined by second sidewalls of the mask and are separated by the spacer. The substrate is etched according to the mask and the spacer.

Abstract: A method including: computing a value of a first variable of a pattern of, or for, a substrate processed by a patterning process by combining a fingerprint of the first variable on the substrate and a certain value of the first variable; and determining a value of a second variable of the pattern based at least in part on the computed value of the first variable.

Abstract: The present disclosure relates to novel multiple trigger monomer containing negative working photoresist compositions and processes. The processes involve removing acid-labile protecting groups from crosslinking functionalities in a first step and crosslinking the crosslinking functionality with an acid sensitive crosslinker in a second step. The incorporation of a multiple trigger pathway in the resist catalytic chain increases the chemical gradient in areas receiving a low dose of irradiation, effectively acting as a built in dose depend quencher-analog and thus enhancing chemical gradient and thus resolution, resolution blur and exposure latitude. The photoresist compositions utilize novel monomers and mixtures of novel monomers. The methods are ideal for fine pattern processing using, for example, ultraviolet radiation, beyond extreme ultraviolet radiation, extreme ultraviolet radiation, X-rays and charged particle rays.

Abstract: A method for producing a microlens according to the present invention includes an etching step and a surface treatment step. In the etching step, a target object which is obtained by forming a second organic film having a lens shape on a first organic film that is formed on a substrate is subjected to etching that uses a plasma of a first processing gas, while using the second organic film as a mask, so that the first organic film is etched so as to transfer the lens shape of the second organic film to the first organic film, thereby forming a microlens in the first organic film. In the surface treatment step, a surface treatment is performed so as to smooth the surface of the microlens that is formed in the first organic film.

Abstract: Porous membranes are provided according to the invention having desirable coefficient of thermal expansion and large surface area, for example at least about 4,000 mm2. These porous membranes may be made according to an exemplary process employing lithographic patterning of a photoresist followed by development of the photoresist and etching. In one aspect, the etch barrier layer is chosen from a material that does not react with or incorporate metal or other contaminants into the membrane layer.

Abstract: A method for forming the gate structure of the NAND memory, comprising the steps of disposing a gate structure layer, a pattern transfer layer, a TEOS structure, and an organic dielectric Tri-Layer on a substrate sequentially; performing a patterning using a first photomask and a first photoresist layer; performing an etching process to form a control gate structure, a peripheral gate structure and a select gate structure; performing a trimming process to them; patterning sidewalls on sides of them; performing a second patterning using a second photomask as a mask and a second photoresist layer to protect the peripheral gate structure, the select gate structure, and their sidewalls; removing the control gate structure between its sidewalls; performing etching by using the sidewalls, the peripheral gate structure and the select gate structure as masks to form the control gate, the peripheral gate, and the select gate.

Abstract: A method of making a printed circuit board includes a step of providing a double-sided plate that is an insulating substrate having conductive layers on respective surfaces thereof, a first coating step of coating a first surface of the double-sided plate with a first photosensitive resin film, a second coating step of coating a second surface of the double-sided plate with a second photosensitive resin film, a first exposure step of exposing the photosensitive resin film coating the first surface after the first and second coating steps, and a second exposure step of exposing the photosensitive resin film coating the second surface after the first exposure step, wherein a maximum depth of a depression in an outermost surface of the second photosensitive resin film used in the second exposure step is less than 1.0 ?m.

Abstract: Disclosed is a flexible display panel, comprising a flexible substrate; an organic light emitting diode layer, disposed on the flexible substrate, wherein the organic light emitting diode layer comprises a plurality of sub pixels arranged at intervals; a metal mesh, disposed on the organic light emitting diode layer, wherein metal traces of the metal mesh are correspondingly arranged in gaps among the plurality of sub pixels disposed at intervals, and the metal traces of the metal mesh surround to form a plurality of touch electrodes, and at least one of the touch electrodes comprises at least one first touch area, and the first touch area is correspondingly arranged with at least two of the sub pixels. The flexible display panel can improve the display effect of the flexible display panel by reducing the arrangement density of the metal traces of the metal mesh.

Abstract: A method for lithography patterning includes depositing a target layer over a substrate, the target layer including an inorganic material; implanting ions into the target layer, resulting in an ion-implanted target layer; forming a photoresist layer directly over the ion-implanted target layer; and exposing the photoresist layer to radiation in a photolithography process. The ion-implanted target layer reduces reflection of the radiation back to the photoresist layer during the photolithography process.

Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over a target layer, forming a second mask layer over the first mask layer, patterning the second mask layer, forming a third mask layer over the patterned second mask layer, patterning the third mask layer, etching the first mask layer using both the patterned second mask layer and the patterned third mask layer as a combined etch mask, removing the patterned third mask layer to expose a portion of the first mask layer, performing a trim process on the exposed portion of the first mask layer, and etching the target layer using the first mask layer to form openings in the target layer.

Abstract: A method of manufacturing an image pattern for a security device includes providing a metallised substrate; applying a first photosensitive resist layer to a substrate first metal layer exposing the resist layer to radiation; exposing the resist layer to a first reactant substance; activating a cross linking agent in the resist layer; exposing first and second pattern elements of the resist layer to radiation of a wavelength to which the resist layer is responsive whereupon newly-exposed first pattern elements of the first photosensitive resist layer react, resulting in increased solubility by the second etchant substance, the second pattern elements remaining relatively insoluble by the second etchant substance; and applying first and second etchant substances to the substrate whereupon the first pattern elements of both the first resist layer and the first metal layer are dissolved, the remaining second pattern elements of the first metal layer forming an image pattern.

Abstract: The manufacturing method for TFT array substrate of the invention exposes the negative photoresist material on the passivation layer with a semi-transmissive mask to form a crosslinked portion, first and second uncrosslinked portion; then, performs the first development to remove the first uncrosslinked portion and forms a via on the passivation layer, performs the ashing treatment for thinning the negative photoresist material to expose the second uncrosslinked portion, performs the second development to remove the second uncrosslinked portion; deposits transparent conductive material on negative photoresist material and exposed passivation layer to form a pixel electrode on passivation layer, and finally removes the remaining negative photoresist material and the transparent conductive material with photoresist stripping solution.

Abstract: Embodiments described herein relate to a method for fabricating word lines of a NAND memory. In the process for fabricating the word lines of the NAND memory, by adding a sacrificial pattern at a position close to a core layer or a sidewall of a select transistor at the edge of the word lines, the actual word line pattern is not at the outermost edge of the pattern, the pattern density of the edge word line pattern is closer to the pattern density of the middle word line pattern, the morphology and size of the edge word line are closer to the morphology and size of the middle area during core layer etching and sidewall etching, and thus the uniformity of the finally etched word lines is improved.

Abstract: Technologies for providing multiple levels of error correction include a memory that includes media access circuitry coupled to a memory media. The media access circuitry is to read data from the memory media. Additionally, the media access circuitry is to perform, with an error correction logic unit located in the media access circuitry, error correction on the read data to produce error-corrected data.

Abstract: The present disclosure provides a method for planarization. The method includes providing a substrate having a top surface and a trench recessed from the top surface; coating a sensitive material layer on the top surface of the substrate, wherein the sensitive material layer fills in the trench; performing an activation treatment to the sensitive material layer so that portions of the material layer are chemically changed; and performing a wet chemical process to the sensitive material layer so that top portions of the sensitive material layer above the trench are removed, wherein remaining portions of the sensitive material layer have top surfaces substantially coplanar with the top surface of the substrate.

Abstract: Resist materials having enhanced sensitivity to radiation are disclosed herein, along with methods for lithography patterning that implement such resist materials. An exemplary resist material includes a polymer, a sensitizer, and a photo-acid generator (PAG). The sensitizer is configured to generate a secondary radiation in response to the radiation. The PAG is configured to generate acid in response to the radiation and the secondary radiation. The PAG includes a sulfonium cation having a first phenyl ring and a second phenyl ring, where the first phenyl ring is chemically bonded to the second phenyl ring.

Abstract: A method for manufacturing a semiconductor device includes forming a hardmask layer on a substrate, forming a plurality of spacers on the hardmask layer, wherein the plurality of spacers comprise a first set of spacers and a second set of spacers, reducing a height of each spacer of the second set of spacers to be less than a height of each spacer of the first set of spacers, removing one or more spacers from at least one of the first set of spacers and the second set of spacers, transferring a pattern of remaining spacers to the hardmask layer to form a plurality of patterned hardmask portions, and transferring a pattern of the plurality of patterned hardmask portions to the substrate to form one of a plurality of patterned substrate portions and a plurality of openings in the substrate.

Abstract: Emission frequency of quantum dots in a photonic crystal membrane can be tuned by laser light treatment. For example, a focused laser can heat InAs quantum dots embedded within a <200 nm photonic crystal GaAs membrane. At temperatures above about 600° C., indium atoms from the quantum dots and gallium atoms from the membrane interdiffuse, alloying the quantum dots with the surrounding membrane. This causes the quantum dots to become more gallium rich, which shifts the emission to higher frequencies.

Abstract: A method of fabricating a semiconductor device includes forming a first etching pattern structure and a second etching pattern structure on a substrate. The first cell etching pattern structure has a top surface at a level that is different from that of a top surface of the second etching pattern structure. The method further includes forming a first spacer layer on the first etching pattern structure and the second etching pattern structure. The first spacer layer covers top and lateral surfaces of the first etching pattern structure and top and lateral surfaces of the second etching pattern structure. The method further includes performing a first etching process on the first spacer layer to form a first spacer and a second spacer. The first spacer layer is fully exposed during the first etching process of the first spacer layer.

Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over an underlying layer, patterning the first mask layer to form a first opening, forming a non-conformal film over the first mask layer, wherein a first thickness of the non-conformal film formed on the top surface of the first mask layer is greater than a second thickness of the non-conformal film formed on a sidewall surface of the first mask layer, performing a descum process, wherein the descum process removes a portion of the non-conformal film within the first opening, and etching the underlying layer using the patterned first mask layer and remaining portions of the non-conformal film as an etching mask.

Abstract: A method for transferring an actual workpiece pattern (23) to a workpiece (24) using a pixelated phase mask (14) includes (i) evaluating a desired workpiece pattern (226) to identify a desired repetitive step cell (230) in the desired workpiece pattern (226), the desired repetitive step cell (230) having a desired step cell width (250), and a desired step cell length (252); (ii) evaluating if the desired step cell width (250) is equal to a first integer multiplied by a pixel width (28A) and an optical adjustment factor; and (iii) evaluating if the desired step cell length (252) is equal to a second integer multiplied by a pixel length (28B) and an optical adjustment factor.

Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A sidewall spacer is arranged adjacent to a sidewall of a gate electrode, a source/drain region is arranged laterally adjacent to the sidewall spacer, and a contact is arranged over the source/drain region and laterally adjacent to the sidewall spacer. The contact is coupled with the source/drain region. A section of an interlayer dielectric layer is laterally arranged between the contact and the sidewall spacer.

Abstract: A method of manufacturing a gate structure for a nonvolatile memory device is disclosed. A tunneling oxide layer is formed on a substrate, and then a first polysilicon layer, a gate dielectric layer, a second polysilicon layer and a hard mask pattern are sequentially formed on the tunneling oxide layer. Then, the second polysilicon layer, the gate dielectric layer, and the first polysilicon layer are patterned through an etching process using the hard mask pattern to form stacked memory gates on the tunnel oxide layer, each including a floating gate, a gate dielectric layer pattern and a control gate on the tunneling oxide layer, and a select gate provided between the memory gates on the tunneling oxide layer.

Abstract: A method for large scale integration of haptic devices is described. The method comprises forming a first elastomer layer of a large scale integration (LSI) device on a substrate according to a specified manufacturing process, the first elastomer layer having a plurality of fluid based circuits, the first elastomer layer adhering to a plurality of formation specifications. The method further comprises curing the first elastomer layer. Additionally, one or more additional elastomer layers of the LSI device are formed with the first elastomer layer according to the specified manufacturing process, the one or more additional elastomer layers having a plurality of fluid based circuits, the one or more additional elastomer layers adhering to the plurality of formation specifications.

Abstract: A plasma etching method includes a first process of generating a first plasma from a first processing gas that contains fluorine-containing gas and hydrogen-containing gas, by using a first radio frequency power, to etch a laminated film including a first silicon-containing film layer and a second silicon-containing film layer that is different from the first silicon-containing film layer, with the generated first plasma; and a second process that is performed after the first process and includes generating a second plasma from a second processing gas that contains bromine-containing gas, by using a second radio frequency power, to etch the laminated film with the generated second plasma. Unevenness is formed at an interface between the first silicon-containing film layer and the second silicon-containing film layer in the first process, and the unevenness is removed in the second process.

Abstract: A method of forming a layout of a semiconductor device includes the following steps. First line patterns extend along a first direction in a first area and a second area, but the first line patterns extend along a second direction in a boundary area. Second line patterns extend along a third direction in the first area and the second area, but the second line patterns extend along a fourth direction in the boundary area, so that minimum distances between overlapping areas of the first line patterns and the second line patterns in the boundary area are larger than minimum distances between overlapping areas of the first line patterns and the second line patterns in the first area and the second area. A trimming process is performed to shade the first line patterns and the second line patterns in the boundary area and the second area.

Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over a target layer, forming a second mask layer over the first mask layer, patterning the second mask layer, forming a third mask layer over the patterned second mask layer, patterning the third mask layer, etching the first mask layer using both the patterned second mask layer and the patterned third mask layer as a combined etch mask, removing the patterned third mask layer to expose a portion of the first mask layer, performing a trim process on the exposed portion of the first mask layer, and etching the target layer using the first mask layer to form openings in the target layer.

Abstract: A method that specifies, signals and uses coding-independent code points (CICP) in processing media contents from multiple media sources is provided. An apparatus implementing the method receives media contents captured by a plurality of media sources in one or more clusters. The apparatus processes the media contents to provide a plurality of coding-independent code points for the plurality of media sources. The apparatus also encodes the media contents to provide at least one elementary stream.

Abstract: A method includes forming at least a first via in a multilayer structure comprising a first layer and a second layer formed over the first layer, the first via extending from a top of the second layer to a top of a first contact formed in the first layer and forming a polymer film on at least a portion of sidewalls of the first via by etching the top of the first contact using a cleaning process.

Abstract: A method of manufacturing a display device, includes providing a substrate including a first stepped part, forming a metal layer on the substrate and the first stepped part, forming an organic layer pattern on the metal layer at a position corresponding to a sidewall of the stepped part, forming a photosensitive layer on the metal layer and the organic layer pattern, patterning the photosensitive layer to form a photosensitive layer pattern adjacent to the organic layer pattern, and forming a metal line by removing the organic layer pattern and an exposed portion of the metal layer through an etching process using the photosensitive layer pattern as a mask.

Abstract: The disclosure herein describes methods for Photosensitized Chemically Amplified Resist Chemicals (PS-CAR) to pattern light sensitive films on a semiconductor substrate. In one embodiment, a two-step exposure process may generate higher acid concentration regions within a photoresist layer. The PS-CAR chemicals may include photoacid generators (PAGs) and photosensitizer elements that enhance the decomposition of the PAGs into acid. The first exposure may be a patterned EUV exposure that generates an initial amount of acid and photosensitizer. The second exposure may be a non-EUV flood exposure that excites the photosensitizer which increases the acid generation rate where the photosensitizer is located on the substrate. The distribution of energy during the exposures may be optimized by using certain characteristics (e.g., thickness, index of refraction, doping) of the photoresist layer, an underlying layer, and/or an overlying layer.

Abstract: A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern has hardmask fins of three mutually selectively etchable compositions. A region on the three-color hardmask fin pattern is masked, leaving one or more fins of a first color exposed. All exposed fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color. The mask and all fins of a second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.

Abstract: One of the broader forms of the present disclosure relates to a method of making a semiconductor device. The method includes exposing a photoresist layer to a radiation source and applying a hardening agent to the photoresist layer. Therefore after applying the hardening agent a first portion of the photoresist layer has a higher glass transition temperature, higher mechanical strength, than a second portion of the photoresist layer.

Abstract: A coating and developing method includes: a step that applies a resist containing a metal to a front surface of a substrate to form a resist film, and exposes the resist film; a developing step that supplies a developer to the front surface of the substrate to develop the resist film; and a step that forms, before the developing step, a first protective film on a peripheral part of the substrate on which the resist film is not formed, so as to prevent the developer from coming into contact with the peripheral part of the substrate, wherein the first protective film is formed at least on a peripheral end surface and a peripheral portion of a rear surface of the substrate in the peripheral part of the substrate.

Abstract: Techniques for increasing Weff VFET devices are provided. In one aspect, a method of forming a fin structure includes: depositing a hardmask onto a substrate; depositing a mandrel material onto the hardmask; patterning the mandrel material along a first direction to form first mandrels; forming first spacers alongside the first mandrels; forming second mandrels in between the first mandrels; pattering the first/second mandrels along a second direction perpendicular to the first direction; forming second spacers, perpendicular to the first spacers, alongside the first/second mandrels; selectively removing the first/second mandrels leaving behind a ladder-shaped pattern formed by the first/second spacers; transferring the ladder-shaped pattern to the hardmask and then to the substrate. A method of forming a VFET device, a VFET fin structure, and a VFET device are also provided.

Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.

Abstract: Embodiments of the invention provide a method for atomic layer etching (ALE) of a substrate. According to one embodiment, the method includes providing a substrate, and exposing the substrate to hydrogen fluoride (HF) gas and a boron-containing gas to etch the substrate. According to another embodiment, the method includes providing a substrate containing a metal oxide film, exposing the substrate to HF gas to form a fluorinated surface layer on the metal oxide film, and exposing the substrate to a boron-containing gas to remove the fluorinated surface layer from the metal oxide film. The exposures may be repeated at least once to further etch the metal oxide film.

Abstract: A coating agent capable of favorably reducing the roughness of a resist pattern and a method for forming a resist pattern in which roughness is reduced. The method includes coating the resist pattern with the coating agent. The coating agent is a composition including a resin, a quaternary carbon-atom-containing compound, and a solvent, the quaternary carbon-atom-containing compound having an aliphatic hydrocarbon group having 1 to 8 carbon atoms and a group having a specific structure having a specific amount of ethylene oxide and/or propylene oxide added thereto.

Abstract: The touch display panel comprises an array substrate, a color film substrate a touch electrode layer located at a side of the color film substrate away from the array substrate, and a transparent electrically conductive layer between the color film substrate and the touch electrode layer and insulated from the touch electrode layer. The transparent electrically conductive layer comprises a first area and a second area, a thickness of the transparent electrically conductive layer in the first area is greater than a thickness of the transparent electrically conductive layer in the second area, the transparent electrically conductive layer is suitable for being electrically connected to ground. A projection area of the touch electrode layer on the color film substrate overlaps with a projection area of the transparent electrically conductive layer located in the second area on the color film substrate.

Abstract: A method for forming patterns of a semiconductor device includes sequentially forming a hard mask layer, a sacrificial layer, and an anti-reflection layer on a substrate, the substrate including a cell region and a peripheral circuit region, patterning the sacrificial layer to form a first sacrificial pattern on the cell region and a second sacrificial pattern on the peripheral circuit region, forming spacers covering sidewalls of the first and second sacrificial patterns, and removing the first sacrificial pattern. The anti-reflection layer includes a lower anti-reflection layer and an upper anti-reflection layer which are formed of materials different from each other. In the patterning of the sacrificial layer, the anti-reflection layer is patterned to form a first anti-reflection pattern on the first sacrificial pattern and a second anti-reflection pattern on the second sacrificial pattern. The second anti-reflection pattern remains when the first sacrificial pattern is removed.

Abstract: A method for fabricating a semiconductor device includes forming a first material layer over a substrate, forming a middle layer over the first material layer, forming a first hard mask (HM) layer over the middle layer, forming a second HM layer over the first HM layer, forming a first trench in the second HM layer that extends into the first HM layer, forming a second trench in the second HM layer, The second trench is parallel to the first trench. The method also includes forming a first hole feature in the middle layer within the first trench by using the second HM layer and the first HM layer as a mask and forming a second hole feature in the middle layer within the second trench by using the second HM layer as a mask.

Abstract: The purpose of the present invention is to provide a method for stripping a resist film, which includes a cured resin having a phosphate ester group or a carboxyl group, by using a resist stripping solution having high strippability, the method being characterized in that deterioration of the strippability of the resist stripping solution is suppressed and the phosphorus concentration in the resist stripping solution is not substantially increased. In this method, a resist stripping solution is brought into contact with a resist film, which includes a cured resin having a phosphate ester group or a carboxyl group and is disposed on a metal plate, and the resist film is stripped from the metal plate. In this method, the resist stripping solution contains a benzyl alcohol, water in a mass ratio to the benzyl alcohol of 0.3-2.5, and a surfactant, and is substantially free of caustic alkali components.