With Formation Of Resist Image, And Etching Of Substrate Or Material Deposition Patents (Class 430/313)
  • Patent number: 11043504
    Abstract: Embodiments described herein relate to a method for fabricating word lines of a NAND memory. In the process for fabricating the word lines of the NAND memory, by adding a sacrificial pattern at a position close to a core layer or a sidewall of a select transistor at the edge of the word lines, the actual word line pattern is not at the outermost edge of the pattern, the pattern density of the edge word line pattern is closer to the pattern density of the middle word line pattern, the morphology and size of the edge word line are closer to the morphology and size of the middle area during core layer etching and sidewall etching, and thus the uniformity of the finally etched word lines is improved.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: June 22, 2021
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Shaokang Yao, Xiaohua Ju, Guanqun Huang
  • Patent number: 11023320
    Abstract: Technologies for providing multiple levels of error correction include a memory that includes media access circuitry coupled to a memory media. The media access circuitry is to read data from the memory media. Additionally, the media access circuitry is to perform, with an error correction logic unit located in the media access circuitry, error correction on the read data to produce error-corrected data.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Wei Wu, Rajesh Sundaram, Chetan Chauhan, Jawad B. Khan, Shigeki Tomishima, Srikanth Srinivasan
  • Patent number: 11022886
    Abstract: The present disclosure provides a method for planarization. The method includes providing a substrate having a top surface and a trench recessed from the top surface; coating a sensitive material layer on the top surface of the substrate, wherein the sensitive material layer fills in the trench; performing an activation treatment to the sensitive material layer so that portions of the material layer are chemically changed; and performing a wet chemical process to the sensitive material layer so that top portions of the sensitive material layer above the trench are removed, wherein remaining portions of the sensitive material layer have top surfaces substantially coplanar with the top surface of the substrate.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: June 1, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO,, LTD.
    Inventors: Ming-Hui Weng, Cheng-Han Wu, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 11003076
    Abstract: Resist materials having enhanced sensitivity to radiation are disclosed herein, along with methods for lithography patterning that implement such resist materials. An exemplary resist material includes a polymer, a sensitizer, and a photo-acid generator (PAG). The sensitizer is configured to generate a secondary radiation in response to the radiation. The PAG is configured to generate acid in response to the radiation and the secondary radiation. The PAG includes a sulfonium cation having a first phenyl ring and a second phenyl ring, where the first phenyl ring is chemically bonded to the second phenyl ring.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: May 11, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Hao Chen, Wei-Han Lai, Chien-Wei Wang, Chin-Hsiang Lin
  • Patent number: 10991584
    Abstract: A method for manufacturing a semiconductor device includes forming a hardmask layer on a substrate, forming a plurality of spacers on the hardmask layer, wherein the plurality of spacers comprise a first set of spacers and a second set of spacers, reducing a height of each spacer of the second set of spacers to be less than a height of each spacer of the first set of spacers, removing one or more spacers from at least one of the first set of spacers and the second set of spacers, transferring a pattern of remaining spacers to the hardmask layer to form a plurality of patterned hardmask portions, and transferring a pattern of the plurality of patterned hardmask portions to the substrate to form one of a plurality of patterned substrate portions and a plurality of openings in the substrate.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: April 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: Peng Xu, Kangguo Cheng, Choonghyun Lee, Juntao Li
  • Patent number: 10921519
    Abstract: Emission frequency of quantum dots in a photonic crystal membrane can be tuned by laser light treatment. For example, a focused laser can heat InAs quantum dots embedded within a <200 nm photonic crystal GaAs membrane. At temperatures above about 600° C., indium atoms from the quantum dots and gallium atoms from the membrane interdiffuse, alloying the quantum dots with the surrounding membrane. This causes the quantum dots to become more gallium rich, which shifts the emission to higher frequencies.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: February 16, 2021
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Joel Q. Grim, Samuel Carter, Allan S. Bracker, Daniel Gammon
  • Patent number: 10910231
    Abstract: A method of fabricating a semiconductor device includes forming a first etching pattern structure and a second etching pattern structure on a substrate. The first cell etching pattern structure has a top surface at a level that is different from that of a top surface of the second etching pattern structure. The method further includes forming a first spacer layer on the first etching pattern structure and the second etching pattern structure. The first spacer layer covers top and lateral surfaces of the first etching pattern structure and top and lateral surfaces of the second etching pattern structure. The method further includes performing a first etching process on the first spacer layer to form a first spacer and a second spacer. The first spacer layer is fully exposed during the first etching process of the first spacer layer.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: February 2, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sanggyo Chung, Kyoung Ha Eom, Hyunchul Lee, Sounghee Lee, Jiseung Lee
  • Patent number: 10867839
    Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over an underlying layer, patterning the first mask layer to form a first opening, forming a non-conformal film over the first mask layer, wherein a first thickness of the non-conformal film formed on the top surface of the first mask layer is greater than a second thickness of the non-conformal film formed on a sidewall surface of the first mask layer, performing a descum process, wherein the descum process removes a portion of the non-conformal film within the first opening, and etching the underlying layer using the patterned first mask layer and remaining portions of the non-conformal film as an etching mask.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Ren Wang, Shing-Chyang Pan, Ching-Yu Chang, Wan-Lin Tsai, Jung-Hau Shiu, Tze-Liang Lee
  • Patent number: 10840103
    Abstract: A method for transferring an actual workpiece pattern (23) to a workpiece (24) using a pixelated phase mask (14) includes (i) evaluating a desired workpiece pattern (226) to identify a desired repetitive step cell (230) in the desired workpiece pattern (226), the desired repetitive step cell (230) having a desired step cell width (250), and a desired step cell length (252); (ii) evaluating if the desired step cell width (250) is equal to a first integer multiplied by a pixel width (28A) and an optical adjustment factor; and (iii) evaluating if the desired step cell length (252) is equal to a second integer multiplied by a pixel length (28B) and an optical adjustment factor.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: November 17, 2020
    Assignee: NIKON CORPORATION
    Inventor: Shane R. Palmer
  • Patent number: 10833160
    Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A sidewall spacer is arranged adjacent to a sidewall of a gate electrode, a source/drain region is arranged laterally adjacent to the sidewall spacer, and a contact is arranged over the source/drain region and laterally adjacent to the sidewall spacer. The contact is coupled with the source/drain region. A section of an interlayer dielectric layer is laterally arranged between the contact and the sidewall spacer.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Michael Aquilino, Daniel Jaeger, Naved Siddiqui, Jessica Dechene, Daniel J. Dechene, Shreesh Narasimha, Natalia Borjemscaia
  • Patent number: 10756191
    Abstract: A method of manufacturing a gate structure for a nonvolatile memory device is disclosed. A tunneling oxide layer is formed on a substrate, and then a first polysilicon layer, a gate dielectric layer, a second polysilicon layer and a hard mask pattern are sequentially formed on the tunneling oxide layer. Then, the second polysilicon layer, the gate dielectric layer, and the first polysilicon layer are patterned through an etching process using the hard mask pattern to form stacked memory gates on the tunnel oxide layer, each including a floating gate, a gate dielectric layer pattern and a control gate on the tunneling oxide layer, and a select gate provided between the memory gates on the tunneling oxide layer.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: August 25, 2020
    Assignee: DB HITEK CO., LTD.
    Inventors: Sung Mo Gu, Sung Bok Ahn
  • Patent number: 10732712
    Abstract: A method for large scale integration of haptic devices is described. The method comprises forming a first elastomer layer of a large scale integration (LSI) device on a substrate according to a specified manufacturing process, the first elastomer layer having a plurality of fluid based circuits, the first elastomer layer adhering to a plurality of formation specifications. The method further comprises curing the first elastomer layer. Additionally, one or more additional elastomer layers of the LSI device are formed with the first elastomer layer according to the specified manufacturing process, the one or more additional elastomer layers having a plurality of fluid based circuits, the one or more additional elastomer layers adhering to the plurality of formation specifications.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: August 4, 2020
    Assignee: Facebook Technologies, LLC
    Inventors: Sean Jason Keller, Tristan Thomas Trutna
  • Patent number: 10707213
    Abstract: A method of forming a layout of a semiconductor device includes the following steps. First line patterns extend along a first direction in a first area and a second area, but the first line patterns extend along a second direction in a boundary area. Second line patterns extend along a third direction in the first area and the second area, but the second line patterns extend along a fourth direction in the boundary area, so that minimum distances between overlapping areas of the first line patterns and the second line patterns in the boundary area are larger than minimum distances between overlapping areas of the first line patterns and the second line patterns in the first area and the second area. A trimming process is performed to shade the first line patterns and the second line patterns in the boundary area and the second area.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: July 7, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chia-Hung Wang, En-Chiuan Liou, Chien-Hao Chen, Sho-Shen Lee, Yi-Ting Chen, Jhao-Hao Lee
  • Patent number: 10707090
    Abstract: A plasma etching method includes a first process of generating a first plasma from a first processing gas that contains fluorine-containing gas and hydrogen-containing gas, by using a first radio frequency power, to etch a laminated film including a first silicon-containing film layer and a second silicon-containing film layer that is different from the first silicon-containing film layer, with the generated first plasma; and a second process that is performed after the first process and includes generating a second plasma from a second processing gas that contains bromine-containing gas, by using a second radio frequency power, to etch the laminated film with the generated second plasma. Unevenness is formed at an interface between the first silicon-containing film layer and the second silicon-containing film layer in the first process, and the unevenness is removed in the second process.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: July 7, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Wataru Takayama, Sho Tominaga, Yoshiki Igarashi
  • Patent number: 10699943
    Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over a target layer, forming a second mask layer over the first mask layer, patterning the second mask layer, forming a third mask layer over the patterned second mask layer, patterning the third mask layer, etching the first mask layer using both the patterned second mask layer and the patterned third mask layer as a combined etch mask, removing the patterned third mask layer to expose a portion of the first mask layer, performing a trim process on the exposed portion of the first mask layer, and etching the target layer using the first mask layer to form openings in the target layer.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yu-Lien Huang
  • Patent number: 10623635
    Abstract: A method that specifies, signals and uses coding-independent code points (CICP) in processing media contents from multiple media sources is provided. An apparatus implementing the method receives media contents captured by a plurality of media sources in one or more clusters. The apparatus processes the media contents to provide a plurality of coding-independent code points for the plurality of media sources. The apparatus also encodes the media contents to provide at least one elementary stream.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: April 14, 2020
    Assignee: MEDIATEK INC.
    Inventors: Xin Wang, Lulin Chen, Wang Lin Lai, Shan Liu
  • Patent number: 10586732
    Abstract: A method includes forming at least a first via in a multilayer structure comprising a first layer and a second layer formed over the first layer, the first via extending from a top of the second layer to a top of a first contact formed in the first layer and forming a polymer film on at least a portion of sidewalls of the first via by etching the top of the first contact using a cleaning process.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yann A. M. Mignot, Chih-Chao Yang
  • Patent number: 10553625
    Abstract: A method of manufacturing a display device, includes providing a substrate including a first stepped part, forming a metal layer on the substrate and the first stepped part, forming an organic layer pattern on the metal layer at a position corresponding to a sidewall of the stepped part, forming a photosensitive layer on the metal layer and the organic layer pattern, patterning the photosensitive layer to form a photosensitive layer pattern adjacent to the organic layer pattern, and forming a metal line by removing the organic layer pattern and an exposed portion of the metal layer through an etching process using the photosensitive layer pattern as a mask.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: February 4, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: In Kyung Yoo, Chong Sup Chang, Dong Hyun Yang
  • Patent number: 10534266
    Abstract: The disclosure herein describes methods for Photosensitized Chemically Amplified Resist Chemicals (PS-CAR) to pattern light sensitive films on a semiconductor substrate. In one embodiment, a two-step exposure process may generate higher acid concentration regions within a photoresist layer. The PS-CAR chemicals may include photoacid generators (PAGs) and photosensitizer elements that enhance the decomposition of the PAGs into acid. The first exposure may be a patterned EUV exposure that generates an initial amount of acid and photosensitizer. The second exposure may be a non-EUV flood exposure that excites the photosensitizer which increases the acid generation rate where the photosensitizer is located on the substrate. The distribution of energy during the exposures may be optimized by using certain characteristics (e.g., thickness, index of refraction, doping) of the photoresist layer, an underlying layer, and/or an overlying layer.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: January 14, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Michael A. Carcasi, Joshua S. Hooge, Benjamen M. Rathsack, Seiji Nagahara
  • Patent number: 10410875
    Abstract: A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern has hardmask fins of three mutually selectively etchable compositions. A region on the three-color hardmask fin pattern is masked, leaving one or more fins of a first color exposed. All exposed fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color. The mask and all fins of a second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: September 10, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sean D. Burns, Nelson M. Felix, Chi-Chun Liu, Yann A. M. Mignot, Stuart A. Sieg
  • Patent number: 10394126
    Abstract: One of the broader forms of the present disclosure relates to a method of making a semiconductor device. The method includes exposing a photoresist layer to a radiation source and applying a hardening agent to the photoresist layer. Therefore after applying the hardening agent a first portion of the photoresist layer has a higher glass transition temperature, higher mechanical strength, than a second portion of the photoresist layer.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: August 27, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Ling Cheng, Ching-Yu Chang, Chien-Wei Wang, Yen-Hao Chen
  • Patent number: 10394125
    Abstract: A coating and developing method includes: a step that applies a resist containing a metal to a front surface of a substrate to form a resist film, and exposes the resist film; a developing step that supplies a developer to the front surface of the substrate to develop the resist film; and a step that forms, before the developing step, a first protective film on a peripheral part of the substrate on which the resist film is not formed, so as to prevent the developer from coming into contact with the peripheral part of the substrate, wherein the first protective film is formed at least on a peripheral end surface and a peripheral portion of a rear surface of the substrate in the peripheral part of the substrate.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: August 27, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Shinichiro Kawakami, Hiroshi Mizunoura
  • Patent number: 10340364
    Abstract: Techniques for increasing Weff VFET devices are provided. In one aspect, a method of forming a fin structure includes: depositing a hardmask onto a substrate; depositing a mandrel material onto the hardmask; patterning the mandrel material along a first direction to form first mandrels; forming first spacers alongside the first mandrels; forming second mandrels in between the first mandrels; pattering the first/second mandrels along a second direction perpendicular to the first direction; forming second spacers, perpendicular to the first spacers, alongside the first/second mandrels; selectively removing the first/second mandrels leaving behind a ladder-shaped pattern formed by the first/second spacers; transferring the ladder-shaped pattern to the hardmask and then to the substrate. A method of forming a VFET device, a VFET fin structure, and a VFET device are also provided.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: July 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chen Zhang, Kangguo Cheng, Tenko Yamashita, Xin Miao, Wenyu Xu
  • Patent number: 10304700
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: May 28, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Shih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Patent number: 10283369
    Abstract: Embodiments of the invention provide a method for atomic layer etching (ALE) of a substrate. According to one embodiment, the method includes providing a substrate, and exposing the substrate to hydrogen fluoride (HF) gas and a boron-containing gas to etch the substrate. According to another embodiment, the method includes providing a substrate containing a metal oxide film, exposing the substrate to HF gas to form a fluorinated surface layer on the metal oxide film, and exposing the substrate to a boron-containing gas to remove the fluorinated surface layer from the metal oxide film. The exposures may be repeated at least once to further etch the metal oxide film.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: May 7, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Robert D. Clark, Kandabara N. Tapily
  • Patent number: 10254651
    Abstract: A coating agent capable of favorably reducing the roughness of a resist pattern and a method for forming a resist pattern in which roughness is reduced. The method includes coating the resist pattern with the coating agent. The coating agent is a composition including a resin, a quaternary carbon-atom-containing compound, and a solvent, the quaternary carbon-atom-containing compound having an aliphatic hydrocarbon group having 1 to 8 carbon atoms and a group having a specific structure having a specific amount of ethylene oxide and/or propylene oxide added thereto.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: April 9, 2019
    Assignee: TOKYO OHKA KOGYO CO., LTD.
    Inventor: Ryoji Watanabe
  • Patent number: 10234998
    Abstract: The touch display panel comprises an array substrate, a color film substrate a touch electrode layer located at a side of the color film substrate away from the array substrate, and a transparent electrically conductive layer between the color film substrate and the touch electrode layer and insulated from the touch electrode layer. The transparent electrically conductive layer comprises a first area and a second area, a thickness of the transparent electrically conductive layer in the first area is greater than a thickness of the transparent electrically conductive layer in the second area, the transparent electrically conductive layer is suitable for being electrically connected to ground. A projection area of the touch electrode layer on the color film substrate overlaps with a projection area of the transparent electrically conductive layer located in the second area on the color film substrate.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: March 19, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Bo Liu, Long Xia, Qinghua Jiang, Xiaohe Li
  • Patent number: 10224213
    Abstract: A method for forming patterns of a semiconductor device includes sequentially forming a hard mask layer, a sacrificial layer, and an anti-reflection layer on a substrate, the substrate including a cell region and a peripheral circuit region, patterning the sacrificial layer to form a first sacrificial pattern on the cell region and a second sacrificial pattern on the peripheral circuit region, forming spacers covering sidewalls of the first and second sacrificial patterns, and removing the first sacrificial pattern. The anti-reflection layer includes a lower anti-reflection layer and an upper anti-reflection layer which are formed of materials different from each other. In the patterning of the sacrificial layer, the anti-reflection layer is patterned to form a first anti-reflection pattern on the first sacrificial pattern and a second anti-reflection pattern on the second sacrificial pattern. The second anti-reflection pattern remains when the first sacrificial pattern is removed.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: March 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyungmun Byun, Sinhae Do, Badro Im
  • Patent number: 10163636
    Abstract: A method for fabricating a semiconductor device includes forming a first material layer over a substrate, forming a middle layer over the first material layer, forming a first hard mask (HM) layer over the middle layer, forming a second HM layer over the first HM layer, forming a first trench in the second HM layer that extends into the first HM layer, forming a second trench in the second HM layer, The second trench is parallel to the first trench. The method also includes forming a first hole feature in the middle layer within the first trench by using the second HM layer and the first HM layer as a mask and forming a second hole feature in the middle layer within the second trench by using the second HM layer as a mask.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yung-Sung Yen
  • Patent number: 10156789
    Abstract: The purpose of the present invention is to provide a method for stripping a resist film, which includes a cured resin having a phosphate ester group or a carboxyl group, by using a resist stripping solution having high strippability, the method being characterized in that deterioration of the strippability of the resist stripping solution is suppressed and the phosphorus concentration in the resist stripping solution is not substantially increased. In this method, a resist stripping solution is brought into contact with a resist film, which includes a cured resin having a phosphate ester group or a carboxyl group and is disposed on a metal plate, and the resist film is stripped from the metal plate. In this method, the resist stripping solution contains a benzyl alcohol, water in a mass ratio to the benzyl alcohol of 0.3-2.5, and a surfactant, and is substantially free of caustic alkali components.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: December 18, 2018
    Assignee: NISSHIN STEEL CO., LTD.
    Inventors: Masaki Satou, Seiju Suzuki, Shuichi Sugita
  • Patent number: 10147611
    Abstract: The present disclosure provides a method for preparing semiconductor structures. The method includes the following steps: A substrate is provided. A plurality of first core features spaced apart from each other is formed over the substrate. A spacer layer is formed over the first core features, and the spacer layer is formed to cover sidewalls and top surfaces of each first core feature. A plurality of second core features is formed over the substrate, and portions of the spacer layer are exposed through the second core features. A densification treatment is performed on the second core features, and the spacer layer is removed to form a plurality of openings between the first core features and the second core features.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: December 4, 2018
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Shing-Yih Shih, Cheng-Wei Wang, Tzu-Li Tseng
  • Patent number: 10103022
    Abstract: Methods of forming fins include forming mask fins on a protection layer over a seed layer. Seed layer fins are etched out of the seed layer. Self-assembled fins are formed by directed self-assembly on the seed layer fins. A three-color hardmask fin pattern that has hardmask fins of three mutually selectively etchable compositions is formed using the self-assembled fins as a mask. A region on the three-color hardmask fin pattern is masked, leaving one or more fins of a first color exposed. All exposed fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color. The mask and all fins of a second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: October 16, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John C. Arnold, Anuja E. DeSilva, Nelson M. Felix, Chi-Chun Liu, Yann A. M. Mignot, Stuart A. Sieg
  • Patent number: 10036091
    Abstract: According to some embodiments, a semiconductor manufacturing apparatus includes a first boat and a second boat, each of the first boat and the second boat having two support rings respectively provided at a top end and a bottom end thereof and a plurality of pillars provided between the top support ring and bottom support ring and spaced apart from one another. The pillar is provided with support protrusions on which a semiconductor substrate can be placed, and vertical positions of upper surfaces of the support protrusions of the second boat are lower than positions of upper surfaces of the support protrusions of the first boat. The semiconductor apparatus is configured to lift the second boat such that the positions of the upper surfaces of the support protrusions provided in the second boat are positioned above the positions of the upper surfaces of the support protrusions provided in the first boat.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: July 31, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hajime Nagano
  • Patent number: 10032631
    Abstract: A method of fabricating a mask pattern includes providing numerous masks on a substrate. A wider trench and a narrower trench are respectively defined between the mask. Subsequently, a mask material is formed to fill in the wider trench and the narrower trench. The top surface of the mask material overlapping the wider trench is lower than the top surface of the mask material overlapping the narrower trench. A photoresist layer is formed on the mask material overlapping the wider trench. Later, the mask material overlapping the narrower trench is etched while the mask material overlapping the wider trench is protected by the photoresist layer.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: July 24, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Chiang Chen, Fu-Che Lee, Ming-Feng Kuo, Hsien-Shih Chu, Cheng-Yu Wang, Yu-Chen Chuang
  • Patent number: 10032640
    Abstract: Methods of fabricating a semiconductor structure using a photoresist cross link process and a photoresist de-cross link process are described. A cross link bottom layer is employed during the fabricating process and the photoresist de-cross link process de-cross links the cross link bottom layer before the bottom layer is removed. The incorporation of the photoresist de-cross link process with the usage of the cross link bottom layer provides a cost effective and low defect level solution to fabricate the semiconductor structure.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: July 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Inc.
    Inventors: Chien-Hua Huang, Chung-Ju Lee, Ming-Hui Weng, Tzu-Hui Wei
  • Patent number: 10008542
    Abstract: In various embodiments, a method for forming a memory array includes forming a plurality of rows and columns of hardmask material, etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material, and forming memory cells in the holes. The corners of the holes can be rounded.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: June 26, 2018
    Assignee: HGST, Inc.
    Inventor: Daniel R. Shepard
  • Patent number: 9980408
    Abstract: A display apparatus includes a plurality of first brackets adhered to the rear panel. A first bracket has a recess on a first surface where an adhesive is applied, and a first protrusion extending from a second surface and a second protrusion extending from the first protrusion. A connection bracket has a side wall and a plurality of first tab portions. The tab portion is provided into an opening of the first protrusion. A second bracket is provided adjacent to the plurality of the first brackets and attached to the connection bracket. A frame is mounted to the at least one second bracket. A light source is provided between the frame and the second bracket.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: May 22, 2018
    Assignee: LG ELECTRONICS INC.
    Inventors: Jonghyun Byeon, Sunghwan Kim, Yunjoo Kim, Cheolsoo Kim, Sangdon Park, Moungyoub Lee, Hyoungsuck Oh, Deogjin Lee
  • Patent number: 9911582
    Abstract: The present disclosure provides methods and an apparatus for controlling and modifying line width roughness (LWR) of a photoresist layer with enhanced electron spinning control. In one embodiment, an apparatus for controlling a line width roughness of a photoresist layer disposed on a substrate includes a processing chamber having a chamber body having a top wall, side wall and a bottom wall defining an interior processing region, a support pedestal disposed in the interior processing region of the processing chamber, and a plasma generator source disposed in the processing chamber operable to provide predominantly an electron beam source to the interior processing region.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: March 6, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Banqiu Wu, Ajay Kumar, Kartik Ramaswamy, Omkaram Nalamasu
  • Patent number: 9899520
    Abstract: A method for forming a semiconductor device includes steps as follows: Firstly, a semiconductor substrate having a circuit element with at least one spacer formed thereon is provided. Next, an acid treatment is performed on a surface of the spacer. A disposable layer is then formed on the circuit element and the spacer. Thereafter, an etching process is performed to form at least one recess in the semiconductor substrate adjacent to the circuit element. Subsequently, a selective epitaxial growth (SEG) process is performed to form an epitaxial layer in the recess.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: February 20, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Liang Ye, Kuang-Hsiu Chen, Chueh-Yang Liu, Yu-Ren Wang
  • Patent number: 9874820
    Abstract: A method of processing semiconductor chips includes measuring locations of semiconductor dies placed on a carrier with a scanner to generate die location information. The method includes applying a dielectric layer over the semiconductor dies and communicating the die location information to a laser assembly. The method includes aligning the laser assembly with the carrier and laser structuring the dielectric layer with the laser assembly based on the die location information generated by the scanner.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: January 23, 2018
    Assignee: Intel Deutschland GMBH
    Inventor: Thorsten Meyer
  • Patent number: 9835948
    Abstract: A developing method can perform a developing process on a resist film that is exposed to light. The developing method includes forming a developing solution film by supplying a developing solution onto a surface of a substrate having thereon a resist film that is exposed to light; thinning the developing solution film by pushing out the developing solution containing components dissolved from the resist film; and supplying a new developing solution onto the thinned developing solution film.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: December 5, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Koshi Muta, Hideharu Kyoda
  • Patent number: 9818613
    Abstract: A method includes forming a mask layer over a target layer. A merge cut feature is formed in the mask layer. A first mandrel layer is formed over the mask layer and the merge cut feature. The first mandrel layer is patterned to form first openings therein. First spacers are formed on sidewalls of the first openings. The first openings are filled with a dielectric material to form plugs. The first mandrel layer is patterned to remove portions of the first mandrel layer interposed between adjacent first spacers. The merge cut feature is patterned using the first spacers and the plugs as a combined mask. The plugs are removed. The mask layer is patterned using the first spacers as a mask. The target layer is patterned, using the mask layer and the merge cut feature as a combined mask, to form second openings therein.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: November 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yan-Jhi Huang, Yu-Yu Chen
  • Patent number: 9741566
    Abstract: Embodiments herein provide apparatus and methods for performing an etching process on a spacer layer with good profile control in multiple patterning processes. In one embodiment, a method for patterning a spacer layer during a multiple patterning process includes conformally forming a spacer layer on an outer surface of a patterned structure disposed on a substrate, wherein the patterned structure has having a first group of openings defined therebetween and etching the spacer layer disposed on the substrate while forming an oxidation layer on the spacer layer.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: August 22, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Dai-Wen Tang, Hui Sun, Chung Liu, Benjamin Schwarz
  • Patent number: 9690196
    Abstract: Embodiments in accordance with the present invention encompass positive-tone, aqueous developable, self-imageable polymer compositions useful for forming films that can be patterned to create structures for microelectronic devices, microelectronic packaging, microelectromechanical systems, optoelectronic devices and displays.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: June 27, 2017
    Assignee: PROMERUS, LLC
    Inventors: Hendra Ng, Sridevi Kaiti
  • Patent number: 9690185
    Abstract: A substrate processing method performs a photolithography processing on a wafer to form a resist pattern on the wafer. Ultraviolet ray is irradiated onto the resist pattern to cut side chains of the resist pattern to improve line edge roughness of the resist pattern. A processing agent is caused to enter the resist pattern and a metal is caused to be infiltrated into the resist pattern through the processing agent. Thereafter, the wafer is heated to vaporize the processing agent from the resist pattern to form a cured resist pattern.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: June 27, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Hidetami Yaegashi
  • Patent number: 9666445
    Abstract: In order to provide a semiconductor device with high reliability while manufacturing cost is being suppressed, dry etching for an insulating film is performed by using mixed gas containing at least CF4 gas and C3H2F4 gas as its components.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: May 30, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Kotaro Horikoshi, Toshikazu Hanawa, Masatoshi Akaishi, Yuji Kikuchi
  • Patent number: 9601489
    Abstract: The described embodiments of mechanisms for placing dummy gate structures next to and/or near a number of wide gate structures reduce dishing effect for gate structures during chemical-mechanical polishing of gate layers. The arrangements of dummy gate structures and the ranges of metal pattern density have been described. Wide gate structures, such as analog devices, can greatly benefit from the reduction of dishing effect.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Chih-Chang Lin, Julie Tran, Jacklyn Chang
  • Patent number: 9576097
    Abstract: Methods and computer program products for decomposing and etching a circuit pattern layout are provided. The methods may include decomposing a circuit pattern layout into a first sub-pattern and second sub-pattern, where the decomposing includes: identifying, from the circuit pattern layout, a design line and a design via location associated with the design line; forming a first pattern line for the first sub-pattern corresponding to a first portion of the design line, and a second pattern line for the second sub-pattern corresponding to a second portion of the design line, with the first and second pattern lines overlapping at the design via location in an overlay of the first sub-pattern with the second sub-pattern. The first sub-pattern may be etched in a first circuit structure layer and the second sub-pattern etched in a second circuit structure layer, the etching at least partially forming a via at the design via location.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: February 21, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Elise Laffosse, Deniz Elizabeth Civay
  • Patent number: 9558957
    Abstract: A substrate is successively provided with a support (7), an electrically insulating layer (8), and a semi-conductor material layer (2). A first protective mask (1) completely covers a second area (B) of the semi-conductor material layer and leaves a first area (A) of the semi-conductor material layer uncovered. A second etching mask (3) partially covers the first area (A) and at least partially covers the second area (B), so as to define and separate a first area and a second area. Lateral spacers are formed on the lateral surfaces of the second etching mask (3) so as to form a third etching mask. The semi-conductor material layer (2) is etched by means of the third etching mask so as to form a pattern made from semi-conductor material in the first area (A), the first etching mask (3) protecting the second area (B).
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: January 31, 2017
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Francois Andrieu, Sebastien Barnola, Jerome Belledent
  • Patent number: 9530646
    Abstract: A method of forming a semiconductor structure includes following steps. First of all, a patterned hard mask layer having a plurality of mandrel patterns is provided. Next, a plurality of first mandrels is formed on a substrate through the patterned hard mask. Following these, at least one sidewall image transferring (SIT) process is performed. Finally, a plurality of fins is formed in the substrate, wherein each of the fins has a predetermined critical dimension (CD), and each of the mandrel patterns has a CD being 5-8 times greater than the predetermined CD.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: December 27, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Hon-Huei Liu, An-Chi Liu, Chih-Wei Wu, Jyh-Shyang Jenq, Shih-Fang Hong, En-Chiuan Liou, Ssu-I Fu, Yu-Hsiang Hung, Chih-Kai Hsu, Mei-Chen Chen, Chia-Hsun Tseng