With Formation Of Resist Image, And Etching Of Substrate Or Material Deposition Patents (Class 430/313)
  • Patent number: 10707090
    Abstract: A plasma etching method includes a first process of generating a first plasma from a first processing gas that contains fluorine-containing gas and hydrogen-containing gas, by using a first radio frequency power, to etch a laminated film including a first silicon-containing film layer and a second silicon-containing film layer that is different from the first silicon-containing film layer, with the generated first plasma; and a second process that is performed after the first process and includes generating a second plasma from a second processing gas that contains bromine-containing gas, by using a second radio frequency power, to etch the laminated film with the generated second plasma. Unevenness is formed at an interface between the first silicon-containing film layer and the second silicon-containing film layer in the first process, and the unevenness is removed in the second process.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: July 7, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Wataru Takayama, Sho Tominaga, Yoshiki Igarashi
  • Patent number: 10707213
    Abstract: A method of forming a layout of a semiconductor device includes the following steps. First line patterns extend along a first direction in a first area and a second area, but the first line patterns extend along a second direction in a boundary area. Second line patterns extend along a third direction in the first area and the second area, but the second line patterns extend along a fourth direction in the boundary area, so that minimum distances between overlapping areas of the first line patterns and the second line patterns in the boundary area are larger than minimum distances between overlapping areas of the first line patterns and the second line patterns in the first area and the second area. A trimming process is performed to shade the first line patterns and the second line patterns in the boundary area and the second area.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: July 7, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chia-Hung Wang, En-Chiuan Liou, Chien-Hao Chen, Sho-Shen Lee, Yi-Ting Chen, Jhao-Hao Lee
  • Patent number: 10699943
    Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over a target layer, forming a second mask layer over the first mask layer, patterning the second mask layer, forming a third mask layer over the patterned second mask layer, patterning the third mask layer, etching the first mask layer using both the patterned second mask layer and the patterned third mask layer as a combined etch mask, removing the patterned third mask layer to expose a portion of the first mask layer, performing a trim process on the exposed portion of the first mask layer, and etching the target layer using the first mask layer to form openings in the target layer.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yu-Lien Huang
  • Patent number: 10623635
    Abstract: A method that specifies, signals and uses coding-independent code points (CICP) in processing media contents from multiple media sources is provided. An apparatus implementing the method receives media contents captured by a plurality of media sources in one or more clusters. The apparatus processes the media contents to provide a plurality of coding-independent code points for the plurality of media sources. The apparatus also encodes the media contents to provide at least one elementary stream.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: April 14, 2020
    Assignee: MEDIATEK INC.
    Inventors: Xin Wang, Lulin Chen, Wang Lin Lai, Shan Liu
  • Patent number: 10586732
    Abstract: A method includes forming at least a first via in a multilayer structure comprising a first layer and a second layer formed over the first layer, the first via extending from a top of the second layer to a top of a first contact formed in the first layer and forming a polymer film on at least a portion of sidewalls of the first via by etching the top of the first contact using a cleaning process.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yann A. M. Mignot, Chih-Chao Yang
  • Patent number: 10553625
    Abstract: A method of manufacturing a display device, includes providing a substrate including a first stepped part, forming a metal layer on the substrate and the first stepped part, forming an organic layer pattern on the metal layer at a position corresponding to a sidewall of the stepped part, forming a photosensitive layer on the metal layer and the organic layer pattern, patterning the photosensitive layer to form a photosensitive layer pattern adjacent to the organic layer pattern, and forming a metal line by removing the organic layer pattern and an exposed portion of the metal layer through an etching process using the photosensitive layer pattern as a mask.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: February 4, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: In Kyung Yoo, Chong Sup Chang, Dong Hyun Yang
  • Patent number: 10534266
    Abstract: The disclosure herein describes methods for Photosensitized Chemically Amplified Resist Chemicals (PS-CAR) to pattern light sensitive films on a semiconductor substrate. In one embodiment, a two-step exposure process may generate higher acid concentration regions within a photoresist layer. The PS-CAR chemicals may include photoacid generators (PAGs) and photosensitizer elements that enhance the decomposition of the PAGs into acid. The first exposure may be a patterned EUV exposure that generates an initial amount of acid and photosensitizer. The second exposure may be a non-EUV flood exposure that excites the photosensitizer which increases the acid generation rate where the photosensitizer is located on the substrate. The distribution of energy during the exposures may be optimized by using certain characteristics (e.g., thickness, index of refraction, doping) of the photoresist layer, an underlying layer, and/or an overlying layer.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: January 14, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Michael A. Carcasi, Joshua S. Hooge, Benjamen M. Rathsack, Seiji Nagahara
  • Patent number: 10410875
    Abstract: A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern has hardmask fins of three mutually selectively etchable compositions. A region on the three-color hardmask fin pattern is masked, leaving one or more fins of a first color exposed. All exposed fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color. The mask and all fins of a second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: September 10, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sean D. Burns, Nelson M. Felix, Chi-Chun Liu, Yann A. M. Mignot, Stuart A. Sieg
  • Patent number: 10394125
    Abstract: A coating and developing method includes: a step that applies a resist containing a metal to a front surface of a substrate to form a resist film, and exposes the resist film; a developing step that supplies a developer to the front surface of the substrate to develop the resist film; and a step that forms, before the developing step, a first protective film on a peripheral part of the substrate on which the resist film is not formed, so as to prevent the developer from coming into contact with the peripheral part of the substrate, wherein the first protective film is formed at least on a peripheral end surface and a peripheral portion of a rear surface of the substrate in the peripheral part of the substrate.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: August 27, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Shinichiro Kawakami, Hiroshi Mizunoura
  • Patent number: 10394126
    Abstract: One of the broader forms of the present disclosure relates to a method of making a semiconductor device. The method includes exposing a photoresist layer to a radiation source and applying a hardening agent to the photoresist layer. Therefore after applying the hardening agent a first portion of the photoresist layer has a higher glass transition temperature, higher mechanical strength, than a second portion of the photoresist layer.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: August 27, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Ling Cheng, Ching-Yu Chang, Chien-Wei Wang, Yen-Hao Chen
  • Patent number: 10340364
    Abstract: Techniques for increasing Weff VFET devices are provided. In one aspect, a method of forming a fin structure includes: depositing a hardmask onto a substrate; depositing a mandrel material onto the hardmask; patterning the mandrel material along a first direction to form first mandrels; forming first spacers alongside the first mandrels; forming second mandrels in between the first mandrels; pattering the first/second mandrels along a second direction perpendicular to the first direction; forming second spacers, perpendicular to the first spacers, alongside the first/second mandrels; selectively removing the first/second mandrels leaving behind a ladder-shaped pattern formed by the first/second spacers; transferring the ladder-shaped pattern to the hardmask and then to the substrate. A method of forming a VFET device, a VFET fin structure, and a VFET device are also provided.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: July 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chen Zhang, Kangguo Cheng, Tenko Yamashita, Xin Miao, Wenyu Xu
  • Patent number: 10304700
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: May 28, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Shih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Patent number: 10283369
    Abstract: Embodiments of the invention provide a method for atomic layer etching (ALE) of a substrate. According to one embodiment, the method includes providing a substrate, and exposing the substrate to hydrogen fluoride (HF) gas and a boron-containing gas to etch the substrate. According to another embodiment, the method includes providing a substrate containing a metal oxide film, exposing the substrate to HF gas to form a fluorinated surface layer on the metal oxide film, and exposing the substrate to a boron-containing gas to remove the fluorinated surface layer from the metal oxide film. The exposures may be repeated at least once to further etch the metal oxide film.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: May 7, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Robert D. Clark, Kandabara N. Tapily
  • Patent number: 10254651
    Abstract: A coating agent capable of favorably reducing the roughness of a resist pattern and a method for forming a resist pattern in which roughness is reduced. The method includes coating the resist pattern with the coating agent. The coating agent is a composition including a resin, a quaternary carbon-atom-containing compound, and a solvent, the quaternary carbon-atom-containing compound having an aliphatic hydrocarbon group having 1 to 8 carbon atoms and a group having a specific structure having a specific amount of ethylene oxide and/or propylene oxide added thereto.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: April 9, 2019
    Assignee: TOKYO OHKA KOGYO CO., LTD.
    Inventor: Ryoji Watanabe
  • Patent number: 10234998
    Abstract: The touch display panel comprises an array substrate, a color film substrate a touch electrode layer located at a side of the color film substrate away from the array substrate, and a transparent electrically conductive layer between the color film substrate and the touch electrode layer and insulated from the touch electrode layer. The transparent electrically conductive layer comprises a first area and a second area, a thickness of the transparent electrically conductive layer in the first area is greater than a thickness of the transparent electrically conductive layer in the second area, the transparent electrically conductive layer is suitable for being electrically connected to ground. A projection area of the touch electrode layer on the color film substrate overlaps with a projection area of the transparent electrically conductive layer located in the second area on the color film substrate.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: March 19, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Bo Liu, Long Xia, Qinghua Jiang, Xiaohe Li
  • Patent number: 10224213
    Abstract: A method for forming patterns of a semiconductor device includes sequentially forming a hard mask layer, a sacrificial layer, and an anti-reflection layer on a substrate, the substrate including a cell region and a peripheral circuit region, patterning the sacrificial layer to form a first sacrificial pattern on the cell region and a second sacrificial pattern on the peripheral circuit region, forming spacers covering sidewalls of the first and second sacrificial patterns, and removing the first sacrificial pattern. The anti-reflection layer includes a lower anti-reflection layer and an upper anti-reflection layer which are formed of materials different from each other. In the patterning of the sacrificial layer, the anti-reflection layer is patterned to form a first anti-reflection pattern on the first sacrificial pattern and a second anti-reflection pattern on the second sacrificial pattern. The second anti-reflection pattern remains when the first sacrificial pattern is removed.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: March 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyungmun Byun, Sinhae Do, Badro Im
  • Patent number: 10163636
    Abstract: A method for fabricating a semiconductor device includes forming a first material layer over a substrate, forming a middle layer over the first material layer, forming a first hard mask (HM) layer over the middle layer, forming a second HM layer over the first HM layer, forming a first trench in the second HM layer that extends into the first HM layer, forming a second trench in the second HM layer, The second trench is parallel to the first trench. The method also includes forming a first hole feature in the middle layer within the first trench by using the second HM layer and the first HM layer as a mask and forming a second hole feature in the middle layer within the second trench by using the second HM layer as a mask.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yung-Sung Yen
  • Patent number: 10156789
    Abstract: The purpose of the present invention is to provide a method for stripping a resist film, which includes a cured resin having a phosphate ester group or a carboxyl group, by using a resist stripping solution having high strippability, the method being characterized in that deterioration of the strippability of the resist stripping solution is suppressed and the phosphorus concentration in the resist stripping solution is not substantially increased. In this method, a resist stripping solution is brought into contact with a resist film, which includes a cured resin having a phosphate ester group or a carboxyl group and is disposed on a metal plate, and the resist film is stripped from the metal plate. In this method, the resist stripping solution contains a benzyl alcohol, water in a mass ratio to the benzyl alcohol of 0.3-2.5, and a surfactant, and is substantially free of caustic alkali components.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: December 18, 2018
    Assignee: NISSHIN STEEL CO., LTD.
    Inventors: Masaki Satou, Seiju Suzuki, Shuichi Sugita
  • Patent number: 10147611
    Abstract: The present disclosure provides a method for preparing semiconductor structures. The method includes the following steps: A substrate is provided. A plurality of first core features spaced apart from each other is formed over the substrate. A spacer layer is formed over the first core features, and the spacer layer is formed to cover sidewalls and top surfaces of each first core feature. A plurality of second core features is formed over the substrate, and portions of the spacer layer are exposed through the second core features. A densification treatment is performed on the second core features, and the spacer layer is removed to form a plurality of openings between the first core features and the second core features.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: December 4, 2018
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Shing-Yih Shih, Cheng-Wei Wang, Tzu-Li Tseng
  • Patent number: 10103022
    Abstract: Methods of forming fins include forming mask fins on a protection layer over a seed layer. Seed layer fins are etched out of the seed layer. Self-assembled fins are formed by directed self-assembly on the seed layer fins. A three-color hardmask fin pattern that has hardmask fins of three mutually selectively etchable compositions is formed using the self-assembled fins as a mask. A region on the three-color hardmask fin pattern is masked, leaving one or more fins of a first color exposed. All exposed fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color. The mask and all fins of a second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: October 16, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John C. Arnold, Anuja E. DeSilva, Nelson M. Felix, Chi-Chun Liu, Yann A. M. Mignot, Stuart A. Sieg
  • Patent number: 10036091
    Abstract: According to some embodiments, a semiconductor manufacturing apparatus includes a first boat and a second boat, each of the first boat and the second boat having two support rings respectively provided at a top end and a bottom end thereof and a plurality of pillars provided between the top support ring and bottom support ring and spaced apart from one another. The pillar is provided with support protrusions on which a semiconductor substrate can be placed, and vertical positions of upper surfaces of the support protrusions of the second boat are lower than positions of upper surfaces of the support protrusions of the first boat. The semiconductor apparatus is configured to lift the second boat such that the positions of the upper surfaces of the support protrusions provided in the second boat are positioned above the positions of the upper surfaces of the support protrusions provided in the first boat.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: July 31, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hajime Nagano
  • Patent number: 10032631
    Abstract: A method of fabricating a mask pattern includes providing numerous masks on a substrate. A wider trench and a narrower trench are respectively defined between the mask. Subsequently, a mask material is formed to fill in the wider trench and the narrower trench. The top surface of the mask material overlapping the wider trench is lower than the top surface of the mask material overlapping the narrower trench. A photoresist layer is formed on the mask material overlapping the wider trench. Later, the mask material overlapping the narrower trench is etched while the mask material overlapping the wider trench is protected by the photoresist layer.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: July 24, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Chiang Chen, Fu-Che Lee, Ming-Feng Kuo, Hsien-Shih Chu, Cheng-Yu Wang, Yu-Chen Chuang
  • Patent number: 10032640
    Abstract: Methods of fabricating a semiconductor structure using a photoresist cross link process and a photoresist de-cross link process are described. A cross link bottom layer is employed during the fabricating process and the photoresist de-cross link process de-cross links the cross link bottom layer before the bottom layer is removed. The incorporation of the photoresist de-cross link process with the usage of the cross link bottom layer provides a cost effective and low defect level solution to fabricate the semiconductor structure.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: July 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Inc.
    Inventors: Chien-Hua Huang, Chung-Ju Lee, Ming-Hui Weng, Tzu-Hui Wei
  • Patent number: 10008542
    Abstract: In various embodiments, a method for forming a memory array includes forming a plurality of rows and columns of hardmask material, etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material, and forming memory cells in the holes. The corners of the holes can be rounded.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: June 26, 2018
    Assignee: HGST, Inc.
    Inventor: Daniel R. Shepard
  • Patent number: 9980408
    Abstract: A display apparatus includes a plurality of first brackets adhered to the rear panel. A first bracket has a recess on a first surface where an adhesive is applied, and a first protrusion extending from a second surface and a second protrusion extending from the first protrusion. A connection bracket has a side wall and a plurality of first tab portions. The tab portion is provided into an opening of the first protrusion. A second bracket is provided adjacent to the plurality of the first brackets and attached to the connection bracket. A frame is mounted to the at least one second bracket. A light source is provided between the frame and the second bracket.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: May 22, 2018
    Assignee: LG ELECTRONICS INC.
    Inventors: Jonghyun Byeon, Sunghwan Kim, Yunjoo Kim, Cheolsoo Kim, Sangdon Park, Moungyoub Lee, Hyoungsuck Oh, Deogjin Lee
  • Patent number: 9911582
    Abstract: The present disclosure provides methods and an apparatus for controlling and modifying line width roughness (LWR) of a photoresist layer with enhanced electron spinning control. In one embodiment, an apparatus for controlling a line width roughness of a photoresist layer disposed on a substrate includes a processing chamber having a chamber body having a top wall, side wall and a bottom wall defining an interior processing region, a support pedestal disposed in the interior processing region of the processing chamber, and a plasma generator source disposed in the processing chamber operable to provide predominantly an electron beam source to the interior processing region.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: March 6, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Banqiu Wu, Ajay Kumar, Kartik Ramaswamy, Omkaram Nalamasu
  • Patent number: 9899520
    Abstract: A method for forming a semiconductor device includes steps as follows: Firstly, a semiconductor substrate having a circuit element with at least one spacer formed thereon is provided. Next, an acid treatment is performed on a surface of the spacer. A disposable layer is then formed on the circuit element and the spacer. Thereafter, an etching process is performed to form at least one recess in the semiconductor substrate adjacent to the circuit element. Subsequently, a selective epitaxial growth (SEG) process is performed to form an epitaxial layer in the recess.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: February 20, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Liang Ye, Kuang-Hsiu Chen, Chueh-Yang Liu, Yu-Ren Wang
  • Patent number: 9874820
    Abstract: A method of processing semiconductor chips includes measuring locations of semiconductor dies placed on a carrier with a scanner to generate die location information. The method includes applying a dielectric layer over the semiconductor dies and communicating the die location information to a laser assembly. The method includes aligning the laser assembly with the carrier and laser structuring the dielectric layer with the laser assembly based on the die location information generated by the scanner.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: January 23, 2018
    Assignee: Intel Deutschland GMBH
    Inventor: Thorsten Meyer
  • Patent number: 9835948
    Abstract: A developing method can perform a developing process on a resist film that is exposed to light. The developing method includes forming a developing solution film by supplying a developing solution onto a surface of a substrate having thereon a resist film that is exposed to light; thinning the developing solution film by pushing out the developing solution containing components dissolved from the resist film; and supplying a new developing solution onto the thinned developing solution film.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: December 5, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Koshi Muta, Hideharu Kyoda
  • Patent number: 9818613
    Abstract: A method includes forming a mask layer over a target layer. A merge cut feature is formed in the mask layer. A first mandrel layer is formed over the mask layer and the merge cut feature. The first mandrel layer is patterned to form first openings therein. First spacers are formed on sidewalls of the first openings. The first openings are filled with a dielectric material to form plugs. The first mandrel layer is patterned to remove portions of the first mandrel layer interposed between adjacent first spacers. The merge cut feature is patterned using the first spacers and the plugs as a combined mask. The plugs are removed. The mask layer is patterned using the first spacers as a mask. The target layer is patterned, using the mask layer and the merge cut feature as a combined mask, to form second openings therein.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: November 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yan-Jhi Huang, Yu-Yu Chen
  • Patent number: 9741566
    Abstract: Embodiments herein provide apparatus and methods for performing an etching process on a spacer layer with good profile control in multiple patterning processes. In one embodiment, a method for patterning a spacer layer during a multiple patterning process includes conformally forming a spacer layer on an outer surface of a patterned structure disposed on a substrate, wherein the patterned structure has having a first group of openings defined therebetween and etching the spacer layer disposed on the substrate while forming an oxidation layer on the spacer layer.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: August 22, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Dai-Wen Tang, Hui Sun, Chung Liu, Benjamin Schwarz
  • Patent number: 9690196
    Abstract: Embodiments in accordance with the present invention encompass positive-tone, aqueous developable, self-imageable polymer compositions useful for forming films that can be patterned to create structures for microelectronic devices, microelectronic packaging, microelectromechanical systems, optoelectronic devices and displays.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: June 27, 2017
    Assignee: PROMERUS, LLC
    Inventors: Hendra Ng, Sridevi Kaiti
  • Patent number: 9690185
    Abstract: A substrate processing method performs a photolithography processing on a wafer to form a resist pattern on the wafer. Ultraviolet ray is irradiated onto the resist pattern to cut side chains of the resist pattern to improve line edge roughness of the resist pattern. A processing agent is caused to enter the resist pattern and a metal is caused to be infiltrated into the resist pattern through the processing agent. Thereafter, the wafer is heated to vaporize the processing agent from the resist pattern to form a cured resist pattern.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: June 27, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Hidetami Yaegashi
  • Patent number: 9666445
    Abstract: In order to provide a semiconductor device with high reliability while manufacturing cost is being suppressed, dry etching for an insulating film is performed by using mixed gas containing at least CF4 gas and C3H2F4 gas as its components.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: May 30, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Kotaro Horikoshi, Toshikazu Hanawa, Masatoshi Akaishi, Yuji Kikuchi
  • Patent number: 9601489
    Abstract: The described embodiments of mechanisms for placing dummy gate structures next to and/or near a number of wide gate structures reduce dishing effect for gate structures during chemical-mechanical polishing of gate layers. The arrangements of dummy gate structures and the ranges of metal pattern density have been described. Wide gate structures, such as analog devices, can greatly benefit from the reduction of dishing effect.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Chih-Chang Lin, Julie Tran, Jacklyn Chang
  • Patent number: 9576097
    Abstract: Methods and computer program products for decomposing and etching a circuit pattern layout are provided. The methods may include decomposing a circuit pattern layout into a first sub-pattern and second sub-pattern, where the decomposing includes: identifying, from the circuit pattern layout, a design line and a design via location associated with the design line; forming a first pattern line for the first sub-pattern corresponding to a first portion of the design line, and a second pattern line for the second sub-pattern corresponding to a second portion of the design line, with the first and second pattern lines overlapping at the design via location in an overlay of the first sub-pattern with the second sub-pattern. The first sub-pattern may be etched in a first circuit structure layer and the second sub-pattern etched in a second circuit structure layer, the etching at least partially forming a via at the design via location.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: February 21, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Elise Laffosse, Deniz Elizabeth Civay
  • Patent number: 9558957
    Abstract: A substrate is successively provided with a support (7), an electrically insulating layer (8), and a semi-conductor material layer (2). A first protective mask (1) completely covers a second area (B) of the semi-conductor material layer and leaves a first area (A) of the semi-conductor material layer uncovered. A second etching mask (3) partially covers the first area (A) and at least partially covers the second area (B), so as to define and separate a first area and a second area. Lateral spacers are formed on the lateral surfaces of the second etching mask (3) so as to form a third etching mask. The semi-conductor material layer (2) is etched by means of the third etching mask so as to form a pattern made from semi-conductor material in the first area (A), the first etching mask (3) protecting the second area (B).
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: January 31, 2017
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Francois Andrieu, Sebastien Barnola, Jerome Belledent
  • Patent number: 9530646
    Abstract: A method of forming a semiconductor structure includes following steps. First of all, a patterned hard mask layer having a plurality of mandrel patterns is provided. Next, a plurality of first mandrels is formed on a substrate through the patterned hard mask. Following these, at least one sidewall image transferring (SIT) process is performed. Finally, a plurality of fins is formed in the substrate, wherein each of the fins has a predetermined critical dimension (CD), and each of the mandrel patterns has a CD being 5-8 times greater than the predetermined CD.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: December 27, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Hon-Huei Liu, An-Chi Liu, Chih-Wei Wu, Jyh-Shyang Jenq, Shih-Fang Hong, En-Chiuan Liou, Ssu-I Fu, Yu-Hsiang Hung, Chih-Kai Hsu, Mei-Chen Chen, Chia-Hsun Tseng
  • Patent number: 9520298
    Abstract: The present disclosure is related to a method for treating a photoresist structure on a substrate, the method comprising producing one or more resist structures on a substrate, introducing the substrate in a plasma reactor, and subjecting the substrate to a plasma treatment at a temperature lower than zero degrees Celsius, such as between zero and ?110° C. The plasma treatment may be a H2 plasma treatment performed in an inductively coupled plasma reactor. The treatment time may be at least 30s.
    Type: Grant
    Filed: February 7, 2015
    Date of Patent: December 13, 2016
    Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU Leuven R&D
    Inventors: Peter De Schepper, Jean-Francois de Marneffe, Efrain Altamirano Sanchez
  • Patent number: 9514955
    Abstract: A method for processing a substrate includes providing the substrate including a photoresist/bottom anti-reflection coating (PR/BARC) layer, a hard mask layer, a stop layer, a carbon layer and a stack including a plurality of layers. The method includes defining a hole pattern including a plurality of holes in the PR/BARC layer using photolithography; transferring the hole pattern into the carbon layer; filling the plurality of holes in the hole pattern with oxide to create oxide pillars; using a planarization technique to remove the hard mask layer, a remaining portion of the PR/BARC layer and the stop layer; stripping the carbon layer to expose the oxide pillars; filling space between the oxide pillars with hard a mask material including metal; planarizing at least part of the hard mask material; and stripping the oxide pillars to expose the hole pattern in the hard mask material.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: December 6, 2016
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Joydeep Guha, Camelia Rusu
  • Patent number: 9508609
    Abstract: Various embodiments provide FinFETs and methods for forming the same. In an exemplary method, a semiconductor substrate having sacrificial layers formed thereon is provided. First sidewall spacers and second sidewall spacers are sequentially formed on both sides of each sacrificial layer. The sacrificial layers can be removed. A first width is measured as a distance between adjacent first sidewall spacers, and a second width is measured as a distance between adjacent second sidewall spacers. When the first width is not equal to the second width, the first sidewall spacers or the second sidewall spacers are correspondingly etched such that the first width is equal to the second width. The semiconductor substrate is etched using the first sidewall spacers and the second sidewall spacers as an etch mask, to form fins, such that a top of each fin has a symmetrical morphology.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: November 29, 2016
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Qiuhua Han
  • Patent number: 9482945
    Abstract: Provided are photoresist compositions useful in forming photolithographic patterns by a negative tone development process. Also provided are methods of forming photolithographic patterns by a negative tone development process and substrates coated with the photoresist compositions. The photoresist compositions include one or more polymer additive that contains a basic moiety and which is substantially non-miscible with a resin component of the resist. The compositions, methods and coated substrates find particular applicability in the manufacture of semiconductor devices.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: November 1, 2016
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: Jong Keun Park, Christopher Nam Lee, Cecily Andes, Deyan Wang
  • Patent number: 9460897
    Abstract: Provided is a plasma etching method of etching OCOC film in which HTO films and carbon films are alternately laminated by plasma of mixed gas containing first CF-based gas or second CF-based gas and oxygen gas using a silicon film formed on OCOC film as a mask. The etching of OCOC film includes a first etching process of etching a region spanning from the top surface to the middle of OCOC film by plasma of mixed gas containing first CF-based gas having a predetermined ratio of content of carbon to content of fluorine and oxygen gas and a second etching process of etching a region spanning from the middle of OCOC film to the lowest layer by plasma of mixed gas containing second CF-based gas having a ratio of content of carbon to content of fluorine, which is higher than the predetermined ratio of first CF-based gas, and oxygen gas.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: October 4, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Takayuki Katsunuma
  • Patent number: 9436098
    Abstract: A maskless exposure device includes an exposure head including a digital micro-mirror device. The digital micro-mirror device is configured to transmit a source beam applied from an exposure source to a substrate. A system control part is configured to control the digital micro-mirror device by using a graphic data system file. The graphic data system file includes data for forming a source electrode, a drain electrode and a channel portion disposed between the source electrode and the drain electrode. The graphic system file includes data for forming the channel portion extending in a diagonal direction with respect to a scan direction of the exposure head.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: September 6, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jung-Chul Heo, Hi-Kuk Lee, Jae-Hyuk Chang, Sang-Hyun Lee, Jung-In Park, Sang-Hyun Yun, Ki-Beom Lee, Hyun-Seok Kim, Kab-Jong Seo, Jun-Ho Sim, Byoung-Min Yun, Sang-Don Jang, Jae-Young Jang, Chang-Hoon Kim
  • Patent number: 9436094
    Abstract: A stripping solution for photolithography which can effectively strip away residual materials of a photoresist pattern and etching residual materials, and has excellent anticorrosion properties on SiO2 and a variety of metal materials; and a method for forming a pattern using the stripping solution. A prescribed basic compound is used as a counter amine of the hydrofluoric acid contained in the stripping solution for photolithography, and the stripping solution for photolithography is adjusted to a pH measured at 23° C. of not more than 6.0 or 8.5 or more.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: September 6, 2016
    Assignee: TOKYO OHKA KOGYO CO., LTD.
    Inventors: Naohisa Ueno, Daijiro Mori, Takayuki Haraguchi
  • Patent number: 9431295
    Abstract: An interconnect structure is provided that may include at least one cured permanent patterned dielectric material located on a surface of a substrate. The at least one cured permanent patterned dielectric material is a cured product of a patterned photoresist that includes a dielectric enabling element therein. The structure further includes at least one conductively filled region embedded within the at least one cured permanent patterned dielectric material.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: August 30, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Qinghuang Lin
  • Patent number: 9411237
    Abstract: In some embodiments, a method of forming an etch mask on a substrate is provided that includes (1) forming a resist layer on a substrate; (2) exposing one or more regions of the resist layer to an energy source so as to alter at least one of a physical property and a chemical property of the exposed regions; (3) performing a hardening process on the resist layer to increase the etch resistance of first regions of the resist layer relative to second regions of the resist layer, the hardening process including exposing the resist layer to one or more reactive species within an atomic layer deposition (ALD) chamber; and (4) dry etching the resist layer to remove the one or more second regions and to form a pattern in the resist layer. Other embodiments are provided.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: August 9, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Peng Xie, Christopher Dennis Bencher, Huixiong Dai, Timothy Michaelson, Subhash Deshmukh
  • Patent number: 9412614
    Abstract: A device comprises a first group of nanowires having a first pattern, a second group of nanowires having a second pattern, a third group of nanowires having a third pattern and a fourth group of nanowires having a fourth pattern, wherein the first pattern, the second pattern, the third pattern and the fourth pattern form a repeating pattern.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: August 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Feng Fu, De-Fang Chen, Yu-Chan Yen, Chia-Ying Lee, Chun-Hung Lee, Huan-Just Lin
  • Patent number: 9406509
    Abstract: Easily removable heteroatom-doped carbon-containing layers are deposited. The carbon-containing layers may be used as hardmasks. The heteroatom-doped carbon-containing hardmasks have high etch selectivity and density and also a low compressive stress, which will reduce or eliminate problems with wafer bow. Heteroatoms incorporated into the hardmask include sulfur, phosphorous, nitrogen, oxygen, and fluorine, all of which have low reactivity towards commonly used etchants. When sulfur is used as the heteroatom, the hardmask is easily removed, which simplifies the fabrication of NAND devices, DRAM devices, and other devices.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: August 2, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Pramit Manna, Abhijit Basu Mallick, Mukund Srinivasan
  • Patent number: RE46100
    Abstract: A method of fabricating a semiconductor device according to an embodiment includes forming a first pattern having linear parts of a constant line width and a second pattern on a foundation layer, the second pattern including parts close to the linear parts of the first pattern and parts away from the linear parts of the first pattern and constituting closed loop shapes independently of the first pattern or in a state of being connected to the first pattern and carrying out a closed loop cut at the parts of the second pattern away from the linear parts of the first pattern.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: August 9, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ryota Aburada, Hiromitsu Mashita, Toshiya Kotani, Chikaaki Kodama