Abstract: A method for forming a minute pattern includes forming a mask layer on an object being patterned. The mask layer is patterned to form a first mask pattern having a first width larger than a predetermined width. The first mask pattern is thermally treated to form a second mask pattern having a second width smaller than the first width. A polymer layer is formed on the second mask pattern. The polymer layer reacts with the second mask pattern to form a hardened layer on a boundary surface between the polymer layer and the second mask pattern, thereby forming a third mask pattern having a third width substantially identical to the predetermined width. The limits of the present photolithography equipment are overcome. Also, a semiconductor device having a CD of below about 100 nm is manufactured.

Abstract: The invention provides a microfabrication process which may be used to manufacture a MEMS device. The process comprises depositing one or a stack of layers on a base layer, said one layer or an uppermost layer in said stack of layers being a sacrificial layer; patterning said one or a stack of layers to provide at least one aperture therethrough through which said base layer is exposed; depositing a photosensitive layer over said one or a stack of layers; and passing light through said at least one aperture to expose said photosensitive layer.

Abstract: A method for semiconductor device feature development using a bi-layer photoresist including providing a non-silicon containing photoresist layer over a substrate; providing a silicon containing photoresist over the non-silicon containing photoresist layer; exposing said silicon containing photoresist layer to an activating light source an exposure surface defined by an overlying pattern according to a photolithographic process; developing said silicon containing photoresist layer according to a photolithographic process to reveal a portion the non-silicon containing photoresist layer; and, dry developing said non-silicon containing photoresist layer in a plasma reactor by igniting a plasma from an ambient mixture including at least oxygen, carbon monoxide, and argon.

Abstract: An apparatus for creating a conductive damascene by filling copper in a plug portion formed on an insulating film, the apparatus comprising an etching chamber 151A for etching a low-k material, a vacuum transfer chamber 153 for transferring in vacuum a sample being etched, a receiving means for receiving the transferred sample, a voltage application means, a copper barrier processing chamber 151B for performing a copper barrier process by reforming the surface of the sample through carbonizing process, nitriding process, brominating process, boride-forming process, reduction process, amorphous-forming process or a combination thereof, which is realized by making ions accelerated by voltage or neutral particles obtained by diselectrifying the accelerated ions collide against the etched surface, and a high vacuum processing chamber 151C where copper is filled in the plug portion having the etched surface with a copper barrier.

Abstract: The method of fabricating a suspended microstructure with a sloped support, comprises the steps of (a) providing a member having three stacked up layers including a first substrate layer, a second temporary layer and a third photoresist layer; (b) photolithographically transferring a sloped pattern to the third photoresist layer by means of a grey scale mask; (c) etching the second layer through the third layer resulting from step (b) to obtain a surface with at least one continuous slope with a predetermined angle with respect to the first substrate layer; (d) depositing a fourth layer on the previous layers; (e) etching the fourth layer to obtain the sloped support; (f) (i) depositing a fifth planarization layer, (ii) depositing a sixth layer, and (iii) etching the sixth layer; and (g) removing the second layer and the fifth layer to obtain the suspended microstructure with the sloped support. The invention is also concerned with a suspended microstructure fabricated by the method.

Abstract: The present invention provides radiation sensitive compositions and methods that comprise novel means for providing relief images of enhanced resolution. In one aspect the invention provides a method for controlling diffusion of photogenerated acid comprising adding a polar compound to a radiation sensitive composition and applying a layer of the composition to a substrate; exposing the composition layer to activating radiation whereby a latent image is generated comprising a distribution of acid moieties complexed with the polar compound; and treating the exposed composition layer to provide an activating amount of acid.

Abstract: A method for improving photoresist layer uniformity and fabricating a lower electrode of a trench capacitor. First, a substrate having a plurality of trenches is provided. Next, a protective photoresist layer is formed on the substrate to fill the trenches. Parts of the protective photoresist layer are removed to form first openings in trenches. A refill photoresist layer with a planar upper surface is blanketly formed to fill the first openings. The protective photoresist and/or the refill photoresist layer are recessed to leave a plurality of second openings with substantially equal depths in each of the trenches.

Abstract: The negative resist composition comprises (1) a film-forming polymer which is itself soluble in basic aqueous solutions, and contains a first monomer unit with an alkali-soluble group in the molecule and a second monomer unit with an alcohol structure on the side chain which is capable of reacting with the alkali-soluble group, and (2) a photo acid generator which, when decomposed by absorption of image-forming radiation, is capable of generating an acid that can induce reaction between the alcohol structure of the second monomer unit and the alkali-soluble group of the first monomer unit, or protect the alkali-soluble group of the first monomer unit. The resist composition can form intricate negative resist patterns with practical sensitivity and no swelling.

Abstract: A method of manufacturing a semiconductor device includes forming a silicon nitride layer on a semiconductor substrate on which a predetermined pattern is formed. The silicon nitride layer includes a plurality of bonds formed between silicon and nitrogen. A portion of the bonds formed between silicon and nitrogen is broken to form at least one free bonding site on a surface of the silicon nitride layer. A silane compound and a flow fill method are used to form a silicon oxide layer on the silicon nitride layer.

Abstract: A composition for a bottom-layer resist, having superior anti-refractivity and dry-etch resistance for use in a bi-layer resist process employing a light source at a wavelength of 193 nm or below, is disclosed.

Abstract: A process of forming a resist image in a microelectronic substrate comprises the steps of contacting the substrate with a composition first comprising carbon dioxide and a component selected from the group consisting of at least one polymeric precursor, at least one monomer, at least one polymeric material, and mixtures thereof to deposit the component on the substrate and form a coating thereon; then imagewise exposing the coating to radiation such that exposed and unexposed coating portions are formed; then subjecting the coating to a second composition comprising carbon dioxide having such that either one of the exposed or the unexposed coating portions are removed from the substrate and the other coating portion is developed and remains on the coating to form an image thereon.

Abstract: A reverse image mask is produced by initially depositing a metallic layer on a substrate. Resist is applied to the metallic layer to pattern desired features. The metallic layer is plated with a metal film, and the resist is then stripped. The metallic layer is etched using the metal film as a mask. Finally, the metal film is etched leaving the metallic layer etched in patterned areas to provide the reverse image mask.

Abstract: The invention relates to a lithographic method for producing microcomponents with component structures in the submillimeter range. According to the inventive method, a structured adhesive layer is applied to a metal layer and then a photostructured epoxy resin layer is applied to said adhesive layer. Said epoxide resin is structured by means of selective exposition and removing the unexposed zones and filling in the gaps between the resin structures with metal by electroplating. The aim of the invention is to provide an adhesive layer that is suitable for photostructured epoxy resins, especially for SU-8 resist material and that prevents the resist material from being detached. To this end, the adhesive layer consists of polyimide or a polyimide mixture.

Abstract: A process and related structure are disclosed for using photo-definable layers that may be selectively converted to insulative materials in the manufacture of semiconductor devices, including for example dynamic random access memories (DRAMs), synchronous DRAMs (SDRAMs), static RAMs (SRAMs), FLASH memories, and other memory devices. One possible photo-definable material for use with the present invention is plasma polymerized methylsilane (PPMS), which may be selectively converted into photo-oxidized siloxane (PPMSO) through exposure to deep ultra-violet (DUV) radiation using standard photolithography techniques. According to the present invention, structures may be formed by converting exposed portions of a photo-definable layer to an insulative material and by using the non-exposed portions in a negative pattern scheme, or the exposed portions in a positive pattern scheme, to transfer a pattern into to an underlying layer.

Abstract: A hybrid photolithography process for printed circuit board patterning combines two types of photoresist applications to achieve superior protection of printed circuit board (PCB) ‘plated through holes’ (PTH). In a first step, electro-deposited (ED) photoresist (also known as “ED resist”) is applied to a fully copper plated PCB including the ‘plated through holes’ to protect the outer layers and the ‘plated through holes’ from copper etchant solution. In a second step, the electro-deposited photoresist is imaged (exposed) and patterned (developed). In a third step, after developing the circuit image, a layer of Dry Film resist is applied to the panel of the PCB on top of the developed electro-deposited (ED) photoresist. This Dry Film resist layer will ‘tent’ the plated through holes by adding an extra layer of protection to the plated through holes. In a fourth step, the dry film resist is then exposed and developed.

Abstract: The invention includes methods of fabricating integrated circuitry and semiconductor processing polymer residue removing solutions. In one implementation, a method of fabricating integrated circuitry includes forming a conductive metal line over a semiconductor substrate. The conductive line is exposed to a solution comprising an inorganic acid, hydrogen peroxide and a carboxylic acid buffering agent. In one implementation, a method of fabricating integrated circuitry includes forming an insulating layer over a semiconductor substrate. A contact opening is at least partially formed into the insulating layer. The contact opening is exposed to a solution comprising an inorganic acid, hydrogen peroxide and a carboxylic acid buffering agent. In one implementation, a semiconductor processing polymer residue removing solution comprises an inorganic acid, hydrogen peroxide and a carboxylic acid buffering agent. Other aspects and implementations are contemplated.

Abstract: The invention relates to methods for producing an electrically-conductive structure on a non-planar surface (1) with the following steps:

Abstract: In an organic electroluminescent device, a plurality of striped lower electrodes are formed on an insulating substrate, and a plurality of fillers made of amorphous carbon are filled between the lower electrodes. Organic thin film layers including an emitting layer is formed on the fillers and the lower electrodes. A plurality of striped upper electrodes are formed on the organic thin film layer along a second direction different from the first direction.

Abstract: A method of forming an electrical feature such as a 3-D circuit on a substrate is described. The method includes the following steps. A catalytic paint is first selectively deposited on the surface of a molded polymer substrate to form a paint coating of the substrate. A conductive metal such as copper or nickel is then deposited onto the coating to form a plating of the substrate. An electrical feature is then obtained by forming a precision conductive pattern in the conductive metal.

Abstract: A programmable resistance memory element using a conductive sidewall layer as the bottom electrode. The programmable resistance memory material deposited over the top edge of the bottom electrode in a slot-like opening formed in a dielectric material. A method of making the opening using a silylated photoresist.

Abstract: The present invention provides a method for manufacturing a triode field emission display (FED) that can accommodate a large screen size and that has holes that are minutely and uniformly formed.

Abstract: A substrate material for LIGA applications w hose general composition is Ti/Cu/Ti/SiO2. The SiO2 is preferably applied to the Ti/Cu/Ti wafer as a sputtered coating, typically about 100 nm thick. This substrate composition provides improved adhesion for epoxy-based photoresist materials, and particularly the photoresist material SU-8.

Abstract: A laser processing apparatus comprises a laser oscillator for producing a laser beam to selectively remove part of a substrate to be processed, a scanning system for applying the laser beam to an arbitrary position of the substrate and incident means for applying the laser beam to the substrate substantially at right angle.

Abstract: The removal of defect particles that may be created during polysilicon hard mask etching, and that are embedded within the polysilicon layer, is disclosed. Oxide is first grown in the polysilicon layer exposed through the patterned hard mask layer, so that the defect particle becomes embedded within the oxide. Oxide growth may be accomplished by rapid thermal oxidation (RTO). The oxide is then exposed to an acidic solution, such as hydrofluoric (HF) acid, to remove the oxide and the embedded defect particle embedded therein.

Abstract: A microchip-based electrospray device, system, and method of fabrication thereof are disclosed. The electrospray device includes a substrate defining a channel between an entrance orifice on an injection surface and an exit orifice on an ejection surface, a nozzle defined by a portion recessed from the ejection surface surrounding the exit orifice, and an electric field generating source for application of an electric potential to the substrate to optimize and generate an electrospray. A method and system are disclosed to generate multiple electrospray plumes from a single fluid stream that provides an ion intensity as measured by a mass spectrometer that is approximately proportional to the number of electrospray plumes formed for analytes contained within the fluid. A plurality of electrospray nozzle devices can be used in the form of an array of miniaturized nozzles for the purpose of generating multiple electrospray plumes from multiple nozzles for the same fluid stream.

Abstract: A method for producing microneedles. The method including disposing a first layer of a radiation sensitive polymer on to a working surface and selectively irradiating the first layer such that the first layer has at least one irradiated region and at least one non-irradiated region. The method also including developing the first layer so as to selectively remove one of the at least one irradiated region and the at least one non-irradiated region such that, at least part of at least one remaining region at least partially defines a form of at least part of a microneedle structure. A microneedle structure including a plurality of microneedles at least partially formed from a radiation sensitive polymer.

Abstract: A method of manufacturing an integrated circuit includes a semiconductor substrate having bitlines under a charge-trapping material over a core region and a gate insulator material over a periphery region. A wordline-gate material, a hard mask, and a first photoresist are deposited and patterned over the core region while covering the periphery region. After removing the first photoresist, wordlines are formed from the wordline-gate material in the core region. An anti-reflective coating and a second photoresist are deposited and patterned over the periphery region and covering the core region. The anti-reflective coating is removable without damaging the charge-trapping material. After removing the second photoresist and the anti-reflective coating, gates are formed from the wordline-gate material in the periphery region and the integrated circuit completed.

Abstract: The invention provides a method for making ink feed vias in semiconductor silicon substrate chips for an ink jet printhead and ink jet printheads containing silicon chips made by the method. The method includes applying a first photoresist material to a first surface side of the chip. The first photoresist material is patterned and developed to define at least one ink via location therein. An etch stop material is applied to a second surface side of the chip. At least one ink via is anisotropically etched with a dry etch process through the thickness of the silicon chip up to the etch stop layer from the first surface side of the chip. As opposed to conventional ink via formation techniques, the method significantly improves the throughput of silicon chip and reduces losses due to chip breakage and cracking. The resulting chips are more reliable for long term printhead use.

Abstract: A new and improved method for measuring dimensions of a photoresist pattern profile on a wafer substrate during photolithography for the fabrication of integrated circuits on the substrate. According to one embodiment, the method includes fixing the photoresist pattern profile on the substrate using a spin-on glass (SOG) procedure. In another embodiment, the method includes fixing the photoresist pattern profile on the substrate using a sputter oxide (SO) procedure. The fixed photoresist pattern is then subjected to a microscopy procedure, typically transmission electron microscopy (TEM), to measure the exact linewidth and other dimensions of the profile. The method prevents distortion of the profile during fixation and facilitates an accurate determination of the profile dimensions.

Abstract: It is an object to provide a manufacturing process for a printed wiring board in which a copper foil and resin as a substrate material of a copper clad laminate are irradiated with carbon dioxide gas laser light to drill in both of them simultaneously. In forming a through hole or a hole such as IVH, BVH or the like in the copper clad laminate using carbon dioxide gas laser light, one of a nickel layer of 0.08 to 2 &mgr;m in thickness, a cobalt layer of 0.05 to 3 &mgr;m in thickness and a zinc layer of 0.03 to 2 &mgr;m in thickness is formed as an additional metal layer on a surface of the copper foil residing in an external layer of the copper clad laminate and thereafter, by performing laser drilling, the copper foil layer and the resin layer as a substrate material of the copper clad laminate are enabled to drill simultaneously.

Abstract: A castellation technique for improved lift-off of deposited thin film on photoresist in thin-film device processing of particular utility in the production of magnetic data transducers and recording heads. By correctly designing the edge boundary of a photoresist structure, enhanced regions of low resist edge bombardment and low deposit penetration may be achieved. These enhanced regions enable the lift-off of extra thick deposited regions that would not be otherwise achievable through the use of conventional techniques with and without castellation.

Abstract: Disclosed herein is a method for inductor An Improved Structure For the Endpiece of Tape Rule of the high frequency integrated passive devices in which a spiral inductor pattern is formed on an insulation substrate, the spiral inductor pattern is spirally coiled outwards from the center. A thick film dielectric layer made of bisbenzocyclobutene (BCB) is formed on the spiral inductor pattern. A metal layer can be formed according to under bump metallization technique (UBM). The metal layer is either formed into a continuous spirally coiled form or a spread discrete configuration. With this structure, laser trimming can be applied to the metal layer pattern so as to acquire an ideal inductance value, thereby achieving wafer level trimming and compensating the process tolerance.

Abstract: Techniques are disclosed for fabricating a device using a photolithographic process. The method includes providing a first anti-reflective coating over a surface of a substrate. A layer which is transparent to a wavelength of light used during the photolithographic process is provided over the first anti-reflective coating, and a photosensitive material is provided above the transparent layer. The photosensitive material is exposed to a source of radiation including the wavelength of light. Preferably, the first anti-reflective coating extends beneath substantially the entire transparent layer. The complex refractive index of the first anti-reflective coating can be selected to maximize the absorption at the first anti-reflective coating to reduce notching of the photosensitive material.

Abstract: A method for making a magnetic sensor for a disk drive read head, the method comprising the steps of depositing a magnetoresistive stack on a surface of a first layer of material, depositing a resist layer on a first portion of the magnetoresistive stack, removing a second portion of the magnetoresistive stack not covered by the resist layer, depositing a layer of additional material on the magnetoresistive stack, the resist material, and the surface of the first layer, removing the additional material from sidewalls of the resist material, and using a lift-off process to remove the resist material. Magnetic sensors made by the above process are also included.

Abstract: In an embodiment, a trench is formed above a via from a photo resist (PR) trench pattern in a dielectric layer. The trench is defined by two sidewall portions and base portions. The base portions of the sidewalls are locally treated by a post treatment using the PR trench pattern as mask to enhance mechanical strength of portions of the dielectric layer underneath the base portions. Seed and barrier layers are deposited on the trench and the via. The trench and via are filled with a metal layer. In another embodiment, a trench is formed from a PR trench pattern in a dielectric layer. A pillar PR is deposited and etched to define a pillar opening having a pillar surface. The pillar opening is locally treated on the pillar surface by a post treatment to enhance mechanical strength of portion of the dielectric layer underneath the pillar surface.

Abstract: Disclosed is a method for manufacturing a semiconductor device by employing a dual damascene process. After a first insulation film including a conductive pattern is formed on a substrate, at least one etch stop film and at least one insulation film are alternatively formed on the first insulation film. A via hole for a contact or a trench for a metal wiring is formed through the insulation film, and then the via hole or the trench is filled with a filling film including a water-soluble polymer. After a photoresist film is coated on the filling film, the photoresist film is patterned to form a photoresist pattern and to remove the filling film. The DOF and processing margin of the photolithography process for forming the photoresist pattern can be improved because the photoresist film can have greatly reduced thickness due to the filling film.

Abstract: Disclosed is a phase shift mask capable of assuring high-precision pattern transfer, an exposure method and apparatus using such phase shift mask, and a device manufacturing method using such phase shift mask. The phase shift mask includes a substrate having an engraved portion and a non-engraved portion, the engraved portion having a side wall and a bottom face, and a light blocking film provided in a portion of the bottom face and the side wall of the engraved portion. Specifically, the size to be defined by subtracting a thickness of the light blocking film at the side wall from a width of the engraved portion is made equal to 1.3 to 2.4 times the width of a light transmitting portion provided at the engraved portion.

Abstract: An exposure method for projecting, through a projection optical system, a predetermined pattern formed on a mask onto an object to be exposed, said exposure method comprising the steps of calculating a Zernike sensitivity coefficient that represents sensitivity of a change of image quality of the predetermined pattern to a change of a Zernike coefficient, when wave front aberration in the projection optical system is developed into a Zernike polynomial in plural point light sources that divide an effective light source area for illuminating the mask, and determining an effective light source distribution based on intensity of each point light source and the Zernike sensitivity coefficient.

Abstract: Disclosed is a technique capable of connecting patterns of a master mask easily. Integrated circuit patterns are transferred onto pattern transfer regions of a product mask by the reduced projection exposure using a plurality of IP masks. Thereafter, the patterns of the adjacent pattern transfer regions are connected by a light-shielding pattern made of an organic film, which is formed by the exposure using an energy beam.

Abstract: A method of manufacturing a semiconductor device is provided. In one example, the method includes fabricating holes and/or trenches in organosiloxane insulating film without damaging the film by ashing and without causing a problem of shape deterioration or obstacles. The method comprising forming a second insulating film and a inorganic thin film soluble to a dissolving solution on an organosiloxane insulating film, fabricating the organosiloxane insulating film using the inorganic thin film as a hard mask, and removing the hard mask after fabrication by a dissolving solution.

Abstract: In a method for forming a photoresist pattern, a method for forming a capacitor, and a capacitor manufactured using the same, a light is selectively irradiated onto a selected portion of a photoresist film formed on a substrate. An interfered light generated from the irradiated light is transmitted through other portions of the photoresist film except a ring-shaped portion of the photoresist film having a predetermined width along a boundary of the selected portion. The photoresist film is exposed using the interfered light and the light irradiated onto the selected portion. A cylindrical photoresist pattern having a minute width may be formed through developing the photoresist film. With the cylindrical pattern, the capacitor can be easily formed.

Abstract: A method of forming a conductive circuit pattern on a circuit board having a first region, on which a desired conductive circuit pattern is to be formed, and a second region. The method includes the step of applying a coating including a solution with conductive particles to the circuit board. The coating is heated to adhere the conductive particles to the circuit board. The conductive particles are removed in the second region. The second region is shielded and, with the second region shielded, a conductive film is formed on the first region.

Abstract: An improved method for forming a self-aligned twin well structure for use in a CMOS semiconductor device including providing a substrate for forming a twin well structure therein; forming an implant masking layer over the substrate to include a process surface said masking layer patterned to expose a first portion of the process surface for implanting ions; subjecting the first portion of the process surface to a first ion implantation process to form a first doped region included in the substrate; forming an implant blocking layer including a material that is selectively etchable to the implant masking layer over the first portion of the process surface; removing the implant masking layer to expose a second portion of the process surface; and, subjecting the second portion of the process surface to a second ion implantation process to form a second doped region disposed adjacent to the first doped region.

Abstract: The present invention provides a method of manufacturing a semiconductor device capable of highly detailed patterning using a resist pattern having smoothed wall surfaces and reduced roughness. The method includes the steps of: forming a resist pattern over a base layer; applying a resist pattern smoothing material onto a surface of the resist pattern, thereafter heating and developing; and etching the base layer using the smoothed resist pattern, wherein one of an application thickness and a heat temperature is adjusted so as to smooth at least wall surfaces of the resist pattern. Aspects in which a maximum opening dimension and a minimum opening dimension of the smoothed resist pattern are ±5% of a predetermined opening dimension D (nm), and an average opening dimension Dav. (nm) of the smoothed resist pattern satisfies Dav. (nm)≧D (nm)×(90/100), are preferable.

Abstract: One example of a separation-material composition for a photo-resist according to the present invention comprises 5.0 weight % of sulfamic acid, 34.7 weight % of H2O, 0.3 weight % of ammonium 1-hydrogen difluoride, 30 weight % of N,N-dimethylacetamide and 30 weight % of diethylene glycol mono-n-buthyl ether. Another example of a separation-material composition for a photo-resist according to the present invention comprises 1-hydroxyethylidene-1, 3.0 weight % of 1-diphosphonic acid, 0.12 weight % of anmonium fluoride, 48.38 weight % of H2O and 48.5 weight % of diethylene glycol mono-n-buthl ether.

Abstract: The color filter of the present invention comprises ink films colored by ink drops 140 inside openings 111 enclosed by banks 112 demarcated and formed on a substrate 110. The banks 112 have a laminar structure comprising a metal film 120 and a photosensitive organic thin film 130 from the substrate 110 side. The inks should contain a solvent having a high boiling point. The bank layer may also be configured so that the peripheral edges of the bottom surface thereof are positioned inside from the peripheral edges of the light blocking layers, so that the light blocking layers have exposed surfaces on the upper surface thereof where the bank layer is not superimposed. Thus color filters can be provided which exhibit outstanding contrast without coloring irregularities.

Abstract: A method of making a magnetic read/write head using a single lithographic step to define both a write coil and a pole tip structure. The use of a thin image resist layer over a hard reactive-ion etch mask and image transfer techniques allows very high resolution optical lithography which can accommodate formation of a very compact coil and pole structure. The use of a single high resolution lithography step on a planarized structure to define both a write pole tip and a write coil coplanar with the write pole tip avoids the problems of reflective notching associated with lithography to define the pole tip in the vicinity of non-planar features of the coil structure and also eliminates alignment inaccuracies inherent in separate lithography processes for the coil and pole.

Abstract: A dual damascene process is provided on a semiconductor substrate, having a conductive structure and a low-k dielectric layer covering the conductive structure. A first hard mask and a second hard mask are sequentially formed on the low-k dielectric layer, in which at least the hard mask contacting the low-k dielectric layer is of metallic material. Next, a first opening is formed in the second hard mask over the conductive structure, and a second opening is then formed in the first hard mask under the first opening. Afterward, the low-k dielectric layer that is not covered by the first hard mask is removed, thus a via hole is formed. Thereafter, the first hard mask that is not covered by the second hard mask is removed, and then the exposed low-k dielectric layer is removed. Thereby, a trench is formed over the via hole.

Abstract: A method of masking and etching a semiconductor substrate includes forming a layer to be etched over a semiconductor substrate. An imaging layer is formed over the layer to be etched. Selected regions of the imaging layer are removed to leave a pattern of openings extending only partially into the imaging layer. After the removing, the layer to be etched is etched using the imaging layer as an etch mask. In one implementation, an ion implant lithography method of processing a semiconductor includes forming a layer to be etched over a semiconductor substrate. An imaging layer of a selected thickness is formed over the layer to be etched. Selected regions of the imaging layer are ion implanted to change solvent solubility of implanted regions versus non-implanted regions of the imaging layer, with the selected regions not extending entirely through the imaging layer thickness.

Abstract: Disclosed is a method of attaching an optical waveguide component to a printed circuit board, which is a double-sided or a multilayer printed circuit board, through pre-bonding and main-bonding by use of an adhesive tape. Prior to being attached to the printed circuit board, the optical waveguide component is preferably subjected to a plasma surface treatment to give a surface roughness thereto. The present method is advantageous in that the optical waveguide component can be attached to the printed circuit board with improved flatness and precise alignment without causing chemical or thermal damage to the optical waveguide component.