Including Etching Substrate Patents (Class 430/323)
  • Patent number: 11990457
    Abstract: A display device includes a substrate, a plurality of pixels arrayed on the substrate, an inorganic light-emitting element provided to each of the pixels, an anode electrode electrically coupled to the inorganic light-emitting element, a transistor provided on a first surface of the substrate, and coupling wiring that couples the anode electrode and the transistor. The anode electrode protrudes from an inside to an outside of the inorganic light-emitting element in planar view from a normal direction of the substrate.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: May 21, 2024
    Assignee: Japan Display Inc.
    Inventors: Masanobu Ikeda, Yasuhiro Kanaya
  • Patent number: 11990334
    Abstract: The disclosure relates to a method for tuning stress transitions of films on a substrate. The method includes forming a stress-adjustment layer on the substrate, wherein the stress-adjustment layer includes first regions formed of a first material and second regions formed of a second material, wherein the first material includes a first internal stress and the second material includes a second internal stress, and wherein the first internal stress is different compared to the second internal stress; and forming transition regions between the first regions and the second regions, wherein the transition regions include an interface between the first material and the second material that has a predetermined slope that is greater than zero degrees and less than 90 degrees.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: May 21, 2024
    Assignee: Tokyo Electron Limited
    Inventors: Daniel Fulford, Jodi Grzeskowiak, Anton J. Devilliers
  • Patent number: 11966163
    Abstract: An imprinting photomask including: a transparent substrate; a light blocking pattern provided on the transparent substrate; and a dry film resist (DFR) pattern provided on the light blocking pattern.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: April 23, 2024
    Assignee: LG CHEM, LTD.
    Inventors: Yong Goo Son, Seung Heon Lee, Nam Seok Bae
  • Patent number: 11960203
    Abstract: A method of forming patterns on a substrate by double nanoimprint processes includes providing a first replicate mold and a second replicate mold. The first replicate mold includes numerous first patterns. The second replicate mold includes at least one second pattern. The second pattern corresponds to at least one of the first patterns. Later, a first substrate is provided. A first polymeric compound layer is coated on the first substrate. Next, the first patterns are nanoimprinted into the first polymeric compound layer. Subsequently, the first substrate is etched by taking the first polymeric compound layer as a mask. After that, a second polymeric compound layer is coated on the first substrate. Later, the second pattern is nanoimprinted into the second polymeric compound layer. Finally, the first substrate is etched by taking the second polymeric compound layer as a mask.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: April 16, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Chieh Lai, Chih-Hsien Tang
  • Patent number: 11953707
    Abstract: A multi-layer lens is disclosed which includes a plurality of dual-layer structures staked on top of one-another, wherein each dual-layer Ri of the plurality of dual-layers includes i) a first curable material having a height of ZLi cured at a predetermined curing level CA, and ii) a second curable material having a height of Zgi cured at a predetermined curing level CB.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: April 9, 2024
    Assignee: Purdue Research Foundation
    Inventors: Laura Daniela Vallejo-Melgarejo, Jose Manuel Garcia-Bravo, Brittany Ann Newell, Ronald George Reifenberger
  • Patent number: 11950372
    Abstract: Methods of making metal patterns on flexible substrates are provided. Releasable solid layer is selectively formed on a patterned surface of the flexible substrate by applying a liquid solution thereon. Metal patterns on the flexible substrate can be formed by removing the releasable solid layer after metallization. In some cases, the releasable solid layer can be transferred from the patterned surface to a transfer layer where the metal patterns are formed.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: April 2, 2024
    Assignee: 3M INNOVATION PROPERTIES
    Inventors: Henrik B. van Lengerich, Matthew S. Stay, Caleb T. Nelson, David J. Tarnowski, David J. Rowe, Edwin L. Kusilek
  • Patent number: 11932948
    Abstract: Etchant solutions, pretreatment and methods for etching electroless nickel on metallic materials are provided herein. More specifically, etchant solutions for selectively removing electroless nickel from the surface of metallic materials containing copper, and optionally as containing stainless steel, methods of etching and pretreatment are provided.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: March 19, 2024
    Assignee: Hutchinson Technology Incorporated
    Inventors: Matthew J. Horner, Gowtham V. Vangara, Douglas P. Riemer
  • Patent number: 11906763
    Abstract: A method of fabricating a blazed diffraction grating comprises providing a master template substrate and imprinting periodically repeating lines on the master template substrate in a plurality of master template regions. The periodically repeating lines in different ones of the master template regions extend in different directions. The method additionally comprises using at least one of the master template regions as a master template to imprint at least one blazed diffraction grating pattern on a grating substrate.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: February 20, 2024
    Assignee: Magic Leap, Inc.
    Inventors: Shuqiang Yang, Kang Luo, Vikramjit Singh, Frank Y. Xu
  • Patent number: 11822229
    Abstract: A reflective mask blank for EUV lithography includes: a substrate; a multilayer reflective film for reflecting EUV light; and a phase shift film for shifting a phase of EUV light, the multilayer reflective film and the phase shift film formed on or above the substrate in this order. The phase shift film includes a layer 1 including ruthenium (Ru) and at least one selected from the group consisting of oxygen (O) and nitrogen (N). Among diffraction peaks derived from the phase shift film observed at 2?: from 20° to 50° by out-of-plane XRD method, a peak having the highest intensity has a half value width FWHM of 1.0° or more.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: November 21, 2023
    Assignee: AGC Inc.
    Inventors: Daijiro Akagi, Hirotomo Kawahara, Toshiyuki Uno, Ichiro Ishikawa, Kenichi Sasaki
  • Patent number: 11803122
    Abstract: A chemically amplified photosensitive composition used for forming a patterned resist film by photolithography on a metal surface of a substrate which at least partly has a surface consisting of metal. The composition includes an acid generator which generates an acid by irradiation of active rays or radioactive rays; and a compound and/or a precursor compound, in which the molar absorption coefficient ? at a wavelength of 365 nm of the compound is at least 3000, the compound has a metal coordination group, and the compound can be formed from the precursor compound during formation of the patterned resist film.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: October 31, 2023
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Yasushi Kuroiwa, Kazuaki Ebisawa
  • Patent number: 11764133
    Abstract: Introduced here are carrier tape assemblies that can improve efficiency and reduce costs when utilized in the handling, transport, or storage of semiconductor components. A carrier tape assembly can include an adhesive film affixed to an elongated and/or extruded carrier tape. For example, the adhesive film may be integrally laminated onto the top surface of the elongate carrier tape as a single continuous (i.e., unbroken) sheet. The adhesive film may substantially conform to the top surface of the elongate carrier tape, including any punched cavities for holding semiconductor components. Proper securement of the semiconductor components to the carrier tape assembly depends on the adhesive property of the constituent material(s) of the adhesive film.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: September 19, 2023
    Assignee: Daewon Semiconductor Packaging Industrial Company
    Inventors: Sunna Chung, John Kim, Ryan Park, Denny Kwon, Matthew Whitlock, Athens Okoren
  • Patent number: 11728570
    Abstract: Electromagnetic bandgap isolation systems and methods are provided. In one example, an electromagnetic bandgap isolator device includes a base support having a curved surface. The electromagnetic bandgap isolator device further includes a metamaterial. The metamaterial includes a continuous curved layer in contact with the base support. The metamaterial is configured to absorb energy associated with a frequency range. Related systems and methods are also provided.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: August 15, 2023
    Assignee: Teledyne FLIR Surveillance, Inc.
    Inventors: Alexandre Marsolais, Patrick Lamontagne, Pierre Poitevin
  • Patent number: 11705527
    Abstract: Embodiments of the present disclosure provide for methods of making substrates having an (AR) antireflective layer, substrates having an antireflective layer, devices including a substrate having an antireflective layer, and the like. The AR layer can have a total specular reflection of less than 10% at a wavelength of about 400-800 nm, and a height of about 500-1000 nm.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: July 18, 2023
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Peng Jiang, Zhuxiao Gu, Ruwen Tan
  • Patent number: 11703760
    Abstract: A fluorocarboxylic acid-containing polymer comprising recurring units having formula (A1), but not acid labile group-containing recurring units is provided. A resist composition comprising the same offers a high sensitivity and is unsusceptible to nano-bridging or pattern collapse independent of whether it is of positive or negative tone.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: July 18, 2023
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Jun Hatakeyama, Masahiro Fukushima
  • Patent number: 11693181
    Abstract: The disclosure relates to a high-density optical waveguide structure, a printed circuit board and a preparation method thereof. The high-density optical waveguide structure comprises an undercladding layer, a core layer and an upper cladding layer in sequence; wherein, the lower cladding layer is arranged at intervals. The trench is filled with an optical waveguide material to form a core layer. The waveguide structure integrates an optical waveguide into a PCB to realize photoelectric interconnection. The waveguide structure can better achieve higher parallel interconnection density, maintain good signal integrity, reduce device and device size, and at the same time, consume less power. The structure is configured to easily dissipate heat, enabling a simpler physical architecture and design, maximizing the wiring space of printed circuit boards, facilitating the fabrication of ultra-fine wire boards; and improving the wiring density and reliability of existing manufacturing methods.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: July 4, 2023
    Assignee: TTM Technologies, Inc.
    Inventors: Xinhong Shi, Haitao Fu, Jun Zhang, Huamei Zhou, Longxiu Zhu, Marika Immonen
  • Patent number: 11673136
    Abstract: The present disclosure provides chips, devices and methods for sequencing a biomolecule. The biomolecule may be DNA, RNA. a protein, or a peptide. The chip comprises a substrate; a first and second fluid chamber; fluid channels connecting the first and second fluid chamber; a first and second electrode disposed on opposing sides of the central fluid channel and having a nanogap therebetween, wherein the width of the nanogap is modulated by confined electrochemical deposition; and a passivation layer disposed on top of the first and second electrodes and the fluid channel.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: June 13, 2023
    Assignee: Arizona Board of Regents on Behalf of Arizona State University
    Inventors: Quan Qing, Yuan Wang, Joshua Sadar
  • Patent number: 11675127
    Abstract: Embodiments herein describe optical interposers that utilize waveguides to detect light. For example, in one embodiment, an apparatus is provided that includes an optical detector having a first layer. The first layer includes at least one of polysilicon or amorphous silicon. The first layer forms a diode that includes a p-doped region and an n-doped region. The apparatus further includes a waveguide optically coupled to the diode and disposed on a different layer than the first layer.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: June 13, 2023
    Assignee: Cisco Technology, Inc.
    Inventors: Sean P. Anderson, Vipulkumar Patel
  • Patent number: 11662663
    Abstract: A composition comprising (A) a polymer comprising recurring units (a1) having a carboxyl group protected with an acid labile group and recurring units (a2) having a cyclic ester, cyclic carbonate or cyclic sulfonate structure, (B) a thermal acid generator, and (C) an organic solvent is suited to form a protective film between a substrate and a resist film. Even when a metal-containing resist film is used, the protective film is effective for preventing the substrate from metal contamination.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: May 30, 2023
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Tomohiro Kobayashi, Kenichi Oikawa, Masayoshi Sagehashi, Teppei Adachi
  • Patent number: 11656553
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a material layer over a substrate and forming a resist layer over the material layer. The method includes exposing a portion of the resist layer. The resist layer includes a photoacid generator (PAG) group, a quencher group, an acid-labile group (ALG) and a polar unit (PU). The method also includes performing a baking process on the resist layer and developing the resist layer to form a patterned resist layer. The method further includes doping a portion of the material layer by using the patterned resist layer as a mask to form a doped region. In addition, the method includes removing the patterned resist layer.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: May 23, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Yen Lin, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 11602945
    Abstract: A metallic stamp and die for the craft industry comprises a predetermined acid-etched design on a surface of a metallic plate. A first layer of a metallic paint is applied over the front and back surfaces of the metallic stamp and die. A second layer of a rubber paint is applied over the metallic paint. The metallic paint facilitates bonding of the rubber paint to the metallic plate and increases the life of the coating of the rubber paint. The rubber paint is configured to absorb and store an ink and facilitate transfer of the ink to one or more substrates, thus enabling stamping of the design on the substrate. The metallic die can be configured for a plurality of uses, such as embossing, cutting, heat-foiling, stamping, scoring, and inserting patterns or designs in a plurality of substrates.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: March 14, 2023
    Inventors: Yong Jia Chen, Earl Brohard
  • Patent number: 11603600
    Abstract: A method of manufacturing a metal mask includes providing a growth substrate with a conductive surface. Then, a cover pattern is formed on the conductive surface, which has at least one opening and an insulated surface touching the conductive surface. Next, using the cover pattern as a mask, a first electroforming is performed to form a mold part on the conductive surface. The mold part fills the opening and has a conductive pattern surface touching the conductive surface. The conductive pattern surface is flush with the insulated surface. After the first electroforming, the growth substrate is removed, while the cover pattern and the mold part are reserved. After removing the growth substrate, a second electroforming is performed to the conductive pattern surface of the mold part to form a metal pattern. Afterwards, the mold part and the cover pattern are removed from the metal pattern.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: March 14, 2023
    Assignee: DARWIN PRECISIONS CORPORATION
    Inventor: Jyun-Yi Yu
  • Patent number: 11581161
    Abstract: A method of processing a workpiece may include forming a first layer on a first side of a base layer. The base layer may be part of a substrate including a plurality of layers. The method may also include forming a second layer on the first layer. A material of the second layer may include metal. The method may also include forming an opening in the second layer, forming an opening in the first layer by etching, and removing the second layer. The method may include dry etching of the first layer.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: February 14, 2023
    Assignee: ASML Netherlands, B.V.
    Inventors: Jie Fang, Yixiang Wang, Qirong Zhang, Haojie Zhang, Jinmei Yang, Fenghui Zhu
  • Patent number: 11574812
    Abstract: A substrate treatment method of treating a substrate using a block copolymer containing a hydrophilic polymer and a hydrophobic polymer, includes: a resist pattern formation step of forming a predetermined resist pattern by a resist film on the substrate; a thin film formation step of forming a thin film for suppressing deformation of the resist pattern on a surface of the resist pattern; a block copolymer coating step of applying a block copolymer to the substrate after the formation of the thin film; and a polymer separation step of phase-separating the block copolymer into the hydrophilic polymer and the hydrophobic polymer.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: February 7, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Makoto Muramatsu, Tadatoshi Tomita, Hisashi Genjima, Gen You, Takahiro Kitano
  • Patent number: 11557515
    Abstract: Disclosed are approaches for forming a semiconductor device. In some embodiments, a method may include providing a plurality of patterning structures over a device layer, each of the plurality of patterning structures including a first sidewall, a second sidewall, and an upper surface, and forming a mask by depositing a masking material at a non-zero angle of inclination relative to a perpendicular to a plane defined by a top surface of the device layer. The mask may be formed over the plurality of patterning structures without being formed along the second sidewall. The method may further include selectively forming a metal layer along the second sidewall of each of the plurality of patterning structures.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: January 17, 2023
    Assignee: Applied Materials, Inc.
    Inventor: Sony Varghese
  • Patent number: 11515178
    Abstract: In one example, a method for wafer drying includes providing a surface of a first wafer, the surface of the first wafer including a liquid to be removed with a drying process. The method further includes replacing the liquid with a first solid film in a first processing chamber, the first solid film covering the surface of the first wafer. The method further includes transferring the first wafer from the first processing chamber to a second processing chamber. The method further includes processing the first wafer in the second processing chamber by flowing a supercritical fluid through the second processing chamber, where the supercritical fluid removes the first solid film.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: November 29, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Trace Hurd, Antonio Luis Pacheco Rotondaro, Derek William Bassett, Hitoshi Kosugi
  • Patent number: 11501977
    Abstract: A semiconductor device includes a substrate, a conductive layer, a nitride mask layer, a carbon mask layer and an anti-reflective coating stack. The conductive layer is disposed on the substrate. The nitride mask layer is disposed on the conductive layer, wherein the nitride mask layer has a first stress. The carbon mask layer is disposed on the nitride mask layer, wherein the carbon mask layer has a second stress and a difference between the second stress and the first stress is smaller than 200 MPa. The anti-reflective coating stack is disposed on the carbon mask layer.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: November 15, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chen-Hao Lien
  • Patent number: 11422464
    Abstract: A photosensitive resin composition includes electrically conductive particles (A) whose surfaces are coated with a carbon simple substance and/or a carbon compound; an alkali-soluble resin (B) containing an acid-dissociation group; and a metal chelate compound (C) wherein the metal chelate compound (C) includes at least one selected from the group consisting of Au, Ag, Cu, Cr, Fe, Co, Ni, Bi, Pb, Zn, Pd, Pt, Al, Ti, Zr, W and Mo.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: August 23, 2022
    Assignee: Toray Industries, Inc.
    Inventors: Yohei Konoshima, Mitsuhito Suwa, Yuka Yamashiki
  • Patent number: 11374203
    Abstract: An organic light-emitting diode (OLED) display panel and a mask are disclosed. The OLED display panel includes a first film layer, and a second film layer disposed on the first film layer and made of an organic material. The second film layer includes an edge slope corner formed at an acute angle less than a predetermined value. Since the edge slope corner of the second film layer is formed at the acute angle less than a predetermined value, a technical problem existing in conventional OLED display panels that edge slope corners of organic layers are formed at approximately a right angle can be mitigated.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: June 28, 2022
    Assignee: Wuhan China Star Optoelectronics Sexiconduetor Display Technology Co., Ltd.
    Inventors: Yonghui Zhang, Peng Li
  • Patent number: 11353995
    Abstract: Embodiments enhance graphic capabilities in projected-capacitive (PCAP) touch sensitive systems, and more specifically to a border component of a PCAP touchscreen. Embodiments include a method and an apparatus for a PCAP touchscreen layered structure. Some embodiments include screen printing a border component on a cover sheet, curing the border component, ablating a pattern on the border component, and screen printing one colored ink onto the pattern on the border component. In some embodiments the border layer is black, and the colored ink is coupled to a cover sheet. The pattern causes the colored ink to appear as a continuous gradient of the colored ink. In some embodiments the border component includes two or more border-layer components. At least one of the border-layer components may include an ablated pattern. Each ablated pattern may be coupled to a different colored ink.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: June 7, 2022
    Assignee: Elo Touch Solutions, Inc.
    Inventors: ShiPeng Wang, Joel C. Kent
  • Patent number: 11333968
    Abstract: An additional non-photoresist layer may be formed on patterned photoresist layers. The additional layer may be preferentially formed on the tops of the photoresist layer versus the sidewalls of the photoresist layer. In addition, the additional layer may be preferential formed on the tops of the photoresist layer versus exposed surfaces of layers underlying the photoresist layer. In this manner, the patterned structures formed by the photoresist layer are less likely to have line opens due to photoresist height variability or the relative thinness of the photoresist height used. Further, the formation of the additional layer may be through a cyclic deposition/trim process. The trim step of the cyclic process may also serve as a descum step that helps reduce line bridging and scumming. In one embodiment, the additional non-photoresist layer may be an organic polymer layer.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: May 17, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Angelique D. Raley, Eric Chih-Fang Liu, Nihar Mohanty
  • Patent number: 11307493
    Abstract: Micro- and nano-patterns in imprint layers formed on a substrate and lithographic methods for forming such layers. The layers include a plurality of structures, and a residual layer having a residual layer thickness (RLT) that extends from the surface of the substrate to a base of the structures, where the RLT varies across the surface of the substrate according to a predefined pattern.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: April 19, 2022
    Assignee: Molecular Imprints, Inc.
    Inventors: Vikramjit Singh, Kang Luo, Michael Nevin Miller, Shuqiang Yang, Frank Y. Xu
  • Patent number: 11130911
    Abstract: A compound represented by formula I, a negative liquid crystal composition comprising such a compound, and a liquid crystal display element or liquid crystal display comprising the compound or liquid crystal composition are provided. The compound represented by formula I contains two hydroxy groups. In an ODF process for a panel, due to an intermolecular force between the hydroxyl groups and the surface of the panel (a glass surface or an ITO electrode surface), the compound is spontaneously aligned, in a standing manner, on the panel glass or transparent ITO electrode substrate, causing liquid crystal molecules similar to the compound represented by formula ITO be vertically aligned, and UV light irradiation, a polymer layer with a rough surface is formed on the substrate by means of polymerization, and achieves the effects of PI insulation and vertical alignment of the liquid crystal molecules.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: September 28, 2021
    Assignee: SHIJIAZHUANG CHENGZHI YONGHUA DISPLAY MATERIAL CO., LTD.
    Inventors: Guoliang Yun, Ming Li, Jinsong Meng, Zhian Liang, Gang Wen, Zhengqiang Li
  • Patent number: 11054740
    Abstract: An imprint mold and a method for manufacturing the same are provided. The imprint mold includes a plurality of substantially identical or different mold patterns, wherein there isn't any height difference between the mold patterns.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: July 6, 2021
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Sheng-Ming Huang, Sheng-Kai Lin, Chih-Chiang Chen, Hui-Ku Chang, Chia-Hsin Chung, Wei-Chi Wang, Ming-Jui Wang, Jen-Kuei Lu, Tsai-Sheng Lo, Huang-Kai Shen
  • Patent number: 10998191
    Abstract: A patterning stack and methods are provided for semiconductor processing. The method includes forming a graded hardmask, the graded hardmask including a first material and a second material with extreme ultraviolet (EUV) absorption cross sections for absorption of EUV wavelengths, the second material configured to provide adhesion to photoresist materials. The method also includes depositing a photoresist layer over the graded hardmask. The method additionally includes patterning the photoresist layer. The method further includes etching the graded hardmask. The method also includes removing the photoresist layer.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: May 4, 2021
    Assignee: International Business Machines Corporation
    Inventors: Jennifer Church, Ekmini A. De Silva, Dario Goldfarb
  • Patent number: 10872760
    Abstract: A cluster tool includes a polyhedral transfer chamber, at least one processing chamber, at least one load lock chamber, and an electron beam (e-beam) source. The processing chamber is connected to the polyhedral transfer chamber. The processing chamber is configured to perform a manufacturing procedure to a wafer present therein. The load lock chamber is connected to the polyhedral transfer chamber. The e-beam source is configured to performing an e-beam treatment to the wafer after the wafer is performed the manufacturing procedure.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Han-Wen Liao
  • Patent number: 10866362
    Abstract: A system and method for manufacturing semiconductor devices is provided. An embodiment comprises using an etchant to remove a portion of a substrate to form an opening with a 45° angle with a major surface of the substrate. The etchant comprises a base, a surfactant, and an oxidant. The oxidant may be hydrogen peroxide.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yu Lee, Ying-Hao Kuo, Hai-Ching Chen, Tien-l Bao
  • Patent number: 10840338
    Abstract: A semiconductor device includes a substrate and a graphene layer. The substrate includes an insulator and a semiconductor. The graphene layer is grown on a surface of the semiconductor. The semiconductor includes at least one of a group IV material and a group III-V compound. A method of manufacturing the semiconductor device is disclosed.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: November 17, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keunwook Shin, Hyeonjin Shin, Yeonchoo Cho, Seunggeol Nam, Seongjun Park, Yunseong Lee
  • Patent number: 10773542
    Abstract: The present disclosure relates to a method for manufacturing decorative panels made of flat glass for electronic household appliances, in particular household appliances that are fixed in position. The method comprises, in the specified order, at least the steps of providing a flat glass, producing a blank decorative panel by forming the provided flat glass with at least one of the steps of forming the outer contour of the decorative panel, edge treatment, or making at least one indentation on the operational front, the thermal tempering of the produced blank decorative panel, and applying at least one decorative print on the operational back of the thermally tempered blank decorative panel by means of a digital printing method.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: September 15, 2020
    Assignees: Schott Gemtron Corp., Schott AG
    Inventors: Adam O'Ryan, Carsten Schwabe, Grant Mason
  • Patent number: 10658179
    Abstract: Aspects of the disclosure provide a method. The method includes providing a substrate having a structure formed on the substrate, and forming a spacer layer on the structure. Then, the method includes forming a mask layer over the spacer layer. The mask layer includes a first layer, a second layer over the first layer, and a third layer over the second layer. Further, the method includes patterning the third layer of the mask layer, and etching the first layer and the second layer of the mask layer with a dry etching process using the third layer as an etch mask to form an opening that exposes a portion of the spacer layer. Then, the method includes removing the second layer using a wet etchant before a formation of a backfill material layer in the opening and over the first layer.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nai-Chia Chen, Wan Hsuan Hsu, Chia-Wei Wu, Neng-Jye Yang, Chun-Li Chou
  • Patent number: 10625289
    Abstract: A mask and a method of manufacturing a mask assembly, the mask including a body, and the body including one end and another end facing each other in a length direction and having a first surface and a second surface facing each other in a thickness direction; and a pattern region between the one end and the other end, the pattern region including a plurality of pattern holes and a plurality of ribs between the plurality of pattern holes, wherein a curl value of the mask, which is defined as a shortest distance from a plane tangent to a center of the body to the one end or the other end of the body, is 1,000 ?m to 4,000 ?m.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: April 21, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Su Cheol Gong, Min Goo Kang, Taek Kyo Kang, Jung Woo Ko, Min Ju Kim, Young Eun Ryu, Jae Suk Moon, Soo Hyun Min
  • Patent number: 10613438
    Abstract: Lithographic patterning methods are provided which implement directed self-assembly (DSA) of block copolymers to enable self-aligned cutting of features. A first layer and second layer of material are formed on a substrate. The second layer of material is lithographically patterning to form a guiding pattern. A DSA process is performed to form a block copolymer pattern around the guiding pattern, which comprises a repeating block chain that includes at least a first block material and a second block material, which have etch selectivity with respect to each other. A selective etch process is performed to selectively etching one of the first block material and the second block material to form self-aligned openings in the block copolymer pattern which expose portions of the first layer of material. The first layer of material is patterned by etching the exposed portions of the first layer of material.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sean D. Burns, Sivananda K Kanakasabapathy, Kafai Lai, Chi-Chun Liu, Kristin Schmidt, Ankit Vora
  • Patent number: 10581003
    Abstract: Methods for patterning highly sensitive materials, such as organic materials, organic semiconductors, biomolecular materials, and the like, with photolithographic resolution are disclosed. In some embodiments, a germanium mask (304) is formed on the surface of the sensitive material (302), thereby protecting it from subsequent processes that employ harsh chemicals that would otherwise destroy the sensitive material (302). A microlithography mask (306) is patterned on the germanium mask layer (304), after which the germanium exposed by the microlithography mask (306) is removed by dissolving it in water. After transferring the pattern of the germanium mask (304) into the sensitive material (302), the germanium and microlithography masks (304, 306) are completely removed by immersing the substrate in water, which dissolves the remaining germanium and lifts off the microlithography mask material.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: March 3, 2020
    Assignee: The Board of Trustee of the Leland Stanford Junior Universtiy
    Inventors: Nicholas Alexander Melosh, Matt R. Angle, Mina-elraheb S. Hanna, Yifan Kong
  • Patent number: 10453812
    Abstract: Techniques that can assist with fabricating a semiconductor package that includes a zero misalignment-via (ZMV) and/or a trace formed using a polarization process are described. The disclosed techniques can result in creation of ZMVs and/or traces between the ZMVs using a process comprising application of polarized light to one or more resist layers (e.g., a photoresist layer, etc.). One embodiment of a technique includes modulating an intensity of light applied to one or more resist layers by interaction of a light source with a photomask and at least one polarizer such that one or more patterns are created on the one or more resist layers. One embodiment of another technique includes creating patterns on one or more resist layers with different types of polarized light formed from a photomask and at least one polarizer. The disclosed techniques can assist with reducing manufacturing costs, reducing development time, and increasing I/O density.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: October 22, 2019
    Assignee: Intel Corporation
    Inventors: Hiroki Tanaka, Aleksandar Aleksov, Sri Ranga Sai Boyapati, Robert A. May, Kristof Darmawikarta
  • Patent number: 10438797
    Abstract: Techniques herein include an etch process that etches a layer of material incrementally, similar to mono-layer etching of atomic layer etching (ALE), but not necessarily including self-limiting, mono-layer action of ALE. Such techniques can be considered as quasi-atomic layer etching (Q-ALE). Techniques herein are beneficial to precision etching applications such as during soft-mask open. Techniques herein enable precise transfer of a given mask pattern into an underlying layer. By carefully controlling the polymer deposition relative to polymer assisted etching through its temporal cycle, a very thin layer of conformal polymer can be activated and used to precisely etch and transfer the desired patterns.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: October 8, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Hongyun Cottle, Andrew W. Metz
  • Patent number: 10409164
    Abstract: A heat-reactive resist material contains copper oxide, and silicon or silicon oxide, and is formed so that the content of silicon or silicon oxide in the heat-reactive resist material is 4.0 mol % or more less than 10.0 mol % in terms of mole of silicon. A heat-reactive resist layer is formed using the heat-reactive resist material, is exposed, and then, is developed with a developing solution. Using the obtained heat-reactive resist layer as a mask, dry etching is performed on a substrate with a fluorocarbon to manufacture a mold having a concavo-convex shape on the substrate surface. At this point, it is possible to control a fine pattern comprised of the concavo-convex shape.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: September 10, 2019
    Assignee: ASAHI KASEI KABUSHIKI KAISHA
    Inventors: Yoshimichi Mitamura, Takuto Nakata
  • Patent number: 10395899
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a first film on a substrate. The method further includes housing the substrate provided with the first film in a chamber, and introducing a first gas into the chamber. The method further includes generating plasma discharge of the first gas in the chamber or applying radiation to the first gas in the chamber. The method further includes introducing a second gas containing a metal component into the chamber to cause the metal component to infiltrate into the first film after the generation of the plasma discharge or the application of the radiation is started.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: August 27, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Ryuichi Saito, Seiji Morita, Ryosuke Yamamoto
  • Patent number: 10381423
    Abstract: A mask frame assembly for an electronic display device includes a frame, and a mask coupled to the frame, in which the mask includes a pattern hole defining a first area over which material may be deposited, and a dam surrounding the pattern hole and defining a second area smaller than the first area over which the material may be deposited. A method of manufacturing a mask frame assembly for an electronic display device is also disclosed.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: August 13, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventor: Sungwoo Jung
  • Patent number: 10372039
    Abstract: A resist underlayer film forming composition for lithography for a resist underlayer film usable as a hardmask. A resist underlayer film forming composition for lithography, including: as a silane, a hydrolyzable silane, a hydrolysis product thereof, or a hydrolysis-condensation product thereof, wherein the hydrolyzable silane includes a hydrolyzable silane of Formula (1) or a hydrolyzable silane containing a combination of a hydrolyzable silane of Formula (1) with a hydrolyzable silane of Formula (2), and a content of the hydrolyzable silane of Formula (1) or the hydrolyzable silane containing a combination of a hydrolyzable silane of Formula (1) with a hydrolyzable silane of Formula (2) in all silanes is less than 50% by mole, R1aR2bSi(R3)4?(a+b)??Formula (1) R4a1R5b1Si(R6)4?(a1+b1)??Formula (2).
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: August 6, 2019
    Assignee: NISSAN CHEMICAL INDUSTRIES, LTD.
    Inventors: Yuta Kanno, Makoto Nakajima, Satoshi Takeda, Hiroyuki Wakayama
  • Patent number: 10323159
    Abstract: An organic layer composition includes a first compound having a thermal shrinkage ratio of about 10% to about 70%, a second compound having a smaller thermal shrinkage ratio than the first compound, and a solvent, and an organic layer obtained by curing the organic layer composition and a method of forming patterns using the organic layer composition are disclosed. A method of measuring the thermal shrinkage ratio is described in the detailed description.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: June 18, 2019
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Minsoo Kim, Younhee Nam, Jaeyeol Baek, Hyunji Song, Byeri Yoon, Seulgi Jeong, Seunghee Hong, Sunmin Hwang
  • Patent number: 10266471
    Abstract: A phenolic hydroxyl-containing compound is provided. The compound dissolves well in solvents and can be formulated into compositions that give coatings superior in thermal decomposition resistance, alkali developability, resolution, and dry-etch resistance. Specifically, the compound is a phenolic hydroxyl-containing calixarene represented by structural formula (1): (where A is a structural unit including a dihydroxynaphthalene- or naphthol-derived structure optionally with a substituent alkyl, alkoxy, aryl, or aralkyl group or halogen atom on the aromatic rings and a methylene group optionally having an alkyl or aryl group in place of one of the hydrogen atoms) and obtained using a dihydroxynaphthalene in combination with a naphthol, with the total repeat number p being an integer of 2 to 10.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: April 23, 2019
    Assignee: DIC Corporation
    Inventors: Tomoyuki Imada, Norio Nagae