Forming Nonplanar Surface Patents (Class 430/322)
  • Patent number: 11415887
    Abstract: A resist composition comprising a base polymer and a quencher in the form of a salt of a cyclic ammonium cation with a carboxylate, sulfonamide, halogenated phenoxide or halide anion offers a high sensitivity and minimal LWR or improved CDU, independent of whether it is of positive or negative tone.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: August 16, 2022
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Jun Hatakeyama, Masaki Ohashi, Takayuki Fujiwara
  • Patent number: 11360348
    Abstract: The present disclosure relates to a liquid crystal display (LCD) system. The system in one example has a light source for generating unpolarized light, and an LCD screen arranged in a path of transmittance of the unpolarized light. First and second wire grid polarizers are arranged adjacent to the LCD screen and each have a plurality of nano-scale wires, with the first and second wire grid polarizers have differing polarizations. A pitch of each of the nano-scale wires is no larger than one-third a wavelength of the unpolarized light from the light source. The wire grid polarizers create, in connection with operation of the LCD screen, a 2D light mask suitable for initiating the polymerization of an optically curable material.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: June 14, 2022
    Assignees: Lawrence Livermore National Security, LLC, Board of Regents, The University of Texas System
    Inventors: Eric B. Duoss, James Oakdale, Nicholas Anthony Rodriguez, Hongtao Song, Richard Crawford, Carolyn Seepersad, Morgan Chen
  • Patent number: 11340510
    Abstract: A method of manufacturing a thin film is provided. The method includes providing a plurality of crystalline cathodic electrochromic particles comprising an alkali metal oxide material, size-reducing the crystalline cathodic electrochromic particles by grinding to produce crystalline cathodic electrochromic nanostructures, providing a substrate, and coating the crystalline cathodic electrochromic nanostructures onto the substrate to produce a thin film, wherein the thin film is an electrochromic thin film.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: May 24, 2022
    Assignee: HALIO, INC.
    Inventors: John Roudebush, Daniel Giaquinta, Howard Turner, Julian Bigi
  • Patent number: 11244991
    Abstract: This disclosure relates to a production method of a display substrate, a display substrate, and a display apparatus. This production method comprises steps of: forming a thin film for a pixel defining layer used to define a light-emitting area of each sub-pixel on a base substrate; forming nanoparticles in a preset area of the thin film for the pixel defining layer, wherein the preset area is an area corresponding to a place between adjacent sub-pixels; and performing patterning treatment on the thin film for the pixel defining layer formed with the nanoparticles, with a material in the preset area being retained, to form a pattern of the pixel defining layer.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: February 8, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Wenjun Hou
  • Patent number: 11221559
    Abstract: A photomask including a photomask body having a surface on which a mask pattern is formed and to be scanned and subjected to pattern transfer to a resist through a lens assembly including a connecting portion and a non-connecting portion. The mask pattern has a first region subjected to the pattern transfer at the connecting portion of the lens assembly and a second region subjected to the pattern transfer at the non-connecting portion. The mask pattern has, in at least one of the first and second regions, a corrected line width which is adjusted by calculation such that the resist is to have a target line width as designed. The corrected line width has a stepwise change in at least one of a scanning direction and a direction orthogonal to the scanning direction. The stepwise change is made by including a correction component based on a random number.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: January 11, 2022
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventors: Akihito Okumura, Hiroaki Miyaji
  • Patent number: 11221476
    Abstract: A microscope directs light through an excitation objective to generate a lattice light sheet (LLS) within a sample. A detection objective collects signal light from the sample in response to the LLS and images the collected light onto a detector. Second and third light beams are imaged onto focal planes of the excitation objective and detection objective, respectively. One or more wavefront detectors determine wavefronts of light emitted from the sample and through the excitation objective in response to the imaged second light beam and emitted from the sample through the detection objective in response to the imaged third light beam. A wavefront of the first light beam is modified to reduce a sample-induced aberration of the LLS within the sample, and a wavefront of the signal light emitted from the sample is modified to reduce a sample-induced aberration of the signal light at the detector.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: January 11, 2022
    Assignee: Howard Hughes Medical Institute
    Inventors: Robert Eric Betzig, Tsung-Li Liu, Daniel E. Milkie, Kai Wang, Wesley Legant
  • Patent number: 11175597
    Abstract: A lithography patterning system includes a reticle having patterned features, a pellicle having a plurality of openings, a radiation source configured for emitting radiation to reflect and/or project the patterned features, and one or more mirrors configured for guiding reflected and/or projected patterned features onto a wafer. The pellicle is configured to protect the reticle against particles and floating contaminants. The plurality of openings include between 5% and 99.9% of lateral surface area of the pellicle. The pellicle can be attached to the reticle on a side of the patterned features, placed beside an optical path between the radiation source and the wafer, or placed in an optical path between mirrors and the radiation source. The plurality of openings in the pellicle are formed by a plurality of bar shaped materials, or formed in a honey comb structure or a mesh structure.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: November 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Ming Chang, Chiu-Hsiang Chen, Ru-Gun Liu, Minfeng Chen
  • Patent number: 11094541
    Abstract: In accordance with an embodiment a bottom anti-reflective layer comprises a surface energy modification group which modifies the surface energy of the polymer resin to more closely match a surface energy of an underlying material in order to help fill gaps between structures. The surface energy of the polymer resin may be modified by either using a surface energy modifying group or else by using an inorganic structure.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: August 17, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yu-Chung Su, Ching-Yu Chang
  • Patent number: 11086218
    Abstract: In accordance with some aspects of the present disclosure, a maskless interferometric lithography system for fabricating a three-dimensional (3D) photonic crystal using a multiple two-beam-exposures is disclosed. The system can comprise an illumination system comprising an optical arrangement operable to receive radiation from a radiation source and provide three or more tilted two-beam interference pattern exposures to be combined into a three-dimensional pattern; and a substrate operable to be supported by a substrate table, wherein the substrate comprises a photoresist formed on a top surface of the substrate and operable to receive the three-dimensional pattern and wherein means are provided to adjust the position of the substrate in all six mechanical degrees of freedom.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: August 10, 2021
    Inventors: Steven R.J. Brueck, Alexander K. Raub
  • Patent number: 11073756
    Abstract: A photomask blank is provided comprising a transparent substrate, a first film of chromium-containing material on the substrate, and a second film of silicon/oxygen-containing material disposed contiguous to the first film. The second film includes a first layer contiguous to the first film and a second layer spaced apart from the first layer in film thickness direction. The oxygen content of the first layer is lower than the oxygen content of the second layer. During etching of the first film, this setting prevents an etching rate from ramping up at the interface between the first and second films.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: July 27, 2021
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Takuro Kosaka, Hideo Kaneko, Shigeo Irie, Naoki Kawaura
  • Patent number: 11067816
    Abstract: Disclosed are systems and methods for achieving sub-diffraction limit resolutions in lithography. In one embodiment, a lithography system is disclosed. The system includes, a first light source, configured to generate excitation laser beams; a second light source, configured to generate depletion laser beams; one or more scattering mediums configured to receive one or more of the excitation laser beams and depletion laser beams and scramble the laser beams; one or more wave-front shaping modules, configured to receive the scrambled laser beams, descramble the laser beams and generate one or more focused laser beams; a numerical aperture device configured to receive the one or more focused laser beams and generate a focused point on a substrate.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: July 20, 2021
    Assignee: Vathys, Inc.
    Inventor: Tapabrata Ghosh
  • Patent number: 11067896
    Abstract: A method of optimizing a lithographic process for semiconductor fabrication includes determining that a semiconductor wafer experienced a photoresist exposure delay. At least one operating parameter of a post exposure baking process is adjusted based on the semiconductor wafer having experienced the photoresist exposure delay. The post exposure baking process is performed on the semiconductor wafer utilizing the adjusted at least one operating parameter.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: July 20, 2021
    Assignee: International Business Machines Corporation
    Inventors: Cody John Murray, Ekmini Anuja De Silva, Alex Richard Hubbard, Karen Elizabeth Petrillo, Nelson Felix
  • Patent number: 10969702
    Abstract: An EUV lithography apparatus may include a light source, an EUV mask and a carbon-based optical filter. The light source may generate an EUV light. The EUV mask may be configured to apply the EUV light to a photoresist film on a substrate. The carbon-based optical filter may filter a light having an OoB wavelength in the EUV light. Thus, the EUV light may not include the light having the OoB wavelength to decrease an error of a photoresist pattern formed using the EUV light.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: April 6, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eokbong Kim, Mun ja Kim
  • Patent number: 10916414
    Abstract: The disclosure features systems and methods that include: exposing a biological sample to an ion beam that is incident on the sample at a first angle to a plane of the sample by translating a position of the ion beam on the sample in a first direction relative to a projection of a direction of incidence of the ion beam on the sample; after each translation of the ion beam in the first direction, adjusting a focal length of an ion source that generates the ion beam; and measuring and analyzing secondary ions generated from the sample by the ion beam after adjustment of the focal length to determine mass spectral information for the sample, where the sample is labeled with one or more mass tags and the mass spectral information includes populations of the mass tags at locations of the sample.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: February 9, 2021
    Assignee: IONpath, Inc.
    Inventors: Harris Fienberg, David Stumbo, Michael Angelo, Rachel Finck
  • Patent number: 10886199
    Abstract: A method of producing a molded semiconductor package includes: attaching a first load terminal at a first side of a semiconductor die to a leadframe, the semiconductor die having a second load terminal at a second side opposite the first side and a control terminal at the first side or the second side; encapsulating the semiconductor die in a laser-activatable mold compound so that the leadframe is at least partly exposed from the laser-activatable mold compound at a first side of the molded semiconductor package, and the second load terminal is at least partly exposed from the laser-activatable mold compound at a second side of the molded semiconductor package opposite the first side; and laser activating a first region of the laser-activatable mold compound to form a first laser-activated region which forms part of an electrical connection to the second load terminal.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: January 5, 2021
    Assignee: Infineon Technologies AG
    Inventors: Chau Fatt Chiang, Swee Kah Lee, Josef Maerz, Thomas Stoek, Chee Voon Tan
  • Patent number: 10879534
    Abstract: Systems for the production of graphene oxide sheets are provided. The systems include electro-deposition and spray deposition techniques. The graphene oxide sheets may be used as pre-cursors for the formation of porous graphene network (PGN) anodes and lithiated porous graphene (Li-PGN) cathodes. The method of making PGN electrodes includes thermally reducing a pre-cursor sheet of graphene oxide to provide a PGN anode and exposing the sheet to lithium or a lithium-containing compound to produce a Li-PGN cathode. The Li-PGN cathode and PGN anode may be combined with an electrolyte to provide an “all-carbon” battery that is useful in various applications, such as automotive applications.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: December 29, 2020
    Assignee: Rensselaer Polytechnic Institute
    Inventors: Rahul Mukherjee, Nikhil Koratkar, Eklavya Singh
  • Patent number: 10825989
    Abstract: A vapor deposition mask includes a metal mask and a resin mask having an opening. An inner wall surface for composing the opening has an inflection point in a thicknesswise cross section of the resin mask. When an intersection of a first surface, not facing the metal mask, of the resin mask and the inner wall surface is set to be a first intersection, an intersection of a second surface, facing the metal mask, of the resin mask and the inner wall surface is set to be a second intersection, and there is set a first inflection point first positioned from the first intersection toward the second intersection, an angle formed by a line connecting the first intersection and the first inflection point and the first surface is larger than an angle formed by a line connecting the first inflection point and the second intersection and the second surface.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: November 3, 2020
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Toshihiko Takeda, Katsunari Obata, Hiroshi Kawasaki
  • Patent number: 10804221
    Abstract: In one embodiment, a substrate treatment apparatus includes a substrate holder configured to hold a substrate provided with a film. The apparatus further includes a film treatment module configured to treat the film in accordance with warpage of the substrate such that the film includes a first region having a first film quality or a first film thickness and a second region having a second film quality or a second film thickness different from the first film quality or the first film thickness.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: October 13, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Fuyuma Ito, Yasuhito Yoshimizu, Hakuba Kitagawa
  • Patent number: 10796948
    Abstract: A pattern forming method includes forming a first resist pattern on a substrate using imprint lithography. And forming a resist onto the substrate at least at positions corresponding to a second resist pattern and then curing the resist to form the second resist pattern on the substrate.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: October 6, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Anupam Mitra, Tetsuro Nakasugi, Kazuhiro Takahata
  • Patent number: 10782311
    Abstract: Imaging of complex, non-stationary three dimensional (3D) flow velocities is achieved by encoding depth into color. A flow volume 22 is illuminated with a continuum 40 of light planes 42 whereby each depth corresponds to a respective light plane 14 having a specific wavelength of light. A diffractive component 46 in the camera 24 optics, which records the trajectories of illuminated particles 20 within the flow volume 22, ensures that all light planes 42 are in focus simultaneously. The setup permits a user to track 3D trajectories of particles 20 within the flow volume 22 by combining two dimensional (2D) spatial and one dimensional (1D) color information. For reconstruction, an image formation model for recovering stationary 3D particle positions is provided. 3D velocity estimation is achieved with a variant of a 3D optical flow approach that accounts for both physical constraints as well as the color (rainbow) image formation model.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: September 22, 2020
    Assignee: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Wolfgang Heidrich, Jinhui Xiong, Xiong Dun, Ramzi Idoughi, Sigurdur Tryggvi Thoroddsen, Andres A. Aguirre-Pablo, Abdulrahman B. Aljedaani, Erqiang Li
  • Patent number: 10770303
    Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Ming-Feng Shieh, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 10737437
    Abstract: A method and apparatus for making a three-dimensional object by solidifying a photohardenable material are shown and described. A photohardening inhibitor is admitted into a surface of a photohardenable material through a flexible film to create a “dead zone” where little or no solidification occurs. The dead zone prevents the exposed surface of the photohardenable material from solidifying in contact with the film. The inhibitor causes the film to deform along the build axis, thereby creating a non-planar interface between the photohardednable material and the film. A method is provided to compensate the three-dimensional object data based on the deformation of the film.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: August 11, 2020
    Assignee: Global Filtration Systems
    Inventors: Ali El-Siblani, Mohamad Janbain, Alexander Nam
  • Patent number: 10725374
    Abstract: A template substrate includes a pedestal portion on a first surface of a substrate. The template substrate defines an opening region provided in a second surface opposite to the first surface of the substrate. The opening region includes an opening end on a second surface side of the opening region corresponding to the second surface and a bottom surface on a first surface side of the opening region corresponding to the first surface. An area of the opening end is different from an area of the bottom surface.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: July 28, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Anupam Mitra
  • Patent number: 10725371
    Abstract: A method of manufacturing a substrate of a display device is provided. The method includes: providing a substrate body; coating a photoresist layer on the substrate body; exposing the photoresist layer by using a plurality lenses of an exposure machine through a mask, wherein the mask includes a light incident region and a light overlap region, the light overlap region includes a transparent zone and a non-transparent zone, and the light incident region includes a transparent zone and a non-transparent zone, and wherein an area of each transparent zone of the light overlap region is larger or smaller than an area of each transparent zone of the light incident region; and developing the photoresist layer after exposing to obtain a photoresist pattern. The embodiment of the disclosure also provides a mask applied to the method.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: July 28, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Kun Yang, Xing Wang
  • Patent number: 10703016
    Abstract: In one instance, a method of manufacturing an integrated circuit includes a method for dicing a semiconductor wafer that includes disposing the semiconductor wafer on a moveable cutting table, cutting the semiconductor wafer, and ejecting a clearing fluid across an exposed side of the semiconductor wafer, with full coverage across the semiconductor wafer, at least during the cutting of the semiconductor wafer. The ejecting clearing fluid is ejected to form a layer or membrane of fluid that clears or reduces other fluids from the exposed side or surface of the semiconductor wafer. Other aspects are presented.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: July 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chi-Hung Chen, Tung-Mei Tien, Hung-Yu Wang
  • Patent number: 10693105
    Abstract: An OLED packaging method is provided, in which a first outer bound confinement layer is first formed and then, a first organic layer is formed on the first inorganic layer in an area enclosed by the first outer bound confinement layer so that facilities for forming the first organic layer can be diversified and an organic material used to form the first organic layer is not subjected to constraint in respect of viscosity thereof, whereby using an organic material with a reduced viscosity allows for better homogeneity of the first organic layer, the thickness reduced, and thus helping reduce a curving radius of the OLED package structure to realize rollable displaying with a reduced curving radius. Further, the first outer bound confinement layer helps block external moisture and oxygen from corroding the first organic layer in a sideway direction.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: June 23, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jiangjiang Jin, Hsianglun Hsu
  • Patent number: 10670971
    Abstract: An imprint lithography method of configuring an optical layer includes selecting one or more parameters of a nanolayer to be applied to a substrate for changing an effective refractive index of the substrate and imprinting the nanolayer on the substrate to change the effective refractive index of the substrate such that a relative amount of light transmittable through the substrate is changed by a selected amount.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: June 2, 2020
    Assignee: Magic Leap, Inc.
    Inventors: Vikramjit Singh, Michael Nevin Miller, Frank Y. Xu, Shuqiang Yang
  • Patent number: 10591815
    Abstract: Embodiments described herein provide a method shifting mask pattern data during a digital lithography process to reduce line waviness of an exposed pattern. The method includes providing a mask pattern data having a plurality of exposure polygons to a processing unit of a digital lithography system. The processing unit has a plurality of image projection systems that receive the mask pattern data. Each image projection system corresponds to a portion of a plurality of portions of a substrate and receives an exposure polygon corresponding to the portion. The substrate is scanned under the plurality of image projection systems and pluralities of shots are projected to the plurality of portions while shifting the mask pattern data. Each shot of the pluralities of shots is inside the exposure polygon corresponding to the portion.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: March 17, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Joseph R. Johnson, Christopher Dennis Bencher, Thomas L. Laidig
  • Patent number: 10551735
    Abstract: A pellicle composition for a photomask, a pellicle for a photomask, the pellicle for a photomask being formed from the pellicle composition, a method of forming the pellicle, a reticle including the pellicle, and an exposure apparatus for lithography including the reticle are provided. The pellicle composition includes: at least one selected from graphene quantum dots and a graphene quantum dot precursor, the graphene quantum dots having a size of about 50 nm or less; and a solvent.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: February 4, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seongjun Jeong, Hyeonjin Shin, Sangwon Kim, Seongjun Park, Minsu Seol, Dongwook Lee, Yunseong Lee, Alum Jung
  • Patent number: 10543659
    Abstract: A thermally expandable sheet includes: a first thermally expansive layer that is formed on one side of a base and contains a first thermally expandable material and a first binder, the first thermally expansive layer having a first ratio of the first thermally expandable material with respect to the first binder; and a second thermally expansive layer that is formed on the first thermally expansive layer and contains a second thermally expandable material and a second binder, the second thermally expansive layer having a second ratio of the second thermally expandable material with respect to the second binder, wherein the second ratio is lower than the first ratio.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: January 28, 2020
    Assignee: CASIO COMPUTER CO., LTD.
    Inventors: Yoshimune Motoyanagi, Yuji Horiuchi
  • Patent number: 10545409
    Abstract: A method of optimizing a lithographic process for semiconductor fabrication includes determining that a semiconductor wafer experienced a photoresist exposure delay. At least one operating parameter of a post exposure baking process is adjusted based on the semiconductor wafer having experienced the photoresist exposure delay. The post exposure baking process is performed on the semiconductor wafer utilizing the adjusted at least one operating parameter.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Cody John Murray, Ekmini Anuja De Silva, Alex Richard Hubbard, Karen Elizabeth Petrillo, Nelson Felix
  • Patent number: 10538117
    Abstract: A thermally expandable sheet includes: a first thermally expansive layer that is formed on one side of a base and contains a first thermally expandable material and a first binder, the first thermally expansive layer having a first ratio of the first thermally expandable material with respect to the first binder; and a second thermally expansive layer that is formed on the first thermally expansive layer and contains a second thermally expandable material and a second binder, the second thermally expansive layer having a second ratio of the second thermally expandable material with respect to the second binder, wherein the first ratio is lower than the second ratio.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: January 21, 2020
    Assignee: CASIO COMPUTER CO., LTD.
    Inventor: Yoshimune Motoyanagi
  • Patent number: 10481510
    Abstract: A pellicle that includes graphene is constructed and arranged for an EUV reticle. A multilayer mirror includes graphene as an outermost layer.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: November 19, 2019
    Assignee: ASML Netherlands B.V.
    Inventors: Andrei Mikhailovich Yakunin, Vadim Yevgenyevich Banine, Erik Roelof Loopstra, Harmen Klaas Van Der Schoot, Lucas Henricus Johannes Stevens, Maarten Van Kampen
  • Patent number: 10460972
    Abstract: Various embodiments provide a method of detaching semiconductor material from a carrier, wherein the method comprises providing a carrier having attached thereto a layer of semiconductor material, wherein the layer comprises an edge portion; and guiding an air stream onto the edge portion of the layer of semiconductor material.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: October 29, 2019
    Assignee: Infineon Technologies AG
    Inventors: Adolf Koller, Florian Sedlmeier
  • Patent number: 10413639
    Abstract: One aspect relates to a composite, including a ceramic body having a first layer surface and a second layer surface and at least one cermet conductor that electrically connects the surfaces. The composite includes a first layer with the first layer surface, a first ceramic, a first hole and a first cermet element in the first hole, a second layer with the second layer surface, a second ceramic, a second hole and a second cermet element in the second hole, and an intermediate layer that is located between the first and the second layer. The intermediate layer includes an intermediate layer ceramic, an intermediate hole and one intermediate cermet element in the intermediate hole. A projection of the cross-section of the first hole and a projection of the cross section of the second hole onto a plane Px,y are arranged offset to each other.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: September 17, 2019
    Assignee: Heraeus Deutschland GmbH & Co. KG
    Inventors: Robert Dittmer, Ulrich Hausch, Jens Trötzschel, Peter Herzog, Josef Roth
  • Patent number: 10414076
    Abstract: An apparatus for forming a three-dimensional image, the apparatus including a cartridge that stores ink which a printing head discharges and which has a photothermal conversion property; a conveying unit that conveys a thermally expandable material so as to pass the thermally expandable material through a first position where the printing head faces and so as to form an image on the thermally expandable material with the ink discharged by the printing head; and a light irradiating unit that emits light toward a second position which is in a downstream side from the first position in a conveying path of the conveying unit, so as to perform photothermal conversion. The cartridge is disposed at a position which deviates from an extending line of an irradiation path of the light irradiation unit.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: September 17, 2019
    Assignee: CASIO COMPUTER CO., LTD.
    Inventor: Yuji Horiuchi
  • Patent number: 10394683
    Abstract: A data transmission method of transmitting data of log information recorded in log data of a manufacturing apparatus to an external device includes: storing correspondence information between information of a first identifier and information of a second identifier, the first identifier being an identifier used to identify a thing about a process performed by the manufacturing apparatus and being shared by the manufacturing apparatus and the external device, the second identifier being an identifier used to identify a thing about a process performed by the manufacturing apparatus and being used by the manufacturing apparatus; and obtaining, based on the correspondence information, information of the first identifier corresponding to information of the second identifier recorded in log information, and transmitting data of the log information to which the obtained information of the first identifier has been added. The storing and the obtaining are executed by an information processing device.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: August 27, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Mitsuhiro Masuda
  • Patent number: 10303058
    Abstract: A pattern forming method includes, in this order: a step (1) of forming a film on a substrate by using an actinic ray-sensitive or radiation-sensitive resin composition containing at least a resin having a group that is decomposed due to an action of an acid so as to generate a polar group; a step (2) of exposing the film; a step (3) of causing the exposed film to come into contact with a component that performs any one interaction of an ionic bond, a hydrogen bond, a chemical bond, and a dipole interaction with a polar group generated in the exposed film without substantially dissolving the exposed film; and a step (4) of forming a pattern by developing the exposed film by using a developer including an organic solvent and removing an area of the film having a small exposure amount.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: May 28, 2019
    Assignee: FUJIFILM Corporation
    Inventors: Hajime Furutani, Michihiro Shirakawa, Akiyoshi Goto, Masafumi Kojima
  • Patent number: 10297510
    Abstract: A method for fabricating a multiple gate width structure for an integrated circuit is described. A fin on a semiconductor substrate with a first hard mask layer is covered by a first and second sacrificial gate each of which includes a second hard mask layer. Spacer layers and a dielectric layer are formed over the first and second sacrificial gate structures. The resulting structure is planarized so that the first and second sacrificial gate structures and the dielectric layer have coplanar top surfaces. The first and second sacrificial gate structures are removed to respectively form first and second trench recesses in the dielectric layer. The trench recesses are filled with a conductor to form permanent gate structures. A first permanent gate structure is formed in the first trench recess has a first length and a second permanent gate structure is formed in the second trench recess has a second length greater than the first length.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: May 21, 2019
    Assignees: Internationel Business Machines Corporation, GlobalFoundries, Inc.
    Inventors: Soon-Cheon Seo, Fee Li Lie, Linus Jang
  • Patent number: 10280319
    Abstract: Ink contains at least one of a compound represented by the following chemical formula 1, a compound represented by chemical formula 2, a compound represented by chemical formula 3, or a compound represented by chemical formula 4.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: May 7, 2019
    Assignee: RICOH COMPANY, LTD.
    Inventors: Mitsunobu Morita, Soh Noguchi, Okitoshi Kimura
  • Patent number: 10260039
    Abstract: The present invention features microgels and microtissues for use in tissue engineering. Featured is a microencapsulation device for making microgels and/or microtissues via an emulsion technology. Also featured are methods of making higher ordered structures that mimic in vivo tissue structures. Methods of us are also featured.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: April 16, 2019
    Assignee: Massachusetts Institute of Technology
    Inventors: Sangeeta N. Bhatia, Cheri Y. Li
  • Patent number: 10249512
    Abstract: Lithographic multilayer structures are disclosed that generally include an organic planarizing layer and a tunable titanium oxynitride layer on the organic planarizing layer, wherein the titanium oxynitride includes TiOxNy, and wherein x is from 2.5 to 3.5 and y is from 0.75 to 1.25. The lithographic multilayer structure further includes a photosensitive resist layer on the titanium oxynitride layer. The tunable titanium oxynitride is configured to function as a hard mask and as an antireflective coating. Also disclosed are methods for patterning the lithographic multilayer structures.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Abraham Arceo De La Pena, Ekmini A. De Silva, Nelson M. Felix, Sivananda K. Kanakasabapathy
  • Patent number: 10231344
    Abstract: Forming a conductive film comprising depositing a non-conductive film on a surface of a substrate, wherein the film contains a plurality of copper nanoparticles and exposing at least a portion of the film to light to make the exposed portion conductive. Exposing of the film to light photosinters or fuses the copper nanoparticles.
    Type: Grant
    Filed: May 15, 2008
    Date of Patent: March 12, 2019
    Assignees: APPLIED NANOTECH HOLDINGS, INC., ISHIHARA CHEMICAL CO., LTD.
    Inventors: Yunjun Li, David Max Roundhill, Mohshi Yang, Igor Pavlovsky, Richard Lee Fink, Zvi Yaniv
  • Patent number: 10203604
    Abstract: Embodiments described herein relate to methods and apparatus for performing immersion field guided post exposure bake processes. Embodiments of apparatus described herein include a chamber body defining a processing volume. A pedestal may be disposed within the processing volume and a first electrode may be coupled to the pedestal. A moveable stem may extend through the chamber body opposite the pedestal and a second electrode may be coupled to the moveable stem. In certain embodiments, a fluid containment ring may be coupled to the pedestal and a dielectric containment ring may be coupled to the second electrode.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: February 12, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Viachslav Babayan, Douglas A. Buchberger, Jr., Qiwei Liang, Ludovic Godet, Srinivas D. Nemani, Daniel J. Woodruff, Randy Harris, Robert B. Moore
  • Patent number: 10197712
    Abstract: A light-diffusing-member manufacturing method includes a step of forming a light diffusion portion on one surface side of a base, by developing an exposed negative photosensitive resin layer with an alkali developing solution, and a step of performing an acid treatment on the light diffusion portion with an acid solution, after removing the alkali developing solution which is adhered to the light diffusion portion and suspended matter in the alkali developing solution in the negative photosensitive resin layer, so as to lower an ionization degree of the negative photosensitive resin layer which is in an ionized state due to the alkali developing solution.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: February 5, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Sho Ochi, Yasushi Asaoka, Tsuyoshi Maeda, Toru Kanno
  • Patent number: 10163631
    Abstract: In accordance with an embodiment a bottom anti-reflective layer comprises a surface energy modification group which modifies the surface energy of the polymer resin to more closely match a surface energy of an underlying material in order to help fill gaps between structures. The surface energy of the polymer resin may be modified by either using a surface energy modifying group or else by using an inorganic structure.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chung Su, Ching-Yu Chang
  • Patent number: 10073349
    Abstract: A pattern-forming method comprises patternwise exposing a predetermined region of a resist material film made from a photosensitive resin composition comprising a chemically amplified resist material to a first radioactive ray that is ionizing radiation or nonionizing radiation having a wavelength of no greater than 400 nm. The resist material film patternwise exposed is floodwise exposed to a second radioactive ray that is nonionizing radiation having a wavelength greater than the wavelength of the nonionizing radiation for the patternwise exposing and greater than 200 nm. The chemically amplified resist material comprises a base component, and a generative component that is capable of generating a radiation-sensitive sensitizer and an acid upon an exposure. The generative component comprises a radiation-sensitive sensitizer generating agent. The radiation-sensitive sensitizer generating agent comprises a compound represented by formula (A).
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: September 11, 2018
    Assignees: OSAKA UNIVERSITY, TOKYO ELECTRON LIMITED, JSR CORPORATION
    Inventors: Hisashi Nakagawa, Takehiko Naruoka, Tomoki Nagai, Seiichi Tagawa, Akihiro Oshima, Seiji Nagahara
  • Patent number: 10073348
    Abstract: A resist-pattern-forming method comprises: patternwise exposing a predetermined region of a resist material film to a first radioactive ray that is ionizing radiation or nonionizing radiation; floodwise exposing the resist material film to a second radioactive ray that is nonionizing radiation; baking the resist material film; and developing the resist material film to form a resist pattern. The resist material film is made from a photosensitive resin composition comprising a chemically amplified resist material. The chemically amplified resist material comprises a base component that is capable of being made soluble or insoluble in a developer solution by an action of an acid and a generative component that is capable of generating a radiation-sensitive sensitizer and an acid upon an exposure. A van der Waals volume of the acid generated from the generative component is no less than 3.0×10?28 m3.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: September 11, 2018
    Assignees: OSAKA UNIVERSITY, TOKYO ELECTRON LIMITED, JSR CORPORATION
    Inventors: Hisashi Nakagawa, Takehiko Naruoka, Tomoki Nagai, Seiichi Tagawa, Akihiro Oshima, Seiji Nagahara
  • Patent number: 10062858
    Abstract: The invention relates to method for manufacturing an electronic device comprising an organic layer (120). According to this method, a stack with a metal layer (130) and an organic layer (120) as first and second outer layers is structured by etching both these outer layers. In one particular embodiment, an additional metal layer (140) may be generated on the outermost metal layer (130) by galvanic growth through a structured isolation 10 layer (150). After removal of said isolation layer (150), the metal (130) may be etched in the openings of the additional metal layer (140). In a further etching step, the organic material (120) may be removed in said openings, too.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: August 28, 2018
    Assignee: OLEDWORKS, LLC
    Inventors: Sören Hartmann, Herbert Lifka
  • Patent number: 10049986
    Abstract: A package structure and method of making the same is provided. A through via is formed on a substrate, the through via extending through a molding material. An upper surface of the molding material is recessed from an upper surface of the through via. A dielectric layer is deposited over the through via and the molding material. The dielectric layer has a first upper surface with a first variation in height between a first area disposed over the through via and a second area disposed over the molding material. Exposure processes are performed on the dielectric layer. The dielectric layer is developed. After the developing, the dielectric layer has a second upper surface with a second variation in height between the first area and the second area. The first variation is greater than the second variation.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zi-Jheng Liu, Chung-Shi Liu, Hung-Jui Kuo, Yu-Hsiang Hu