Having Metal Oxide Or Copper Sulfide Compound Semiconductor Component Patents (Class 438/104)
  • Patent number: 11309429
    Abstract: A thin film transistor includes an active layer over a substrate, a gate electrode over the active layer, a gate line connected with the gate electrode, and a gate insulation film between the active layer and the gate electrode. The active layer includes a channel region overlapping the gate electrode, and a drain region and a source region on respective sides of the channel region. A length of a straight line connecting the drain region and the source region by a shortest distance may be greater than a width of the gate line parallel to the straight line.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: April 19, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Joonseok Park, Jihun Lim, Myounghwa Kim, Taesang Kim, Yeonkeon Moon
  • Patent number: 11289648
    Abstract: Various embodiments of the present application are directed towards an integrated circuit comprising a resistive random-access memory (RRAM) cell with recessed bottom electrode sidewalls to mitigate the effect of sidewall plasma damage. In some embodiments, the RRAM cell includes a lower electrode, a data storage element, and an upper electrode. The lower electrode includes a pair of recessed bottom electrode sidewalls respectively on opposite sides of the lower electrode. The data storage element overlies the lower electrode and includes a pair of storage sidewalls. The storage sidewalls are respectively on the opposite sides of the lower electrode, and the recessed bottom electrode sidewalls are laterally spaced from and laterally between the storage sidewalls. The upper electrode overlies the data storage element.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yuan-Tai Tseng, Shih-Chang Liu
  • Patent number: 11239237
    Abstract: A semiconductor device having high operation frequency is provided. The semiconductor device includes a transistor including a first conductive layer, a first insulating layer, a second insulating layer, a first oxide, a second oxide, a third oxide, a third insulating layer, and a second conductive layer that are stacked in this order, and a fourth insulating layer. The first conductive layer and the second conductive layer include a region overlapping with the second oxide. In a channel width direction of the transistor, a level of the bottom surface of the second oxide is from more than or equal to ?5 nm to less than 0 nm when a level of a region of the bottom surface of the second conductive layer which does not overlap with the second oxide is regarded as a reference.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: February 1, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yusuke Nonaka, Noritaka Ishihara, Tomoki Hiramatsu, Ryunosuke Honda, Tomoyo Kamogawa, Ryota Hodo, Katsuaki Tochibayashi, Shunpei Yamazaki
  • Patent number: 11217359
    Abstract: A method for synthesizing a copper-silver alloy includes an ink preparation step, a coating step, a crystal nucleus formation step and a crystal nucleus synthesis step. In the ink preparation step, a copper salt particle, an amine-based solvent, and a silver salt particle are mixed, thereby preparing a copper-silver ink. In the coating step, a member to be coated is coated with the copper-silver ink. In the crystal nucleus formation step, at least one of a crystal nucleus of copper having a crystal grain diameter of 0.2 ?m or less and a crystal nucleus of silver having a crystal grain diameter of 0.2 ?m or less is formed from the copper-silver ink. In the crystal nucleus synthesis step, the crystal nucleus of copper and the crystal nucleus of silver are synthesized.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: January 4, 2022
    Assignees: SENJU METAL INDUSTRY CO., LTD., OSAKA UNIVERSITY
    Inventors: Jinting Jiu, Minoru Ueshima, Katsuaki Suganuma, Wanli Li
  • Patent number: 11164951
    Abstract: The present disclosure relates to a thin film transistor and a manufacturing method thereof, a flexible display screen and a display device. The thin film transistor is disposed on a substrate. The thin film transistor includes: an active layer, a source-drain conductive layer, and a gate conductive layer. The gate conductive layer includes a gate electrode, and the gate conductive layer is disposed on one side of the active layer away from the substrate and insulated from the active layer. The source-drain conductive layer includes a first electrode and a second electrode. The orthogonal projections of the first electrode, the gate electrode, and the second electrode on the substrate are sequentially nested from inside to outside and separately disposed. The reliability of image display may be improved.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: November 2, 2021
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD, BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Mengyu Luan, Yuching Peng, Fei Li, Lin Chen, Youyuan Hu, Huihui Li, Xinfeng Wu, Xinzhu Wang
  • Patent number: 11158793
    Abstract: Cross bar arrays and a method for forming cross-bar arrays are provided. The cross bar array device includes first conductive lines spaced apart and extending in a first direction in a first plane, the first conductive lines including a bottom electrode layer. Second conductive lines are spaced apart and arranged transversely to the first conductive lines in a second plane, the second conductive lines including a top electrode layer. An oxide layer formed on the bottom electrode layer of the first conductive lines and in contact with the top electrode layer of the second conductive lines such that a resistive element is formed through the oxide layer at intersection points between the first conductive lines and the second conductive lines. A multivalent oxide spacer that switches between at least two oxidative states on at least one sidewall of the oxide layer between the first plane and the second plane.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: October 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Ramachandran Muralidhar
  • Patent number: 11152512
    Abstract: A semiconductor device with favorable electrical characteristics, a semiconductor device with stable electrical characteristics, or a highly reliable semiconductor device or display device is provided. A first insulating layer and a first conductive layer are stacked over a first region of a first metal oxide layer. A first layer is formed in contact with a second metal oxide layer and a second region of the first metal oxide layer that is not overlapped by the first insulating layer. Heat treatment is performed to lower the resistance of the second region and the second metal oxide layer. A second insulating layer is formed. A second conductive layer electrically connected to the second region is formed over the second insulating layer. Here, the first layer is formed to contain at least one of aluminum, titanium, tantalum, and tungsten.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: October 19, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Masami Jintyou, Yasutaka Nakazawa, Toshimitsu Obonai
  • Patent number: 11145679
    Abstract: A method for manufacturing an active matrix board includes (E) a step of forming a source contact hole and a drain contact hole in an interlayer insulating layer such that a portion of a source contact region of an oxide semiconductor layer and a portion of a drain contact region thereof are exposed and forming a connecting portion contact hole in the interlayer insulating layer and a lower insulating layer such that a portion of a lower conductive layer is exposed; and (F) a step of forming a source electrode, a drain electrode, and an upper conductive layer on the interlayer insulating layer; and the step (E) includes (e-1) a step of forming a photoresist film on the interlayer insulating layer and (e-2) a step of forming a photoresist layer in such a manner that the photoresist film is exposed to light using a multi-tone mask and is then developed.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: October 12, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kengo Hara, Tohru Daitoh, Hajime Imai, Tetsuo Kikuchi, Masahiko Suzuki, Setsuji Nishimiya, Masamitsu Yamanaka, Teruyuki Ueda, Hitoshi Takahata
  • Patent number: 11107929
    Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a first insulator, a second insulator over the first insulator, a third insulator over the second insulator, a fourth insulator and a first conductor over the third insulator, a fifth insulator over the fourth insulator and the first conductor, a first oxide over the fifth insulator, a second conductor and a third conductor over the first oxide, a second oxide over the first oxide and between the second conductor and the third conductor, a sixth insulator over the second oxide, and a fourth conductor over the sixth insulator. The hydrogen concentration of the second insulator is lower than that of the first insulator. The hydrogen concentration of the third insulator is lower than that of the second insulator.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: August 31, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Tsutomu Murakawa, Hideomi Suzawa
  • Patent number: 11081338
    Abstract: A method of forming an oxide film including two non-oxygen elements includes providing a first source material on a substrate, the first source material including a first central element, providing an electron donor compound to be bonded to the first source material, providing a second source material on the substrate after the providing of the electron donor compound, the second source material including a second central element, and providing an oxidant on the substrate.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: August 3, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Younsoo Kim, Haeryong Kim, Seungmin Ryu, Sunmin Moon, Jeonggyu Song, Changsu Woo, Kyooho Jung, Younjoung Cho
  • Patent number: 11049975
    Abstract: A dual-gate thin film transistor, a manufacturing method thereof, an array substrate and a display device are provided. The dual-gate thin film transistor includes: a base substrate and a first gate, a first gate insulating layer, an active layer, a second gate insulating layer, a first electrode, a second electrode, a second gate and a connection electrode, formed on the base substrate. The second gate, the first electrode and the second electrode are formed on the same level. The first gate insulating layer includes a first via hole exposing a portion of the first gate, and the connection electrode is electrically connected with the second gate and is electrically connected with the first gate through the first via hole.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: June 29, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Lianjie Qu, Jinchao Bai
  • Patent number: 11043533
    Abstract: A switch includes a first electrode layer, a second electrode layer disposed over the first electrode layer, and a selecting element layer interposed between the first electrode layer and the second electrode layer. The selecting element layer includes a gas region in which a current flows or does not flow according to a voltage applied to the switch. When the current flows, the switch is in an on-state, and, when the current does not flow, the switch is in an off-state.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: June 22, 2021
    Assignee: SK hynix Inc.
    Inventors: Beom Yong Kim, Soo Gil Kim
  • Patent number: 11011550
    Abstract: Non-planar thin film transistors (TFTs) incorporating an oxide semiconductor for the channel material. Memory devices may include an array of one thin film transistor and one capacitor (1TFT-1C) memory cells. Methods for fabricating non-planar thin film transistors may include a sacrificial gate/top-gate replacement technique with self-alignment of source/drain contacts.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventors: Van Le, Abhishek Sharma, Gilbert Dewey, Ravi Pillarisetty, Shriram Shivaraman, Tahir Ghani, Jack Kavalieros
  • Patent number: 11011387
    Abstract: A subtractive forming method that includes providing a material stack including a samarium and selenium containing layer and an aluminum containing layer in direct contact with the samarium and selenium containing layer. The samarium component of the samarium and selenium containing layer of the exposed portion of the material stack is etched with an etch chemistry comprising citric acid and hydrogen peroxide that is selective to the aluminum containing layer. The hydrogen peroxide reacts with the aluminum containing layer to provide an oxide etch protectant surface on the aluminum containing layer, and the citric acid etches samarium selectively to the oxide etch protectant surface. Thereafter, a remaining selenium component of is removed by elevating a temperature of the selenium component.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: May 18, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christine Armstrong, Matthew W. Copel, Yu Luo, Paul M. Solomon
  • Patent number: 11011650
    Abstract: A thin-film transistor is disclosed. The thin-film transistor includes an oxide semiconductor layer disposed on a substrate, a gate electrode disposed so as to overlap at least a portion of the oxide semiconductor layer and isolated from the oxide semiconductor layer, a source electrode connected to the oxide semiconductor layer, and a drain electrode connected to the oxide semiconductor layer and spaced apart from the source electrode, wherein the oxide semiconductor layer includes a first sub layer disposed on the substrate, a second sub layer disposed on the first sub layer, and a third sub layer disposed on the second sub layer, the second sub layer has larger resistance than the first sub layer and the third sub layer and lower carrier concentration than the first sub layer and the third sub layer, the first sub layer has higher hydrogen concentration than the second sub layer and the third sub layer, and each of the first sub layer and the second sub layer has crystallinity.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: May 18, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Seoyeon Im, HeeSung Lee, SeungJin Kim, SungKi Kim
  • Patent number: 11000975
    Abstract: A method of creating a polymer surface with surface structures is disclosed. The method includes creating a mold, forming a metal sheet into the molds, creating a surface structure on a surface of the metal sheet by exposing the surface to laser pulses, and bringing a curable polymer to be in contact with the surface of the metal sheet containing the surface structure, curing the curable polymer, and separating the cured polymer from the metal sheet, resulting in a polymer surface containing the surface structure. The polymer surfaces with the surface structures can be hydrophobic or superhydrophobic depending on the micro and nano features contained by the surface structures.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: May 11, 2021
    Assignee: Purdue Research Foundation
    Inventors: Yung C Shin, Shashank Sarbada
  • Patent number: 11004882
    Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes a first opening, a second opening, and a third opening which are formed by performing first etching and second etching. By the first etching, the first insulator is etched for forming the first opening, the second opening, and the third opening. By the second etching, the first metal oxide, the second insulator, the third insulator, the fourth insulator, the second metal oxide, and the fifth insulator are etched for forming the first opening; the first metal oxide, the second insulator, and the third insulator are etched for forming the second opening; and the first metal oxide is etched for forming the third opening.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: May 11, 2021
    Inventors: Motomu Kurata, Ryota Hodo, Yuta Iida
  • Patent number: 10964787
    Abstract: A semiconductor device includes a first conductor; a first insulator thereover; a first oxide thereover; a second oxide thereover; a second conductor and a third conductor that are separate from each other thereover; a third oxide over the first insulator, the second oxide, the second conductor, and the third conductor; a second insulator thereover; a fourth conductor thereover; and a third insulator over the first insulator, the second insulator, and the fourth conductor. The second oxide includes a region where the energy of the conduction band minimum of an energy band is low and a region where the energy of the conduction band minimum of the energy band is high. The energy of the conduction band minimum of the third oxide is higher than that of the region of the second oxide where the energy of the conduction band minimum is low. Side surfaces of the first oxide and the second oxide are covered with the third oxide.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: March 30, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tsutomu Murakawa, Toshihiko Takeuchi, Hiroki Komagata, Hiromi Sawai, Yasumasa Yamane, Shota Sambonsuge, Kazuya Sugimoto, Shunpei Yamazaki
  • Patent number: 10943928
    Abstract: A display substrate, a method for manufacturing the same and a display device are provided. The method includes steps of forming a common electrode line, a semiconductor pattern, and a data line on a base substrate, so that the semiconductor pattern is located between the common electrode line and the data line; and irradiating the semiconductor pattern by using light in a predetermined wavelength range from a side of the base substrate distal to the semiconductor pattern, to generate a dangling-bond defect state in a band gap of the semiconductor pattern.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: March 9, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., FUZHOU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zihua Zhuang, Xi Chen, Jiamin Liao, Zhendian Wu, Dahai Li, Linlin Lin, Gaopan Tang, Guichun Hong, Jin Wang, Xinmao Qiu, Changhong Shi, Yaochao Lv, Jiarong Liu, Zongxiang Li, Hongtao Lin
  • Patent number: 10930706
    Abstract: Systems and methods for reducing RRAM relaxation in crossbar array circuits for low current applications are provided. In some implementations, an apparatus comprises: a first row wire; a first column wire; an RRAM device; an access control device, wherein the RRAM device and the access control device serially connected and connecting between the first row wire and the first column wire, and wherein the RRAM device comprises: a first electrode; a first switching layer formed on the first electrode; and a second electrode formed on the first switching layer, wherein the first switching layer is doped with a first oxide material comprising SiO2, or Al2O3. The first electrode and the second electrode are, in some implementations, made of one of the following materials: Pt, Pd, Ta, Ti, Hf, W, TiN, and TaN.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: February 23, 2021
    Inventors: Ning Ge, Minxian Zhang
  • Patent number: 10930725
    Abstract: An organic light emitting diode display includes a first thin film transistor of which a channel is formed in a polycrystalline transistor, a second thin film transistor of which a channel is formed in an oxide semiconductor layer, an organic light emitting diode electrically connected to the first thin film transistor, a storage capacitor having a first electrode and a second electrode, wherein the second electrode of the storage capacitor is electrically connected to a gate electrode of the first thin film transistor, and an overlapping layer overlapping the oxide semiconductor layer in a plan view and receiving a positive voltage. The oxide semiconductor layer is positioned higher than the gate electrode of the first thin film transistor and the second electrode of the storage capacitor.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: February 23, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Myoung Geun Cha, Sang Gun Choi, Sang Sub Kim, Ji Yeong Shin, Yong Su Lee, Ki Seok Choi
  • Patent number: 10916566
    Abstract: It is an object to manufacture and provide a highly reliable display device including a thin film transistor with a high aperture ratio which has stable electric characteristics. In a manufacturing method of a semiconductor device having a thin film transistor in which a semiconductor layer including a channel formation region is formed using an oxide semiconductor film, a heat treatment for reducing moisture and the like which are impurities and for improving the purity of the oxide semiconductor film (a heat treatment for dehydration or dehydrogenation) is performed. Further, an aperture ratio is improved by forming a gate electrode layer, a source electrode layer, and a drain electrode layer using conductive films having light transmitting properties.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: February 9, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masayuki Sakakura
  • Patent number: 10910407
    Abstract: A high-performance semiconductor device is provided. The semiconductor device includes a transistor, an insulating film over the transistor, an electrode, and a metal oxide over the insulating film. The transistor includes a first gate electrode, a first gate insulating film over the first gate electrode, an oxide over the first gate insulating film, a source electrode and a drain electrode electrically connected to the oxide, a second gate insulating film over the oxide, and a second gate electrode over the second gate insulating film. The electrode includes a region in contact with the insulating film. The first gate insulating film is in contact with the insulating film. The thicknesses of the insulating film over the second gate electrode, the insulating film over the source electrode, and the insulating film over the drain electrode are substantially the same, and the insulating film includes excess oxygen.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: February 2, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshinori Ando, Takashi Hamada, Yasumasa Yamane
  • Patent number: 10903368
    Abstract: The reliability of a transistor including an oxide semiconductor can be improved by suppressing a change in electrical characteristics. A transistor included in a semiconductor device includes a first oxide semiconductor film over a first insulating film, a gate insulating film over the first oxide semiconductor film, a second oxide semiconductor film over the gate insulating film, and a second insulating film over the first oxide semiconductor film and the second oxide semiconductor film. The first oxide semiconductor film includes a channel region in contact with the gate insulating film, a source region in contact with the second insulating film, and a drain region in contact with the second insulating film. The second oxide semiconductor film has a higher carrier density than the first oxide semiconductor film.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: January 26, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Masami Jintyou, Yukinori Shima
  • Patent number: 10892284
    Abstract: A display substrate, a manufacturing method thereof, and a display device are provided. According to embodiments of the present disclosure, the manufacturing method of a display substrate comprises: fabricating a gate electrode, a gate electrode insulating layer, and a semiconductor active layer sequentially on a base substrate; fabricating a first etching stopping layer and a second etching stopping layer on the base substrate with the semiconductor active layer fabricated thereon, wherein the first etching stopping layer is disposed in a display area of the display substrate, the second etching stopping layer is disposed in a peripheral area of the display substrate, and the second etching stopping layer is a non-transparent layer; and fabricating source/drain electrodes by a patterning process, on the base substrate with the first and second etching stopping layers fabricated thereon, wherein the second etching stopping layer is used as an alignment marker in fabricating the source/drain electrodes.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: January 12, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ming Wang, Wei Song, Hui Li
  • Patent number: 10889888
    Abstract: There have been cases where transistors formed using oxide semiconductors are inferior in reliability to transistors formed using amorphous silicon. Thus, in the present invention, a semiconductor device including a highly reliable transistor formed using an oxide semiconductor is manufactured. An oxide semiconductor film is deposited by a sputtering method, using a sputtering target including an oxide semiconductor having crystallinity, and in which the direction of the c-axis of a crystal is parallel to a normal vector of the top surface of the oxide semiconductor. The target is formed by mixing raw materials so that its composition ratio can obtain a crystal structure.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: January 12, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Tetsunori Maruyama, Yuki Imoto, Hitomi Sato, Masahiro Watanabe, Mitsuo Mashiyama, Kenichi Okazaki, Motoki Nakashima, Takashi Shimazu
  • Patent number: 10868043
    Abstract: A first oxide semiconductor layer of a pixel TFT has a first structure in which a first source electrode and a first drain electrode have, at both end portions thereof, two types of reduction action regions formed by the first oxide semiconductor layer protruding outward in a channel width direction of a first channel portion from both the first source electrode and the first drain electrode. A second oxide semiconductor layer of a drive circuit TFT has a second structure formed without protruding outward in a channel width direction of a second channel portion from a second source electrode and a second drain electrode. A protective insulation film is provided to cover the first oxide semiconductor layer, the first source electrode, and the first drain electrode.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: December 15, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Akihiko Hosono, Kazunori Inoue
  • Patent number: 10861981
    Abstract: The reliability of a transistor including an oxide semiconductor can be improved by suppressing a change in electrical characteristics. A transistor included in a semiconductor device includes a first oxide semiconductor film over a first insulating film, a gate insulating film over the first oxide semiconductor film, a second oxide semiconductor film over the gate insulating film, and a second insulating film over the first oxide semiconductor film and the second oxide semiconductor film. The first oxide semiconductor film includes a channel region in contact with the gate insulating film, a source region in contact with the second insulating film, and a drain region in contact with the second insulating film. The second oxide semiconductor film has a higher carrier density than the first oxide semiconductor film.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: December 8, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Masami Jintyou, Yukinori Shima
  • Patent number: 10859877
    Abstract: The present disclosure provides a display panel, a manufacturing method thereof and a display device. The display panel includes an opposite substrate and a display substrate opposite each other, a sealant is disposed between the opposite substrate and the display substrate, and the display substrate may be divided into a display area and a peripheral area around the display area. The display substrate includes a first base substrate; a first resin pattern on the first base substrate in the display area; and a protection layer in the display area and the peripheral area and between the first resin pattern and the first base substrate. The sealant is in the peripheral area and in contact with a portion of the protection layer in the peripheral area.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: December 8, 2020
    Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Pengcheng Tian, Bin Zhao, Xin Li, Detao Zhao, Le Zhang
  • Patent number: 10852610
    Abstract: An opening insulation film covers a substrate and is in contact with a side surface of a gate electrode. The opening insulation film is provided with a first opening portion having a side surface on the gate electrode. A gate insulation film made of an oxide insulator is on the gate electrode and the opening insulation film. A semiconductor channel film made of an oxide semiconductor is on the gate insulation film and is encompassed by the first opening portion. Source and drain electrodes are on the semiconductor channel film. A source upper-layer electrode and a drain upper-layer electrode both made of an oxide are provided at least on upper surfaces of the source electrode and the drain electrode, respectively. An interlayer insulation film made of an oxide has a portion provided on the source upper-layer electrode and the drain upper-layer electrode and is in contact the semiconductor channel film.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: December 1, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazunori Inoue, Koji Oda, Takafumi Hashiguchi, Takeshi Kubota
  • Patent number: 10822276
    Abstract: There are provided an oxide sintered material containing an In2O3 crystal phase, a Zn4In2O7 crystal phase and a ZnWO4 crystal phase, and a method of producing the oxide sintered material. The method includes forming the oxide sintered material by sintering a molded body containing In, W and Zn, and forming the oxide sintered material including placing the molded body at a first constant temperature selected from a temperature range of 500° C. or more and 1000° C. or less for 30 minutes or longer.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: November 3, 2020
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kenichi Watatani, Miki Miyanaga, Hideaki Awata
  • Patent number: 10714633
    Abstract: In a transistor including an oxide semiconductor film, field-effect mobility and reliability are improved. A semiconductor device includes a gate electrode, an insulating film over the gate electrode, an oxide semiconductor film over the insulating film, and a pair of electrodes over the oxide semiconductor film. The oxide semiconductor film includes a first oxide semiconductor film, a second oxide semiconductor film over the first oxide semiconductor film, and a third oxide semiconductor film over the second oxide semiconductor film. The first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film include the same elements. The second oxide semiconductor film includes a region having a higher carrier density than the first oxide semiconductor film and the third oxide semiconductor film.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: July 14, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10707240
    Abstract: The purpose of the invention is to countermeasure a disconnection between the drain electrode or the source electrode and the wiring or the electrode formed on the insulating film via through hole. The concrete structure is that: A display device having a display area including a plurality of pixels comprising: the pixel includes a thin film transistor having a semiconductor layer as an active element, a first insulating film is formed to cover a drain electrode of the thin film transistor, the drain electrode is connected with an electrode or an wiring that are formed on the first insulating film via a through hole, an oxide semiconductor layer exists between the drain electrode and the first insulating film, the oxide semiconductor layer does not exist at the bottom of the through hole.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: July 7, 2020
    Assignee: Japan Display Inc.
    Inventor: Manabu Yamashita
  • Patent number: 10700097
    Abstract: The present application discloses an array substrate having a display area and a peripheral area. The array substrate includes a plurality of first thin film transistors respectively in a plurality of subpixels in the display area; and a plurality of second thin film transistors in the peripheral area, an oxygen content in active layers of the plurality of first thin film transistors being higher than that in active layers of the plurality of second thin film transistors.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: June 30, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Seungjin Choi
  • Patent number: 10700212
    Abstract: A semiconductor device includes a first insulator, a transistor over the first insulator, a second insulator over the transistor, and a third insulator over the second insulator. The transistor includes an oxide semiconductor. The amount of oxygen released from the second insulator when converted into oxygen molecules is larger than or equal to 1×1014 molecules/cm2 and smaller than 1×1016 molecules/cm2 in thermal desorption spectroscopy at a surface temperature of a film of the second insulator of higher than or equal to 50° C. and lower than or equal to 500° C. The second insulator includes oxygen, nitrogen, and silicon.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: June 30, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromi Sawai, Akihisa Shimomura
  • Patent number: 10644164
    Abstract: To provide an oxide semiconductor film having stable electric conductivity and a highly reliable semiconductor device having stable electric characteristics by using the oxide semiconductor film. The oxide semiconductor film contains indium (In), gallium (Ga), and zinc (Zn) and includes a c-axis-aligned crystalline region aligned in the direction parallel to a normal vector of a surface where the oxide semiconductor film is formed. Further, the composition of the c-axis-aligned crystalline region is represented by In1+?Ga1??O3(ZnO)m (0<?<1 and m=1 to 3 are satisfied), and the composition of the entire oxide semiconductor film including the c-axis-aligned crystalline region is represented by InxGayO3(ZnO)m (0<x<2, 0<y<2, and m=1 to 3 are satisfied).
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: May 5, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masahiro Takahashi, Kengo Akimoto, Shunpei Yamazaki
  • Patent number: 10642110
    Abstract: A display device with a narrow frame is provided. A display device with high visibility is provided. A display device with low power consumption is provided. A novel display device is provided. A structure having a stack structure in which a gate driver including a first transistor and a common driver including a second transistor which includes a metal oxide in its channel formation region are stacked has been conceived. Because the gate driver has a larger area than the common driver, part of the gate driver may be formed on the same plane as the common driver.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: May 5, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kei Takahashi
  • Patent number: 10636817
    Abstract: The present application discloses an array substrate having a display area and a peripheral area. The array substrate includes a plurality of first thin film transistors respectively in a plurality of subpixels in the display area; and a plurality of second thin film transistors in the peripheral area, an oxygen content in active layers of the plurality of first thin film transistors being higher than that in active layers of the plurality of second thin film transistors.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: April 28, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Seungjin Choi
  • Patent number: 10615284
    Abstract: The present disclosure provides a thin film transistor, a method for fabricating the same, a display substrate, and a display apparatus, and belongs to the field of display technology. The method includes: forming a metal oxide semiconductor pattern comprising first and second metal oxide semiconductor layers, the second metal oxide semiconductor layer being above the first metal oxide semiconductor layer; depositing a source-drain metal layer on the metal oxide semiconductor pattern; etching the source-drain metal layer and the second metal oxide semiconductor layer to form source and drain electrodes and an active layer of the thin film transistor. The active layer is obtained after removing the second metal oxide semiconductor layer between the source and drain electrodes using a first etchant, and the first etchant has a higher etching rate on the second metal oxide semiconductor layer than on the first metal oxide semiconductor layer.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: April 7, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wei Yang, Ce Ning, Hehe Hu, Ke Wang
  • Patent number: 10593878
    Abstract: An electronic device includes a semiconductor memory, wherein the semiconductor memory comprises a plurality of memory stacks neighboring each other in a first direction and a second direction, the second direction intersecting the first direction, a plurality of first liner layers covering sidewalls of memory stacks that neighbor each other in the second direction, the plurality of first liner layers extending in the second direction, a plurality of first air gaps located in spaces covered by the first liner layers, and a plurality of second air gaps located between each pair of memory stacks that neighbor each other in the first direction, the plurality of second air gaps extending in the second direction.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: March 17, 2020
    Assignee: SK hynix Inc.
    Inventor: Kyoung Su Choi
  • Patent number: 10586869
    Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor film, which has stable electric characteristics and high reliability. A crystalline oxide semiconductor film is formed, without performing a plurality of steps, as follows: by utilizing a difference in atomic weight of plural kinds of atoms included in an oxide semiconductor target, zinc with low atomic weight is preferentially deposited on an oxide insulating film to form a seed crystal including zinc; and tin, indium, or the like with high atomic weight is deposited on the seed crystal while causing crystal growth. Further, a crystalline oxide semiconductor film is formed by causing crystal growth using a seed crystal with a hexagonal crystal structure including zinc as a nucleus, whereby a single crystal oxide semiconductor film or a substantially single crystal oxide semiconductor film is formed.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: March 10, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yusuke Nonaka, Takayuki Inoue, Masashi Tsubuku, Kengo Akimoto, Akiharu Miyanaga
  • Patent number: 10573758
    Abstract: Provided is a semiconductor device in which deterioration of electric characteristics which becomes more noticeable as the semiconductor device is miniaturized can be suppressed. The semiconductor device includes a first oxide film, an oxide semiconductor film over the first oxide film, a source electrode and a drain electrode in contact with the oxide semiconductor film, a second oxide film over the oxide semiconductor film, the source electrode, and the drain electrode, a gate insulating film over the second oxide film, and a gate electrode in contact with the gate insulating film. A top end portion of the oxide semiconductor film is curved when seen in a channel width direction.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: February 25, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuya Hanaoka, Daisuke Matsubayashi, Yoshiyuki Kobayashi, Shunpei Yamazaki, Shinpei Matsuda
  • Patent number: 10557192
    Abstract: In a method for using a sputtering target, by making an ion collide with the sputtering target, a sputtered particle whose size is greater than or equal to 1/3000 and less than or equal to 1/20, preferably greater than or equal to 1/1000 and less than or equal to 1/30 of a crystal grain is generated.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: February 11, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10559669
    Abstract: A semiconductor device that includes source and drain regions that are doped to an n-type conductivity and are comprised of a type III-V semiconductor material. The semiconductor device further includes a contact to at least one of the source and drain regions. The contact includes an interface passivation layer atop the at least one source and drain region, and an n-type zinc oxide layer. A conduction band of the type III-V semiconductor material of the at least one source and drain region is substantially aligned with a conduction band of the n-type zinc oxide containing layer.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: February 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ning Li, Yun Seog Lee, Joel P. de Souza, Devendra K. Sadana
  • Patent number: 10497620
    Abstract: The present disclosure provides a TFT substrate and a manufacturing method thereof and a manufacturing method of an OLED panel. In the manufacturing method of the TFT substrate of the present disclosure, firstly formed a first inter layer dielectric covering the gate and the active layer on the buffer layer, wherein material of the first inter layer dielectric is provided as silicon oxynitride; Further, forming a second inter layer dielectric on the first inter layer dielectric, wherein material of the second inter layer dielectric is provided as silicon oxide, which can prevent excessive hydrogen elements from being introduced into the active layer, improve the working stability of the TFT device. The TFT substrate of the present disclosure is manufactured by using the above manufacturing method of a TFT substrate, the gate and the active layer have stable performance, and the TFT device has better working stability.
    Type: Grant
    Filed: November 25, 2017
    Date of Patent: December 3, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Zhaosong Liu, Yuanjun Hsu
  • Patent number: 10475936
    Abstract: The disclosure relates to a thin film transistor and a method for making the same. The thin film transistor includes a substrate; a gate on the substrate; a dielectric layer on the gate, wherein the dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer stacked on one another, and the first sub-dielectric layer is a first oxide dielectric layer formed by magnetron sputtering and in direct contact with the gate; a semiconductor layer on the dielectric layer, wherein the semiconductor layer includes nano-scaled semiconductor materials; and a source and a drain, wherein the source and the drain are on the dielectric layer, spaced apart from each other, and electrically connected to the semiconductor layer. The thin film transistor almost has no current hysteresis.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: November 12, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Jia Huo, Yu-Dan Zhao, Xiao-Yang Xiao, Ying-Cheng Wang, Tian-Fu Zhang, Yuan-Hao Jin, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 10475822
    Abstract: The present application discloses an array substrate, a display panel and a display apparatus having the same, and a fabricating method thereof. The array substrate includes a base substrate; a first electrode and a second electrode, the first electrode and the second electrode being two different electrodes selected from a pixel electrode and a common electrode; and a thin film transistor including an active layer, an etch stop layer on a side of the active layer distal to the base substrate, a first node, and a second node.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: November 12, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zhuo Xu, Yajie Bai, Xiaolin Wang, Rui Wang, Fei Shang, Haijun Qiu
  • Patent number: 10461099
    Abstract: A metal oxide film including a crystal part and having highly stable physical properties is provided. The size of the crystal part is less than or equal to 10 nm, which allows the observation of circumferentially arranged spots in a nanobeam electron diffraction pattern of the cross section of the metal oxide film when the measurement area is greater than or equal to 5 nm? and less than or equal to 10 nm?.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: October 29, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masahiro Takahashi, Takuya Hirohashi, Masashi Tsubuku, Noritaka Ishihara, Masashi Oota
  • Patent number: 10453966
    Abstract: The present disclosure provides in some embodiments an oxide TFT display substrate, a manufacture method thereof and a display device. The oxide TFT display substrate includes a first region at least corresponding to a semiconducting region of an oxide TFT and a second region other than the first region. The method includes steps of: forming, after the formation of the oxide TFT, a SiON layer at least covering the first region; and forming a SiNx layer covering the second region.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: October 22, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., FUZHOU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xiaowei Liu, Fanqing Meng, Yang Wang, Yabin An, Zhiyong Fan, Chenglong Wu
  • Patent number: 10438982
    Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes a first opening, a second opening, and a third opening which are formed by performing first etching and second etching. By the first etching, the first insulator is etched for forming the first opening, the second opening, and the third opening. By the second etching, the first metal oxide, the second insulator, the third insulator, the fourth insulator, the second metal oxide, and the fifth insulator are etched for forming the first opening; the first metal oxide, the second insulator, and the third insulator are etched for forming the second opening; and the first metal oxide is etched for forming the third opening.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: October 8, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Motomu Kurata, Ryota Hodo, Yuta Iida