Having Metal Oxide Or Copper Sulfide Compound Semiconductor Component Patents (Class 438/104)
  • Patent number: 10439050
    Abstract: A hydrogen barrier layer is selectively provided over an oxide semiconductor layer including hydrogen and hydrogen is selectively desorbed from a given region in the oxide semiconductor layer by conducting oxidation treatment, so that regions with different conductivities are formed in the oxide semiconductor layer. After that, a channel formation region, a source region, and a drain region can be formed with the use of the regions with different conductivities formed in the oxide semiconductor layer.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: October 8, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Junichiro Sakata
  • Patent number: 10438982
    Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes a first opening, a second opening, and a third opening which are formed by performing first etching and second etching. By the first etching, the first insulator is etched for forming the first opening, the second opening, and the third opening. By the second etching, the first metal oxide, the second insulator, the third insulator, the fourth insulator, the second metal oxide, and the fifth insulator are etched for forming the first opening; the first metal oxide, the second insulator, and the third insulator are etched for forming the second opening; and the first metal oxide is etched for forming the third opening.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: October 8, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Motomu Kurata, Ryota Hodo, Yuta Iida
  • Patent number: 10389922
    Abstract: A detector (10) that detects light (237) includes a sensor array (232) having a plurality of pixels (234). Each pixel (234) can include a first pixel layer (236A), and a second pixel layer (236B) stacked on top of the first pixel layer (236A). The first pixel layer (236A) can include a first, fast conductor electrode (238A) and a plurality of first quantum dots (240A) that absorb light (237) in a first range of wavelengths. The second pixel layer (236B) can include a second, fast conductor electrode (238B) and a plurality of second quantum dots (240B) that absorb light (237) in a second range of wavelengths. The second range of wavelengths is higher energy than the first range of wavelengths.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: August 20, 2019
    Assignee: NIKON CORPORATION
    Inventor: Mark Takita
  • Patent number: 10388864
    Abstract: Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. First channel material is between the gate and the source region. The first channel material is spaced from the gate by one or more insulative materials. Second channel material is between the first channel material and the source region, and directly contacts the source region. The first and second channel materials are transition metal chalcogenide. One of the source and drain regions is a hole reservoir region and the other is an electron reservoir region. Tunnel dielectric material may be between the first and second channel materials.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Gurtej S. Sandhu, Chandra Mouli
  • Patent number: 10374096
    Abstract: According to one embodiment, a semiconductor device includes contact holes passing through a source region of a drain region of an interlayer insulating film and oxide semiconductor layer to reach an insulating substrate, wherein a source electrode and a drain electrode are formed inside the contact holes, respectively.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: August 6, 2019
    Assignee: Japan Display Inc.
    Inventors: Miyuki Ishikawa, Arichika Ishida, Masayoshi Fuchi, Hajime Watakabe, Takashi Okada
  • Patent number: 10367066
    Abstract: Disclosed are a thin film transistor and a method for manufacturing the same, which relates to the technical field of display. Each of a source and a drain of the thin film transistor includes a first metal layer, a second metal layer, and a third metal layer. The first metal layer is in contact with an IGZO (indium gallium zinc oxide) layer, and a metal diffusion layer is provided at a contact face. Meanwhile, disclosed is a method for manufacturing the thin film transistor: sequentially obtaining the first metal layer, the second metal layer, and the third metal layer through deposition; then obtaining PV layers; and then performing high temperature annealing treatment on the PV layers to diffuse a metal within the first metal layer into the IGZO layer, thereby forming a metal diffusion layer. The metal diffusion layer forms Ohmic contact between the first metal layer and the IGZO layer, thus reducing contact resistance both between the source and the IGZO layer and between the drain and the IGZO layer.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: July 30, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Longqiang Shi
  • Patent number: 10351957
    Abstract: In a method for producing a metal oxide film according to the present invention, a solution containing zinc is sprayed onto a substrate placed under non-vacuum, and then, a dopant solution containing a dopant is sprayed onto the substrate. After that, a deposited metal oxide film is subjected to a resistance reducing treatment. A molar concentration of the dopant supplied to the substrate with respect to a molar concentration of the zinc supplied to the substrate is not less than a predetermined value.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: July 16, 2019
    Assignee: TOSHIBA MITSUBISHI-ELECTRIC INDUSTRIAL SYSTEMS CORPORATION
    Inventors: Takahiro Shirahata, Hiroyuki Orita, Takahiro Hiramatsu
  • Patent number: 10347893
    Abstract: Provided is a secondary battery which is small in size and in which current capacity per unit volume can be increased. The present invention provides a secondary battery including two cell units each including a charging layer between a first electrode layer and a second electrode layer, the two cell units being parallel-connected by juxtaposing and connecting a first electrode layer of one cell unit and a first electrode layer of the other cell unit or a second electrode layer of the one cell unit and a second electrode layer of the other cell unit, and by wire-connecting the second electrode layer of the one cell unit and the second electrode layer of the other cell unit or the first electrode layer of the one cell unit and the first electrode layer of the other cell unit.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: July 9, 2019
    Assignees: KABUSHIKI KAISHA NIHON MICRONICS, GUALA TECHNOLOGY CO., LTD.
    Inventors: Takuo Kudoh, Kiyoyasu Hiwada, Tatsuo Inoue, Akira Nakazawa, Nobuaki Terakado
  • Patent number: 10332989
    Abstract: The invention provides a BCE TFT substrate and manufacturing method thereof. The method comprises forming a first IGZO thin film with polycrystalline IGZO particles in a predetermined area of active layer before sputtering IGZO, the polycrystalline IGZO particles in the first IGZO thin film used as seed crystal during sputtering to grow a C-axis crystallized IGZO in good crystalline state to form a second IGZO thin film. The first and second IGZO thin films form an active layer. Because the surface of the active layer is presented as C-axis crystallized IGZO, the active layer is not damaged by the copper etchant during etching source and drain so as to ensure stable performance of active layer and to avoid the development of special copper etching solution. As such, the BCE TFT substrate has stable electrical performance. The BCE TFT substrate manufactured by the above manufacturing method has stable electrical performance.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 25, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Chunsheng Jiang
  • Patent number: 10304859
    Abstract: The stability of a step of processing a wiring formed using copper, aluminum, gold, silver, molybdenum, or the like is increased. Moreover, the concentration of impurities in a semiconductor film is reduced. Moreover, the electrical characteristics of a semiconductor device are improved. In a transistor including an oxide semiconductor film, an oxide film in contact with the oxide semiconductor film, and a pair of conductive films being in contact with the oxide film and including copper, aluminum, gold, silver, molybdenum, or the like, the oxide film has a plurality of crystal parts and has c-axis alignment in the crystal parts, and the c-axes are aligned in a direction parallel to a normal vector of a top surface of the oxide semiconductor film or the oxide film.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: May 28, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Yasutaka Nakazawa, Yukinori Shima, Masami Jintyou, Masayuki Sakakura, Motoki Nakashima
  • Patent number: 10297679
    Abstract: Disclosed is a method to manufacture a thin film transistor having an oxide semiconductor as a channel formation region. The method includes; forming an oxide semiconductor layer over a gate insulating layer; forming a source and drain electrode layers over and in contact with the oxide semiconductor layer so that at least portion of the oxide semiconductor layer is exposed; and forming an oxide insulating film over and in contact with the oxide semiconductor layer. The exposed portion of the oxide semiconductor may be exposed to a gas containing oxygen in the presence of plasma before the formation of the oxide insulating film. The method allows oxygen to be diffused into the oxide semiconductor layer, which contributes to the excellent characteristics of the thin film transistor.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: May 21, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiaki Oikawa, Kenichi Okazaki, Hotaka Maruyama
  • Patent number: 10290719
    Abstract: A semiconductor device that includes source and drain regions that are doped to an n-type conductivity and are comprised of a type III-V semiconductor material. The semiconductor device further includes a contact to at least one of the source and drain regions. The contact includes an interface passivation layer atop the at least one source and drain region, and an n-type zinc oxide layer. A conduction band of the type III-V semiconductor material of the at least one source and drain region is substantially aligned with a conduction band of the n-type zinc oxide containing layer.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: May 14, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ning Li, Yun Seog Lee, Joel P. de Souza, Devendra K. Sadana
  • Patent number: 10290781
    Abstract: Provided is a color filter array panel. The color filter array panel according to exemplary embodiments of the present invention includes: a substrate; a color filter disposed on the substrate and including a colorant including at least one of a pigment and a dye, and a solid fluorescent material; and a light source unit supplying light to the color filter, in which the solid fluorescent material is an aggregation induced emission enhancement (AIEE) material of which a liquid state is solidified to increase fluorescence efficiency.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: May 14, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Young Do Kim, Jin Ho Ju, Min Kang, Woo Sub Shim
  • Patent number: 10256291
    Abstract: An object is to provide a method for manufacturing a highly reliable semiconductor device including a transistor with stable electric characteristics. A method for manufacturing a semiconductor device includes the steps of: forming a gate electrode over a substrate having an insulating surface; forming a gate insulating film over the gate electrode; forming an oxide semiconductor film over the gate insulating film; irradiating the oxide semiconductor film with an electromagnetic wave such as a microwave or a high frequency; forming a source electrode and a drain electrode over the oxide semiconductor film irradiated with the electromagnetic wave; and forming an oxide insulating film, which is in contact with part of the oxide semiconductor film, over the gate insulating film, the oxide semiconductor film, the source electrode, and the drain electrode.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: April 9, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Akiharu Miyanaga
  • Patent number: 10249645
    Abstract: To provide a semiconductor device including a planar transistor having an oxide semiconductor and a capacitor. In a semiconductor device, a transistor includes an oxide semiconductor film, a gate insulating film over the oxide semiconductor film, a gate electrode over the gate insulating film, a second insulating film over the gate electrode, a third insulating film over the second insulating film, and a source and a drain electrodes over the third insulating film; the source and the drain electrodes are electrically connected to the oxide semiconductor film; a capacitor includes a first and a second conductive films and the second insulating film; the first conductive film and the gate electrode are provided over the same surface; the second conductive film and the source and the drain electrodes are provided over the same surface; and the second insulating film is provided between the first and the second conductive films.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: April 2, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kenichi Okazaki, Masahiro Katayama, Masataka Nakada
  • Patent number: 10236389
    Abstract: A miniaturized transistor is provided. A first layer is formed over a third insulator over a semiconductor; a second layer is formed over the first layer; an etching mask is formed over the second layer; the second layer is etched using the etching mask until the first layer is exposed to form a third layer; a selective growth layer is formed on a top surface and a side surface of the third layer; the first layer is etched using the third layer and the selective growth layer until the third insulator is exposed to form a fourth layer; and the third insulator is etched using the third layer, the selective growth layer, and the fourth layer until the semiconductor is exposed to form a first insulator.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: March 19, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Hideomi Suzawa, Sachiaki Tezuka, Tetsuhiro Tanaka, Toshiya Endo, Mitsuhiro Ichijo
  • Patent number: 10236361
    Abstract: A method for forming a mask pattern is provided, comprising forming a negative photoresist on a substrate; in an environment without oxygen, to performing a first exposure on the negative photoresist by use of a first ordinary mask plate, so that a fully-cured portion of the negative photoresist is exposed to light and a semi-cured portion and a removed portion of the negative photoresist are not exposed to light; in an environment with oxygen, performing a second exposure on the negative photoresist by use of a second ordinary mask plate, so that the semi-cured portion of the negative photoresist is exposed to light and the removed portion of the negative photoresist not exposed to light; removing the uncured negative photoresist and forming the mask pattern.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: March 19, 2019
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Bin Zhang, Tingting Zhou, Zhen Liu, Zhanfeng Cao, Shi Shu, Qi Yao, Feng Guan
  • Patent number: 10217776
    Abstract: A semiconductor device including a capacitor having an increased charge capacity without decreasing an aperture ratio is provided. The semiconductor device includes a transistor including a light-transmitting semiconductor film, a capacitor in which a dielectric film is provided between a pair of electrodes, and a pixel electrode electrically connected to the transistor. In the capacitor, a conductive film formed on the same surface as the light-transmitting semiconductor film in the transistor serves as one electrode, the pixel electrode serves as the other electrode, and a nitride insulating film and a second oxide insulating film which are provided between the light-transmitting semiconductor film and the pixel electrode serve as the a dielectric film.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: February 26, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Katayama, Ami Sato, Yukinori Shima
  • Patent number: 10192900
    Abstract: Methods for fabricating a thin film transistor and an array substrate, an array substrate and a display device are provided, and the fabrication method of a thin film transistor includes: forming a first photoresist pattern on the active layer film, wherein the first photoresist pattern comprises a photoresist area of a first thickness and a photoresist area in a second thickness; etching the active layer film by using the first photoresist pattern as a mask to form an active layer; ashing the first photoresist pattern to remove the photoresist area of the second thickness and to reduce a thickness of the photoresist area of the first thickness to form the second photoresist pattern. The second photoresist pattern is used as the mask to etch the source-drain electrode thin film.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: January 29, 2019
    Assignees: BOE Technology Group Co., Ltd., Beijing BOE Optoelectronics Technology Co., Ltd.
    Inventors: Jiaxiang Zhang, Kai Lu
  • Patent number: 10192876
    Abstract: According to one embodiment, a transistor includes: a gate electrode; a gate insulating layer provided on the gate electrode; an oxide semiconductor layer provided on the gate insulating layer; an oxygen supply layer provided on the oxide semiconductor layer; a first oxygen barrier layer provided on the oxygen supply layer; a source electrode provided to penetrate the oxygen supply layer and the first oxygen barrier layer and connected to the oxide semiconductor layer; and a drain electrode spaced apart from the source electrode, provided to penetrate the oxygen supply layer and the first oxygen barrier layer, and connected to the oxide semiconductor layer.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: January 29, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Kentaro Miura, Tomomasa Ueda, Keiji Ikeda, Nobuyoshi Saito
  • Patent number: 10170631
    Abstract: The manufacturing method of oxide thin film transistors (TFTs) includes: providing a substrate and forming an oxide semiconductor active layer on the substrate; depositing an insulation dielectric layer on the active layer; and applying an annealing process to components formed after the insulation dielectric layer is deposited. After depositing the gate insulation layer on the oxide semiconductor active layer, the annealing process is applied to the formed component, which eliminates the difference of the component performance caused by the insulation dielectric layer formed by different film formation processes such that the reproducibility of the film formation processes may be enhanced.
    Type: Grant
    Filed: October 9, 2016
    Date of Patent: January 1, 2019
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd
    Inventor: Yingtao Xie
  • Patent number: 10170600
    Abstract: A manufacturing method of a semiconductor device including a step of forming a silicon layer over a formation substrate, a step of forming a resin layer over the silicon layer, a step of forming a transistor over the resin layer, a step of forming a conductive layer over the silicon layer and the resin layer, and a step of separating the formation substrate and the transistor. The resin layer has an opening over the silicon layer. The conductive layer is in contact with the silicon layer through the opening in the resin layer. In the step of separating the formation substrate and the transistor, the silicon layer is irradiated with light, so that silicon contained in the silicon layer reacts with a metal contained in the conductive layer, and a metal silicide layer is formed.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: January 1, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiro Jinbo
  • Patent number: 10168805
    Abstract: A device including a transparent or semitransparent substrate and at least one layered structure disposed on a first major surface of the substrate is described. The layered structure includes a first ITO layer on the substrate, a silicon dioxide layer on the first ITO layer opposite the substrate, and a second ITO layer on the silicon dioxide layer opposite the first ITO layer. The silicon dioxide layer includes an edge that is offset inwardly from an edge of the first ITO layer and from an edge of the second ITO layer. Methods of making the device are described.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: January 1, 2019
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Muthu Sebastian, Bret R. Humphries
  • Patent number: 10141423
    Abstract: The disclosure provides a thin film transistor (TFT) and a fabrication method thereof, an array substrate and a fabrication method thereof, and a display apparatus. The fabrication method of a TFT includes: forming a protection layer in an area on an active layer between a source electrode and a drain electrode to be formed, forming a source-drain metal layer above the active layer having the protection layer formed thereon, coating a photoresist on the source-drain metal layer, and forming a photoresist reserved area corresponding to areas of the source electrode and the drain electrode to be formed and a photoresist non-reserved area corresponding to the other area; etching off the source-drain metal layer corresponding to the photoresist non-reserved area to form the source and drain electrodes and expose the protection layer above the active layer; and removing the photoresist above the source and drain electrodes and the protection layer.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: November 27, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Huibin Guo, Xiaoxiang Zhang, Jing Wang
  • Patent number: 10128108
    Abstract: Provided are an oxide sintered compact whereby low carrier density and high carrier mobility are obtained when the oxide sintered compact is used to obtain an oxide semiconductor thin film by a sputtering method, and a sputtering target which uses the oxide sintered compact. This oxide sintered compact contains oxides of indium, gallium, and aluminum. The gallium content is from 0.15 to 0.49 by Ga/(In+Ga) atomic ratio, and the aluminum content is from 0.0001 to less than 0.25 by Al/(In+Ga+Al) atomic ratio. A crystalline oxide semiconductor thin film formed using this oxide sintered compact as a sputtering target is obtained at a carrier density of 4.0×1018 cm?3 or less and a carrier mobility of 10 cm?2V?1sec?1 or greater.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: November 13, 2018
    Assignee: SUMITOMO METAL MINING CO., LTD.
    Inventors: Eiichiro Nishimura, Tokuyuki Nakayama, Fumihiko Matsumura
  • Patent number: 10121776
    Abstract: A film-type semiconductor package includes a semiconductor integrated circuit and a dummy metal pattern. The semiconductor integrated circuit is formed on a film and includes an electrostatic discharge (ESD) protection circuit. The dummy metal pattern is formed on the film and is electrically connected to the ESD protection circuit through a first wiring formed on the film.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: November 6, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Jun Song, Young-Min Kim, Chang-Su Kim, Han-Gu Kim
  • Patent number: 10115748
    Abstract: Provided are a thin film transistor array substrate and a manufacture method thereof, comprising: providing a substrate, and the substrate comprises a first surface and a second surface, which are oppositely located; forming a gate on the first surface; forming a first insulative layer, which covers on the gate; forming a metal oxide semiconductor layer on the first insulative layer; implementing ion implantation to two end regions of the metal oxide semiconductor layer, and the two end regions after the ion implantation respectively are a source and a drain, and a region without the ion implantation is an active layer; forming a second insulative layer, which covers the source, the drain and the active layer; opening a via exposing the source or the drain in the second insulative layer; forming a pixel electrode on the second insulative layer, and connected with the source or the drain through the via.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: October 30, 2018
    Assignee: Shenzhen China Star Optoelectronics Co., Ltd
    Inventor: Jiangbo Yao
  • Patent number: 10056494
    Abstract: A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer. The source electrode and the drain electrode include an oxide region formed by oxidizing a side surface thereof. Note that the oxide region of the source electrode and the drain electrode is preferably formed by plasma treatment with a high frequency power of 300 MHz to 300 GHz and a mixed gas of oxygen and argon.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: August 21, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 10050153
    Abstract: To reduce defects in an oxide semiconductor film in a semiconductor device. To improve electrical characteristics of and reliability in the semiconductor device including an oxide semiconductor film. A method for manufacturing a semiconductor device includes the steps of forming a gate electrode and a gate insulating film over a substrate, forming an oxide semiconductor film over the gate insulating film, forming a pair of electrodes over the oxide semiconductor film, forming a first oxide insulating film over the oxide semiconductor film and the pair of electrodes by a plasma CVD method in which a film formation temperature is 280° C. or higher and 400° C. or lower, forming a second oxide insulating film over the first oxide insulating film, and performing heat treatment at a temperature of 150° C. to 400° C. inclusive, preferably 300° C. to 400° C. inclusive, further preferably 320° C. to 370° C. inclusive.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: August 14, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Yukinori Shima, Suzunosuke Hiraishi, Kenichi Okazaki
  • Patent number: 10043679
    Abstract: A method of fabricating an array substrate including forming an oxide semiconductor layer on a substrate; sequentially forming a gate insulating layer and a gate electrode corresponding to a central portion of the oxide semiconductor layer; forming source and drain areas having conductive properties in the oxide semiconductor layer by irradiating X-rays or UV rays to the oxide semiconductor layer exposed outside the gate electrode; forming an inter insulating layer on the gate electrode and having first contact holes that expose the source and drain areas; and forming source and drain electrodes on the inter insulating layer and contacting the source and drain areas through the first contact holes, respectively.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: August 7, 2018
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Hee-Jung Yang, Hyung-Tae Kim, Jae-Young Jeong, Gyu-Won Han, Dong-Sun Kim, Won-Joon Ho
  • Patent number: 10043939
    Abstract: A technique is described depositing a new formula of indium and tin salt solutions as a precursor to form a solid transparent indium tin oxide (ITO) film on non-conductive solid substrates. The utilization of this new composition of matter prompted the discovery of a method for preparing the first top-to-bottom completely solution processed solar cell. The specific patterning of the liquid-processed ITO precursor solution and the subsequent layers of a solar cell outlined here also demonstrate a unique way to connect solution processed (as opposed to deposited using vacuum techniques) solar cells in series and in parallel. Also disclosed are related methods for zinc tin oxide (ZTO), indium oxide (IO), indium zinc oxide (IZO), cadmium tin oxide (CTO), aluminum zinc oxide (AZO), and zinc oxide (ZO).
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: August 7, 2018
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Edward E. Foos, Troy K. Townsend
  • Patent number: 10038049
    Abstract: A display device, includes a substrate; first to fourth subpixels sequentially arranged on the substrate; a first power line on a left side of the first subpixel and shared by the first and second subpixels; a sensing line between the second subpixel and the third subpixel and shared by the first to fourth subpixels; a second power line on a right side of the fourth subpixel and shared by the third and fourth subpixels; and a first data line on the left side of the first subpixel, a second data line on a right side of the second subpixel, a third data line on a left side of the third subpixel, and a fourth data line on the right side of the fourth subpixel. The first and second power lines and the sensing line are disposed on a layer different from the first to fourth data lines.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: July 31, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Byeonguk Gang, Jongsik Shim, Hyunjin Kim, Joondong Kim
  • Patent number: 10014434
    Abstract: A technique is described depositing a new formula of indium and tin salt solutions as a precursor to form a solid transparent indium tin oxide (ITO) film on non-conductive solid substrates. The utilization of this new composition of matter prompted the discovery of a method for preparing the first top-to-bottom completely solution processed solar cell. The specific patterning of the liquid-processed ITO precursor solution and the subsequent layers of a solar cell outlined here also demonstrate a unique way to connect solution processed (as opposed to deposited using vacuum techniques) solar cells in series and in parallel. Also contemplated are similar compositions capable of forming zinc tin oxide (ZTO), indium oxide (IO), indium zinc oxide (IZO), cadmium tin oxide (CTO), aluminum zinc oxide (AZO), or zinc oxide (ZO).
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: July 3, 2018
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Edward E. Foos, Troy K. Townsend
  • Patent number: 9991135
    Abstract: A method for fabricating a metal oxide thin film transistor comprises selecting a substrate and fabricating a gate electrode thereon; growing a layer of dielectric or high permittivity dielectric on the substrate to serve as a gate dielectric layer; growing a first metal layer on the gate dielectric layer and a second metal layer on the first metal layer; fabricating a channel region at a middle position of the first metal layer and a passivation region at a middle position of the second metal layer; anodizing the metals of the passivation region and the channel region at atmospheric pressure and room temperature; fabricating a source and a drain; forming an active region comprising the source, the drain, and the channel region; depositing a silicon nitride layer on the active region; fabricating two electrode contact holes; depositing a metal aluminum film; and fabricating two metal contact electrodes by photolithography and etching.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: June 5, 2018
    Assignee: SHENZHEN GRADUATE SCHOOL, PEKING UNIVERSITY
    Inventors: Shengdong Zhang, Yang Shao, Xiang Xiao, Xin He
  • Patent number: 9947777
    Abstract: Provided is a semiconductor device having favorable reliability.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: April 17, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kazutaka Kuriki, Yuji Egi, Hiromi Sawai, Yusuke Nonaka, Noritaka Ishihara, Daisuke Matsubayashi
  • Patent number: 9917206
    Abstract: A semiconductor element having high mobility, which includes an oxide semiconductor layer having crystallinity, is provided. The oxide semiconductor layer includes a stacked-layer structure of a first oxide semiconductor film and a second oxide semiconductor film having a wider band gap than the first oxide semiconductor film, which is in contact with the first oxide semiconductor film. Thus, a channel region is formed in part of the first oxide semiconductor film (that is, in an oxide semiconductor film having a smaller band gap) which is in the vicinity of an interface with the second oxide semiconductor film. Further, dangling bonds in the first oxide semiconductor film and the second oxide semiconductor film are bonded to each other at the interface therebetween. Accordingly, a decrease in mobility resulting from an electron trap or the like due to dangling bonds can be reduced in the channel region.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: March 13, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Junichi Koezuka
  • Patent number: 9911602
    Abstract: A method and structure for integrating gallium nitride into a semiconductor substrate. The method may also include means for isolating the gallium nitride from the semiconductor substrate.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: March 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: William J. Gallagher, Effendi Leobandung, Devendra K. Sadana, Ghavam G. Shahidi
  • Patent number: 9911765
    Abstract: A thin film transistor (TFT) located on a thin film transistor substrate includes a first insulating film formed so as to cover a gate electrode, a channel layer that is formed at a position on the first insulating film overlapping the gate electrode and formed of an oxide semiconductor, a second insulating film formed on the channel layer, and a third insulating film formed so as to cover the second insulating film. A source electrode and a drain electrode are formed on the third insulating film. Each of the source electrode and the drain electrode is connected to the channel layer through the corresponding one of contact holes penetrating the second insulating film and the third insulating film.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: March 6, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ken Imamura, Kazushi Yamayoshi, Kazunori Inoue
  • Patent number: 9893198
    Abstract: A method for manufacturing a thin film transistor (TFT) which includes a gate, a gate insulation layer, a channel layer, an etching stopping layer, a source, and a drain. The gate is formed on a substrate. The gate insulation layer covers the gate and the substrate. The channel layer is formed on the gate insulation layer to correspond with the gate. The etching stopping layer is formed on a surface of the channel layer. The channel layer and the etching stopping layer are formed in a same photo etching process.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: February 13, 2018
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Kuo-Lung Fang, Yi-Chun Kao, Hsin-Hua Lin, Po-Li Shih, Chih-Lung Lee
  • Patent number: 9893196
    Abstract: A transistor including an oxide semiconductor with favorable electric characteristics and a manufacturing method thereof are provided. A semiconductor device includes a transistor. The transistor includes an oxide semiconductor film over a base insulating film, a gate electrode overlapping with the oxide semiconductor film with a gate insulating film interposed therebetween, and a pair of electrodes in contact with the oxide semiconductor film and serving as a source electrode and a drain electrode. The base insulating film includes a first oxide insulating film partly in contact with the oxide semiconductor film and a second oxide insulating film in the periphery of the first oxide insulating film. An end portion of the oxide semiconductor film which crosses the channel width direction of the transistor is located over the second oxide insulating film.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: February 13, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9887291
    Abstract: A change in electrical characteristics is suppressed and reliability is improved in a semiconductor device provided with a transistor including an oxide semiconductor. A semiconductor device includes a transistor. The transistor includes a gate electrode, a first insulating film over the gate electrode, a second insulating film over the first insulating film, an oxide semiconductor film over the second insulating film, a first buffer film over the oxide semiconductor film, a second buffer film over the oxide semiconductor film, a source electrode electrically connected with the oxide semiconductor film, and a drain electrode electrically connected with the oxide semiconductor film. The source electrode is electrically connected with the oxide semiconductor film through the first buffer film. The drain electrode is electrically connected with the oxide semiconductor film through the second buffer film.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: February 6, 2018
    Assignee: Semiconductor Energy Laboratory Co., LTD.
    Inventors: Yukie Suzuki, Yoshiaki Oikawa
  • Patent number: 9880436
    Abstract: A liquid crystal display device includes a gate electrode, a first insulating film, an element layer, a first transparent electrode, and a second transparent electrode. The first insulating film includes a part that covers the gate electrode. The element layer is directly disposed on the first insulating film, includes a channel region that faces the gate electrode across the first insulating film, and is made of a transparent oxide. The first transparent electrode is directly disposed on the first insulating film while being separated from the element layer, and has the same metal composition as the metal composition of the element layer. The second transparent electrode forms a storage capacitance with the first transparent electrode by facing the first transparent electrode while being electrically insulated from the first transparent electrode.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: January 30, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yuki Tsuda, Takuji Imamura
  • Patent number: 9865744
    Abstract: The semiconductor device includes a power element which is in an on state when voltage is not applied to a gate, a switching field-effect transistor for applying first voltage to the gate of the power element, and a switching field-effect transistor for applying voltage lower than the first voltage to the gate of the power element. The switching field-effect transistors have small off-state current.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: January 9, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 9853157
    Abstract: A method includes forming a metal-oxide-semiconductor field-effect transistor (MOSFET). The Method includes performing an implantation to form a pre-amorphization implantation (PAI) region adjacent to a gate electrode of the MOSFET, forming a strained capping layer over the PAI region, and performing an annealing on the strained capping layer and the PAI region to form a dislocation plane. The dislocation plane is formed as a result of the annealing, with a tilt angle of the dislocation plane being smaller than about 65 degrees.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: December 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Wei-Yuan Lu
  • Patent number: 9853214
    Abstract: A resistive random access memory includes a first electrode, a separating medium, a resistance changing layer and a second electrode. The first electrode has a mounting face. The separating medium has a first face in contact with the mounting face, a second face opposite to the first face, and an inner face extending between the first and second faces. The separating medium forms a through hole extending from the first to second face. A part of the mounting face is not covered by the separating medium. The separating medium has a first dielectric. The resistance changing layer extends along the part of the mounting face as well as the inner and second faces. The resistance changing layer has a second dielectric having a dielectric constant larger than a dielectric constant of the first dielectric by 2 or less. The second electrode is arranged on the resistance changing layer.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: December 26, 2017
    Assignee: National Sun Yat-Sen University
    Inventors: Ting-Chang Chang, Kuan-Chang Chang, Tsung-Ming Tsai, Tian-Jian Chu, Chih-Hung Pan
  • Patent number: 9829533
    Abstract: An oxide semiconductor film having high stability with respect to light irradiation or a semiconductor device having high stability with respect to light irradiation is provided. One embodiment of the present invention is a semiconductor film including an oxide in which light absorption is observed by a constant photocurrent method (CPM) in a wavelength range of 400 nm to 800 nm, and in which an absorption coefficient of a defect level, which is obtained by removing light absorption due to a band tail from the light absorption, is lower than or equal to 5×10?2/cm. Alternatively, a semiconductor device is manufactured using the semiconductor film.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: November 28, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Tsubuku, Ryosuke Watanabe
  • Patent number: 9822322
    Abstract: The invention relates to a coating comprising at least one molybdenum-containing layer having molybdenum oxide, said molybdenum being essentially molybdenum monoxide. The invention further relates to a PVD process for producing the disclosed coating, in which the layer comprising the molybdenum monoxide is produced using arc evaporation. The invention also relates to a component that has said coating.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: November 21, 2017
    Assignee: OERLIKON SURFACE SOLUTIONS AG, PFAFFIKON
    Inventors: Jurgen Ramm, Beno Widrig, Kerstin Glantz, Florian Seibert
  • Patent number: 9778521
    Abstract: A display apparatus includes pixels. Each pixel includes a first pixel electrode, a second pixel electrode, a black matrix, a shielding electrode, and first and second sub-shielding electrodes. The first pixel electrode is disposed in a first pixel area. The second pixel electrode is disposed in a second pixel area. The black matrix is disposed in a predetermined area of a first boundary area between the first pixel area and the second pixel area. The shielding electrode is disposed between first pixel areas and between second pixel areas, which are arranged in a first direction, and extends in a second direction crossing the first direction. The first and second sub-shielding electrodes branch from the shielding electrode along the first direction and are spaced apart from each other in the first boundary area while the black matrix is disposed therebetween.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: October 3, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyunggi Jung, Younggoo Song, Kipyo Hong
  • Patent number: 9768314
    Abstract: To reduce defects in an oxide semiconductor film in a semiconductor device. To improve electrical characteristics of and reliability in the semiconductor device including an oxide semiconductor film. A method for manufacturing a semiconductor device includes the steps of forming a gate electrode and a gate insulating film over a substrate, forming an oxide semiconductor film over the gate insulating film, forming a pair of electrodes over the oxide semiconductor film, forming a first oxide insulating film over the oxide semiconductor film and the pair of electrodes by a plasma CVD method in which a film formation temperature is 280° C. or higher and 400° C. or lower, forming a second oxide insulating film over the first oxide insulating film, and performing heat treatment at a temperature of 150° C. to 400° C. inclusive, preferably 300° C. to 400° C. inclusive, further preferably 320° C. to 370° C. inclusive.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: September 19, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Yukinori Shima, Suzunosuke Hiraishi, Kenichi Okazaki
  • Patent number: 9768317
    Abstract: Provided is a semiconductor device which can suppress an increase in oxygen vacancies in an oxide semiconductor layer and a manufacturing method of the semiconductor device. The semiconductor device includes a first oxide semiconductor layer over the first insulating layer; a second oxide semiconductor layer over the first oxide semiconductor layer; a third oxide semiconductor layer over the second oxide semiconductor layer; a source electrode layer and a drain electrode layer each over the third oxide semiconductor layer; a fourth semiconductor layer over the source and drain electrode layers, and the third oxide semiconductor layer; a gate insulating layer over the fourth oxide semiconductor layer; a gate electrode layer over the gate electrode layer and overlapping with the source and drain electrode layers, and the fourth oxide semiconductor layer; and a second insulating layer over the first insulating layer, and the source, gate, and drain electrode layers.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: September 19, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daigo Ito, Takahisa Ishiyama, Kazuya Hanaoka