Having Metal Oxide Or Copper Sulfide Compound Semiconductor Component Patents (Class 438/104)
  • Patent number: 9437627
    Abstract: A manufacturing method of a thin film transistor includes the following steps. A substrate is provided first. A semiconductor layer is then formed on the substrate. Next, a photoresist pattern including a middle portion and two peripheral portions is formed on the semiconductor layer. The middle portion is disposed between two peripheral portions, and the thickness of the middle portion is greater than each of the peripheral portions. Next, an etching process is performed on the semiconductor layer for forming a patterned semiconductor layer. A photoresist ashing process is then performed to remove at least the peripheral portions of the photoresist pattern to form a channel defining photoresist pattern and expose two portions of the patterned semiconductor layer. Next, the patterned semiconductor layer is treated to form a semiconductor portion and two conductor portions. The channel defining photoresist pattern is then removed.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: September 6, 2016
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Chin-Tzu Kao, Wen-Cheng Lu, Ya-Ju Lu
  • Patent number: 9412519
    Abstract: A method is provided for concurrently forming terminals on a multilayer capacitor having a first plurality of interior plates with edges that are brought to and exposed upon a first surface and a second plurality of interior plates, interleaved with the first plurality of interior plates, and spaced from the first plates by a dielectric. The second plurality of interior plates has edges that are brought to and exposed upon a second surface, which is not adjacent to the first surface. A first terminal is formed by plating a layer of electrically-conductive first metal directly onto the first surface including where the edges of the first plates are exposed upon the first surface and concurrently forming a second terminal by plating a layer of electrically-conductive first metal directly onto the second surface including where the edges of the second plates are exposed upon the second surface.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: August 9, 2016
    Assignee: Presido Components, Inc.
    Inventor: Hung Van Trinh
  • Patent number: 9391267
    Abstract: A method for etching a stack with at least one metal layer in one or more cycles is provided. An initiation step is preformed, transforming part of the at least one metal layer into metal oxide, metal halide, or lattice damaged metallic sites. A reactive step is performed providing one or more cycles, where each cycle comprises providing an organic solvent vapor to form a solvated metal, metal halide, or metal oxide state and providing an organic ligand solvent to form volatile organometallic compounds.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: July 12, 2016
    Assignee: Lam Research Corporation
    Inventors: Meihua Shen, Harmeet Singh, Samantha S. H. Tan, Jeffrey Marks, Thorsten Lill, Richard P. Janek, Wenbing Yang, Prithu Sharma
  • Patent number: 9391096
    Abstract: To provide a highly reliable semiconductor device. The semiconductor device includes a first oxide layer over an insulating film; an oxide semiconductor layer over the first oxide layer; a gate insulating film over the oxide semiconductor layer; and a gate electrode over the gate insulating film. The first oxide layer contains indium. The oxide semiconductor layer contains indium and includes a channel formation region. The distance from the interface to the channel formation region is 20 nm or more, preferably 30 nm or more, further preferably 40 nm or more, still further preferably 60 nm or more.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: July 12, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Daisuke Matsubayashi, Hideomi Suzawa, Tetsuhiro Tanaka, Hirokazu Watanabe
  • Patent number: 9384976
    Abstract: It is an object to drive a semiconductor device at high speed or to improve the reliability of the semiconductor device. In a method for manufacturing the semiconductor device, in which a gate electrode is formed over a substrate with an insulating property, a gate insulating film is formed over the gate electrode, and an oxide semiconductor film is formed over the gate insulating film, the gate insulating film is formed by deposition treatment using high-density plasma. Accordingly, dangling bonds in the gate insulating film are reduced and the quality of the interface between the gate insulating film and the oxide semiconductor is improved.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: July 5, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Mitsuhiro Ichijo, Tetsuhiro Tanaka, Seiji Yasumoto, Shun Mashiro, Yoshiaki Oikawa, Kenichi Okazaki
  • Patent number: 9379250
    Abstract: This semiconductor device (100A) includes: a substrate (2); a gate electrode (3) formed on the substrate (2); a gate insulating layer (4) formed over the gate electrode (3); an oxide semiconductor layer (5) formed on the gate insulating layer (4); source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5); a first transparent electrode (7) electrically connected to the drain electrode (6d); an interlayer insulating layer (8a) including portions formed on the source and drain electrodes (6s, 6d); and a second transparent electrode (9) formed on the interlayer insulating layer (8a). At least a portion of the second transparent electrode (9) overlaps with the first transparent electrode (7) with the interlayer insulating layer (8a) interposed between them. And the oxide semiconductor layer (5) and the first transparent electrode (7) are formed out of a same oxide film.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: June 28, 2016
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Seiichi Uchida, Yasuyuki Ogawa, Tadayoshi Miyamoto, Kazuatsu Ito, Yutaka Takamaru, Makoto Nakazawa, Mitsunobu Miyamoto
  • Patent number: 9368633
    Abstract: An object is to provide a material suitably used for a semiconductor included in a transistor, a diode, or the like. Another object is to provide a semiconductor device including a transistor in which the condition of an electron state at an interface between an oxide semiconductor film and a gate insulating film in contact with the oxide semiconductor film is favorable. Further, another object is to manufacture a highly reliable semiconductor device by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used for a channel. A semiconductor device is formed using an oxide material which includes crystal with c-axis alignment, which has a triangular or hexagonal atomic arrangement when seen from the direction of a surface or an interface and rotates around the c-axis.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: June 14, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Motoki Nakashima, Tatsuya Honda
  • Patent number: 9353433
    Abstract: A method of fabricating a liquid for an oxide thin film is provided, which includes mixing at least two kinds of dispersoids selected from the group consisting of a Zinc compound, an Indium compound, a Gallium compound, a Tin compound and a Thallium compound, with dispersion media corresponding to the selected dispersoids to form a dispersion system, and stirring and aging the dispersion system at a predetermined temperature for a predetermined time, wherein a molar ratio of the Zinc compound to each of the Indium compound, Gallium compound, Tin compound and Thallium compound is 1:0.1 to 1:2. According to the present invention, the liquid for the oxide thin film may be fabricated by a sol-gel method making it capable of being implemented in mass production in a simple and low-cost manner as opposed to the conventional vacuum deposition method.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: May 31, 2016
    Assignee: Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Hyun Jae Kim, Kyung Ho Kim, Gun Hee Kim, Tae Hoon Jeong, Hyun Soo Shin, Won Jun Park, Yun Jung Choi, Ka Young Lee
  • Patent number: 9305989
    Abstract: An organic light-emitting display and a method of manufacturing an organic light-emitting display are described. According to an aspect, the organic light-emitting display includes a substrate, a photodiode on the substrate, a planarization layer covering the photodiode, a first electrode on the planarization layer, a pixel defining layer at least partially exposing the first electrode, an organic layer covering the first electrode which is exposed by the pixel defining layer and a second electrode covering the pixel defining layer and the organic layer.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: April 5, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hai Jung In, Yong Sung Park
  • Patent number: 9287390
    Abstract: A transistor with superior electric characteristics is manufactured. An oxide insulating film is formed over a substrate, an oxide semiconductor film is formed over the oxide insulating film, heat treatment is then conducted at a temperature at which hydrogen contained in the oxide semiconductor film is desorbed and part of oxygen contained in the oxide insulating film is desorbed, then the heated oxide semiconductor film is etched into a predetermined shape to form an island-shaped oxide semiconductor film, a pair of electrodes is formed over the island-shaped oxide semiconductor film, a gate insulating film is formed over the pair of electrodes and the island-shaped oxide semiconductor film, and a gate electrode is formed over the gate insulating film.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: March 15, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kosei Noda, Toshinari Sasaki
  • Patent number: 9276124
    Abstract: Provided is a method for manufacturing a semiconductor device so as not expose a semiconductor layer to moisture and the number of masks is reduced. For example, a first conductive film, a first insulating film, a semiconductor film, a second conductive film, and a mask film are formed. The first mask film is processed to form a first mask layer. Dry etching is performed on the first insulating film, the semiconductor film, and the second conductive film with the use of the first mask layer to form a thin film stack body, so that a surface of the first conductive film is at least exposed. Sidewall insulating layers covering side surfaces of the thin film stack body are formed. The first conductive film is side-etched to form a first electrode. A second electrode layer is formed with the second mask layer.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: March 1, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takafumi Mizoguchi, Kojiro Shiraishi
  • Patent number: 9246011
    Abstract: A semiconductor device including a transistor having a reduced number of oxygen vacancies in a channel formation region of an oxide semiconductor with stable electrical characteristics or high reliability is provided. A gate insulating film is formed over a gate electrode; an oxide semiconductor layer is formed over the gate insulating film; an oxide layer is formed over the oxide semiconductor layer by a sputtering method to form an stacked-layer oxide film including the oxide semiconductor layer and the oxide layer; the stacked-layer oxide film is processed into a predetermined shape; a conductive film containing Ti as a main component is formed over the stacked-layer oxide film; the conductive film is etched to form source and drain electrodes and a depression portion on a back channel side; and portions of the stacked-layer oxide film in contact with the source and drain electrodes are changed to an n-type by heat treatment.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: January 26, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasutaka Nakazawa, Masami Jintyou, Junichi Koezuka, Kenichi Okazaki, Takuya Hirohashi, Shunsuke Adachi
  • Patent number: 9240489
    Abstract: An object is to provide a material suitably used for a semiconductor included in a transistor, a diode, or the like. Another object is to provide a semiconductor device including a transistor in which the condition of an electron state at an interface between an oxide semiconductor film and a gate insulating film in contact with the oxide semiconductor film is favorable. Further, another object is to manufacture a highly reliable semiconductor device by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used for a channel. A semiconductor device is formed using an oxide material which includes crystal with c-axis alignment, which has a triangular or hexagonal atomic arrangement when seen from the direction of a surface or an interface and rotates around the c-axis.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: January 19, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Motoki Nakashima, Tatsuya Honda
  • Patent number: 9236454
    Abstract: A method of fabricating a thin-film transistor, the method including: film-forming an active layer, that contains as a main component thereof an oxide semiconductor structured by O and at least two elements among In, Ga and Zn, in a film formation chamber into which at least oxygen is introduced, and b) heat treating the active layer at less than 300° C. in a dry atmosphere, wherein the film-forming a) and the heat treating are carried out such that, given that an oxygen partial pressure with respect to an entire pressure of an atmosphere within the film formation chamber in the film-forming is PO2depo (%), and an oxygen partial pressure with respect to an entire pressure of an atmosphere during the heat treating is PO2anneal (%), the oxygen partial pressure PO2anneal (%) at the time of the heat treating b) satisfies a relationship: ?20/3PO2depo+40/3?PO2anneal??800/43PO2depo+5900/43.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: January 12, 2016
    Assignee: FUJIFILM Corporation
    Inventors: Masashi Ono, Masahiro Takata, Atsushi Tanaka, Masayuki Suzuki
  • Patent number: 9231110
    Abstract: It is an object to provide a highly reliable semiconductor device including a thin film transistor whose electric characteristics are stable. In addition, it is another object to manufacture a highly reliable semiconductor device at low cost with high productivity. In a semiconductor device including a thin film transistor, a semiconductor layer of the thin film transistor is formed with an oxide semiconductor layer to which a metal element is added. As the metal element, at least one of metal elements of iron, nickel, cobalt, copper, gold, manganese, molybdenum, tungsten, niobium, and tantalum is used. In addition, the oxide semiconductor layer contains indium, gallium, and zinc.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: January 5, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Junichiro Sakata
  • Patent number: 9224838
    Abstract: An object is to provide an oxide semiconductor having stable electric characteristics and a semiconductor device including the oxide semiconductor. A manufacturing method of a semiconductor film by a sputtering method includes the steps of holding a substrate in a treatment chamber which is kept in a reduced-pressure state; heating the substrate at lower than 400° C.; introducing a sputtering gas from which hydrogen and moisture are removed in the state where remaining moisture in the treatment chamber is removed; and forming an oxide semiconductor film over the substrate with use of a metal oxide which is provided in the treatment chamber as a target. When the oxide semiconductor film is formed, remaining moisture in a reaction atmosphere is removed; thus, the concentration of hydrogen and the concentration of hydride in the oxide semiconductor film can be reduced. Thus, the oxide semiconductor film can be stabilized.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: December 29, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Akiharu Miyanaga, Masayuki Sakakura, Junichi Koezuka, Tetsunori Maruyama, Yuki Imoto
  • Patent number: 9209358
    Abstract: Disclosed are a semiconductor device and a method of fabricating the same. A light emitting diode (LED) includes a conductive substrate, and a gallium nitride (GaN)-based semiconductor stack positioned on the conductive substrate. The semiconductor stack includes an active layer that is a semi-polar semiconductor layer. Accordingly, it is possible to provide an LED having improved light emitting efficiency.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: December 8, 2015
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Won Cheol Seo, Dae Sung Cho, Chung Hoon Lee, Ki Bum Nam
  • Patent number: 9203029
    Abstract: A method for producing an electronic component with at least one first electrode zone (21) and one second electrode zone (23), which are separated from one another by an insulator (9) and each comprise at least one sublayer of a first electrically conductive material. Also disclosed is an electronic component, which may be produced using the disclosed method.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: December 1, 2015
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Andrew Ingle, Tilman Schlenker, Karsten Heuser
  • Patent number: 9184245
    Abstract: To provide a highly reliable semiconductor device exhibiting stable electrical characteristics. To fabricate a highly reliable semiconductor device. Included are an oxide semiconductor stack in which a first to a third oxide semiconductor layers are stacked, a source and a drain electrode layers contacting the oxide semiconductor stack, a gate electrode layer overlapping with the oxide semiconductor layer with a gate insulating layer provided therebetween, and a first and a second oxide insulating layers between which the oxide semiconductor stack is sandwiched. The first to the third oxide semiconductor layers each contain indium, gallium, and zinc. The proportion of indium in the second oxide semiconductor layer is higher than that in each of the first and the third oxide semiconductor layers. The first and the third oxide semiconductor layers are each an amorphous semiconductor film. The second oxide semiconductor layer is a crystalline semiconductor film.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: November 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9178145
    Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: November 3, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Nitin Kumar, Tony P. Chiang, Chi-I Lang, Zhi-Wen Wen Sun, Jinhong Tong
  • Patent number: 9171959
    Abstract: Provided is a miniaturized transistor with stable and high electrical characteristics with high yield. In a semiconductor device including the transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode layer are stacked in this order, a first sidewall insulating layer is provided in contact with a side surface of the gate electrode layer, and a second sidewall insulating layer is provided to cover a side surface of the first sidewall insulating layer. The first sidewall insulating layer is an aluminum oxide film in which a crevice with an even shape is formed on its side surface. The second sidewall insulating layer is provided to cover the crevice. A source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor film and the second sidewall insulating layer.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: October 27, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Motomu Kurata, Shinya Sasagawa, Taiga Muraoka, Tetsuhiro Tanaka, Junichi Koezuka
  • Patent number: 9159815
    Abstract: An object is, in a thin film transistor in which an oxide semiconductor is used as an active layer, to prevent change in composition, film quality, an interface, or the like of an oxide semiconductor region serving as an active layer, and to stabilize electrical characteristics of the thin film transistor. In a thin film transistor in which a first oxide semiconductor region is used as an active layer, a second oxide semiconductor region having lower electrical conductivity than the first oxide semiconductor region is formed between the first oxide semiconductor region and a protective insulating layer for the thin film transistor, whereby the second oxide semiconductor region serves as a protective layer for the first oxide semiconductor region; thus, change in composition or deterioration in film quality of the first oxide semiconductor region can be prevented, and electrical characteristics of the thin film transistor can be stabilized.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: October 13, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Toshinari Sasaki, Hideaki Kuwabara
  • Patent number: 9153651
    Abstract: Provided are a thin film transistor and a method for manufacturing the same. The thin film transistor manufacturing method includes forming a gate electrode on a substrate, forming an active layer that is adjacent to the gate electrode and includes an oxide semiconductor, forming an oxygen providing layer on the active layer, forming a gate dielectric between the gate electrode and the active layer, forming source and drain electrodes coupled to the active layer, forming a planarizing layer covering the gate electrode and the gate dielectric, forming a hole exposing the active layer, and performing a heat treatment process onto the planarizing layer in an atmosphere of oxygen.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: October 6, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sang Chul Lim, Ji-Young Oh, Seongdeok Ahn, Kyoung Ik Cho, Sang Seok Lee, Jae Bon Koo
  • Patent number: 9142683
    Abstract: A semiconductor device includes an oxide semiconductor layer including a channel formation region which includes an oxide semiconductor having a wide band gap and a carrier concentration which is as low as possible, and a source electrode and a drain electrode which include an oxide conductor containing hydrogen and oxygen vacancy, and a barrier layer which prevents diffusion of hydrogen and oxygen between an oxide conductive layer and the oxide semiconductor layer. The oxide conductive layer and the oxide semiconductor layer are electrically connected to each other through the barrier layer.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: September 22, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto
  • Patent number: 9136390
    Abstract: A semiconductor device which includes a thin film transistor having an oxide semiconductor layer and excellent electrical characteristics is provided. Further, a method for manufacturing a semiconductor device in which plural kinds of thin film transistors of different structures are formed over one substrate to form plural kinds of circuits and in which the number of steps is not greatly increased is provided. After a metal thin film is formed over an insulating surface, an oxide semiconductor layer is formed thereover. Then, oxidation treatment such as heat treatment is performed to oxidize the metal thin film partly or entirely. Further, structures of thin film transistors are different between a circuit in which emphasis is placed on the speed of operation, such as a logic circuit, and a matrix circuit.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: September 15, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Jun Koyama
  • Patent number: 9136115
    Abstract: An object is to manufacture a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which an oxide semiconductor film is used for a semiconductor layer including a channel formation region, heat treatment (for dehydration or dehydrogenation) is performed to improve the purity of the oxide semiconductor film and reduce impurities including moisture or the like. After that, slow cooling is performed under an oxygen atmosphere. Besides impurities including moisture or the like exiting in the oxide semiconductor film, heat treatment causes reduction of impurities including moisture or the like exiting in a gate insulating layer and those in interfaces between the oxide semiconductor film and films which are provided over and below the oxide semiconductor and in contact therewith.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: September 15, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshinari Sasaki, Junichiro Sakata, Hiroki Ohara, Shunpei Yamazaki
  • Patent number: 9130158
    Abstract: A method for etching a stack with at least one metal layer in one or more cycles is provided. An initiation step is preformed, transforming part of the at least one metal layer into metal oxide, metal halide, or lattice damaged metallic sites. A reactive step is performed providing one or more cycles, where each cycle comprises providing an organic solvent vapor to form a solvated metal, metal halide, or metal oxide state and providing an organic ligand solvent to form volatile organometallic compounds. A desorption of the volatile organometallic compounds is performed.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: September 8, 2015
    Assignee: Lam Research Corporation
    Inventors: Meihua Shen, Harmeet Singh, Samantha S. H. Tan, Jeffrey Marks, Thorsten Lill, Richard P. Janek, Wenbing Yang, Prithu Sharma
  • Patent number: 9123751
    Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks. In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by dry etching in which an etching gas is used, and a second etching step is performed by wet etching in which an etchant is used.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: September 1, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunichi Ito, Miyuki Hosoba, Hideomi Suzawa, Shinya Sasagawa, Taiga Muraoka
  • Patent number: 9112040
    Abstract: Embodiments of the disclosed technology provide an amorphous oxide thin film transistor (TFT), a method for preparing an amorphous oxide TFT, and a display panel. The amorphous oxide thin film transistor includes: a gate electrode, a gate insulating layer, a semiconductor active layer, a source electrode and a drain electrode. The semiconductor active layer comprises a channel layer and an ohmic contact layer, and the channel layer has a greater content of oxygen than the ohmic contact layer; the channel layer contacts the gate insulating layer, and the ohmic contact layer comprises two separated ohmic contact regions, one of which contacts the source electrode and the other of which contacts the drain electrode.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: August 18, 2015
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiaodi Liu, Li Sun, Haijing Chen
  • Patent number: 9105668
    Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor film, which has stable electric characteristics and high reliability. A crystalline oxide semiconductor film is formed, without performing a plurality of steps, as follows: by utilizing a difference in atomic weight of plural kinds of atoms included in an oxide semiconductor target, zinc with low atomic weight is preferentially deposited on an oxide insulating film to form a seed crystal including zinc; and tin, indium, or the like with high atomic weight is deposited on the seed crystal while causing crystal growth. Further, a crystalline oxide semiconductor film is formed by causing crystal growth using a seed crystal with a hexagonal crystal structure including zinc as a nucleus, whereby a single crystal oxide semiconductor film or a substantially single crystal oxide semiconductor film is formed.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: August 11, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yusuke Nonaka, Takayuki Inoue, Masashi Tsubuku, Kengo Akimoto, Akiharu Miyanaga
  • Patent number: 9105659
    Abstract: An embodiment is to include a staggered (top gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: August 11, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Akiharu Miyanaga, Kengo Akimoto, Kojiro Shiraishi
  • Patent number: 9096441
    Abstract: Disclosed is a composition for forming a zinc oxide thin film, which contains an organic zinc compound as a starting material, is not ignitable, and can be easily handled. The composition for forming a zinc oxide thin film is capable of forming a transparent zinc oxide thin film which is not doped or doped with a group 3B element by being heated at 300° C. or less. Also disclosed is a method for obtaining a transparent zinc oxide thin film, which is not doped or doped with a group 3B element, using the composition. Specifically, the composition for forming a zinc oxide thin film contains a product which is obtained by partially hydrolyzing an organic zinc compound by adding water to the organic zinc compound or a solution of the organic zinc compound and a group 3B element compound. In cases when a group 3B element compound is contained, the molar ratio of the group 3B element compound to the organic zinc compound is within the range of 0.005-0.3.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: August 4, 2015
    Assignee: TOSOH FINECHEM CORPORATION
    Inventors: Koichiro Inaba, Kouji Toyota, Kenichi Haga, Kouichi Tokudome
  • Patent number: 9099178
    Abstract: This invention belongs to the technical field of memories and specifically relates to a resistive random access memory structure with an electric-field strengthened layer and a manufacturing method thereof. The resistive random access memory in the present invention can include a top electrode, a bottom electrode and a composite layer which is placed between the top electrode and the bottom electrode and have a first resistive switching layer and a second resistive switching and electric-field strengthened layer; the second resistive switching and electric-field strengthened layer cab be adjacent to the first resistive switching layer and have a dielectric constant lower than that of the first resistive switching layer. The electric-field distribution in the RRAM unit is adjustable.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: August 4, 2015
    Assignee: Fudan University
    Inventors: Wei Zhang, Lin Chen, Peng Zhou, Qingqing Sun, Pengfei Wang
  • Patent number: 9093427
    Abstract: A method for fabricating a semiconductor device is disclosed in the present invention. The abovementioned method comprises the following steps. Firstly, a gate is formed on a substrate. A gate insulating layer is then formed on the gate, and further an active layer is disposed on the gate insulating layer, wherein the active layer is composed of a microwave absorbing material. Source/drain is defined on the active layer to form the semiconductor device, and a microwave annealing process is finally performed thereon.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: July 28, 2015
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Po-Tsun Liu, Li-Feng Teng, Yuan-Jou Lo, Yao-Jen Lee
  • Patent number: 9093262
    Abstract: An object is to provide a semiconductor device having stable electric characteristics in which an oxide semiconductor is used. An oxide semiconductor layer is subjected to heat treatment for dehydration or dehydrogenation treatment in a nitrogen gas or an inert gas atmosphere such as a rare gas (e.g., argon or helium) or under reduced pressure and to a cooling step for treatment for supplying oxygen in an atmosphere of oxygen, an atmosphere of oxygen and nitrogen, or the air (having a dew point of preferably lower than or equal to ?40° C., still preferably lower than or equal to ?50° C.) atmosphere. The oxide semiconductor layer is thus highly purified, whereby an i-type oxide semiconductor layer is formed. A semiconductor device including a thin film transistor having the oxide semiconductor layer is manufactured.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: July 28, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Miyuki Hosoba, Junichiro Sakata, Hiroki Ohara, Shunpei Yamazaki
  • Patent number: 9087907
    Abstract: According to example embodiments, a thin film transistor (TFT) includes a channel layer including zinc, nitrogen, and oxygen; an etch stop layer on the channel layer; source and drain electrodes respectively contacting both ends of the channel layer; a gate electrode corresponding to the channel layer; and a gate insulating layer between the channel layer and the gate electrode. The etch stop layer includes fluorine. The channel layer may be on the gate electrode.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: July 21, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-suk Kim, Sun-jae Kim, Tae-sang Kim, Myung-kwan Ryu, Joon-seok Park, Kyoung-seok Son
  • Patent number: 9087745
    Abstract: It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: July 21, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Kengo Akimoto, Kojiro Shiraishi
  • Patent number: 9082858
    Abstract: The band tail state and defects in the band gap are reduced as much as possible, whereby optical absorption of energy which is in the vicinity of the band gap or less than or equal to the band gap is reduced. In that case, not by merely optimizing conditions of manufacturing an oxide semiconductor film, but by making an oxide semiconductor to be a substantially intrinsic semiconductor or extremely close to an intrinsic semiconductor, defects on which irradiation light acts are reduced and the effect of light irradiation is reduced essentially. That is, even in the case where light with a wavelength of 350 nm is delivered at 1×1013 photons/cm2·sec, a channel region of a transistor is formed using an oxide semiconductor, in which the absolute value of the amount of the variation in the threshold voltage is less than or equal to 0.65 V.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: July 14, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Tsubuku, Kosei Noda
  • Patent number: 9082794
    Abstract: A method is provided for fabricating a thin film transistor. An insulating and a metal gate contact layer are deposited on a substrate with the insulating layer being positioned between the gate contact layer and the substrate. A portion of the gate contact layer is selectively removed utilizing reactive ion etching incorporating a gas that etches the gate contact layer but not the insulating layer. A plurality of layers is deposited over a remaining portion of the gate contact layer and insulating layer, which include a gate insulating layer, a channel layer, and a metal film. A portion of the metal film is selectively removed utilizing reactive ion etching incorporating the gas that etches the metal film but not the channel layer. The insulating layer includes a high resistivity insulator that can be deposited at temperatures less than 400° C. and the channel layer is comprised of a metal oxide semiconductor.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: July 14, 2015
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Burhan Bayraktaroglu, Kevin D Leedy
  • Patent number: 9076871
    Abstract: One embodiment of the present invention is a material which is suitable for a semiconductor included in a transistor, a diode, or the like. One embodiment of the present invention is an oxide material represented as InM1XM2(1-X)ZnYOZ (0<X<1, 0<Y<1, and Z<1), where M1 is an element belonging to Group 13 and preferably Ga, and M2 is an element belonging to Group 4 or 14. Typically, the content of M2 is arranged to be greater than or equal to 1 atomic % and less than 50 atomic % of that of M1. Generation of oxygen vacancies can be suppressed in an oxide semiconductor material having the above composition. It is also possible to further improve reliability of a transistor with the oxide semiconductor material with the above composition by compensating oxygen vacancies with excessive oxygen.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: July 7, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daisuke Matsubayashi
  • Patent number: 9076647
    Abstract: A method of forming an oxide layer. The method includes: forming a layer of reaction-inhibiting functional groups on a surface of a substrate; forming a layer of precursors of a metal or a semiconductor on the layer of the reaction-inhibiting functional groups; and oxidizing the precursors of the metal or the semiconductor in order to obtain a layer of a metal oxide or a semiconductor oxide. According to the method, an oxide layer having a high thickness uniformity may be formed and a semiconductor device having excellent electrical characteristics may be manufactured.
    Type: Grant
    Filed: April 28, 2012
    Date of Patent: July 7, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk-jin Chung, Youn-soo Kim, Cha-young Yoo, Jong-cheol Lee, Sang-yeol Kang
  • Patent number: 9064791
    Abstract: A method for producing a p-type ZnO based compound semiconductor layer including the steps of (a) supplying (i) Zn, (ii) O, (iii) optional Mg, and (iv) a Group 11 element which is Cu and/or Ag to form a MgxZn1-xO (0?x?0.6) single crystal film doped with the Group 11 element; (b) supplying at least one Group 13 element selected from the group consisting of B, Ga, Al, and In on the MgxZn1-xO (0?x?0.6) single crystal film; (c) alternately carrying out the steps (a) and (b) to form a laminate structure; and (d) annealing the laminate structure to form a p-type MgxZn1-xO (0?x?0.6) layer co-doped with the Group 11 element and the Group 13 element.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: June 23, 2015
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventors: Chizu Saito, Hiroyuki Kato, Michihiro Sano
  • Patent number: 9064907
    Abstract: A highly reliable semiconductor device which includes a transistor including an oxide semiconductor is provided. In the semiconductor device including a bottom-gate transistor including an oxide semiconductor layer, a stacked layer of an insulating layer and an aluminum film is provided in contact with the oxide semiconductor layer. Oxygen doping treatment is performed in such a manner that oxygen is introduced to the insulating layer and the aluminum film from a position above the aluminum film, whereby a region containing oxygen in excess of the stoichiometric composition is formed in the insulating layer, and the aluminum film is oxidized to form an aluminum oxide film.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: June 23, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9064790
    Abstract: A method for producing a p-type ZnO based compound semiconductor layer is provided. The method comprises the steps of (a) preparing an n-type single crystal ZnO based compound semiconductor structure containing a Group 11 element which is Cu and/or Ag and at least one Group 13 element selected from the group consisting of B, Ga, Al, and In, and (b) annealing the n-type single crystal ZnO based compound semiconductor structure to form the p-type ZnO based compound semiconductor layer co-doped with the Group 11 element and the Group 13 element.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: June 23, 2015
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventors: Chizu Saito, Hiroyuki Kato, Michihiro Sano
  • Patent number: 9054137
    Abstract: An object is to manufacture a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which an oxide semiconductor film is used for a semiconductor layer including a channel formation region, heat treatment (for dehydration or dehydrogenation) is performed to improve the purity of the oxide semiconductor film and reduce impurities including moisture or the like. After that, slow cooling is performed under an oxygen atmosphere. Besides impurities including moisture or the like exiting in the oxide semiconductor film, heat treatment causes reduction of impurities including moisture or the like exiting in a gate insulating layer and those in interfaces between the oxide semiconductor film and films which are provided over and below the oxide semiconductor and in contact therewith.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: June 9, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshinari Sasaki, Junichiro Sakata, Hiroki Ohara, Shunpei Yamazaki
  • Publication number: 20150144941
    Abstract: Disclosed is a display substrate including a driving unit on a substrate comprising a first thin film transistor and a display unit on the substrate being adjacent to the driving unit and comprising a second thin film transistor.
    Type: Application
    Filed: October 10, 2014
    Publication date: May 28, 2015
    Inventors: Masataka KANO, Sang-Ho PARK, So-Young KOO, Myoung-Hwa KIM, Yeon-Hong KIM, Jung-Hun NOH, Jun-Hyung LIM, Sang-Hee JANG
  • Publication number: 20150144939
    Abstract: A thin film transistor array panel includes: a gate line including a gate electrode; a first gate insulating layer on the gate line; a semiconductor layer on the first gate insulating layer and overlapping the gate electrode; a second gate insulating layer on the semiconductor layer and the first gate insulating layer, and an opening in the second gate insulating layer and through which the semiconductor layer is exposed; drain and source electrodes on the second gate insulating and semiconductor layers and facing each other; a first field generating electrode; and a second field generating electrode connected to the drain electrode. The semiconductor layer includes an oxide semiconductor layer, and first and second auxiliary layers on the oxide semiconductor layer and separated from each other. An edge of the drain and source electrodes is disposed inside an edge of the first and second auxiliary layers, respectively.
    Type: Application
    Filed: May 30, 2014
    Publication date: May 28, 2015
    Applicant: Samsung Display Co., Ltd.
    Inventors: Young Joo CHOI, Joon Geol KIM, Seung-Ho JUNG, Kang Moon JO
  • Publication number: 20150144857
    Abstract: In fabricating a memory device, a first electrode is provided. An alloy is formed thereon, and the alloy is oxidized to provide an oxide layer. A second electrode is provided on the oxide layer. In a further method of fabricating a memory device, a first electrode is provided. Oxide is provided on the first electrode, and an implantation step in undertaken to implant material in the oxide to form a layer including oxide and implanted material having an oxygen deficiency and/or defects therein. A second electrode is the formed on the layer.
    Type: Application
    Filed: February 2, 2015
    Publication date: May 28, 2015
    Inventors: Matthew BUYNOSKI, Seungmoo CHOI, Chakravarthy GOPALAN, Dongxiang LIAO, Christie MARRIAN
  • Patent number: 9040396
    Abstract: An object is to provide a technique by which a semiconductor device including a high-performance and high-reliable transistor is manufactured. A protective conductive film which protects an oxide semiconductor layer when a wiring layer is formed from a conductive layer is formed between the oxide semiconductor layer and the conductive layer, and an etching process having two steps is performed. In a first etching step, an etching is performed under conditions that the protective conductive film is less etched than the conductive layer and the etching selectivity of the conductive layer to the protective conductive film is high. In a second etching step, etching is performed under conditions that the protective conductive film is more easily etched than the oxide semiconductor layer and the etching selectivity of the protective conductive film to the oxide semiconductor layer is high.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: May 26, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masami Jintyou, Yamato Aihara, Katsuaki Tochibayashi, Toru Arakawa
  • Patent number: 9040982
    Abstract: An electrical device with light-responsive layers is disclosed. One or more electrically conducting stripes, each insulated from each other, are deposited on a smooth surface of a substrate. Then metal oxide layers, separated by a composite diffusion layer, are deposited. On top of the topmost metal oxide layer another set of elongated conductive strips are disposed in contact with the topmost metal oxide layer such that junctions are formed wherever the top and bottom conducting stripes cross. The resulting device is light responsive only when a certain sign of bias voltage is applied and may be used as a photodetector. An advantage that may be realized in the practice of some disclosed embodiments of the device is that this device may be formed without the use of conventional patterning, thereby significantly reducing manufacturing difficulty.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: May 26, 2015
    Assignee: Research Foundation of the City University of New York
    Inventor: Fred J. Cadieu