Having Metal Oxide Or Copper Sulfide Compound Semiconductor Component Patents (Class 438/104)
  • Patent number: 10038049
    Abstract: A display device, includes a substrate; first to fourth subpixels sequentially arranged on the substrate; a first power line on a left side of the first subpixel and shared by the first and second subpixels; a sensing line between the second subpixel and the third subpixel and shared by the first to fourth subpixels; a second power line on a right side of the fourth subpixel and shared by the third and fourth subpixels; and a first data line on the left side of the first subpixel, a second data line on a right side of the second subpixel, a third data line on a left side of the third subpixel, and a fourth data line on the right side of the fourth subpixel. The first and second power lines and the sensing line are disposed on a layer different from the first to fourth data lines.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: July 31, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Byeonguk Gang, Jongsik Shim, Hyunjin Kim, Joondong Kim
  • Patent number: 10014434
    Abstract: A technique is described depositing a new formula of indium and tin salt solutions as a precursor to form a solid transparent indium tin oxide (ITO) film on non-conductive solid substrates. The utilization of this new composition of matter prompted the discovery of a method for preparing the first top-to-bottom completely solution processed solar cell. The specific patterning of the liquid-processed ITO precursor solution and the subsequent layers of a solar cell outlined here also demonstrate a unique way to connect solution processed (as opposed to deposited using vacuum techniques) solar cells in series and in parallel. Also contemplated are similar compositions capable of forming zinc tin oxide (ZTO), indium oxide (IO), indium zinc oxide (IZO), cadmium tin oxide (CTO), aluminum zinc oxide (AZO), or zinc oxide (ZO).
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: July 3, 2018
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Edward E. Foos, Troy K. Townsend
  • Patent number: 9991135
    Abstract: A method for fabricating a metal oxide thin film transistor comprises selecting a substrate and fabricating a gate electrode thereon; growing a layer of dielectric or high permittivity dielectric on the substrate to serve as a gate dielectric layer; growing a first metal layer on the gate dielectric layer and a second metal layer on the first metal layer; fabricating a channel region at a middle position of the first metal layer and a passivation region at a middle position of the second metal layer; anodizing the metals of the passivation region and the channel region at atmospheric pressure and room temperature; fabricating a source and a drain; forming an active region comprising the source, the drain, and the channel region; depositing a silicon nitride layer on the active region; fabricating two electrode contact holes; depositing a metal aluminum film; and fabricating two metal contact electrodes by photolithography and etching.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: June 5, 2018
    Assignee: SHENZHEN GRADUATE SCHOOL, PEKING UNIVERSITY
    Inventors: Shengdong Zhang, Yang Shao, Xiang Xiao, Xin He
  • Patent number: 9947777
    Abstract: Provided is a semiconductor device having favorable reliability.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: April 17, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kazutaka Kuriki, Yuji Egi, Hiromi Sawai, Yusuke Nonaka, Noritaka Ishihara, Daisuke Matsubayashi
  • Patent number: 9917206
    Abstract: A semiconductor element having high mobility, which includes an oxide semiconductor layer having crystallinity, is provided. The oxide semiconductor layer includes a stacked-layer structure of a first oxide semiconductor film and a second oxide semiconductor film having a wider band gap than the first oxide semiconductor film, which is in contact with the first oxide semiconductor film. Thus, a channel region is formed in part of the first oxide semiconductor film (that is, in an oxide semiconductor film having a smaller band gap) which is in the vicinity of an interface with the second oxide semiconductor film. Further, dangling bonds in the first oxide semiconductor film and the second oxide semiconductor film are bonded to each other at the interface therebetween. Accordingly, a decrease in mobility resulting from an electron trap or the like due to dangling bonds can be reduced in the channel region.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: March 13, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Junichi Koezuka
  • Patent number: 9911602
    Abstract: A method and structure for integrating gallium nitride into a semiconductor substrate. The method may also include means for isolating the gallium nitride from the semiconductor substrate.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: March 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: William J. Gallagher, Effendi Leobandung, Devendra K. Sadana, Ghavam G. Shahidi
  • Patent number: 9911765
    Abstract: A thin film transistor (TFT) located on a thin film transistor substrate includes a first insulating film formed so as to cover a gate electrode, a channel layer that is formed at a position on the first insulating film overlapping the gate electrode and formed of an oxide semiconductor, a second insulating film formed on the channel layer, and a third insulating film formed so as to cover the second insulating film. A source electrode and a drain electrode are formed on the third insulating film. Each of the source electrode and the drain electrode is connected to the channel layer through the corresponding one of contact holes penetrating the second insulating film and the third insulating film.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: March 6, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ken Imamura, Kazushi Yamayoshi, Kazunori Inoue
  • Patent number: 9893198
    Abstract: A method for manufacturing a thin film transistor (TFT) which includes a gate, a gate insulation layer, a channel layer, an etching stopping layer, a source, and a drain. The gate is formed on a substrate. The gate insulation layer covers the gate and the substrate. The channel layer is formed on the gate insulation layer to correspond with the gate. The etching stopping layer is formed on a surface of the channel layer. The channel layer and the etching stopping layer are formed in a same photo etching process.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: February 13, 2018
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Kuo-Lung Fang, Yi-Chun Kao, Hsin-Hua Lin, Po-Li Shih, Chih-Lung Lee
  • Patent number: 9893196
    Abstract: A transistor including an oxide semiconductor with favorable electric characteristics and a manufacturing method thereof are provided. A semiconductor device includes a transistor. The transistor includes an oxide semiconductor film over a base insulating film, a gate electrode overlapping with the oxide semiconductor film with a gate insulating film interposed therebetween, and a pair of electrodes in contact with the oxide semiconductor film and serving as a source electrode and a drain electrode. The base insulating film includes a first oxide insulating film partly in contact with the oxide semiconductor film and a second oxide insulating film in the periphery of the first oxide insulating film. An end portion of the oxide semiconductor film which crosses the channel width direction of the transistor is located over the second oxide insulating film.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: February 13, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9887291
    Abstract: A change in electrical characteristics is suppressed and reliability is improved in a semiconductor device provided with a transistor including an oxide semiconductor. A semiconductor device includes a transistor. The transistor includes a gate electrode, a first insulating film over the gate electrode, a second insulating film over the first insulating film, an oxide semiconductor film over the second insulating film, a first buffer film over the oxide semiconductor film, a second buffer film over the oxide semiconductor film, a source electrode electrically connected with the oxide semiconductor film, and a drain electrode electrically connected with the oxide semiconductor film. The source electrode is electrically connected with the oxide semiconductor film through the first buffer film. The drain electrode is electrically connected with the oxide semiconductor film through the second buffer film.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: February 6, 2018
    Assignee: Semiconductor Energy Laboratory Co., LTD.
    Inventors: Yukie Suzuki, Yoshiaki Oikawa
  • Patent number: 9880436
    Abstract: A liquid crystal display device includes a gate electrode, a first insulating film, an element layer, a first transparent electrode, and a second transparent electrode. The first insulating film includes a part that covers the gate electrode. The element layer is directly disposed on the first insulating film, includes a channel region that faces the gate electrode across the first insulating film, and is made of a transparent oxide. The first transparent electrode is directly disposed on the first insulating film while being separated from the element layer, and has the same metal composition as the metal composition of the element layer. The second transparent electrode forms a storage capacitance with the first transparent electrode by facing the first transparent electrode while being electrically insulated from the first transparent electrode.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: January 30, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yuki Tsuda, Takuji Imamura
  • Patent number: 9865744
    Abstract: The semiconductor device includes a power element which is in an on state when voltage is not applied to a gate, a switching field-effect transistor for applying first voltage to the gate of the power element, and a switching field-effect transistor for applying voltage lower than the first voltage to the gate of the power element. The switching field-effect transistors have small off-state current.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: January 9, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 9853157
    Abstract: A method includes forming a metal-oxide-semiconductor field-effect transistor (MOSFET). The Method includes performing an implantation to form a pre-amorphization implantation (PAI) region adjacent to a gate electrode of the MOSFET, forming a strained capping layer over the PAI region, and performing an annealing on the strained capping layer and the PAI region to form a dislocation plane. The dislocation plane is formed as a result of the annealing, with a tilt angle of the dislocation plane being smaller than about 65 degrees.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: December 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Wei-Yuan Lu
  • Patent number: 9853214
    Abstract: A resistive random access memory includes a first electrode, a separating medium, a resistance changing layer and a second electrode. The first electrode has a mounting face. The separating medium has a first face in contact with the mounting face, a second face opposite to the first face, and an inner face extending between the first and second faces. The separating medium forms a through hole extending from the first to second face. A part of the mounting face is not covered by the separating medium. The separating medium has a first dielectric. The resistance changing layer extends along the part of the mounting face as well as the inner and second faces. The resistance changing layer has a second dielectric having a dielectric constant larger than a dielectric constant of the first dielectric by 2 or less. The second electrode is arranged on the resistance changing layer.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: December 26, 2017
    Assignee: National Sun Yat-Sen University
    Inventors: Ting-Chang Chang, Kuan-Chang Chang, Tsung-Ming Tsai, Tian-Jian Chu, Chih-Hung Pan
  • Patent number: 9829533
    Abstract: An oxide semiconductor film having high stability with respect to light irradiation or a semiconductor device having high stability with respect to light irradiation is provided. One embodiment of the present invention is a semiconductor film including an oxide in which light absorption is observed by a constant photocurrent method (CPM) in a wavelength range of 400 nm to 800 nm, and in which an absorption coefficient of a defect level, which is obtained by removing light absorption due to a band tail from the light absorption, is lower than or equal to 5×10?2/cm. Alternatively, a semiconductor device is manufactured using the semiconductor film.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: November 28, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Tsubuku, Ryosuke Watanabe
  • Patent number: 9822322
    Abstract: The invention relates to a coating comprising at least one molybdenum-containing layer having molybdenum oxide, said molybdenum being essentially molybdenum monoxide. The invention further relates to a PVD process for producing the disclosed coating, in which the layer comprising the molybdenum monoxide is produced using arc evaporation. The invention also relates to a component that has said coating.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: November 21, 2017
    Assignee: OERLIKON SURFACE SOLUTIONS AG, PFAFFIKON
    Inventors: Jurgen Ramm, Beno Widrig, Kerstin Glantz, Florian Seibert
  • Patent number: 9778521
    Abstract: A display apparatus includes pixels. Each pixel includes a first pixel electrode, a second pixel electrode, a black matrix, a shielding electrode, and first and second sub-shielding electrodes. The first pixel electrode is disposed in a first pixel area. The second pixel electrode is disposed in a second pixel area. The black matrix is disposed in a predetermined area of a first boundary area between the first pixel area and the second pixel area. The shielding electrode is disposed between first pixel areas and between second pixel areas, which are arranged in a first direction, and extends in a second direction crossing the first direction. The first and second sub-shielding electrodes branch from the shielding electrode along the first direction and are spaced apart from each other in the first boundary area while the black matrix is disposed therebetween.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: October 3, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyunggi Jung, Younggoo Song, Kipyo Hong
  • Patent number: 9768314
    Abstract: To reduce defects in an oxide semiconductor film in a semiconductor device. To improve electrical characteristics of and reliability in the semiconductor device including an oxide semiconductor film. A method for manufacturing a semiconductor device includes the steps of forming a gate electrode and a gate insulating film over a substrate, forming an oxide semiconductor film over the gate insulating film, forming a pair of electrodes over the oxide semiconductor film, forming a first oxide insulating film over the oxide semiconductor film and the pair of electrodes by a plasma CVD method in which a film formation temperature is 280° C. or higher and 400° C. or lower, forming a second oxide insulating film over the first oxide insulating film, and performing heat treatment at a temperature of 150° C. to 400° C. inclusive, preferably 300° C. to 400° C. inclusive, further preferably 320° C. to 370° C. inclusive.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: September 19, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Yukinori Shima, Suzunosuke Hiraishi, Kenichi Okazaki
  • Patent number: 9768317
    Abstract: Provided is a semiconductor device which can suppress an increase in oxygen vacancies in an oxide semiconductor layer and a manufacturing method of the semiconductor device. The semiconductor device includes a first oxide semiconductor layer over the first insulating layer; a second oxide semiconductor layer over the first oxide semiconductor layer; a third oxide semiconductor layer over the second oxide semiconductor layer; a source electrode layer and a drain electrode layer each over the third oxide semiconductor layer; a fourth semiconductor layer over the source and drain electrode layers, and the third oxide semiconductor layer; a gate insulating layer over the fourth oxide semiconductor layer; a gate electrode layer over the gate electrode layer and overlapping with the source and drain electrode layers, and the fourth oxide semiconductor layer; and a second insulating layer over the first insulating layer, and the source, gate, and drain electrode layers.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: September 19, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daigo Ito, Takahisa Ishiyama, Kazuya Hanaoka
  • Patent number: 9741588
    Abstract: A method of manufacturing a thin-film transistor substrate which includes a thin-film transistor includes: forming a planarization layer comprising polyimide material above the thin-film transistor; and heating the thin-film transistor at a temperature of 240° C. or lower after the planarization layer is formed.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: August 22, 2017
    Assignee: JOLED INC.
    Inventors: Yuji Kishida, Toshiaki Yoshitani
  • Patent number: 9722049
    Abstract: Embodiments described herein provide method for forming crystalline indium-gallium-zinc oxide (IGZO). A substrate is provided. A seed layer is formed above the substrate. The seed layer has a crystalline structure that is substantially dominant along the c-axis. An IGZO layer is formed above the seed layer. The seed layer may include zinc oxide. A stack of alternating seed layers and IGZO layers may be formed.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: August 1, 2017
    Assignees: Intermolecular, Inc., LG Display Co., Ltd.
    Inventors: Sang Lee, Khaled Ahmed, Youn-Gyoung Chang, Min-Cheol Kim, Minh Huu Le, Kwon-Sik Park, Woosup Shin
  • Patent number: 9722088
    Abstract: Provided is a semiconductor device in which deterioration of electric characteristics which becomes more noticeable as the semiconductor device is miniaturized can be suppressed. The semiconductor device includes a first oxide film, an oxide semiconductor film over the first oxide film, a source electrode and a drain electrode in contact with the oxide semiconductor film, a second oxide film over the oxide semiconductor film, the source electrode, and the drain electrode, a gate insulating film over the second oxide film, and a gate electrode in contact with the gate insulating film. A top end portion of the oxide semiconductor film is curved when seen in a channel width direction.
    Type: Grant
    Filed: May 14, 2014
    Date of Patent: August 1, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuya Hanaoka, Daisuke Matsubayashi, Yoshiyuki Kobayashi, Shunpei Yamazaki, Shinpei Matsuda
  • Patent number: 9716003
    Abstract: Provided are an oxide semiconductor layer in which the number of defects is reduced and a highly reliable semiconductor device including the oxide semiconductor. A first oxide semiconductor layer containing a single metal element as a constituent element is formed over a substrate by a thermal chemical vapor deposition method. A second oxide semiconductor layer containing two or more metal elements as constituent elements is formed successively after the first oxide semiconductor layer is formed. The second oxide semiconductor layer is formed by epitaxial growth using the first oxide semiconductor layer as a seed crystal. A channel is formed in the second oxide semiconductor layer.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: July 25, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9716118
    Abstract: A thin film transistor (TFT) located on a thin film transistor substrate includes a first insulating film formed so as to cover a gate electrode, a channel layer that is formed at a position on the first insulating film overlapping the gate electrode and formed of an oxide semiconductor, a second insulating film formed on the channel layer, and a third insulating film formed so as to cover the second insulating film. A source electrode and a drain electrode are formed on the third insulating film. Each of the source electrode and the drain electrode is connected to the channel layer through the corresponding one of contact holes penetrating the second insulating film and the third insulating film.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: July 25, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ken Imamura, Kazushi Yamayoshi, Kazunori Inoue
  • Patent number: 9708710
    Abstract: Methods for providing one or more coating layers on a surface of a substrate by successive surface reactions of at least a first and second precursor are provided. The methods generally include supplying the first precursor from a first precursor nozzle and the second precursor from a second precursor nozzle to the surface of the substrate, and moving the substrate relative to at least one of the first and second precursor nozzle. The methods can further include subjecting only one or more first limited sub-areas of the surface of the substrate to the first and second precursor by cooperation of supplying the first and second precursor and simultaneously moving the substrate relative to at least one of the first and second precursor nozzle.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: July 18, 2017
    Assignee: BENEQ OY
    Inventors: Tapani Alasaarela, Pekka Soininen
  • Patent number: 9691979
    Abstract: A resistive random access memory includes a first electrode layer, a second electrode layer, and a stacked structure disposed between the first electrode layer and the second electrode layer. The stacked structure includes a conductive layer and a resistance variable layer. The material of the conductive layer includes HfOx, the material of the resistance variable layer includes HfOy, and x<y. Additionally, the diffusion rate of oxygen ions in the conductive layer is lower than the diffusion rate of the oxygen ions in metal.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: June 27, 2017
    Assignee: Winbond Electronics Corp.
    Inventors: Shuo-Che Chang, Chia-Hua Ho
  • Patent number: 9685546
    Abstract: A semiconductor device of an embodiment includes a first layer, a second layer provided on the first layer, the second layer forming a two-dimensional electron gas in the first layer; a source electrode provided on the second layer, a drain electrode provided on the second layer, a gate electrode provided between the source electrode and the drain electrode on the second layer and a first insulating layer provided between the gate electrode and the drain electrode on the second layer. The first insulating layer includes a first film, a second film having a higher oxygen density than the first film and a first region provided between the first film and the second film. The first region contains at least one first element selected from the group consisting of F, H, and D, the first region having a first peak of concentration of the first element.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: June 20, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Hisashi Saito
  • Patent number: 9685610
    Abstract: A method for producing a resistive random access memory includes preparing a first metal layer and sputtering a resistive switching layer on the first metal layer. Surface treatment is conducted on the resistive switching layer by using a plasma containing mobile ions to dope the mobile ions into the resistive switching layer. The polarity of the mobile ions is opposite to the polarity of oxygen ions. Then, a second metal layer is sputtered on the resistive switching layer.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: June 20, 2017
    Assignee: NATIONAL SUN YAT-SEN UNIVERSITY
    Inventors: Ting-Chang Chang, Kuan-Chang Chang, Tsung-Ming Tsai, Tian-Jian Chu, Chih-Hung Pan
  • Patent number: 9660103
    Abstract: This thin film transistor comprises, on a substrate, at least a gate electrode, a gate insulating film, an oxide semiconductor layer, a source-drain electrode, and two or more protective films. The oxide semiconductor layer comprises Sn, O and one or more elements selected from the group consisting of In, Ga and Zn. In addition, the two or more protective films are composed of at least a first protective film that is in contact with the oxide semiconductor film, and one or more second protective films other than the first protective film. The first protective film is a SiOx film having a hydrogen concentration of 3.5 atomic % or lower.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: May 23, 2017
    Assignee: Kobe Steel, Ltd.
    Inventors: Mototaka Ochi, Shinya Morita, Yasuyuki Takanashi, Hiroshi Goto, Toshihiro Kugimiya
  • Patent number: 9653482
    Abstract: A display panel comprises a TFT substrate and a display medium layer. The display medium layer is disposed on the TFT substrate. The TFT substrate comprises a TFT and a substrate. The TFT is disposed on the substrate and comprises a gate, a metal oxide layer, a source, a drain and a protection layer. The gate is disposed corresponding to the metal oxide layer. The protection layer is disposed on the metal oxide layer. Each of the source and the drain contacts the metal oxide layer through an opening of the protection layer. One side of the gate or one side of the metal oxide layer partially overlaps at least one of the openings. In addition, a display device is also disclosed.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: May 16, 2017
    Assignee: Innolux Corporation
    Inventors: Hui-Min Huang, Hsin-Hung Lin, Li-Wei Sung
  • Patent number: 9627414
    Abstract: The present invention provides a metallic oxide thin film transistor and its manufacturing method, an array substrate and its manufacturing method, as well as a display device, which is belong to the field of thin film transistor manufacturing technology. The method for manufacturing the metallic oxide thin film transistor comprises a step of forming patterns of an oxide active layer and an etch stopping layer through a one-time patterning process.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: April 18, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Lei Zhao, Wei Guo
  • Patent number: 9614104
    Abstract: The present invention provides a co-planar oxide semiconductor TFT substrate structure and a manufacture method thereof. In the co-planar oxide semiconductor TFT substrate structure, the active layer comprises a main body and a plurality of short channels connected to the main body, and the plurality of short channels are separated with the plurality of strip metal electrodes to make the active layer possess higher mobility and lower leak current. Thus, the performance of the TFT element can be improved. The present invention provides a manufacture method of a co-planar oxide semiconductor TFT substrate structure. With forming the plurality of strip metal electrodes between the source and the drain, which are separately positioned, as deposing the oxide semiconductor layer, the plurality of short channels can be formed between the source and the drain. The method is simple and does not require additional mask or process to obtain the active layer structure different from prior art.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: April 4, 2017
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xiaowen Lv, Chihyuan Tseng
  • Patent number: 9608121
    Abstract: To reduce defects in an oxide semiconductor film in a semiconductor device. To improve electrical characteristics of and reliability in the semiconductor device including an oxide semiconductor film. A method for manufacturing a semiconductor device includes the steps of forming a gate electrode and a gate insulating film over a substrate, forming an oxide semiconductor film over the gate insulating film, forming a pair of electrodes over the oxide semiconductor film, forming a first oxide insulating film over the oxide semiconductor film and the pair of electrodes by a plasma CVD method in which a film formation temperature is 280° C. or higher and 400° C. or lower, forming a second oxide insulating film over the first oxide insulating film, and performing heat treatment at a temperature of 150° C. to 400° C. inclusive, preferably 300° C. to 400° C. inclusive, further preferably 320° C. to 370° C. inclusive.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: March 28, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Yukinori Shima, Suzunosuke Hiraishi, Kenichi Okazaki
  • Patent number: 9570594
    Abstract: A semiconductor device which is miniaturized while favorable characteristics thereof are maintained is provided. In addition, the miniaturized semiconductor device is provided with a high yield. The semiconductor device has a structure including an oxide semiconductor film provided over a substrate having an insulating surface; a source electrode layer and a drain electrode layer which are provided in contact with side surfaces of the oxide semiconductor film and have a thickness larger than that of the oxide semiconductor film; a gate insulating film provided over the oxide semiconductor film, the source electrode layer, and the drain electrode layer; and a gate electrode layer provided in a depressed portion formed by a step between a top surface of the oxide semiconductor film and top surfaces of the source electrode layer and the drain electrode layer.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: February 14, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takehisa Hatano, Sachiaki Tezuka, Atsuo Isobe
  • Patent number: 9548198
    Abstract: A method of manufacturing a semiconductor device including forming a thin film containing silicon, oxygen and carbon on a substrate by performing a cycle a predetermined number of times, the cycle including: supplying a precursor gas containing silicon, carbon and a halogen element and having an Si—C bonding, and a first catalytic gas to the substrate; and supplying an oxidizing gas and a second catalytic gas to the substrate.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: January 17, 2017
    Assignees: HITACHI KOKUSAI ELECTRIC INC., L'AIR LIQUIDE, SOCIETE ANONYME POUR L'ETUDE ET L'EXPLOITATION DES PROCEDES GEORGES CLAUDE
    Inventors: Yoshiro Hirose, Norikazu Mizuno, Kazutaka Yanagita, Shingo Okubo
  • Patent number: 9543143
    Abstract: A method for producing an amorphous oxide thin film includes: a pre-treatment process of selectively changing a binding state of an organic component, at a temperature lower than a pyrolysis temperature of the organic component, in a first oxide precursor film containing the organic component and In, to obtain a second oxide precursor film in which, when an infrared wave number range of from 1380 cm?1 to 1520 cm?1 in an infrared absorption spectrum obtained by performing a measurement by Fourier transform infrared spectroscopy is divided into an infrared wave number range of from 1380 cm?1 to 1450 cm?1 and an infrared wave number range of from more than 1450 cm?1 to 1520 cm?1, a peak positioned within the infrared wave number range of from 1380 cm?1 to 1450 cm?1 exhibits the maximum value in the infrared absorption spectrum within an infrared wave number range of from 1350 cm?1 to 1750 cm?1; and a post-treatment process of removing the organic component remaining in the second oxide precursor film, to transfo
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: January 10, 2017
    Assignee: FUJIFILM Corporation
    Inventors: Kenichi Umeda, Atsushi Tanaka, Masayuki Suzuki, Tatsuya Shimoda
  • Patent number: 9543330
    Abstract: A method manufacturing a thin film transistor is provided. A gate, a first insulation layer covering the gate, a semiconductor layer over the gate, and a first photoresist pattern are sequentially formed on a substrate. The semiconductor layer is patterned into a channel layer by using the first photoresist pattern as a mask and the first photoresist pattern is subsequently shrunken to remain a portion of the first photoresist pattern on the channel layer. A conductive material layer covering the remained portion of the first photoresist pattern, the channel layer and the first insulation layer is patterned by using a second photoresist pattern as a mask to form a source and a drain separated by a gap region exposing the remained portion. The second photoresist pattern and the remained portion are removed by performing a stripping process to expose the channel layer between the source and the drain.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: January 10, 2017
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Der-Chun Wu, Shin-Chuan Chiang, Yu-Hsien Chen, Po-Lung Chen, Yi-Hsien Lin, Cheng-Jung Yang, Kuo-Hsing Tseng
  • Patent number: 9543009
    Abstract: Methods for forming non-volatile storage elements in a non-volatile storage system are described. In some embodiments, during a forming operation, a cross-point memory array may be biased such that waste currents are minimized or eliminated. In one example, the memory array may be biased such that a first word line comb is set to a first voltage, a second word line comb interdigitated with the first word line comb is set to the first voltage, and selected vertical bit lines are set to a second voltage such that a forming voltage is applied across non-volatile storage elements to be formed. In some embodiments, a memory array may include a plurality of word line comb layers and a forming operation may be concurrently performed on non-volatile storage elements on all of the plurality of word line comb layers or a subset of the plurality of word line comb layers.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: January 10, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Chang Siau, Tianhong Yan
  • Patent number: 9536912
    Abstract: A method of transferring a thin film is a method of transferring a thin film formed on a first substrate to a second substrate, the method including: allowing the first substrate to come into contact with a liquid to swell the first substrate; allowing the second substrate and the thin film to come into contact with each other via the liquid; and drying the liquid to allow the thin film to adhere to the second substrate.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: January 3, 2017
    Assignee: NIKON CORPORATION
    Inventors: Makoto Nakazumi, Yasutaka Nishi
  • Patent number: 9530892
    Abstract: A semiconductor device includes a transistor including a gate electrode over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, and an oxide insulating film covering the transistor. The multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the oxide insulating film contains more oxygen than that in the stoichiometric composition, and in the transistor, by a bias-temperature stress test, threshold voltage does not change or the amount of the change in a positive direction or a negative direction is less than or equal to 1.0 V, preferably less than or equal to 0.5 V.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: December 27, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Yukinori Shima, Hajime Tokunaga, Toshinari Sasaki, Keisuke Murayama, Daisuke Matsubayashi
  • Patent number: 9525133
    Abstract: Disclosed is a resistive random access memory, comprising a substrate, an insulating layer, a bottom electrode, a resistive material film, and a top electrode in an order from bottom to top, wherein the resistive material film is a four-layer structure composed of a same metal oxide; and the four layers in the four-layer structure from bottom to top have resistance values which are increased one after another by more than 10 times, oxygen concentrations which are increased one after another and thickness which are decreased one after another. The present invention may achieve complete formation-rupture of oxygen vacancy conductive filaments (CF) in each layer by dividing the resistive material film of the same metal oxide into four layers according to the different oxygen concentrations, so as to control accurately the resistance values, so that 2-bit storage with high uniformity is achieved.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: December 20, 2016
    Assignee: PEKING UNIVERSITY
    Inventors: Ru Huang, Muxi Yu, Yimao Cai, Zhenxing Zhang, Qiang Li, Ming Li
  • Patent number: 9520476
    Abstract: A semiconductor device (100A) includes a substrate (2), an oxide semiconductor layer (5) formed on the substrate (2), source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5), a first transparent electrode (7) electrically connected to the drain electrode (6d), a dielectric layer (8) formed on the source and drain electrodes (6s, 6d), and a second transparent electrode (9) formed on the dielectric layer (8). The upper and/or lower surface(s) of the first transparent electrode (7) contacts with a reducing insulating layer (8a) with the property of reducing an oxide semiconductor included in the oxide semiconductor layer (5). The second transparent electrode (9) overlaps at least partially with the first transparent electrode (7) via the dielectric layer (8). The oxide semiconductor layer (5) and the first transparent electrode (7) are formed out of the same oxide film.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: December 13, 2016
    Assignee: Sharp kabushiki Kaisha
    Inventors: Tadayoshi Miyamoto, Kazuatsu Ito, Shigeyasu Mori, Mitsunobu Miyamoto, Yasuyuki Ogawa, Makoto Nakazawa, Seiichi Uchida, Takuya Matsuo
  • Patent number: 9520412
    Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: December 13, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Pil-Sang Yun, Ki-Won Kim, Hye-Young Ryu, Woo-Geun Lee, Seung-Ha Choi, Jae-Hyoung Youn, Kyoung-Jae Chung, Young-Wook Lee, Je-Hun Lee, Kap-Soo Yoon, Do-Hyun Kim, Dong-Ju Yang, Young-Joo Choi
  • Patent number: 9502246
    Abstract: A method of forming an oxide semiconductor device may be provided. In the method, a substrate comprising a first major surface and a second major surface that faces away from the first major surface may be provided. An oxide semiconductor device may be formed over the first major surface to provide an intermediate device, and the semiconductor device may comprise an oxide active layer. The intermediate device may be subjected to ultraviolet (UV) light (e.g., ultraviolet ray irradiation process) for a first period, and subjected to heat (e.g., thermal treatment process) for a second period. The first and second periods may at least partly overlap.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: November 22, 2016
    Assignees: Samsung Display Co., Ltd., University-Industry Foundation (UIF), Yonsei University
    Inventors: Yeon-Hong Kim, Byung-Du Ahn, Hyeon-Sik Kim, Yeon-Gon Mo, Ji-Hun Lim, Hyun-Jae Kim
  • Patent number: 9496376
    Abstract: To provide a semiconductor device with improved reliability. To provide a semiconductor device with stable characteristics. To provide a transistor having a low off-state current. To provide a transistor having a high on-state current. To provide a novel semiconductor device, a novel electronic device, or the like. A method for manufacturing the semiconductor device includes the steps of forming a first semiconductor over a substrate; forming a second semiconductor over and in contact with the first semiconductor; forming a first layer over the second semiconductor; performing oxygen plasma treatment and then removing the first layer to expose at least part of a surface of the second semiconductor; forming a third semiconductor over and in contact with the second semiconductor; forming a first insulator over and in contact with the third semiconductor; and forming a first conductor over the first insulator.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: November 15, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Tetsuhiro Tanaka, Sachiaki Tezuka, Mitsuhiro Ichijo, Noriyoshi Suzuki
  • Patent number: 9466508
    Abstract: The present invention provides a liquid composition used for etching a multilayer film containing copper and molybdenum, an etching method for etching a multilayer film containing copper and molybdenum, and a substrate. The present invention further provides a liquid composition for etching a multilayer-film wiring substrate which has an oxide layer (IGZO) including indium, gallium and zinc laminated on the substrate, and further a multilayer film including at least a layer containing molybdenum and a layer containing copper provided thereon, a method for etching a multilayer film containing copper and molybdenum from the substrate, and a substrate.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: October 11, 2016
    Assignee: MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Satoshi Tamai, Kunio Yube
  • Patent number: 9464220
    Abstract: Technologies are generally described for forming a nanofluid coolant and structures including a nanofluid coolant. In an example, a method of forming a nanofluid coolant may comprise combining a compound with an acid and with purified water to form a solution. The compound may include manganese. The method may further include heating the solution and, after heating the solution, cooling the solution effective to form at least one precipitate that includes manganese and oxygen. The method may further include filtering the at least one precipitate to form a powder that includes manganese oxide nanotubes. The method may further include functionalizing the nanotubes by irradiating them with UV radiation. The method may further include combining the functionalized manganese oxide nanotubes with a polar solvent to form the nanofluid coolant.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: October 11, 2016
    Assignee: Indian Institute of Technology Madras
    Inventors: Sundara Ramaprabhu, Jyothirmayee Aravind Sasidharannair Sasikaladevi
  • Patent number: 9461176
    Abstract: To reduce defects in an oxide semiconductor film in a semiconductor device. To improve electrical characteristics of and reliability in the semiconductor device including an oxide semiconductor film. A method for manufacturing a semiconductor device includes the steps of forming a gate electrode and a gate insulating film over a substrate, forming an oxide semiconductor film over the gate insulating film, forming a pair of electrodes over the oxide semiconductor film, forming a first oxide insulating film over the oxide semiconductor film and the pair of electrodes by a plasma CVD method in which a film formation temperature is 280° C. or higher and 400° C. or lower, forming a second oxide insulating film over the first oxide insulating film, and performing heat treatment at a temperature of 150° C. to 400° C. inclusive, preferably 300° C. to 400° C. inclusive, further preferably 320° C. to 370° C. inclusive.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: October 4, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Yukinori Shima, Suzunosuke Hiraishi, Kenichi Okazaki
  • Patent number: 9450080
    Abstract: The semiconductor device is manufactured by the following method. A first oxide semiconductor film is formed over a first gate electrode and a first insulating film, oxygen is added to the first oxide semiconductor film, and then a second oxide semiconductor film is formed over the first oxide semiconductor film. Then, heat treatment is performed. Next, part of the first insulating film, part of the first oxide semiconductor film, and part of the second oxide semiconductor film are etched to form a first gate insulating film having a projection. Next, a pair of electrodes is formed over the second oxide semiconductor film, and a third oxide semiconductor film is formed over the second oxide semiconductor film and the pair of electrodes. Then, a second gate insulating film is formed over the third oxide semiconductor film, and a second gate electrode is formed over the second gate insulating film.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: September 20, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Naoto Yamade, Yoshitaka Yamamoto, Hideomi Suzawa, Masayuki Sakakura, Yuhei Sato, Yasumasa Yamane
  • Patent number: 9443987
    Abstract: In a semiconductor device using a transistor including an oxide semiconductor, a change in electrical characteristics is suppressed and reliability is improved. The semiconductor device includes a gate electrode over an insulating surface; an oxide semiconductor film overlapping with the gate electrode; a gate insulating film that is between the gate electrode and the oxide semiconductor film and in contact with the oxide semiconductor film; a protective film in contact with a surface of the oxide semiconductor film that is an opposite side of a surface in contact with the gate insulating film; and a pair of electrodes in contact with the oxide semiconductor film. The spin density of the gate insulating film or the protective film measured by electron spin resonance spectroscopy is lower than 1×1018 spins/cm3, preferably higher than or equal to 1×1017 spins/cm3 and lower than 1×1018 spins/cm3.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: September 13, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Akiharu Miyanaga, Yasuharu Hosaka, Toshimitsu Obonai, Junichi Koezuka, Motoki Nakashima, Masahiro Takahashi, Shunsuke Adachi, Takuya Hirohashi