Abstract: In a semiconductor device formed by mounting a chip laminate including a semiconductor chip having a small diameter and a semiconductor chip having a large diameter over the top surface of a substrate, an excessive stress is prevented from being added to a joint of the two semiconductor chips. By mounting a first semiconductor chip having a large diameter over a support substrate and thereafter mounting a second semiconductor chip having a small diameter over the first semiconductor chip, it is possible to: suppress the inclination and unsteadiness of the second semiconductor chip mounted over the first semiconductor chip; and hence inhibit an excessive stress from being added to a joint of the first semiconductor chip and the second semiconductor chip.

Abstract: In one embodiment, an electronic memory module may be provided to couple two or more stacked memory dies. The memory module may include a first substrate that couples the first memory die in a flip chip configuration. The substrate also includes connectors to couple to a second substrate, which has a flip chip connection to a second memory die. A surface of the first substrate opposite the flip chip connection of the first memory die may include connectors to couple to the first memory die (through the first substrate) and may include connectors to couple to the second memory die (through the connectors that couple to the second substrate, and through the first substrate.

Abstract: A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts.

Abstract: A method for manufacturing a package on package structure includes the steps of: providing a connection substrate comprising a main body and electrically conductive posts, the main body comprising a first surface and an opposite second surface, each electrically conductive post passing through the first and second surfaces, and each end of the two ends of the electrically conductive post protruding from the main body; arranging a first package device on a side of the first surface of the connection substrate, arranging a package adhesive on a side of the second surface of the connection substrate, thereby obtaining a semi-finished package on package structure; and arranging a second package device on a side of the package adhesive furthest from the first package device, thereby obtaining a package on package structure.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for surface treatment of an integrated circuit (IC) substrate. In one embodiment, an apparatus includes an integrated circuit substrate, an interconnect structure disposed on the integrated circuit substrate, the interconnect structure being configured to route electrical signals to or from the integrated circuit substrate and comprising a metal surface, and a protective layer disposed on the metal surface of the interconnect structure, the protective layer comprising a first functional group bonded with the metal surface and a second functional group bonded with the first functional group, wherein the second functional group is hydrophobic to inhibit contamination of the metal surface by hydrophilic materials and further inhibits oxidation of the metal surface. Other embodiments may be described and/or claimed.

Abstract: A self-aligning hybridization method enabling small pixel pitch hybridizations with self-alignment and run-out protection. The method requires providing a first IC, the surface of which includes at least one electrical contact for connection to a mating IC, depositing an insulating layer on the IC's surface, patterning and etching the insulating layer to provide recesses in the insulating layer above each of the electrical contacts, and depositing a deformable conductive material in each of the recesses. A mating IC is provided which includes conductive pins, preferably comprising nickel, positioned to align with the deformable conductive material in respective ones of the recesses on the first chip. The first and mating ICs are then hybridized by bringing the conductive pins into contact with the deformable conductive material in the recesses, such that the conductive material deforms and the pins make electrical contact with the first IC's electrical contacts.

Abstract: A method of manufacturing a semiconductor device, wherein a first substrate where first electrode pads are formed and a second substrate where second electrode pads are formed are stacked and the first electrode pads and the corresponding second electrode pads are electrically connected thereby forming the semiconductor device is disclosed. The method includes steps of performing a first hydrophilic treatment with respect to the first electrode pads; supplying liquid to a surface where the first electrode pads are formed in the first substrate; and placing the second substrate on the first substrate to which the liquid is supplied so that the surface where the first electrode pads are formed opposes a surface where the second electrode pads are formed, thereby aligning the first electrode pads and the second electrode pads by the liquid that gathers in the first electrode pads that have been subject to the first hydrophilic treatment.

Abstract: An interconnection component includes a substrate, and an active through-substrate via (TSV) penetrating through the substrate. Active metal connections are formed over the substrate and electrically connected to the active TSV. At least one of a dummy pad and a dummy solder bump are formed at surfaces of the interconnection component. The dummy pad is over the substrate and electrically connected to the active TSV and the active metal connections. The dummy solder bump is under the substrate and electrically connected to the active metal connections. The dummy pad and the dummy solder bump are open ended.

Abstract: A method and device for preventing the bridging of adjacent metal traces in a bump-on-trace structure. An embodiment comprises determining the coefficient of thermal expansion (CTE) and process parameters of the package components. The design parameters are then analyzed and the design parameters may be modified based on the CTE and process parameters of the package components.

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract: A semiconductor device has a semiconductor chip and a first interconnection tape. The semiconductor chip has a plurality of first electrode pads arranged on a first surface. The first interconnection tape is in contact with each of the plurality of first electrode pads such that the plurality of first electrode pads are electrically connected with each other.

Abstract: Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of stacked microelectronic packages. In one embodiment, the method includes producing a partially-completed stacked microelectronic package including a package body having a vertical package sidewall, a plurality microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the vertical package sidewall. A flowable conductive material is applied on the vertical package sidewall and contacts the package edge conductors. Selected portions of the flowable conductive material are then removed to define, at least in part, electrically-isolated sidewall conductors electrically coupled to different ones of the package edge conductors.

Abstract: A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate.

Abstract: One method of making an electronic assembly includes mounting one electrical substrate on another electrical substrate with a face surface on the one substrate oriented transversely of a face surface of the other substrate. The method also includes inkjet printing on the face surfaces a conductive trace that connects an electrical contact on the one substrate with an electrical connector on the other substrate. An electronic assembly may include a first substrate having a generally flat surface with a first plurality of electrical contacts thereon; a second substrate having a generally flat surface with a second plurality of electrical contacts thereon, the surface of the second substrate extending transversely of the surface of said first substrate; and at least one continuous conductive ink trace electrically connecting at least one of the first plurality of electrical contacts with at least one of the second plurality of electrical contacts.

Abstract: An embodiment method of forming a package-on-package (PoP) device includes temporarily mounting a substrate on a carrier, stacking a first die on the substrate, at least one of the die and the substrate having a coefficient of thermal expansion mismatch relative to the carrier, and stacking a second die on the first die. The substrate may be formed from one of an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, and a laminate substrate.

Abstract: A semiconductor device and method of forming the semiconductor device, the semiconductor device includes a package having at least one first die and at least one second die. The semiconductor device further includes a set of conductive elements electrically connecting the at least one first and the at least one second die to a substrate. The semiconductor device further includes a thermal contact pad between the at least one first die and the at least one second die, to thermally isolate the at least one first die from the at least one second die.

Abstract: A method of manufacturing a stacked wafer level package includes: preparing a substrate; forming a conductive layer on the substrate; forming chip connection pads and internal connection pads on the conductive layer; forming solder balls connected to the internal connection pads; mounting a semiconductor chip on the conductive layer to be connected to the chip connection pads; forming a sealing member to seal the solder balls and the semiconductor chip; separating the substrate from the conductive layer; forming a rearrangement wiring layer by etching the conductive layer; forming an external connection on the rearrangement wiring layer; forming contact holes in the sealing member to expose the solder balls; and stacking an electronic component to be electrically connected to the solder balls exposed through the contact holes.

Abstract: A PoP (package-on-package) package includes a bottom package with a substrate encapsulated in an encapsulant with a die coupled to the top of the substrate. At least a portion of the die is exposed above the encapsulant on the bottom package substrate. A top package includes a substrate with encapsulant on both the frontside and the backside of the substrate. The backside of the top package substrate is coupled to the topside of the bottom package substrate with at least part of the die being located in a recess in the encapsulant on the backside of the top package substrate.

Abstract: A multi-chip electronic package and methods of manufacture are provided. The multi-chip package includes a plurality of chips mounted on a chip carrier. The multi-chip package further includes a lid mounted on the chip carrier using a bonding material or compression seal, and at least one single piston extending from the lid. Each piston covers an entirety of multiple chips of the plurality of chips.

Abstract: An electronic switching device array encapsulated in an encapsulating structure; wherein said array is exposed to one or more gas pockets between said array and said encapsulating structure.

Abstract: A method (112) of forming a sensor panel (146) that includes an array (144) of sensor structures (22, 24) encapsulated in a mold material (148) and forming a controller panel (158) that includes an array (156) of controller dies (26) encapsulated in a mold material (160). The arrays (144, 156) are arranged so that locations of the sensor structures (22, 24) correspond with locations of the controller dies (26). The controller panel (158) is bonded (162) to the sensor panel (146) to form a stacked panel structure (164). After bonding, methodology (112) entails forming (178) conductive elements (84) on the controller dies (26), removing (174) material sections (126, 142, 168) from the controller panel 158 and the sensor panel (146) to expose bond pads (42, 58), forming (178) electrical interconnects (80), applying (182) packaging material (90), and singulating (196) the stacked panel structure (164) to produce sensor packages (20, 104).

Abstract: An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural portion of the package. Assemblies using the abovementioned transistor with another transistor can be formed, where the source of one transistor can be electrically connected to a conducting structural portion of a package containing the transistor and a drain of the second transistor is electrically connected to the second conductive structural portion of a package that houses the second transistor. Alternatively, the source of the second transistor is electrically isolated from its conductive structural portion, and the drain of the second transistor is electrically isolated from its conductive structural portion.

Abstract: A package and method for packaging a semiconductor device formed in a surface portion of a semiconductor wafer. The package includes: a dielectric layer disposed on the surface portion of the semiconductor wafer having a device exposing opening to expose one of the devices and an electrical contacts pad opening to expose an electrical contact pad; and a porous material in the device exposing opening over said one of the devices.

Abstract: A low thermal conductivity material layer covers a peripheral portion of the bottom surface of the conductive plate of a chip bonder head. The center portion of the conductive plate is exposed or covered with another conductive plate laterally surrounded by the low thermal conductivity material layer. During bonding, the chip bonder head holds a first substrate upside down and heats the first substrate through the conductive plate. Heating of a fillet, i.e., the laterally extruding portion, of a pre-applied underfill material is reduced because the temperature at the exposed surfaces of the low thermal conductivity material layer is lower than the temperature at the bottom surface of the conductive plate. The longer curing time and the more uniform shape of the fillet in the bonded structure enhance the structural reliability of the bonded substrates.

Abstract: A semiconductor device includes a first semiconductor package having at least one first semiconductor chip and a first sealing member covering the at least one first semiconductor chip. The semiconductor device also includes a second semiconductor package stacked on the first semiconductor package. The second semiconductor package has at least one second semiconductor chip, leads electrically connected to the at least one second semiconductor chip, and a second sealing member covering the at least one second semiconductor chip. At least one signal connection member is disposed in the first sealing member of the first semiconductor package. The at least one signal connection member electrically connects the at least one first semiconductor chip with the leads of the at least one second semiconductor chip.

Abstract: A system and method for providing an interposer is provided. An embodiment comprises forming a first region and a second region on an interposer wafer with a scribe region between the first region and the second region. The first region and the second region are then connected to each other through circuitry located over the scribe region. In another embodiment, the first region and the second region may be separated from each other and then encapsulated together prior to the first region being connected to the second region.

Abstract: An embodiment is a package-on-package (PoP) device comprising a first package on a first substrate and a second package over the first package. A plurality of wire sticks disposed between the first package and the second package and the plurality of wire sticks couple the first package to the second package. Each of the plurality of wire sticks comprise a conductive wire of a first height affixed to a bond pad on the first substrate and each of the plurality of wire sticks is embedded in a solder joint.

Abstract: A multi-chip module (MCM) that includes at least two substrates, having facing surfaces, which are mechanically coupled by a set of coupling elements having a reflow characteristic, is described. One of the two substrates includes another set of coupling elements having another reflow characteristic, which is different than the reflow characteristic. These different reflow characteristics of the sets of coupling elements allow different temperature profiles to be used when bonding the two substrates to each other than when bonding the one of the two substrates to a carrier. For example, the temperature profiles may have different peak temperatures and/or different durations from one another. These reflow characteristics may facilitate low-cost, high-yield assembly and alignment of the substrates in the MCM, and may allow temperature-sensitive components to be included in the MCM.

Abstract: A microelectronic package includes first and second encapsulated microelectronic elements, each of which includes a semiconductor die having a front face and contacts thereon. An encapsulant contacts at least an edge surface of each semiconductor die and extends in at least one lateral direction therefrom. Electrically conductive elements extend from the contacts and over the front face to locations overlying the encapsulant. The first and second microelectronic elements are affixed to one another such that one of the front or back surfaces of one of the first and second semiconductor dies is oriented towards one of the front or back surfaces of the other of the first and second semiconductor dies. A plurality of electrically conductive interconnects extend through the encapsulants of the first and second microelectronic elements and are electrically connected with at least one semiconductor die of the first and second microelectronic elements by the conductive elements.

Abstract: Systems and methods are provided for an interposer for coupling two or more integrated circuit dies to a circuit package. A first integrated circuit portion is disposed on a first location of a single semiconductor substrate. A second integrated circuit portion is disposed on a second location of the single semiconductor substrate, where the second integrated circuit portion is electrically isolated from the first integrated circuit portion along a first axis. The first and second integrated circuit portions are configured to provide an electrical coupling to two or more corresponding top die integrated circuits across a second axis that is perpendicular to the first axis.

Abstract: A method of manufacturing a semiconductor package includes preparing a parent substrate including package board parts laterally spaced apart from each other, mounting a first chip including a through-via electrode on each of the package board parts, forming a first mold layer on the parent substrate having the first chips, planarizing the first mold layer to expose back sides of the first chips, etching the exposed back sides of the first chips to expose back sides of the through-via electrodes, forming a passivation layer on the planarized first mold layer, the etched back sides of the first chips, and the back sides of the through-via electrodes, and selectively removing the passivation layer to expose the back sides of the through-via electrodes.

Abstract: Semiconductor devices and methods for forming a semiconductor device are disclosed. The semiconductor device includes a die. The die includes a die substrate having first and second major surfaces. The semiconductor device includes a power module disposed below the second major surface of the die substrate. The power module is electrically coupled to the die through through silicon via (TSV) contacts.

Abstract: A seek-scan probe (SSP) memory involves multiple-wafer bonding needing precision small gaps in between. Solder reflow bonding is typically used to join the wafers due to its reliability and ability to hermetically seal. However, solder reflow bonding may not provide a consistently controllable gap due to flowing solder during the bonding process. Thus, a bond stop technique and process is used to provide accurate cantilever to media gap control.

Abstract: Reliable electrical contact is made with electronic components and effective electrical isolation is produced between the top and bottom of the electronic components. An electronic component is arranged inside a window in a first layer on a substrate. Next, a second layer is put on such that contact areas on the component and contact points on the first layer are freely accessible. Electrical contacts and electrical connecting lines are produced by electrodeposition. The second layer is used to produce bridges over an interval range between the electronic component and the first layer. The bridges have connecting lines formed on them. The second layer can be removed again. Radio-frequency modules can be produced in compact fashion and can be combined with audio-frequency components.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a rounded interconnect on a package carrier having an integrated circuit attached thereto, the rounded interconnect having an actual center; forming an encapsulation over the package carrier covering the rounded interconnect; removing a portion of the encapsulation over the rounded interconnect with an ablation tool; calculating an estimated center of the rounded interconnect; aligning the ablation tool over the estimated center; and exposing a surface area of the rounded interconnect with the ablation tool.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a mountable assembly includes: forming an integrated circuit device having a non-horizontal device side, an active device side, and a passive device side, providing a first integrated circuit die having an active side, a passive side, and an internal interconnect on the active side, applying a die attach adhesive on the passive side, attaching the passive side to the passive device side with the die attach adhesive, and applying an underfill on the passive device side and the internal interconnect, the underfill having a non-horizontal underfill side coplanar with the non-horizontal device side; and mounting on a substrate the mountable assembly.

Abstract: A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. A shielding layer is formed between the first and second semiconductor die. An electrical interconnect, such as conductive pillar, bump, or bond wire, is formed between the first and second semiconductor die. A conductive TSV can be formed through the first and second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and electrical interconnect. A heat sink is formed over the second semiconductor die. An interconnect structure, such as a bump, can be formed over the second semiconductor die. A portion of a backside of the first semiconductor die is removed. A protective layer is formed over exposed surfaces of the first semiconductor die. The protective layer covers the exposed backside and sidewalls of the first semiconductor die.

Abstract: A multi-chip electronic package and methods of manufacture are provided. The method includes adjusting a piston position of one or more pistons with respect to one or more chips on a chip carrier. The adjusting includes placing a chip shim on the chips and placing a seal shim between a lid and the chip carrier. The seal shim is thicker than the chip shim. The adjusting further includes lowering the lid until the pistons contact the chip shim. The method further includes separating the lid and the chip carrier and removing the chip shim and the seal shim. The method further includes dispensing thermal interface material on the chips and lowering the lid until a gap filled with the thermal interface material is about a particle size of the thermal interface material. The method further includes sealing the lid to the chip carrier with sealant.

Abstract: An aggregation of semiconductor devices, comprising: a first layer comprising a first surface and a second surface; a second layer comprising a first region and a second region; and a plurality of semiconductor devices disposed between the first layer and the second region wherein a shape of the second region comprises a curve and a mark.

Abstract: To provide an interlayer filler composition which, in 3D lamination of semiconductor device chips, forms a highly thermally conductive filling interlayer simultaneously with the bonding of solder bumps or the like and lands between semiconductor device chips, a coating fluid and a process for producing a three-dimensional integrated circuit. An interlayer filler composition for a three-dimensional integrated circuit, which comprises a resin (A) having a melt viscosity at 120° C. of at most 100 Pa·s and a flux (B), the content of the flux (B) being at least 0.1 part by weight and at most 10 parts by weight per 100 parts by weight of the resin (A).

Abstract: A bonded device having at least one porosified surface is disclosed. The porosification process introduces nanoporous holes into the microstructure of the bonding surfaces of the devices. The material property of a porosified material is softer as compared to a non-porosified material. For the same bonding conditions, the use of the porosified bonding surfaces enhances the bond strength of the bonded interface as compared to the non-porosified material.

Abstract: A method of assembling a semiconductor device includes providing a substrate having an array of substrate elements linked by substrate corner elements and separated by slots extending between the corner elements. Semiconductor dies are positioned on the substrate elements. A cap, frame and contact structure is provided that has a corresponding array of caps supported by corner legs linking the caps to frame corner elements, frame elements linking the frame corner elements, and sets of electrical contact elements supported by the frame elements. The cap, frame and contact structure is fitted on the substrate with the caps extending over corresponding dies, the frame corner elements extending over the substrate corner elements, and the sets of electrical contact elements disposed in the slots. The dies are connected electrically with the electrical contact elements and the assembly is encapsulated and singulated. Singulating removes the frame elements.

Abstract: A combined battery and device apparatus and associated method. This apparatus includes a first conductive layer, a battery comprising a cathode layer; an anode layer, and an electrolyte layer located between and electrically isolating the anode layer from the cathode layer, wherein the anode or the cathode or both include an intercalation material, the battery disposed such that either the cathode layer or the anode layer is in electrical contact with the first conductive layer, and an electrical circuit adjacent face-to-face to and electrically connected to the battery. Some embodiments further include a photovoltaic cell and/or thin-film capacitor. In some embodiments, the substrate includes a polymer having a melting point substantially below 700 degrees centigrade. In some embodiments, the substrate includes a glass. For example, some embodiments include a battery deposited directly on the back of a liquid-crystal display (LCD) device.

Abstract: A method for making an actuator device includes providing a wafer comprising a layer of an electrically conductive material and forming a plurality of rotationally symmetrical dies in the electrically conductive material, each die including a plurality of radial tabs and complementarily sized radial recesses arranged in alternating fashion and at equal angular increments around the circumfery of the die. To maximize the use of available wafer space, the dies are arranged in a pattern on the wafer in which each die is rotated relative to adjacent dies through an angle of 360 degrees divided by twice the number of tabs or recesses on the die and, except for dies located at an outer periphery of the wafer, each die is disposed in edge-to-edge near abutment with an adjacent die and each tab of each die is nested within a complementary recess of an adjacent die.

Abstract: In an embodiment, there is provided a packaging arrangement comprising a substrate; a multi-memory die coupled to the substrate, wherein the multi-memory die comprises multiple individual memory dies, and each of the multiple individual memory dies is defined as an individual memory die within a wafer of semiconductor material during production of memory dies, and the multi-memory die is created by singulating the wafer of semiconductor material into memory dies, where at least one of the memory dies is the multi-memory die that includes the multiple individual memory dies that are still physically connected together; and a semiconductor die coupled to the multi-memory die and the substrate, wherein the semiconductor die is configured as a system on a chip, wherein at least one of the multi-memory die and the semiconductor die is attached to the substrate.

Abstract: A semiconductor-device mounting structure includes a first semiconductor device and a plate-shaped second semiconductor device connected to the first semiconductor device. The first semiconductor device includes a flexible board, an electronic component, and a sealing resin. The flexible board includes a bendable flexible portion and a hard portion. The flexible portion is bent at a boundary with the hard portion, along a shape of the electronic component such that the flexible board covers the electronic component. The flexible board and the electronic component are sealed with the sealing resin. The first semiconductor device is provided vertical to the second semiconductor device such that the hard portion is provided parallel to the second semiconductor device.

Abstract: A three-dimensional integrated circuit is disclosed, including a first interposer including through substrate vias (TSV) therein and circuits thereon; a plurality of first active dies disposed on a first side of the first interposer, a plurality of first intermediate interposers, each including through substrate vias (TSV), disposed on the first side of the first interposer, and a second interposer including through substrate vias (TSV) therein and circuits thereon supported by the first intermediate interposers.

Abstract: A method includes providing a carrier having a first cavity, providing a dielectric foil with a metal layer attached to the dielectric foil, placing a first semiconductor chip in the first cavity of the carrier, and applying the dielectric foil to the carrier.

Abstract: A wafer of passive components is diced to leave a flat passive chip. The flat passive chip has bond pads for passive components on a same side of the flat passive chip. The flat passive chip is stacked onto an active chip. The passive components are wirebonded together to connect the passive components in series or parallel, resulting in the flat passive chip having an overall passive characteristic equal to a target characteristic.

Abstract: A semiconductor device is provided with a semiconductor element having a plurality of electrodes, a plurality of terminals electrically connected to the plurality of electrodes, and a sealing resin covering the semiconductor element. The sealing resin covers the plurality of terminals such that a bottom surface of the semiconductor element in a thickness direction is exposed. A first terminal, which is one of the plurality of terminals, is disposed in a position that overlaps a first electrode, which is one of the plurality of electrodes, when viewed in the thickness direction. The semiconductor device is provided with a conductive connection member that contacts both the first terminal and the first electrode.