Stacked Array (e.g., Rectifier, Etc.) Patents (Class 438/109)
  • Patent number: 10903200
    Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: January 26, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuji Karakane, Masatoshi Fukuda, Soichi Homma, Naoyuki Komuta, Yukifumi Oyama
  • Patent number: 10879260
    Abstract: A bonded assembly includes a first memory die containing a first three-dimensional memory device, a second memory die containing a second three-dimensional memory device, and a support die bonded to the first memory die and comprising a peripheral circuitry configured to control the first three-dimensional memory device and the second three-dimensional memory device. The first memory die includes multiple rows of first-die proximal bonding pads, multiple rows of first-die distal bonding pads, and a plurality of first-die laterally-shifting electrically conductive paths connecting a respective one of the first-die proximal bonding pads and a respective one of the first-die distal bonding pads that is laterally offset from the respective one of the first-die proximal bonding pads. The first memory die and the second memory die can have an identical layout, and electrical connections can be shifted through the first memory die by the offset distance.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: December 29, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Tatsuya Uryu, Satoshi Shimizu, Nobuyuki Fujimura
  • Patent number: 10872866
    Abstract: A semiconductor package including a substrate having a surface, and a conductive element on the first surface and electrically coupled to the substrate. The conductive element has a principal axis forming an angle less than 90 degrees with the surface.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: December 22, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Jenchun Chen
  • Patent number: 10867956
    Abstract: A method for manufacturing a semiconductor device, for example formed utilizing component stacking. As non-limiting examples, various aspects of this disclosure provide a method for reducing warpage and/or stress in stacked semiconductor devices.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: December 15, 2020
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Won Chul Do, Jin Hee Park
  • Patent number: 10851269
    Abstract: A pressure-sensitive adhesive composition, which may have excellent durability under high temperature or humidity conditions and exhibit high close adhesion to optical films, thereby forming a pressure-sensitive adhesive having superior cuttability and re-workability, is provided. Also, a pressure-sensitive adhesive composition capable of forming a pressure-sensitive adhesive capable of effectively inhibiting bending when applied to a thin substrate such as a very thin glass substrate, minimizing a time required to stabilize physical properties, and preventing a degradation of the secured physical properties in time, a pressure-sensitive adhesive optical member formed using such a pressure-sensitive adhesive composition, an optical laminate, and a display device are provided.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: December 1, 2020
    Inventors: Kee Young Kim, Il Jin Kim, Jeong Ae Yoon, Sung Soo Yoon, Su Jeong Kim, Sang Hyun Hong
  • Patent number: 10854565
    Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure and a first chip structure over the redistribution structure. The chip package structure also includes a first solder bump between the redistribution structure and the first chip structure and a first molding layer surrounding the first chip structure. The chip package structure further includes a second chip structure over the first chip structure and a second molding layer surrounding the second chip structure. In addition, the chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump. A portion of the third molding layer is between the first molding layer and the redistribution structure.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Yu Chen, Li-Hsien Huang, An-Jhih Su, Hsien-Wei Chen
  • Patent number: 10811386
    Abstract: The present technology relates to a semiconductor device. The semiconductor device comprises: a plurality of dies stacked on top of each other, each of the dies comprising a first major surface, an IO conductive pattern on the first major surface and extended to a minor surface substantially perpendicular to the major surfaces to form at least one IO electrical contact on the minor surface, and the plurality of dies aligned so that the corresponding minor surfaces of all dies substantially coplanar with respect to each other to form a common flat sidewall, and a plurality of IO routing traces formed over the sidewall and at least partially spaced away from the sidewall. The plurality of IO routing traces are spaced apart from each other in a first direction on the sidewall, and each of IO routing traces is electrically connected to a respective IO electrical contact and extended across the sidewall in a second direction substantially perpendicular to the first direction on the sidewall.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: October 20, 2020
    Assignee: SanDisk Information Technology (Shanghai) Co., Ltd.
    Inventors: Chin Tien Chiu, Hem Takiar, Gursharan Singh, Fisher Yu, C C Liao
  • Patent number: 10804413
    Abstract: A package component includes a base layer, a sensing layer, a photo-curable adhesive, a cover layer and a first filter structure. The photo-curable adhesive and the sensing layer are disposed on the base layer. The sensing layer includes a sensing unit surrounded by the photo-curable adhesive. The cover layer is disposed on the sensing layer. The first filter structure faces the photo-curable adhesive and is disposed on the cover layer. The first filter structure is configured for transmitting a curing light which is used to cure the photo-curable adhesive, and for reflecting a detectable light which is to be sensed by the sensing unit, where the wavelength of the curing light is different from the wavelength of the detectable light.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: October 13, 2020
    Assignee: KINGPAK TECHNOLOGY INC
    Inventor: Yu-Hsuan Tsai
  • Patent number: 10741499
    Abstract: A system-level packaging method includes providing a packaging substrate having a first functional surface and a second surface with wiring arrangement within the packaging substrate and between the first functional surface and the second surface. The method also includes forming at least two package layers on the first functional surface of the packaging substrate, wherein each package layer is formed by subsequently forming a mounting layer, a sealant layer, and a wiring layer. Further, the method includes forming a top sealant layer and planting connection balls on the second functional surface of the packaging substrate.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: August 11, 2020
    Assignee: TONGFU MICROELECTRONICS CO., LTD.
    Inventors: Yujuan Tao, Lei Shi, Honghui Wang
  • Patent number: 10707181
    Abstract: A semiconductor device with redistribution layers formed utilizing dummy substrates is disclosed and may include forming a first redistribution layer on a first dummy substrate, forming a second redistribution layer on a second dummy substrate, electrically connecting a semiconductor die to the first redistribution layer, electrically connecting the first redistribution layer to the second redistribution layer, and removing the dummy substrates. The first redistribution layer may be electrically connected to the second redistribution layer utilizing a conductive pillar. An encapsulant material may be formed between the first and second redistribution layers. Side portions of one of the first and second redistribution layers may be covered with encapsulant. A surface of the semiconductor die may be in contact with the second redistribution layer. The dummy substrates may be in panel form. One of the dummy substrates may be in panel form and the other in unit form.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: July 7, 2020
    Assignee: AMKOR TECHNOLOGY INC.
    Inventors: Jin Young Kim, Ji Young Chung, Doo Hyun Park, Choon Heung Lee
  • Patent number: 10685934
    Abstract: A semiconductor device package includes an electronic component, a first set of conductive wires electrically connected to the electronic component, and an insulation layer surrounding the first set of conductive wires. The insulation layer exposes a portion of the first set of the conductive wires. The insulation layer is devoid of a filler.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: June 16, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jen-Kuang Fang, Wen-Long Lu
  • Patent number: 10679921
    Abstract: Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. An uppermost semiconductor die of the stack of semiconductor dice located on a side of the stack of semiconductor dice opposite the substrate may be a heat-generating component configured to generate more heat than each other semiconductor die of the stack of semiconductor dice. Vias may directly electrically connect the uppermost semiconductor die to the substrate.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: June 9, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Steven Groothuis, Jian Li, Shijian Luo
  • Patent number: 10600773
    Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: March 24, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuji Karakane, Masatoshi Fukuda, Soichi Homma, Naoyuki Komuta, Yukifumi Oyama
  • Patent number: 10566370
    Abstract: An image sensing apparatus includes a first substrate structure, a second substrate structure, and a memory chip. The first substrate structure includes a pixel region having a photoelectric conversion element. The second substrate structure includes a first surface connected to the first substrate structure and a second surface opposite the first surface, and also includes a circuit region to drive the pixel region. The memory chip is mounted on the second surface of the second substrate structure. The first substrate structure and the second substrate structure are electrically connected by first connection vias passing through the first substrate structure. The second substrate structure and the memory chip are electrically connected by second connection vias passing through a portion of the second substrate structure. The first connection vias and the second connection vias are at different positions on a plane.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: February 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Hyun Yoon, Doo Won Kwon, Kwan Sik Kim, Tae Young Song, Min Jun Choi
  • Patent number: 10546809
    Abstract: A method is provided to supply power to wafer-scale ICs. The method includes receiving a wafer containing ICs placed on the top of the wafer. The wafer has through-silicon vias to provide power from the bottom to the ICs. The method also includes a printed circuit board, which has power rails in a pattern on the top of the printed circuit board, where the rails provide voltage and ground. The method continues with placing metal solder spheres between the bottom of the wafer and the top of the printed circuit board, where the spheres provide connections between the two, and where the spheres are free to move and operate as mechanical springs to resist clamping forces. The method also includes applying clamping pressure to the structure to establish connections by compressing the spheres, where no soldering is required.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles E. Cox, Harald Huels, Arvind Kumar, Xiao Hu Liu, Ahmet S. Ozcan, Winfried W. Wilcke
  • Patent number: 10490520
    Abstract: In a multi-chip module (MCM), a “super” chip (110N) is attached to multiple “plain” chips (110F? “super” and “plain” chips can be any chips). The super chip is positioned above the wiring board (WB) but below at least some of plain chips (110F). The plain chips overlap the super chip. Further, the plain chips' low speed IOs can be connected to the WB by long direct connections such as bond wires (e.g. BVAs) or solder stacks; such connections can be placed side by side with the super chip. Such connections can be long, so the super chip is not required to be thin. Also, if through-substrate vias (TSVs) are omitted, the manufacturing yield is high and the manufacturing cost is low. Other structures are provided that combine the short and long direct connections to obtain desired physical and electrical properties.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: November 26, 2019
    Assignee: Invensas Corporation
    Inventors: Liang Wang, Rajesh Katkar, Hong Shen
  • Patent number: 10455704
    Abstract: A method of filling a hole formed in a component carrier with copper is disclosed. The method comprises i) forming a layer of an electrically conductive material covering at least part of a surface of a wall, wherein the wall delimits the hole, and subsequently ii) covering at least partially the layer and filling at least partially an unfilled volume of the hole with copper using a plating process including a bath. Hereby, the bath comprises a concentration of a copper ion, in particular Cu2+, in a range between 50 g/L and 75 g/L, in particular in a range between 60 g/L and 70 g/L.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: October 22, 2019
    Assignee: AT&S AUSTRIA TECHNOLOGIE & SYSTEMTECHNIK AKTIENGESELLSCHAFT
    Inventors: Ares Wang, Yee-Bing Ling, Annie Tay
  • Patent number: 10438935
    Abstract: According to one embodiment, the first end part of the first semiconductor chip in a lower stage protrudes to a larger extent in a first direction than the first end part of the first semiconductor chip in an upper stage. The second end part of the second semiconductor chip in a lower stage protrudes to a larger extent in a second direction opposite from the first direction than the second end part of the second semiconductor chip in an upper stage. The first interlayer semiconductor chip includes a first portion, a second portion, and a third electrode pad. The first portion overlaps the first chip group. The second portion protrudes in the second direction beyond the first chip group and the second chip group and is thicker than the first portion. The third electrode pad is provided on the second portion and bonded with the third metal wire.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: October 8, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuo Shimokawa, Masayuki Uchida, Akira Tojo, Masatoshi Tanabe, Takashi Ito
  • Patent number: 10418321
    Abstract: A compact semiconductor device with an isolator. The semiconductor device includes two chips, namely a first semiconductor chip and a second semiconductor chip which are stacked with the main surfaces of the semiconductor chips partially facing each other. A first coil and a second coil which are formed in the first semiconductor chip and the second semiconductor chip respectively are arranged to face each other so as to be magnetically coupled during operation of the semiconductor device. The pair of first and second coils make up an isolator. The first coil is arranged in a manner to overlap part of the circuit region of the first semiconductor chip in plan view and the second coil is arranged in a manner to overlap part of the circuit region of the second semiconductor chip in plan view.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: September 17, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Kuwabara, Tetsuya Iida, Yasutaka Nakashiba
  • Patent number: 10373888
    Abstract: An electronic package assembly is disclosed. A substrate can have an upper surface area. A first active die can have an upper surface area and a bottom surface, the bottom surface operably coupled to the substrate. A second active die can have an upper surface area and a bottom surface, the bottom surface operably coupled to the substrate. A capillary underfill material can at least partially encapsulate the bottom surface of the first active die and the second active die and extend upwardly upon inside side surfaces of the first and second active dies. A combined area of the upper surface area of the first active die and an upper surface area of the second active die is at least about 90% of the upper surface area of the substrate.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventors: Eric J. Li, Vipul V. Mehta, Digvijay A. Raorane
  • Patent number: 10347585
    Abstract: A fan-out semiconductor package includes: a first semiconductor chip having a first active surface having first connection pads; a first encapsulant encapsulating the first semiconductor chip; a first connection member disposed on the first active surface and including a first redistribution layer electrically connected to the first connection pads; a second semiconductor chip having a second active surface having second connection pads; a second encapsulant covering the first connection member and encapsulating the second semiconductor chip; a second connection member disposed on the second active surface and including a second redistribution layer electrically connected to the second connection pads; and a third via penetrating through the second encapsulant, connecting the first redistribution layer and the second redistribution layer to each other, and including a metal post connected to the first redistribution layer and a via conductor disposed on the metal post and connected to the second redistributio
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: July 9, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Seung Wan Shin, Seung Chul Oh
  • Patent number: 10297541
    Abstract: Microelectronic devices having a multiple-component substrate assembly. A primary supports one or more integrated circuits, and an auxiliary substrate is coupled to, and makes electrical connections with, the primary substrate. The primary substrate will define a pinout for some or all contacts of the integrated circuit, and the auxiliary substrate will provide an additional pinout option. Different configurations of a single primary substrate may be adapted to different applications through use of different configurations of auxiliary substrates.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Min Suet Lim, Mooi Ling Chang, Eng Huat Goh, Say Thong Tony Tan, Tin Poay Chuah
  • Patent number: 10283485
    Abstract: A semiconductor device is disclosed including semiconductor die stacked in a stepped, offset configuration, where die bond pads of semiconductor die on different levels are interconnected using one or more conductive bumps.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: May 7, 2019
    Assignee: SanDisk Semiconductor (Shanghai) Co. Ltd.
    Inventors: Junrong Yan, Xiaofeng Di, Chee Keong Chin, Kim Lee Bock, Mingxia Wu
  • Patent number: 10269782
    Abstract: Apparatuses and methods for forming die stacks are disclosed herein. An example method includes dispensing a temporary adhesive onto a substrate, placing a base die onto the temporary adhesive, curing the temporary adhesive, forming a die stack that includes the base die, activating a release layer disposed on the substrate, wherein the release layer is between the substrate and the temporary adhesive, removing the die stack from the substrate, and removing the temporary adhesive from the die stack.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: April 23, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Michel Koopmans
  • Patent number: 10163701
    Abstract: Multi-stack package-on-package structures are disclosed. In a method, a first stacked semiconductor device is formed on a first carrier wafer. The first stacked semiconductor device is singulated. The first stacked semiconductor device is adhered to a second carrier wafer. A second semiconductor device is attached on the first stacked semiconductor device. The second semiconductor device and the first stacked semiconductor device are encapsulated. Electrical connections are formed on and electrically coupled to the first stacked semiconductor device and the second semiconductor device.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Jung Lee, Hsien-Wei Chen, An-Jhih Su, Wei-Yu Chen, Tien-Chung Yang, Li-Hsien Huang
  • Patent number: 10163849
    Abstract: A method of manufacturing a semiconductor structure, including receiving a first substrate including a plurality of conductive bumps disposed over the first substrate; receiving a second substrate; disposing an adhesive over the first substrate; removing a portion of the adhesive to expose at least one of the plurality of conductive bumps; and bonding the first substrate with the second substrate.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Alexander Kalnitsky, Yi-Yang Lei, Hsi-Ching Wang, Cheng-Yu Kuo, Tsung Lung Huang, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu, Chin-Yu Ku, De-Dui Liao, Kuo-Chio Liu, Kai-Di Wu, Kuo-Pin Chang, Sheng-Pin Yang, Isaac Huang
  • Patent number: 10157825
    Abstract: A structure includes a metal pad, a passivation layer having a portion covering edge portions of the metal pad, and a dummy metal plate over the passivation layer. The dummy metal plate has a plurality of through-openings therein. The dummy metal plate has a zigzagged edge. A dielectric layer has a first portion overlying the dummy metal plate, second portions filling the first plurality of through-openings, and a third portion contacting the first zigzagged edge.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Hsien-Wei Chen, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Li-Han Hsu, Wei-Cheng Wu
  • Patent number: 10147676
    Abstract: A method is provided to supply power to wafer-scale ICs. The method includes receiving a wafer containing ICs placed on the top of the wafer. The wafer has through-hole vias to provide power from the bottom to the ICs. The method also includes a printed circuit board, which has power rails in a pattern on the top of the printed circuit board, where the rails provide voltage and ground. The method continues with placing metal solder spheres between the bottom of the wafer and the top of the printed circuit board, where the spheres provide connections between the two, and where the spheres are free to move and operate as mechanical springs to resist clamping forces. The method also includes applying clamping pressure to the structure to establish connections by compressing the spheres, where no soldering is required.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: December 4, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles E. Cox, Harald Huels, Arvind Kumar, Xiao Hu Liu, Ahmet S. Ozcan, Winfried W. Wilcke
  • Patent number: 10128223
    Abstract: A semiconductor device includes a first chip, a second chip stacked on the first chip, and a third chip stacked on the second chip. The second chip includes a second semiconductor layer having a second circuit surface facing the first wiring layer and a second rear surface opposite to the second circuit surface, a second wiring layer provided on the second circuit surface and connected to a first wiring layer of the first chip, and a second electrode extending through the second semiconductor layer and connected to the second wiring layer. The third chip includes a third semiconductor layer having a third circuit surface and a third rear surface facing the second chip, a third wiring layer provided on the third circuit surface, and a third electrode extending through the third semiconductor layer, connected to the third wiring layer and connected to the second electrode through bumps.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: November 13, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Kazushige Kawasaki, Yoichiro Kurita
  • Patent number: 10115694
    Abstract: An electronic device includes an electronic part including a first substrate having a group of first terminals over a first front surface and having a concavity in a back surface, a filler placed in the concavity, and a flat plate placed over the back surface with the filler therebetween, and further includes a second substrate disposed on the first front surface side of the first substrate and having a group of second terminals bonded to the group of first terminals over a second front surface opposite the first front surface. The filler and flat plate minimize deformation of the first substrate and variation in the distance between the group of first terminals and the group of second terminals caused by the deformation of the first substrate, which thereby reduces the occurrence of a failure in bonding together the group of first terminals and the group of second terminals.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: October 30, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Hidehiko Kira, Naoaki Nakamura, Sanae Iijima
  • Patent number: 10103126
    Abstract: A laminated semiconductor device includes: three or more semiconductor chips that are laminated; resins that are disposed among the semiconductor chips, the resins softening by heating; and support members that are disposed among the semiconductor chips and that contacts the adjacent semiconductor chips, the support members deforming by external force when a temperature of the support members reaching a predetermined temperature.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: October 16, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Hidehiko Kira, Norio Kainuma
  • Patent number: 10083916
    Abstract: A semiconductor device is made by forming a first conductive layer over a sacrificial carrier. A conductive pillar is formed over the first conductive layer. An active surface of a semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the conductive pillar. The carrier and adhesive layer are removed. A stress relief insulating layer is formed over the active surface of the semiconductor die and a first surface of the encapsulant. The stress relief insulating layer has a first thickness over the semiconductor die and a second thickness less than the first thickness over the encapsulant. A first interconnect structure is formed over the stress relief insulating layer. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The first and second interconnect structures are electrically connected through the conductive pillar.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: September 25, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Il Kwon Shim, Seng Guan Chow, Yaojian Yaojian
  • Patent number: 10056351
    Abstract: An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a through intervia (TIV) extending through the molding compound. One or more first fan-out redistribution layers (RDLs) are disposed over the first fan-out tier and bonded to the first device die. A second fan-out tier having a second device die is disposed over the one or more first fan-out RDLs. The one or more first fan-out RDLs electrically connects the first and second device dies. The TIV electrically connects the one or more first fan-out RDLs to one or more second fan-out RDLs. The package further includes a plurality of external connectors at least partially disposed in the one or more second fan-out RDLs. The plurality of external connectors are further disposed on conductive features in the one or more second fan-out RDLs.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: August 21, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee
  • Patent number: 10037958
    Abstract: Wafers include multiple bulk redistribution layers. A terminal contact pad is on a surface of one of the bulk redistribution layers. A final redistribution layer is formed on the surface and in contact with the terminal contact pad. The final redistribution layer is formed from a material other than a material of the plurality of bulk redistribution layers. A solder ball is formed on the terminal contact pad.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: July 31, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toyohiro Aoki, Takashi Hisada, Eiji I. Nakamura
  • Patent number: 10026702
    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a passivation layer disposed on the second interconnection member.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: July 17, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Doo Hwan Lee, Jong Rip Kim, Hyoung Joon Kim, Jin Yul Kim, Kyung Seob Oh
  • Patent number: 9972554
    Abstract: A wafer level chip scale package (WLCSP) has a device chip, a carrier chip, an offset pad, a conductive spacing bump and a through hole via (THV). The device chip is attached to the carrier chip. The offset pad is disposed on a first surface of the device chip. The conductive spacing bump is formed on the offset pad. The through hole via includes a through hole and a hole metal layer. The through hole penetrates through the carrier chip and the device chip, and the hole metal layer is formed in the through hole and in contact with the offset pad.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: May 15, 2018
    Assignee: POWERTECH TECHNOLOGY INC.
    Inventors: Li-Chih Fang, Chia-Chang Chang, Hung-Hsin Hsu, Wen-Hsiung Chang, Kee-Wei Chung, Chia-Wen Lien
  • Patent number: 9966278
    Abstract: There is provided a method of manufacturing a stack package. The method includes vertically stacking core dies on a base die wafer to provide a stack structure, forming partition walls on the base die wafer to surround the stack structure, and forming an underfill material layer that includes under-filling portions filling gaps between the core dies, and filling fillet portions covering side surfaces of the core dies. The fillet portions are formed to have a width confined by the partition walls. The partition walls are removed, and a mold layer is formed to cover the fillet portions. Related stack packages are also provided.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: May 8, 2018
    Assignee: SK hynix Inc.
    Inventors: Taehoon Kim, Hyun Kyu Ryu
  • Patent number: 9960128
    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a passivation layer disposed on the second interconnection member.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: May 1, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Doo Hwan Lee, Jong Rip Kim, Hyoung Joon Kim, Jin Yul Kim, Kyung Seob Oh
  • Patent number: 9941252
    Abstract: A semiconductor package includes a first semiconductor chip including a through silicon via in the first semiconductor chip and a first trench portion in an upper portion of the first semiconductor chip, a second semiconductor chip on an upper surface of the first semiconductor chip and being electrically connected to the first semiconductor chip through the through silicon via of the first semiconductor chip, and an insulating bonding layer between the first semiconductor chip and the second semiconductor chip. The insulating bonding layer fills the first trench portion.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: April 10, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kunsil Lee
  • Patent number: 9929149
    Abstract: Various implementations described herein may be directed to using inter-tier vias (IVs) in integrated circuits (ICs). In one implementation, a three-dimensional (3D) IC may include a plurality of tiers disposed on a substrate layer, where the tiers may include a first tier having a first active device layer electrically coupled to first interconnect layers, and may also include a second tier having a second active device layer electrically coupled to a second interconnect layer, where the first interconnect layers include an uppermost layer that is least proximate to the first active device layer. The 3D IC may further include IVs to electrically couple the second interconnect layer and the uppermost layer. The uppermost layer may be electrically coupled to a power source at peripheral locations of the first tier, thereby electrically coupling the power source to the first active device layer and to the second active device layer.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: March 27, 2018
    Assignee: ARM Limited
    Inventors: Saurabh Pijuskumar Sinha, Robert Campbell Aitken, Brian Tracy Cline, Gregory Munson Yeric, Kyungwook Chang
  • Patent number: 9754918
    Abstract: Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL and the second RDL. First vias extend from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side. First spacers are interposed between the first semiconductor substrate and the first vias and each extend from a respective one of the first conductive elements through the first semiconductor substrate.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: September 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Ching Tsai, Sung-Feng Yeh
  • Patent number: 9741680
    Abstract: A stackable integrated circuit chip layer and module device that avoids the use of electrically conductive elements on the external surfaces of a layer containing an integrated circuit die by taking advantage of conventional wire bonding equipment to provide an electrically conductive path defined by a wire bond segment that is encapsulated in a potting material so as to define an electrically conductive wire bond “through-via” accessible from at least the lower or second surface of the layer.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: August 22, 2017
    Assignee: PFG IP LLC
    Inventors: Randy Bindrup, W. Eric Boyd, John Leon, James Yamaguchi, Angel Pepe
  • Patent number: 9711494
    Abstract: Methods of fabricating multi-die assemblies including a base semiconductor die bearing a peripherally encapsulated stack of semiconductor dice of lesser lateral dimensions, the dice vertically connected by conductive elements between the dice, resulting assemblies, and semiconductor devices comprising such assemblies.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: July 18, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Luke G. England, Paul A. Silvestri, Michel Koopmans
  • Patent number: 9601463
    Abstract: An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a through intervia (TIV) extending through the molding compound. One or more first fan-out redistribution layers (RDLs) are disposed over the first fan-out tier and bonded to the first device die. A second fan-out tier having a second device die is disposed over the one or more first fan-out RDLs. The one or more first fan-out RDLs electrically connects the first and second device dies. The TIV electrically connects the one or more first fan-out RDLs to one or more second fan-out RDLs. The package further includes a plurality of external connectors at least partially disposed in the one or more second fan-out RDLs. The plurality of external connectors are further disposed on conductive features in the one or more second fan-out RDLs.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee
  • Patent number: 9583525
    Abstract: An image sensor. Implementations may include: a first die including a plurality of pixels; a second die including a plurality of transistors, capacitors, or both transistors and capacitors; a third die including analog circuitry, logic circuitry, or analog and logic circuitry. The first die may be hybrid bonded to the second die, and the second die may be fusion bonded to the third die. The plurality of transistors, capacitors or transistors and capacitors of the second die may be adapted to enable operation of the plurality of pixels of the first die. The analog circuitry, logic circuitry, and analog circuitry and logical circuitry may be adapted to perform signal routing.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: February 28, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Swarnal Borthakur, Marc Sulfridge, Vladimir Korobov
  • Patent number: 9497861
    Abstract: Methods and apparatus for an interposer with a dam used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: November 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Lin Lu, Kai-Chiang Wu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang
  • Patent number: 9490173
    Abstract: A method for processing a wafer including a plurality of chips is provided. The method may include: forming a trench in the wafer between the plurality of chips; forming a diffusion barrier layer at least over the sidewalls of the trench; forming encapsulation material over the plurality of chips and in the trench; and singularizing the plurality of chips from a side opposite the encapsulation material.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: November 8, 2016
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Hubert Maier
  • Patent number: 9431334
    Abstract: In one embodiment, a semiconductor device includes a single layer substrate having an insulation layer and conductive patterns on a first surface of the insulation layer. A semiconductor die is attached on a first surface of the single layer substrate and electrically connected to the conductive patterns. Conductive bumps are also on the first surface of the single layer substrate and electrically connected to the semiconductor die through the conductive patterns. An encapsulant overlaps at least portions of the first surface of the single layer substrate. The conductive bumps are at least partially exposed in the encapsulant.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: August 30, 2016
    Assignee: Amkor Technology, Inc.
    Inventors: Hyung Il Jeon, Byong Jin Kim, Gi Jeong Kim, Jae Min Bae, Tae Ki Kim
  • Patent number: 9425177
    Abstract: A method of manufacturing a semiconductor device according to one embodiment includes: preparing a semiconductor water which is partitioned into a plurality of first semiconductor chips, the plurality of first semiconductor chips including a first group of first semiconductor chips and a second group of first semiconductor chips; providing a second semiconductor chip over at least one of first semiconductor chips of the first group; providing a sealer on the first semiconductor chips of the second group; and grinding one face of the semiconductor wafer which is on the opposite side from a face on which the second semiconductor chip and the sealer are provided.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: August 23, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Tadashi Koyanagi, Youkou Ito
  • Patent number: 9412675
    Abstract: Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive member coupled to a first semiconductor die and a second conductive member coupled to second semiconductor die. The first conductive member includes a recessed surface defining a depression. The second conductive member extends at least partially into the depression of the first conductive member. A bond material within the depression can at least partially encapsulate the second conductive member and thereby bond the second conductive member to the first conductive member.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: August 9, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Jaspreet S. Gandhi, Wayne H. Huang, James M. Derderian