Stacked Array (e.g., Rectifier, Etc.) Patents (Class 438/109)
  • Patent number: 11929345
    Abstract: In an embodiment, a device includes: a first device including: an integrated circuit device having a first connector; a first photosensitive adhesive layer on the integrated circuit device; and a first conductive layer on the first connector, the first photosensitive adhesive layer surrounding the first conductive layer; a second device including: an interposer having a second connector; a second photosensitive adhesive layer on the interposer, the second photosensitive adhesive layer physically connected to the first photosensitive adhesive layer; and a second conductive layer on the second connector, the second photosensitive adhesive layer surrounding the second conductive layer; and a conductive connector bonding the first and second conductive layers, the conductive connector surrounded by an air gap.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chun Hui Yu, Kuo-Chung Yee
  • Patent number: 11887963
    Abstract: According to one embodiment, a semiconductor device includes a support and a stacked body on the support. The stacked body is formed of a plurality of semiconductor chips that are stacked on each other. The stacked body has a lower surface facing the support and an upper surface facing away from the support. A first wire is connected to one of the semiconductor chips in the stack and extends upward from the semiconductor chip to at least the height of the upper surface of the stacked body. A second wire is connected to the support and extends upward from the support to at least the height of the upper surface of the stacked body.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: January 30, 2024
    Assignee: Kioxia Corporation
    Inventor: Kazuma Hasegawa
  • Patent number: 11881398
    Abstract: A first semiconductor substrate contains a first semiconductor material, such as silicon. A second semiconductor substrate containing a second semiconductor material, such as gallium nitride or aluminum gallium nitride, is formed on the first semiconductor substrate. The first semiconductor substrate and second semiconductor substrate are singulated to provide a semiconductor die including a portion of the second semiconductor material supported by a portion of the first semiconductor material. The semiconductor die is disposed over a die attach area of an interconnect structure. The interconnect structure has a conductive layer and optional active region. An underfill material is deposited between the semiconductor die and die attach area of the interconnect structure. The first semiconductor material is removed from the semiconductor die and the interconnect structure is singulated to separate the semiconductor die. The first semiconductor material can be removed post interconnect structure singulation.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: January 23, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Gordon M. Grivna, Stephen St. Germain
  • Patent number: 11881524
    Abstract: A semiconductor device includes: a first semiconductor chip having first and second electrodes on a first surface and having a third electrode on a second surface; a second semiconductor chip having first and second electrodes on a first surface and having a third electrode on a second surface; a first electrode plate bonded to the second electrode of the first semiconductor chip; a second electrode plate bonded to the third electrode of the second semiconductor chip; and a third electrode plate having a first area sandwiched between the first and second semiconductor chips and a second area not sandwiched between the first and second semiconductor chips, one surface of the first area is bonded to the second electrode of the second semiconductor chip, and another surface is bonded to the third electrode of the first semiconductor chip, and the first area is thinner than the second area.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: January 23, 2024
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Hisato Michikoshi
  • Patent number: 11869870
    Abstract: First and second contacts are formed on first and second wafers from disparate first and second conductive materials, at least one of which is subject to surface oxidation when exposed to air. A layer of oxide-inhibiting material is disposed over a bonding surface of the first contact and the first and second wafers are positioned relative to one another such that a bonding surface of the second contact is in physical contact with the layer of oxide-inhibiting material. Thereafter, the first and second contacts and the layer of oxide-inhibiting material are heated to a temperature that renders the first and second contacts and the layer of oxide-inhibiting material to liquid phases such that at least the first and second contacts alloy into a eutectic bond.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: January 9, 2024
    Assignee: SiTime Corporation
    Inventors: Paul M. Hagelin, Charles I. Grosjean
  • Patent number: 11869849
    Abstract: A semiconductor package includes a carrier substrate having a top surface; a semiconductor die mounted on the top surface; first bonding wires connecting the semiconductor die to the carrier substrate; an insulating material encapsulating the plurality of first bonding wires; a component having a metal layer mounted on the insulating material; second bonding wires connecting the metal layer of the component to the carrier substrate; and a molding compound covering the top surface of the carrier substrate and encapsulating the semiconductor die, the component, the first bonding wires, the second bonding wires, and the insulating material. The metal layer and the second bonding wires constitute an electromagnetic interference (EMI) shielding structure.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: January 9, 2024
    Assignee: MEDIATEK INC.
    Inventor: Shiann-Tsong Tsai
  • Patent number: 11862545
    Abstract: An integrated substrate, an electronic assembly, and manufacturing methods thereof are provided. The integrated substrate structure includes a coarse redistribution structure, fine redistribution segments, and conductive connectors. The coarse redistribution structure includes a coarse dielectric layer and a coarse circuitry embedded therein. The fine redistribution segments disposed over the coarse redistribution structure and disposed side by side and apart from one another. The respective fine redistribution segment includes a fine dielectric layer thinner than the coarse dielectric layer, and a fine circuitry embedded in the fine dielectric layer. The fine circuitry includes a dimension and a pitch finer than those of the coarse circuitry, and a layout density of the fine circuitry is denser than that of the coarse circuitry.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: January 2, 2024
    Inventor: Dyi-Chung Hu
  • Patent number: 11862481
    Abstract: Chip sealing designs to accommodate die-to-die communication are described. In an embodiment, a chip structure includes a split metallic seal structure including a lower metallic seal and an upper metallic seal with overlapping metallization layers, and a through seal interconnect navigating through the split metallic seal structure.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: January 2, 2024
    Assignee: Apple Inc.
    Inventors: Sanjay Dabral, Chi Nung Ni, Long Huang, SivaChandra Jangam
  • Patent number: 11862605
    Abstract: A package and a method of forming the same are provided. A method includes forming a first die structure. The first die structure includes a die stack and a stacked dummy structure bonded to a carrier. A second die structure is formed. The second die structure includes a first integrated circuit die. The first die structure is bonded to the second die structure by bonding a topmost integrated circuit die of the die stack to the first integrated circuit die. The topmost integrated circuit die of the die stack is a farthest integrated circuit die of the die stack from the carrier. A singulation process is performed on the first die structure to form a plurality of individual die structures. The singulation process singulates the stacked dummy structure into a plurality of individual stacked dummy structures.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Fa Chen, Hsien-Wei Chen, Chen-Hua Yu
  • Patent number: 11855045
    Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Wen Hsiao, Chen-Shien Chen, Wei Sen Chang, Shou-Cheng Hu
  • Patent number: 11855010
    Abstract: A semiconductor structure is provided. The semiconductor structure includes two circuit regions, two inner seal rings, an outer seal ring, a first redundant region, and an electrical circuit. Each of the inner seal rings surrounding one of the circuit regions. The outer seal ring is disposed around the inner seal rings, and each of the inner seal rings contacts the outer seal ring at different interior corners of the outer seal ring. The first redundant region is located between at least one of the inner seal rings and the outer seal ring. The electrical circuit is formed in the first redundant region and electrically connected to at least one of the circuit regions.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shan-Yu Huang, Shih-Chang Chen, Hsiao-Wen Chung, Yilun Chen, Huang-Sheng Lin
  • Patent number: 11854939
    Abstract: Disclosed is a three-dimensional integrated system for DRAM chips and a fabrication method thereof. A plurality of trench structures are etched on the front and back of a silicon wafer; then, a TSV structure is etched between the two upper and lower trenches opposite to each other for electrical connection; then, DRAM chips are placed in the trenches, and copper-copper bonding is used to make the chips electrically connected to the TSV structure in a vertical direction; finally, redistribution is done to make the chips in a horizontal direction electrically connected. The invention can make full use of silicon materials, and can avoid problems such as warpage and deformation of an interposer. In addition, placing the chips in the trenches will not increase the overall package thickness, while protecting the chips from external impact.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: December 26, 2023
    Assignees: Fudan University, Shanghai Integrated Circuit Manufacturing Innovation Center Co., Ltd.
    Inventors: Bao Zhu, Lin Chen, Qingqing Sun, Wei Zhang
  • Patent number: 11855006
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Patent number: 11848237
    Abstract: An electronic component includes a semiconductor device including a semiconductor die including a first surface, the first surface including a first metallization structure and edge regions surrounding the first metallization structure, a second surface opposing the first surface and including a second metallization structure, and side faces extending between the first surface and the second surface, wherein the edge regions of the first surface and portions of the side faces are covered by a first polymer layer, wherein the electronic component further includes a plurality of leads and a plastic housing composition, wherein the first metallization structure is coupled to a first lead and the second metallization structure is coupled to a second lead of the plurality of leads.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: December 19, 2023
    Assignee: Infineon Technologies AG
    Inventors: Paul Ganitzer, Carsten von Koblinski, Thomas Feil, Gerald Lackner, Jochen Mueller, Martin Poelzl, Tobias Polster
  • Patent number: 11842979
    Abstract: The disclosure provides a method of manufacturing a semiconductor device including bonding a second device wafer to a first device wafer, such that a first bonding interface including a dielectric-to-dielectric bonding interface and a metal-to-metal bonding interface is formed between the first device wafer and the second device wafer, wherein the second device wafer is electrically coupled to the first device wafer, and a function of the first device wafer and the second device wafer are the same kind of device wafer. A semiconductor device is also provided.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: December 12, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Yi-Jen Lo, Hsih Yang Chiu, Ching Hung Chang, Chiang-Lin Shih
  • Patent number: 11837581
    Abstract: A semiconductor package includes a package substrate, a lower semiconductor chip on the package substrate, an interposer on the lower semiconductor chip, the interposer including a plurality of pieces spaced apart from each other, an upper semiconductor chip on the interposer, and a molding member covering the lower semiconductor chip and the interposer.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: December 5, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngsang Cho, Heeseok Lee, Yunhyeok Im, Moonseob Jeong
  • Patent number: 11824042
    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: November 21, 2023
    Assignee: Xcelsis Corporation
    Inventors: Javier A. DeLaCruz, Steven L. Teig, Ilyas Mohammed
  • Patent number: 11825639
    Abstract: An example electronic device includes a printed circuit board on which one or more circuit components are disposed, and an interposer surrounding at least some circuit components of the one or more circuit components and including an inner surface adjacent to the at least some circuit components and an outer surface facing away from the inner surface and having a plurality of through holes. The interposer is disposed on the printed circuit board such that one or more through holes of the plurality of through holes are electrically connected with a ground of the printed circuit board.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: November 21, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyelim Yun, Bongkyu Min, Dohoon Kim, Taewoo Kim, Jinyong Park, Jungje Bang, Hyeongju Lee
  • Patent number: 11824028
    Abstract: The present disclosure relates to a die comprising metal pillars extending from a surface of the die, the height of each pillar being substantially equal to or greater than 20 ?m, the pillars being intended to raise the die when fastening the die by means of a bonding material on a surface of a support. The metal pillars being inserted into the bonding material at which point the bonding material is annealed to be cured and hardened solidifying the bonding material to couple the die to the surface of the support.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: November 21, 2023
    Assignee: STMICROELECTRONICS (TOURS) SAS
    Inventors: Olivier Ory, Christophe Lebrere
  • Patent number: 11804424
    Abstract: A semiconductor device includes a carrier, a first external contact, a second external contact, and a semiconductor die. The semiconductor die has a first main face, a second main face opposite to the first main face, a first contact pad disposed on the first main face, a second contact pad disposed on the second main face, a third contact pad disposed on the second main face, and a vertical transistor. The semiconductor die is disposed with the first main face on the carrier. A clip connects the second contact pad to the second external contact. A first bond wire is connected between the third contact pad and the first external contact. The first bond wire is disposed at least partially under the clip.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: October 31, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Chii Shang Hong, Jo Ean Joanna Chye, Teck Sim Lee, Hui Kin Lit, Ke Yan Tean, Lee Shuang Wang, Wei-Shan Wang
  • Patent number: 11804444
    Abstract: A semiconductor package includes; a semiconductor chip including a top surface and an opposing bottom surface, a heat dissipation structure including a lower adhesive layer adhered to the top surface of the semiconductor chip, a heat dissipation layer disposed on the lower adhesive layer, and a conductive layer disposed on the heat dissipation layer, a core layer including a cavity and a lower surface, wherein a combination of the semiconductor chip and the heat dissipation structure is disposed within the cavity, and a bottom re-wiring layer including a bottom re-wiring line connected to the semiconductor chip.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: October 31, 2023
    Inventors: Yongjin Park, Myungsam Kang, Youngchan Ko, Seonho Lee
  • Patent number: 11784163
    Abstract: A package structure includes a plurality of stacked die units and an insulating encapsulant. The plurality of stacked die units is stacked on top of one another, where each of the plurality of stacked die units include a first semiconductor die, a first bonding chip. The first semiconductor die has a plurality of first bonding pads. The first bonding chip is stacked on the first semiconductor die and has a plurality of first bonding structure. The plurality of first bonding structures is bonded to the plurality of first bonding pads through hybrid bonding. The insulating encapsulant is encapsulating the plurality of stacked die units.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: October 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Patent number: 11776926
    Abstract: Systems and methods for semiconductor devices having a substrate with bond pads, a die pair in a stacked configuration above the bond pads and having a first die having an oxide layer, a second die having an oxide layer attached to the first oxide layer, and conductive bonds electrically coupling the dies. Interconnects extend between the bond pads and the die pair, electrically coupling die pair to the substrate. The device may include a second die pair electrically coupled to: (1) the first die pair with secondary interconnects; and (2) the substrate with through-silicon vias extending through the first die pair. The top die of a die pair may be a thick die for use at the top of a pair stack. Pairs may be created by matching dies of a first silicon wafer to dies of a second silicon wafer, combination bonding the wafers, and dicing the die pairs.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: October 3, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Bret K. Street
  • Patent number: 11769754
    Abstract: A manufacturing method for a semiconductor apparatus sequentially includes bonding a first chip and a second chip together using an adhesive. The first chip includes a first electrode and has a protrusion, and the second chip has a recess. In the bonding, the first chip and the second chip are bonded together in such a manner that the protrusion is positioned into the recess. Further, the method includes forming a through hole in the second chip to expose the first electrode, the first surface being opposite to a second surface having the recess, and forming the second electrode which is electrically connected to the first electrode, in the through hole.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: September 26, 2023
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tatsuya Saito, Takayuki Sumida
  • Patent number: 11769712
    Abstract: A semiconductor package structure includes a first electronic component, a conductive element and a first redistribution structure. The first electronic component has a first surface and a second surface opposite to the first surface, and includes a first conductive via. The first conductive via has a first surface exposed from the first surface of the first electronic component. The conductive element is disposed adjacent to the first electronic component. The conductive element has a first surface substantially coplanar with the first surface of the first conductive via of the first electronic component. The first redistribution structure is configured to electrically connect the first conductive via of the first electronic component and the conductive element.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: September 26, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsiao-Yen Lee, Hung-Yi Lin
  • Patent number: 11769724
    Abstract: A package has a first region and a second region surrounded by the first region. The package includes a first die, a second die, an encapsulant, and an inductor. The first die extends from the first region to the second region. The second die is bonded to the first die and is located within a span of the first die. The encapsulant is aside the second die. At least a portion of the encapsulant is located in the second region. The inductor is located in the second region. The inductor laterally has an offset from the second die. A metal density in the first region is greater than a metal density in the second region.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: September 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen, Sen-Bor Jan
  • Patent number: 11769731
    Abstract: A method includes forming a reconstructed wafer, which includes forming a redistribution structure over a carrier, bonding a first plurality of memory dies over the redistribution structure, bonding a plurality of bridge dies over the redistribution structure, and bonding a plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies. Each of the plurality of bridge dies interconnects, and is overlapped by corner regions of, four of the plurality of logic dies. A second plurality of memory dies are bonded over the plurality of logic dies. The plurality of logic dies form a first array, and the second plurality of memory dies form a second array.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: September 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chen-Hua Yu, Chieh-Yen Chen, Chuei-Tang Wang, Chung-Hao Tsai
  • Patent number: 11765838
    Abstract: Electronic modules and methods of fabrication are described. In an embodiment, an electronic module includes a molded system-in-package, and a flexible circuit mounted on a side surface of a molding compound layer such that the flexible circuit is in electrical contact with a lateral interconnect exposed along the side surface of the molding compound layer.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: September 19, 2023
    Assignee: Apple Inc.
    Inventors: Bilal Mohamed Ibrahim Kani, Ali N. Ergun, Kishore N. Renjan, Kyusang Kim, Manoj Vadeentavida, Benjamin J. Grena, David M. Kindlon, Lan H. Hoang
  • Patent number: 11764126
    Abstract: An object of the present invention is to provide a semiconductor device whose surfaces on both sides can be cooled and which has a function of insulating, on both the surfaces, the internal structure of a semiconductor package from the outside. The semiconductor device includes a first semiconductor package and a second semiconductor package. The second semiconductor package is joined on the first semiconductor package in such a manner that a first exposed surface of the first semiconductor package and a fourth exposed surface of the second semiconductor package are connected so as to face each other, and a second exposed surface of the first semiconductor package and a third exposed surface of the second semiconductor package are connected so as to face each other.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: September 19, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hideo Komo, Takeshi Omaru, Takuya Tsuru
  • Patent number: 11764148
    Abstract: A method for forming an integrated circuit device includes providing a first substrate having a first conductive portion, providing a second substrate having a second conductive portion, performing a first chemical reaction to form a first expanding pad on the first conductive portion to provide a first expanded contact area, performing a second chemical reaction to form a second expanding pad on the second conductive portion to provide a second expanded contact area, and bonding the first substrate to the second substrate with a bonding structure.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: September 19, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tzu-Ching Tsai
  • Patent number: 11756901
    Abstract: A structure includes a first die and a second die. The first die includes a first bonding layer having a first plurality of bond pads disposed therein and a first seal ring disposed in the first bonding layer. The first bonding layer extends over the first seal ring. The second die includes a second bonding layer having a second plurality of bond pads disposed therein. The first plurality of bond pads is bonded to the second plurality of bond pads. The first bonding layer is bonded to the second bonding layer. An area interposed between the first seal ring and the second bonding layer is free of bond pads.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: September 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chia Hu, Chun-Chiang Kuo, Sen-Bor Jan, Ming-Fa Chen, Hsien-Wei Chen
  • Patent number: 11749647
    Abstract: A semiconductor device includes a vertical column of wire bonds on substrate contact fingers of the device. Semiconductor dies are mounted on a substrate, and electrically coupled to the substrate such that groups of semiconductor dies may have bond wires extending to the same contact finger on the substrate. By bonding those wires to the contact finger in a vertical column, as opposed to separate, side-by-side wire bonds on the contact finger, an area of the contact finger may be reduced.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: September 5, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Xiaofeng Di, Junrong Yan, CheeKeong Chin, Weili Wang, Xin Lu, Qi Deng, Chaur Yang Ng, Cong Zhang, Chenlin Yang, Chin-Tien Chiu
  • Patent number: 11749645
    Abstract: Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a through-silicon via (TSV) may be disposed through at least one of the microelectronic substrates. The TSV is exposed at the bonding interface of the substrate and functions as a contact surface for direct bonding.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: September 5, 2023
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventors: Guilian Gao, Bongsub Lee, Gaius Gillman Fountain, Jr., Cyprian Emeka Uzoh, Belgacem Haba, Laura Wills Mirkarimi, Rajesh Katkar
  • Patent number: 11749592
    Abstract: A lower semiconductor package of a package-on-package type semiconductor package includes: a package substrate; a semiconductor chip mounted on the package substrate; a chip connecting terminal disposed between the semiconductor chip and the package substrate and configured to connect the semiconductor chip to the package substrate; conductive pillars arranged on the package substrate to at least partially surround the semiconductor chip; and a dam structure configured to cover the conductive pillars on the package substrate and having a first opening at least partially surrounding the semiconductor chip.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: September 5, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Donguk Kwon, Jiwon Shin, Kwangbok Woo, Minseung Ji
  • Patent number: 11749668
    Abstract: A semiconductor device is formed by providing a semiconductor package including a shielding layer and forming a slot in the shielding layer using a laser. The laser is turned on and exposed to the shielding layer with a center of the laser disposed over a first point of the shielding layer. The laser is moved in a loop while the laser remains on and exposed to the shielding layer. Exposure of the laser to the shielding layer is stopped when the center of the laser is disposed over a second point of the shielding layer. A distance between the first point and the second point is approximately equal to a radius of the laser.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: September 5, 2023
    Assignee: STATS ChipPAC Pte. Ltd
    Inventors: ChangOh Kim, JinHee Jung
  • Patent number: 11749665
    Abstract: Semiconductor device assemblies can include a substrate having a substrate contact. The assemblies can include a first semiconductor device and a second semiconductor device arranged in a face-to-face configuration. The assemblies can include a fan-out porch on the substrate at a lateral side of the first semiconductor device and including a wirebond contact, the wirebond contact being electrically coupled to the first semiconductor device. The assemblies can include a wirebond operably coupling the wirebond contact to the substrate contact. The assemblies can include a pillar or bump operably coupling the active side of the first semiconductor device to the active side of the second semiconductor device. In some embodiments, the wirebond contact is operably couple to the active side of the first semiconductor device.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: September 5, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Jong Sik Paek, Yeongbeom Ko
  • Patent number: 11742323
    Abstract: A semiconductor structure includes a first semiconductor package, a second semiconductor package, a heat spreader and an underfill layer. The first semiconductor package includes a plurality of lower semiconductor chips and a first dielectric encapsulation layer disposed around the plurality of the lower semiconductor chips. The second semiconductor package is disposed over and corresponds to one of the plurality of lower semiconductor chips, wherein the second semiconductor package includes a plurality of upper semiconductor chips and a second dielectric encapsulation layer disposed around the plurality of upper semiconductor chips. The heat spreader is disposed over and corresponds to another of the plurality of lower semiconductor chips. The underfill layer is disposed over the first semiconductor package and around the second semiconductor package and the heat spreader.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: August 29, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Pan, Pu Wang, Li-Hui Cheng, An-Jhih Su, Szu-Wei Lu
  • Patent number: 11728217
    Abstract: An embodiment is a package including a first package component. The first package component including a first die attached to a first side of a first interconnect structure, a molding material surrounding the first die, and a second interconnect structure over the molding material and the first die, a first side of the second interconnect structure coupled to the first die with first electrical connectors. The first package component further includes a plurality of through molding vias (TMVs) extending through the molding material, the plurality of TMVs coupling the first interconnect structure to the second interconnect structure, and a second die attached to a second side of the second interconnect structure with second electrical connectors, the second side of the second interconnect structure being opposite the first side of the second interconnect structure.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Mirng-Ji Lii, Chien-Hsun Lee, Jiun Yi Wu
  • Patent number: 11728315
    Abstract: Semiconductor die assemblies including stacked semiconductor dies having parallel plate capacitors formed between adjacent pairs of semiconductor dies in the stack, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die and a second semiconductor die stacked over the first semiconductor die. The first semiconductor die includes an upper surface having a first capacitor plate formed thereon, and the second semiconductor die includes a lower surface facing the upper surface of the first semiconductor die and having a second capacitor plate formed thereon. A dielectric material is formed at least partially between the first and second capacitor plates. The first capacitor plate, second capacitor plate, and dielectric material together form a capacitor that stores charge locally within the stack, and that can be accessed by the first and/or second semiconductor dies.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: August 15, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Anthony D. Veches
  • Patent number: 11715929
    Abstract: Embodiments of the present disclosure include method for sequentially mounting multiple semiconductor devices onto a substrate having a composite metal structure on both the semiconductor devices and the substrate for improved process tolerance and reduced device distances without thermal interference. The mounting process causes “selective” intermixing between the metal layers on the devices and the substrate and increases the melting point of the resulting alloy materials.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: August 1, 2023
    Assignee: Aeva, Inc.
    Inventors: Zhizhong Tang, Pradeep Srinivasan, Kevin Masuda, Wenjing Liang
  • Patent number: 11715697
    Abstract: A semiconductor package may include a lower package including a first substrate, a first semiconductor chip on the first substrate, and a first molding portion on the first substrate to cover the first semiconductor chip, an interposer substrate on the first semiconductor chip, a supporting portion between the interposer substrate and the first substrate to support the interposer substrate, a connection terminal connecting the interposer substrate to the first substrate, and an upper package on the interposer substrate. The upper package may include a second substrate, a second semiconductor chip on the second substrate, and a second molding portion on the second substrate to cover the second semiconductor chip.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: August 1, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sungbum Kim, Taewoo Kang, Jaewon Choi
  • Patent number: 11710717
    Abstract: A method includes providing a structure including a carrier wafer, and a first device wafer with an adhesion layer between the carrier wafer and the first device wafer; and forming a plurality of first ablation structures in the structure, each of the plurality of first ablation structures extending through the first device wafer, the adhesion layer and a portion of the carrier wafer. Each of the plurality of first ablation structures has a portion inside the carrier wafer with a depth no greater than one half of a thickness of the carrier wafer. The first device wafer includes a plurality of first dies, each pair of adjacent first dies being separated by one of the plurality of first ablation structures. The plurality of first ablation structures are formed by either laser grooving or mechanical sawing.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: July 25, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Jialan He
  • Patent number: 11705399
    Abstract: There is provided a terminal that includes a first conductive layer; a wiring layer on the first conductive layer; a second conductive layer on the wiring layer; and a conductive bonding layer which is in contact with a bottom surface and a side surface of the first conductive layer, a side surface of the wiring layer, a portion of a side surface of the second conductive layer, and a portion of a bottom surface of the second conductive layer, wherein an end portion of the second conductive layer protrudes from an end portion of the first conductive layer and an end portion of the wiring layer, and wherein the conductive bonding layer is in contact with a bottom surface of the end portion of the second conductive layer.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: July 18, 2023
    Assignee: ROHM CO., LTD.
    Inventors: Hideaki Yanagida, Yoshihisa Takada
  • Patent number: 11694950
    Abstract: A semiconductor package has a substrate, a chip and an encapsulation. The substrate has a dielectric layer, a copper wiring layer and a solder resist layer formed thereon. The copper wiring layer is formed on the dielectric layer and is covered by the solder resist layer. The solder resist layer has a chip area defined thereon and an annular opening formed thereon. The annular opening surrounds the chip area and exposes part of the copper wiring layer. The chip is mounted on the chip area and is encapsulated by the encapsulation. Therefore, the semiconductor package with the annular opening makes the solder resist layer discontinuous, and the concentration stress is decreased to avoid a crack formed on the solder resist layer or the copper wiring layer when doing thermal-cycle test.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: July 4, 2023
    Assignee: Powertech Technology Inc.
    Inventors: Chih-Yen Su, Chun-Te Lin
  • Patent number: 11694949
    Abstract: A semiconductor package includes a package substrate, an interposer on the package substrate, and a first semiconductor device and a second semiconductor device on the interposer, the first and second semiconductor devices connected to each other by the interposer, wherein at least one of the first semiconductor device and the second semiconductor device includes an overhang portion protruding from a sidewall of the interposer.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: July 4, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yun-Seok Choi
  • Patent number: 11682600
    Abstract: An arrangement includes a panel configured as a pre-form for manufacturing a plurality of component carriers; a protection layer covering a surface portion of a main surface of the panel, wherein the protection layer is detachable from the surface portion without leaving residues on the panel. A handling tool for handling the panel includes a surface onto which the panel is arrangeable. The panel includes a handling surface, with which the panel is arrangeable onto the handling tool, wherein the handling surface comprises at least part of the surface portion covered by the protection layer.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: June 20, 2023
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Markus Leitgeb, Marco Gavagnin, Heinz Habenbacher
  • Patent number: 11664352
    Abstract: A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: May 30, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Hwan Hwang, Sang-Sick Park, Tae-Hong Min, Geol Nam
  • Patent number: 11664350
    Abstract: A structure includes core substrates attached to a first side of a redistribution structure, wherein the redistribution structure includes first conductive features and first dielectric layers, wherein each core substrate includes conductive pillars, wherein the conductive pillars of the core substrates physically and electrically contact first conductive features; an encapsulant extending over the first side of the redistribution structure, wherein the encapsulant extends along sidewalls of each core substrate; and an integrated device package connected to a second side of the redistribution structure.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiun Yi Wu, Chen-Hua Yu, Chung-Shi Liu
  • Patent number: 11658107
    Abstract: A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: May 23, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji Hwang Kim, Hyunkyu Kim, Jongbo Shim, Eunhee Jung, Kyoungsei Choi
  • Patent number: 11646255
    Abstract: A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: May 9, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo Lung Pan, Yu-Chia Lai, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu, Po-Yuan Teng, Teng-Yuan Lo, Mao-Yen Chang