Stacked Array (e.g., Rectifier, Etc.) Patents (Class 438/109)
  • Patent number: 11450583
    Abstract: Provided is a stacked semiconductor package including a package base substrate including a plurality of signal wires and at least one power wire, wherein a plurality of top downsurface connecting pads and a plurality of bottom surface connecting pads are on a top surface and a bottom surface of the package base substrate, respectively; and a plurality of semiconductor chips that are sequentially stacked on the package base substrate and are electrically connected to the top surface connecting pads, the plurality of semiconductor chips including a first semiconductor chip that is a bottommost semiconductor chip, and a second semiconductor chip that is on the first semiconductor chip, wherein the signal wires are arranged apart from a portion of the package base substrate, the first portion that overlaps a first edge of the first semiconductor chip, the first edge overlapping the second semiconductor chip in a vertical direction.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: September 20, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Keun-Ho Choi
  • Patent number: 11444052
    Abstract: A semiconductor package includes a package substrate including: first and second bond finger arrays, each of the first and second finger arrays arranged in a first direction on a surface of the package substrate; a first semiconductor chip disposed on the surface of the package substrate and including a first chip pad array corresponding to the first bond finger array; a second semiconductor chip disposed on the surface of the package substrate and including a second chip pad array corresponding to the second bond finger array; first bonding wires connecting bond fingers of the first bond finger array to chip pads of the first chip pad array; and second bonding wires connecting bond fingers of the second bond finger array to chip pads of the second chip pad array.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: September 13, 2022
    Assignee: SK hynix Inc.
    Inventor: Jong Hui Kim
  • Patent number: 11437326
    Abstract: A semiconductor package includes a first substrate, a second substrate provided on the first substrate, a semiconductor chip provided between the first substrate and the second substrate, solder structures extending between the first substrate and the second substrate and spaced apart from the semiconductor chip, and bumps provided between the semiconductor chip and the second substrate. The solder structures electrically connect the first substrate and the second substrate.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: September 6, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Juhyeon Oh, Sunchul Kim, Hyunki Kim
  • Patent number: 11437422
    Abstract: A hybrid bonded structure including a first integrated circuit component and a second integrated circuit component is provided. The first integrated circuit component includes a first dielectric layer, first conductors and isolation structures. The first conductors and the isolation structures are embedded in the first dielectric layer. The isolation structures are electrically insulated from the first conductors and surround the first conductors. The second integrated circuit component includes a second dielectric layer and second conductors. The second conductors are embedded in the second dielectric layer. The first dielectric layer is bonded to the second dielectric layer and the first conductors are bonded to the second conductors.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: September 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Bo-Tsung Tsai
  • Patent number: 11430824
    Abstract: An integrated circuit (IC) device includes a first substrate and a first structure on a front surface of the first substrate. The first structure includes a first interlayer insulating layer structure including a plurality of first conductive pad layers spaced apart from one another at different levels of the first interlayer insulating layer structure. The IC device includes a second substrate on the first substrate and a second structure on a front surface of the second substrate, which faces the front surface of the first substrate. The second structure includes a second interlayer insulating layer structure bonded to the first interlayer insulating layer structure. A through-silicon via (TSV) structure penetrates the second substrate and the second interlayer insulating layer structure. The TSV structure is in contact with at least two first conductive pad layers of the plurality of first conductive pad layers located at different levels.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: August 30, 2022
    Inventors: Sun-hyun Kim, Sang-il Jung, Byung-jun Park
  • Patent number: 11424172
    Abstract: A semiconductor package includes: a first semiconductor chip including a first surface and a second surface opposite to each other and including first through electrodes; at least a second semiconductor chip stacked on the first surface of the first semiconductor chip and comprising second through electrodes electrically connected to the first through electrodes; and a molding layer contacting the first surface of the first semiconductor chip and a side wall of the at least one second semiconductor chip and including a first external side wall connected to and on the same plane as a side wall of the first semiconductor chip, wherein the first external side wall of the molding layer extends to be inclined with respect to a first direction orthogonal to the first surface of the first semiconductor chip, and both the external first side wall of the molding layer and the side wall of the first semiconductor chip have a first slope that is the same for both the first external side wall of the molding layer and the
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: August 23, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yeongkwon Ko, Seunghun Shin, Junyeong Heo
  • Patent number: 11424190
    Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a dielectric body, a plurality of semiconductor bodies separated by the dielectric body, a through via penetrating through the dielectric body, and a wiring structure located in each of the plurality of semiconductor bodies; a plurality of semiconductor chips located side by side on a first surface of the interposer and electrically connected to the wiring structure; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface of the interposer and electrically connected to the plurality of semiconductor chips through the through via.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: August 23, 2022
    Assignee: Industrial Technology Research Institute
    Inventors: Chao-Jung Chen, Yu-Min Lin, Sheng-Tsai Wu, Shin-Yi Huang, Ang-Ying Lin, Tzu-Hsuan Ni, Yuan-Yin Lo
  • Patent number: 11410962
    Abstract: A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: August 9, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Wei Zhou, Bret K. Street, Benjamin L. McClain, Mark E. Tuttle
  • Patent number: 11410963
    Abstract: A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: August 9, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Wei Zhou, Bret K. Street, Benjamin L. McClain, Mark E. Tuttle
  • Patent number: 11367737
    Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a method for forming a 3D memory device is disclosed. A first semiconductor device is formed on a first substrate. A first single-crystal silicon layer is transferred from a second substrate onto the first semiconductor device on the first substrate. A dielectric stack including interleaved sacrificial layers and dielectric layers is formed on the first single-crystal silicon layer. A channel structure extending vertically through the dielectric stack is formed. The channel structure includes a lower plug extending into the first single-crystal silicon layer and including single-crystal silicon. A memory stack including interleaved conductor layers and the dielectric layers is formed by replacing the sacrificial layers in the dielectric stack with the conductor layers.
    Type: Grant
    Filed: November 21, 2020
    Date of Patent: June 21, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Li Hong Xiao
  • Patent number: 11322472
    Abstract: Provided is a module which has a package-on-package structure including a redistribution layer and can be easily reduced in height. A module 1 includes an upper module including a substrate, a first component, and a sealing resin layer, and a lower module including an intermediate layer and a redistribution layer. The first component is connected to the redistribution layer with a columnar conductor interposed therebetween and provided in the intermediate layer, and both the first component and a second component are rewired by the redistribution layer. Since the intermediate layer is formed by using a frame-shaped substrate, the upper module and the lower module can be connected without necessarily a bump, so that it is possible to provide a module which has a fanout-type package-on-package structure and can be easily reduced in height.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: May 3, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshihito Otsubo, Yukio Yamamoto
  • Patent number: 11296063
    Abstract: Disclosed is an LED display panel including inner LED display modules and outer LED display modules. Each of the inner LED display modules and the outer LED display modules includes a first flexible circuit board and a second flexible circuit board arrayed in a row in the lengthwise direction and on which LEDs are arrayed, and an upper viscoelastic film and a lower viscoelastic film bonded to each other through the first flexible circuit board and the second flexible circuit board. Each of the first flexible circuit board and the second flexible circuit board includes a folded edge portion and an unfolded edge portion opposite to the folded edge portion. A controller unit is disposed under the folded edge portion to control the LEDs. The folded edge portion of the first flexible circuit board faces the folded edge portion of the second flexible circuit board in each of the inner LED display modules.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: April 5, 2022
    Assignee: LUMENS CO., LTD.
    Inventors: Taekyung Yoo, Bogyun Kim, Minpyo Kim, Jugyeong Mun
  • Patent number: 11289467
    Abstract: A memory device includes a memory cell array, a row decoder connected to the memory cell array by a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines, and a common source line driver connected to the memory cell array by a common source line. The memory cell array is located in an upper chip, at least a portion of the row decoder is located in a lower chip, at least a portion of the common source line driver is located in the upper chip, and a plurality of upper bonding pads of the upper chip are connected to a plurality of lower bonding pads of the lower chip to connect the upper chip to the lower chip.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: March 29, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Taehong Kwon, Youngsun Min, Daeseok Byeon, Kyunghwa Yun
  • Patent number: 11270960
    Abstract: A radio-frequency module includes a radio-frequency integrated circuit (RFIC) including a base connection terminal, and a first radio-frequency (RF) connection terminal; a first connection member including a mounting area on which the RFIC is mounted, a base wiring electrically connected to the base connection terminal of the RFIC, and a first RF wiring electrically connected to the first RF connection terminal of the RFIC; a second connection member including a second RF wiring electrically connected to the first RF wiring of the first connection member, and a third RF wiring, at least a portion of the second connection member being more flexible than the first connection member; and a front-end integrated circuit (FEIC) mounted on the second connection member and configured to amplify the first RF signal to generate the first communications signal or amplify the first communications signal to generate the first RF signal.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: March 8, 2022
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Doo Il Kim, Bang Chul Ko, Sung Youl Choi
  • Patent number: 11270923
    Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip which are disposed side-by-side on a surface of a package substrate. A heat insulation wall is disposed between the first semiconductor chip and the second semiconductor chip. The heat insulation wall thermally isolates the first semiconductor chip from the second semiconductor chip.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: March 8, 2022
    Assignee: SK hynix Inc.
    Inventors: Min Kyu Kang, Jae Hyun Son, Ji Hyeok Shin
  • Patent number: 11257784
    Abstract: A semiconductor package includes a package substrate, a logic chip on an upper surface of the package substrate and electrically connected to the package substrate, a heat sink contacting an upper surface of the logic chip to dissipate a heat generating from the logic chip, and a memory chip disposed on an upper surface of the heat sink and electrically connected to the package substrate.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: February 22, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Bongken Yu
  • Patent number: 11222880
    Abstract: A package structure for a semiconductor device includes a first conductive layer, a second conductive layer, a first die, a second die, a plurality of first blind via pillars and a conductive structure. The first conductive layer has a first surface and a second surface. The first die and the second die respectively have an active surface and a back surface, which are disposed opposite to each other. There is a plurality of metal pads disposed on the active surface. The first die is attached to the first surface of the first conductive layer with its back surface, and the second die is attached to the second surface of the first conductive layer with its back surface. The first and second conductive layers, the first and second dies, the first blind hole pillars and conductive structure are covered by a dielectric material.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: January 11, 2022
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Che-Wei Hsu, Shih-Ping Hsu
  • Patent number: 11211520
    Abstract: Embodiments are related to systems and methods for fluidic assembly, and more particularly to systems and methods for increasing the efficiency of fluidic assembly.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: December 28, 2021
    Assignee: eLux Inc.
    Inventor: Po Ki Yuen
  • Patent number: 11195726
    Abstract: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide a method for manufacturing a semiconductor device, and a semiconductor device produced thereby, that comprises an interposer without through silicon vias.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: December 7, 2021
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Dong Jin Kim, Jin Han Kim, Won Chul Do, Jae Hun Bae, Won Myoung Ki, Dong Hoon Han, Do Hyung Kim, Ji Hun Lee, Jun Hwan Park, Seung Nam Son, Hyun Cho, Curtis Zwenger
  • Patent number: 11183479
    Abstract: In a method for manufacturing a semiconductor device, a plurality of first provisional fixing portions are supplied on a front surface of a substrate such that the plurality of first provisional fixing portions are spaced from each other and thus dispersed. A first solder layer processed into a plate to be a first soldering portion is disposed in contact with the plurality of first provisional fixing portions. A semiconductor chip is disposed on the first solder layer. In addition a conductive member in the form of a flat plate is disposed thereon via a second provisional fixing portion and a second solder layer. A reflow process is performed to solder the substrate, the semiconductor chip and the conductive member together.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: November 23, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Shohei Ogawa, Junji Fujino, Isao Oshima, Satoru Ishikawa, Takumi Shigemoto
  • Patent number: 11177237
    Abstract: A manufacturing method for semiconductor packages is provided. Chips are provided on a carrier. Through interlayer vias are formed over the carrier to surround the chips. A molding compound is formed over the carrier to partially and laterally encapsulate the chip and the through interlayer vias. The molding compound comprises pits on a top surface thereof. A polymeric molding compound is formed on the molding compound to fill the pits of the molding compound.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Ching-Hua Hsieh, Chung-Shi Liu, Chih-Wei Lin
  • Patent number: 11172600
    Abstract: A semiconductor mounting device for mounting chip components on a substrate, wherein the device is reduced in size. A semiconductor mounting device 10 comprises: a temporary placement stage 12 on which are loaded a plurality of chip components 30a, 30b, 30c; a conveyance head 14 that conveys the chip components 30a, 30b, 30c to the temporary placement stage 12, and also loads each of the chip components 30a, 30b, 30c on the temporary placement stage 12 so that the relative positions of the plurality of chip components 30a, 30b, 30c reach predetermined positions; a mounting stage 16 that secures a substrate 36 by suction; and a mounting head 18 that suctions the plurality of chip components 30a, 30b, 30c loaded on the temporary placement stage 12, and pressurizes while keeping the relative positions at prescribed positions on the substrate 36 that is secured by suction to the mounting stage 16.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: November 9, 2021
    Assignee: SHINKAWA LTD.
    Inventors: Tomonori Nakamura, Toru Maeda
  • Patent number: 11164848
    Abstract: A semiconductor structure includes a stacked structure. The stacked structure includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first semiconductor substrate having a first active surface and a first back surface opposite to the first active surface. The second semiconductor die is over the first semiconductor die, and includes a second semiconductor substrate having a second active surface and a second back surface opposite to the second active surface. The second semiconductor die is bonded to the first semiconductor die through joining the second active surface to the first back surface at a first hybrid bonding interface along a vertical direction. Along a lateral direction, a first dimension of the first semiconductor die is greater than a second dimension of the second semiconductor die.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: November 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Chao-Wen Shih, Min-Chien Hsiao, Sung-Feng Yeh, Tzuan-Horng Liu, Chuan-An Cheng
  • Patent number: 11164824
    Abstract: A package structure includes a circuit substrate and a semiconductor package. The semiconductor package is disposed on the circuit substrate, and includes a plurality of semiconductor dies, an insulating encapsulant and a connection structure. The insulating encapsulant comprises a first portion and a second portion protruding from the first portion, the first portion is encapsulating the plurality of semiconductor dies and has a planar first surface, and the second portion has a planar second surface located at a different level than the planar first surface. The connection structure is located over the first portion of the insulating encapsulant on the planar first surface, and located on the plurality of semiconductor dies, wherein the connection structure is electrically connected to the plurality of semiconductor dies and the circuit substrate.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: November 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Kung-Chen Yeh, Li-Chung Kuo, Szu-Wei Lu, Ying-Ching Shih
  • Patent number: 11158603
    Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first semiconductor structure and a second semiconductor structure that are on the first semiconductor chip and spaced apart from each other across the second semiconductor chip, and a resin-containing member between the second semiconductor chip and the first semiconductor structure and between the second semiconductor chip and the second semiconductor structure. The semiconductor package may be fabricated at a wafer level.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: October 26, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyoeun Kim, Ji Hwang Kim, Jisun Yang, Seunghoon Yeon, Chajea Jo, Sang-Uk Han
  • Patent number: 11145633
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die an insulating encapsulation laterally covering the semiconductor die. The semiconductor die includes a semiconductor substrate, a plurality of conductive pads distributed over the semiconductor substrate, a plurality of conductive vias disposed on and electrically connected to the conductive pads, and a dielectric layer disposed over the semiconductor substrate and spaced the conductive vias apart from one another. A sidewall of the dielectric layer extends along sidewalls of the conductive vias, the conductive vias are recessed from a top surface of the dielectric layer, and a sloped surface of the dielectric layer is connected to the top surface of the dielectric layer and the sidewall of the dielectric layer.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, An-Jhih Su, Li-Hsien Huang, Tien-Chung Yang, Ming-Shih Yeh
  • Patent number: 11139275
    Abstract: According to one embodiment, a semiconductor device includes a wiring board having a first surface. A first element is disposed on the first surface of the wiring board. A first resin layer covers the first element. A second element is larger than the first element and disposed on the first resin layer. The second element is superposed above the first element. A reinforcement member is disposed at a peripheral portion of the first resin layer and includes an edge disposed inside of the first resin layer. The reinforcement member has an upper surface above the first surface of the wiring board. The reinforcement member has a coefficient of linear expansion lower than the first resin layer. An encapsulating resin material, over the first surface of the wiring board, covers the first element, the second element, the first resin layer, and the reinforcement member.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: October 5, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Satoru Takaku
  • Patent number: 11127665
    Abstract: A module assembly includes an adapter substrate with at least one cavity and a surface mounted die mounted on a top surface of the adapter substrate. The first cavity extends through the adapter substrate and has at least one first side wall. A first metallization layer is provided within the cavity. A first recessed die is attached to the first metallization layer and mounted within the cavity such that the first recessed die is at least partially recessed into the first cavity and surrounded by a gap filler that resides between side portions of the first recessed die and the at least one first side wall. The top surface of the gap filler is flush with the top surface of the adapter substrate and a top surface of the first recessed die.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: September 21, 2021
    Assignee: Qorvo US, Inc.
    Inventor: Deep C. Dumka
  • Patent number: 11121127
    Abstract: An integrated circuit chip includes a circuit structure, a grounding structure, a bonding layer between the circuit structure and the grounding structure. The circuit structure includes a first substrate, an FEOL structure, and a BEOL structure. The grounding structure includes a second substrate and a grounding conductive layer. The integrated circuit chip includes a first penetrating electrode portion connected to the grounding conductive layer based on extending through the first substrate, the FEOL structure, the BEOL structure, and the bonding layer such that the first penetrating electrode portion is isolated from direct contact with the integrated circuit portion in a horizontal direction extending parallel to an active surface of the first substrate. An integrated circuit package and a display device each include the integrated circuit chip.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: September 14, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-gu Kang, Young-mok Kim, Woon-bae Kim, Dae-cheol Seong, Yune-seok Chung
  • Patent number: 11114415
    Abstract: A semiconductor device includes a first die; a second die attached over the first die; a metal enclosure directly contacting and extending between the first die and the second die, wherein the first metal enclosure is continuous and encircles a set of one or more internal interconnects, wherein the first metal enclosure is configured to electrically connect to a first voltage level; and a second metal enclosure directly contacting and extending between the first die and the second die, wherein the second metal enclosure is continuous and encircles the first metal enclosure and is configured to electrically connect to a second voltage level; wherein the first metal enclosure and the second metal enclosure are configured to provide an enclosure capacitance encircling the set of one or more internal interconnects for shielding signals on the set of one or more internal interconnects.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: September 7, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Wei Zhou, Bret K. Street
  • Patent number: 11114413
    Abstract: A package structure includes a plurality of stacked die units and an insulating encapsulant. The plurality of stacked die units is stacked on top of one another, where each of the plurality of stacked die units include a first semiconductor die, a first bonding chip. The first semiconductor die has a plurality of first bonding pads. The first bonding chip is stacked on the first semiconductor die and has a plurality of first bonding structure. The plurality of first bonding structures is bonded to the plurality of first bonding pads through hybrid bonding. The insulating encapsulant is encapsulating the plurality of stacked die units.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: September 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Patent number: 11081427
    Abstract: A semiconductor device includes at least one wafer and at least one TSV (through silicon via) structure. The at least one wafer each includes a substrate, an isolation structure, and a conductive pad. The isolation structure is formed in the substrate and extends from a first side of the substrate toward a second side opposite to the first side of the substrate. The conductive pad is formed at a dielectric layer disposed on the first side of the substrate, wherein the conductive pad is electrically connected to an active area in the substrate. The at least one TSV structure penetrates the at least one wafer. The conductive pad contacts a sidewall of the at least one TSV structure, and electrically connects the at least one TSV structure and the active area in the substrate. The isolation structure separates from and surrounds the at least one TSV structure.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: August 3, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhao-Bing Li, Ju-Bao Zhang, Chi Ren
  • Patent number: 11075184
    Abstract: A semiconductor package has at least one die, a first redistribution layer and a second redistribution layer. The first redistribution layer includes a first dual damascene redistribution pattern having a first via portion and a first routing portion. The second redistribution layer is disposed on the first redistribution layer and over the first die and electrically connected with the first redistribution layer and the first die. The second redistribution layer includes a second dual damascene redistribution pattern having a second via portion and a second routing portion. A location of the second via portion is aligned with a location of first via portion.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Chun-Hui Yu
  • Patent number: 11069658
    Abstract: An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Feng Yeh, Chen-Hua Yu, Ming-Fa Chen
  • Patent number: 11069651
    Abstract: A method of mounting a die includes: preparing a die having a bump formation surface on which a plurality of bump electrodes are formed; disposing a vacuum suction tool having a suction surface above the die such that the suction surface faces toward the bump formation surface; sandwiching a porous sheet between the suction surface and the bump formation surface and suctioning the die by the vacuum suction tool; and mounting the die that has been suctioned by the vacuum suction tool in a bonding region of a substrate with an adhesive material interposed therebetween, the porous sheet having a thickness equal to or greater than the protrusion height of the bump electrodes on the bump formation surface. Stabilization and ease of maintenance of vacuum suction can thereby be improved.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: July 20, 2021
    Assignees: SHINKAWA LTD., VALQUA, LTD.
    Inventors: Osamu Watanabe, Tomonori Nakamura, Yoshihito Hagiwara, Yuji Kanai
  • Patent number: 11043446
    Abstract: A semiconductor package includes a connection structure including a first insulating layer, a first redistribution layer disposed on the first insulating layer, and a first connection via penetrating through the first insulating layer and connected to the first redistribution layer, a semiconductor chip disposed on the connection structure, an encapsulant covering at least a portion of the semiconductor chip, a second insulating layer disposed on the encapsulant, a second redistribution layer including a signal line disposed on the encapsulant, and a heat dissipation layer disposed on the encapsulant and electrically insulated from the signal line.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: June 22, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jungsoo Park, Kyoungmoo Harr, Jihyun Lee, Doohwan Lee, Junggon Choi
  • Patent number: 11040870
    Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a dielectric structure disposed over a first semiconductor substrate, where the dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the dielectric structure. The second semiconductor substrate includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. An anti-stiction structure is disposed between the movable mass and the dielectric structure, where the anti-stiction structure is a first silicon-based semiconductor.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: June 22, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuei-Sung Chang, Chun-Wen Cheng, Fei-Lung Lai, Shing-Chyang Pan, Yuan-Chih Hsieh, Yi-Ren Wang
  • Patent number: 11037879
    Abstract: According to one embodiment, a semiconductor device includes a wiring board, a spacer board that is mounted on the wiring board and in which a power supply conductor layer and a ground conductor layer are provided, at least one first semiconductor chip that is mounted on the spacer board including a power supply layer electrically connected to the power supply conductor layer and a ground layer electrically connected to the ground conductor layer, and a second semiconductor chip that is mounted on the wiring board.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: June 15, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yasuo Otsuka
  • Patent number: 10978424
    Abstract: A semiconductor device including a first integrated circuit component, a second integrated circuit component, a third integrated circuit component and a dielectric encapsulation is provided. The second integrated circuit component is stacked on and electrically connected to the first integrated circuit component. The third integrated circuit component is stacked on and electrically connected to the second integrated circuit component. The dielectric encapsulation laterally encapsulates the second integrated circuit component or the third integrated circuit component. In addition, manufacturing methods of the above-mentioned semiconductor device are provided.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou
  • Patent number: 10971479
    Abstract: A semiconductor package includes: a substrate; a first interposer disposed over the substrate; a first chip stack disposed on the substrate on one side of the first interposer, wherein the first chip stack includes a plurality of first semiconductor chips stacked with an offset in a first direction; a second chip stack disposed on the first chip stack, wherein the second chip stack includes a plurality of second semiconductor chips stacked with an offset in a second direction opposite to the first direction; and a third chip stack disposed on the substrate on an other side of the first interposer, wherein the third chip stack includes a plurality of third semiconductor chips stacked with an offset in the second direction.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: April 6, 2021
    Assignee: SK hynix Inc.
    Inventor: Suk-Won Lee
  • Patent number: 10957625
    Abstract: Semiconductor devices having one or more vias filled with an electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate having a first side, a plurality of circuit elements proximate to the first side, and a second side opposite the first side. A via can extend between the first and second sides, and a conductive material in the via can extend beyond the second side of the substrate to define a projecting portion of the conductive material. The semiconductor device can have a tall conductive pillar formed over the second side and surrounding the projecting portion of the conductive material, and a short conductive pad formed over the first side and electrically coupled to the conductive material in the via.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Anilkumar Chandolu, Wayne H. Huang, Sameer S. Vadhavkar
  • Patent number: 10943897
    Abstract: A method (of forming an integrated circuit) includes: forming a first diode on a first substrate of two or more stacked substrates, the first substrate having a first predetermined doping type; forming a second diode on a second substrate of the two or more stacked substrates, the second substrate being formed on the first substrate, and the second substrate having the first predetermined doping type; and forming conductive paths electrically connecting the first diode 3A and the second diode between a circuit and a first common ground rail, the first diode and the second diode being connected in parallel and having opposite polarities.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: March 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei Yu Ma, Chia-Hui Chen, Kuo-Ji Chen
  • Patent number: 10903200
    Abstract: A semiconductor device manufacturing method includes stacking a second semiconductor chip on a first surface of a first semiconductor chip such that the at bump electrode overlies the position of a first through silicon via in the first semiconductor chip, stacking a third semiconductor chip on the second semiconductor chip such that a second bump electrode on the second semiconductor chip overlies the position of a second through silicon via in the third semiconductor chip to form a chip stacked body, connecting the first and second bump electrodes of the chip stacked body to the first and the second through silicon vias by reflowing the bump material, placing the chip stacked body on the first substrate such that the first surface of the first semiconductor chip faces the second surface, and sealing the second surface and the first, second, and third semiconductor chips with a filling resin.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: January 26, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuji Karakane, Masatoshi Fukuda, Soichi Homma, Naoyuki Komuta, Yukifumi Oyama
  • Patent number: 10879260
    Abstract: A bonded assembly includes a first memory die containing a first three-dimensional memory device, a second memory die containing a second three-dimensional memory device, and a support die bonded to the first memory die and comprising a peripheral circuitry configured to control the first three-dimensional memory device and the second three-dimensional memory device. The first memory die includes multiple rows of first-die proximal bonding pads, multiple rows of first-die distal bonding pads, and a plurality of first-die laterally-shifting electrically conductive paths connecting a respective one of the first-die proximal bonding pads and a respective one of the first-die distal bonding pads that is laterally offset from the respective one of the first-die proximal bonding pads. The first memory die and the second memory die can have an identical layout, and electrical connections can be shifted through the first memory die by the offset distance.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: December 29, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Tatsuya Uryu, Satoshi Shimizu, Nobuyuki Fujimura
  • Patent number: 10872866
    Abstract: A semiconductor package including a substrate having a surface, and a conductive element on the first surface and electrically coupled to the substrate. The conductive element has a principal axis forming an angle less than 90 degrees with the surface.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: December 22, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Jenchun Chen
  • Patent number: 10867956
    Abstract: A method for manufacturing a semiconductor device, for example formed utilizing component stacking. As non-limiting examples, various aspects of this disclosure provide a method for reducing warpage and/or stress in stacked semiconductor devices.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: December 15, 2020
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Won Chul Do, Jin Hee Park
  • Patent number: 10851269
    Abstract: A pressure-sensitive adhesive composition, which may have excellent durability under high temperature or humidity conditions and exhibit high close adhesion to optical films, thereby forming a pressure-sensitive adhesive having superior cuttability and re-workability, is provided. Also, a pressure-sensitive adhesive composition capable of forming a pressure-sensitive adhesive capable of effectively inhibiting bending when applied to a thin substrate such as a very thin glass substrate, minimizing a time required to stabilize physical properties, and preventing a degradation of the secured physical properties in time, a pressure-sensitive adhesive optical member formed using such a pressure-sensitive adhesive composition, an optical laminate, and a display device are provided.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: December 1, 2020
    Inventors: Kee Young Kim, Il Jin Kim, Jeong Ae Yoon, Sung Soo Yoon, Su Jeong Kim, Sang Hyun Hong
  • Patent number: 10854565
    Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure and a first chip structure over the redistribution structure. The chip package structure also includes a first solder bump between the redistribution structure and the first chip structure and a first molding layer surrounding the first chip structure. The chip package structure further includes a second chip structure over the first chip structure and a second molding layer surrounding the second chip structure. In addition, the chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump. A portion of the third molding layer is between the first molding layer and the redistribution structure.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Yu Chen, Li-Hsien Huang, An-Jhih Su, Hsien-Wei Chen
  • Patent number: 10811386
    Abstract: The present technology relates to a semiconductor device. The semiconductor device comprises: a plurality of dies stacked on top of each other, each of the dies comprising a first major surface, an IO conductive pattern on the first major surface and extended to a minor surface substantially perpendicular to the major surfaces to form at least one IO electrical contact on the minor surface, and the plurality of dies aligned so that the corresponding minor surfaces of all dies substantially coplanar with respect to each other to form a common flat sidewall, and a plurality of IO routing traces formed over the sidewall and at least partially spaced away from the sidewall. The plurality of IO routing traces are spaced apart from each other in a first direction on the sidewall, and each of IO routing traces is electrically connected to a respective IO electrical contact and extended across the sidewall in a second direction substantially perpendicular to the first direction on the sidewall.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: October 20, 2020
    Assignee: SanDisk Information Technology (Shanghai) Co., Ltd.
    Inventors: Chin Tien Chiu, Hem Takiar, Gursharan Singh, Fisher Yu, C C Liao
  • Patent number: 10804413
    Abstract: A package component includes a base layer, a sensing layer, a photo-curable adhesive, a cover layer and a first filter structure. The photo-curable adhesive and the sensing layer are disposed on the base layer. The sensing layer includes a sensing unit surrounded by the photo-curable adhesive. The cover layer is disposed on the sensing layer. The first filter structure faces the photo-curable adhesive and is disposed on the cover layer. The first filter structure is configured for transmitting a curing light which is used to cure the photo-curable adhesive, and for reflecting a detectable light which is to be sensed by the sensing unit, where the wavelength of the curing light is different from the wavelength of the detectable light.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: October 13, 2020
    Assignee: KINGPAK TECHNOLOGY INC
    Inventor: Yu-Hsuan Tsai