Having Light Transmissive Window Patents (Class 438/116)
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Patent number: 8076744Abstract: A photosensitizing chip package construction and manufacturing method thereof is comprised of photosensitizing chips constructed on one side of a wafer using a bonding layer; a color attachment array being disposed over those photosensitizing chips; a glass substrate provided with weir and covered up over the color attachment array; a proper gap being defined between the glass substrate and the color attachment array to promote permeability of stream of light by direct receiving stream of light from those photosensitizing chips constructed over the wafer.Type: GrantFiled: January 25, 2007Date of Patent: December 13, 2011Inventor: Chien-Hung Liu
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Patent number: 8042248Abstract: Disclosed embodiments demonstrate batch processing methods for producing optical windows for micro-devices. The windows protect the active elements of the micro-device from contaminants, while allowing light to pass into and out of the hermetically sealed micro-device package. Windows may be batch produced, reducing the cost of production, by fusing multiple metal frames to a single sheet of glass. In order to allow windows to be welded atop packages, disclosed embodiments keep a lip of metal without any glass after the metal frames are fused to the sheet of glass. Several techniques may accomplish this goal, including grinding grooves in the glass to provide a gap that prevents fusion of the glass to the metal frames along the outside edges in order to form a lip. The disclosed batch processing techniques may allow for more efficient window production, taking advantage of the economy of scale.Type: GrantFiled: September 29, 2006Date of Patent: October 25, 2011Assignee: Texas Instruments IncorporatedInventors: Wei-Yan Shih, Bradley M. Haskett
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Patent number: 8026583Abstract: The invention relates to a flip-chip module with a semiconductor chip with contact posts, wherein the contact posts are connected electrically and mechanically to a substrate. Provided between the substrate and the semiconductor chip is a spacer, which is coupled mechanically to the substrate and/or the semiconductor chip. By this means, thermal stresses in the flip-chip module are absorbed by the spacer and kept away from the semiconductor chip. The invention also relates to a method for the production of a flip-chip module, in which firstly a spacer is located between the semiconductor chip and the substrate, after which the contact posts are soldered to the contact points of the substrate. Through the provision of the spacer the distance between the semiconductor chip and the substrate is set precisely, thereby improving the quality of the soldering points.Type: GrantFiled: September 13, 2006Date of Patent: September 27, 2011Assignee: HTC Beteiligungs GmbHInventors: Ernst-A. Weissbach, Juergen Ertl
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Patent number: 8021912Abstract: A method of manufacturing an image sensor is provided. In this method, a photoelectric conversion unit may be formed within a semiconductor substrate, wherein the semiconductor substrate includes an active pixel region and an optical black region. An annealing layer may be formed on the active pixel region and the optical black region and etched so that the annealing layer covers at least a portion of the optical black region. A wiring pattern may be formed on the annealing layer. A light-blocking pattern may be formed on the wiring pattern so as to cover the entire photoelectric conversion unit of the optical black region, thereby blocking light from being incident upon the optical black region.Type: GrantFiled: January 29, 2009Date of Patent: September 20, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Yi Tae Kim, Kyung Ho Lee, Sae-Young Kim, Yun Ho Jang, Jung Chak Ahn
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Patent number: 8017417Abstract: Embodiments of the present invention provide an LED having a Wavelength Shift Layer (WSL) and method of manufacture. Specifically, under embodiment of the present invention, a WSL layer is applied over an LED chip. The WSL itself typically comprises two layers: an adhesion layer applied over a set (at least one) of LED chips, and a conformal coating over the adhesion layer. The adhesion layer provides improved adhesive effect of the conformal coating to the LED chip(s). The conformal coating is comprised of a particular phosphor ratio that is determined based on a wavelength measurement of the underlying LED chip(s). Specifically, under the present invention, a wavelength of a light output by an LED chip(s) (e.g., blue or ultra-violet (UV)) is measured (e.g., at the wafer level). Typically, the phosphor ratio of is comprised of at least one of the following colors: yellow, green, or red. Regardless, this conformal coating is applied over a glue layer that itself is applied over the LED chip.Type: GrantFiled: March 31, 2010Date of Patent: September 13, 2011Assignee: Lightizer Korea Co.Inventor: Byoung gu Cho
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Patent number: 8017443Abstract: A light transmissive cover for a device comprising: a cover member of light transmissive material; and a junction member joined to the cover member, the junction member being a member used to be joined to the body of the device and having a light interrupting film on the inner surface thereof. A device provided with a light transmissive cover, the device being provided with a cover member of light transmissive material joined to the body of device via a junction member so as to cover at least a part of the device, and having a light interrupting film on the inner surface of the junction member is also disclosed. In addition, methods for manufacturing them disclosed.Type: GrantFiled: January 3, 2006Date of Patent: September 13, 2011Assignee: Shinko Electric Industries Co., LtdInventor: Akinori Shiraishi
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Patent number: 8008762Abstract: Packaging assemblies for optically interactive devices and methods of forming the packaging assemblies in an efficient manner that eliminates or reduces the occurrence of process contaminants. In a first embodiment, a transparent cover is attached to a wafer of semiconductor material containing a plurality of optically interactive devices. The wafer is singulated, and the optically interactive devices are mounted on an interposer and electrically connected with wire bonds. In a second embodiment, the optically interactive devices are electrically connected to the interposer with back side conductive elements. In a third embodiment, the optically interactive devices are mounted to the interposer prior to attaching a transparent cover. A layer of encapsulant material is formed over the interposer, and the interposer and encapsulant material are cut to provide individual packaging assemblies. In a fourth embodiment, the optically interactive devices are mounted in a preformed leadless chip carrier.Type: GrantFiled: December 28, 2006Date of Patent: August 30, 2011Assignee: Round Rock Research, LLCInventors: Todd O. Bolken, Chad A. Cobbley
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Patent number: 8003442Abstract: The invention provides an integrated circuit package and method of fabrication thereof. The integrated circuit package comprises an integrated circuit chip having a photosensitive device thereon; a bonding pad formed on an upper surface of the integrated circuit chip and electrically connected to the photosensitive device; a barrier formed between the bonding pad and the photosensitive device; and a conductive layer formed on a sidewall of the integrated circuit chip and electrically connected to the bonding pad. The barrier layer blocks overflow of the adhesive layer into a region, on which the photosensitive device is formed, to improve yield for fabricating the integrated circuit package.Type: GrantFiled: July 25, 2007Date of Patent: August 23, 2011Inventors: Yu-Lin Yen, Chen-Mei Fan
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Patent number: 7998781Abstract: A method of manufacturing a semiconductor device includes: forming a first resin layer on a wafer having a light receiving portion; patterning the first resin layer into a predetermined shape and forming a first resin film on the light receiving portion; dividing the wafer into light receiving elements; mounting the light receiving elements on an upper surface of a lead frame; a sealing step of forming a sealing resin layer around the first resin film; and removing the first resin film such that a portion of the light receiving element is exposed to the outside, and in the sealing step, the upper surface of the first resin film is flush with the upper surface of the sealing resin layer, or the upper surface of the first resin film is higher than the upper surface of the sealing resin layer.Type: GrantFiled: August 13, 2009Date of Patent: August 16, 2011Assignee: Renesas Electronics CorporationInventors: Kenji Uchida, Koki Hirasawa
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Patent number: 7993977Abstract: A method of forming molding standoff structures on integrated circuit devices is disclosed which includes forming a plurality of standoff structures on a substantially rectangular sheet of transparent material and, after forming the standoff structures, singulating the substantially rectangular sheet of transparent material into a plurality of individual transparent members, each of which comprise at least one of the plurality of standoff structures.Type: GrantFiled: July 2, 2007Date of Patent: August 9, 2011Assignee: Micron Technology, Inc.Inventors: Frank Hall, James Voelz
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Patent number: 7994618Abstract: A sensor module has a carrier substrate having a bottom side and a top side, a sensor chip arranged on the top side of the carrier substrate and having a pressure-sensitive active area, a signal-processing chip arranged on the top side of the carrier substrate next to the sensor chip and being connected to the sensor chip in an electrically conducting manner, a continuous casting material covering the top side of the carrier substrate and the signal-processing chip and being in mechanical contact with both, the casting material having a recess which is arranged such that the casting material does not cover at least a part of the active area of the sensor chip.Type: GrantFiled: November 14, 2006Date of Patent: August 9, 2011Assignee: Infineon Technologies AGInventors: Alfons Dehe, Marc Fueldner
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Publication number: 20110186975Abstract: A semiconductor package includes a substrate with a first surface and an opposite second surface, a plurality of metal rods throughout the first surface and the second surface of the substrate, a reflector surrounding the first surface of the substrate to form a functional area, a glass reflection layer covering the surfaces of reflector and the functional area and exposing a part of a first electrode area and a part of a second electrode area, at least one semiconductor chip adhered on the functional area, and a transparent gel covering the at least one semiconductor chip.Type: ApplicationFiled: November 19, 2010Publication date: August 4, 2011Applicant: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.Inventor: CHIH-MING CHEN
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Patent number: 7989836Abstract: A light emitting device includes a light emitting element, including a substrate including group III nitride compound semiconductor, a luminous layer structure including group III nitride compound semiconductor, the luminous layer structure formed on a first surface of the substrate, and an irregular surface formed on a second surface of the substrate, the second surface including a principal light emission surface, and a translucent sealing member for sealing the light emitting element, the translucent sealing member being separated from the second surface. At least one of translucent gel material and an inert gas is filled between the light emitting element and the translucent sealing member.Type: GrantFiled: February 3, 2010Date of Patent: August 2, 2011Assignee: Toyoda Gosei Co., Ltd.Inventor: Toshiya Uemura
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Publication number: 20110147904Abstract: This invention provides a semiconductor device with increased moisture resistance. The semiconductor device includes: a semiconductor substrate; an optical element provided in a front surface of the semiconductor substrate; a light-transmissive substrate provided above the front surface of the semiconductor substrate; an adhesive layer provided between the front surface of the semiconductor substrate and a front surface of the light-transmissive substrate, and fixing the light-transmissive substrate to the semiconductor substrate; and an insulating film covering a lateral surface of said adhesive layer which is not in contact with the light-transmissive substrate and the semiconductor substrate.Type: ApplicationFiled: March 1, 2011Publication date: June 23, 2011Applicant: PANASONIC CORPORATIONInventor: Hikari SANO
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Patent number: 7964954Abstract: An integrated circuit having a semiconductor sensor device including a sensor housing partly filled with a rubber-elastic composition is disclosed. One embodiment has a sensor chip with sensor region arranged in the interior of the housing. The sensor housing has an opening to the surroundings which is arranged in such a way that the sensor region faces the opening. The sensor chip is embedded into a rubber-elastic composition on all sides in the interior of the housing. The sensor housing has a sandwich-like framework having three regions arranged one above another, including an intermediate region with the rubber-elastic composition.Type: GrantFiled: March 19, 2007Date of Patent: June 21, 2011Assignee: Infineon Technologies AGInventor: Jean Schmitt
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Publication number: 20110133332Abstract: There is provided a package substrate allowing for enhanced reliability by improving the structure of a solder bump and a method of fabricating the same. The package substrate includes: a substrate having at least one conductive pad; an insulating layer provided on the substrate and having an opening to expose the conductive pad; a post terminal provided on the conductive pad inside the opening; and a solder bump provided on the post terminal and having an angle between a bottom surface and a side surface thereof ranging from 80° to 120°.Type: ApplicationFiled: November 5, 2010Publication date: June 9, 2011Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: Seon Jae Mun, Dae Young Lee, Tae Joon Chung, Dong Gyu Lee, Jin Won Choi
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Patent number: 7955904Abstract: A wirebond protector has an elongated shape that corresponds to the elongated array of wirebonds along the edge of a microelectronic device that connect a semiconductor die to electrical conductors on a substrate. In making the microelectronic device with wirebond protection, wirebonds are first formed in the conventional manner The wirebond protector is then attached to the device in an orientation in which it extends along the array of wirebonds to at least partially cover the wirebonds.Type: GrantFiled: July 27, 2010Date of Patent: June 7, 2011Assignee: Avago Technologies Fiber IP (Singapore) Pte. Ltd.Inventor: David J. K. Meadowcroft
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Patent number: 7947531Abstract: Combinatorial evaluation of dry semiconductor processes is described, including rotating a mask comprising a plurality of apertures, wherein the mask is positioned between a dry semiconductor processing source and the substrate, and performing a dry semiconductor process through the apertures of the mask at a plurality of intervals during the rotating the mask to combinatorially create a plurality of processed regions on the substrate, wherein the apertures of the mask are arranged in such a way that the plurality of processed regions have different geometries relative to the processing source, and analyzing the processed regions to determine effects of time and geometry on the processed regions.Type: GrantFiled: August 28, 2009Date of Patent: May 24, 2011Assignee: Intermolecular, Inc.Inventor: Tony Chiang
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Patent number: 7936033Abstract: According to one embodiment, a micro-optical device includes an electro-optical circuit and an annular frame disposed on a surface of a substrate. The electro-optical circuit has an active region that is encapsulated by a window and an interconnect region adjacent at least one edge of the electro-optical circuit. The annular frame extends around an outer periphery of the window and is separated from the window by a gap, the annular frame and the electro-optical circuit form a cavity for placement of a plurality of bonding wires the interconnect that electro-optical circuit to the substrate.Type: GrantFiled: December 29, 2008Date of Patent: May 3, 2011Assignees: Texas Instruments Incorporated, Amkor Technology, Inc.Inventors: Bradley Morgan Haskett, John Patrick O'Connor, Mark Myron Miller, Sean Timothy Crowley, Jeffery Alan Miks, Mark Phillip Popovich
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Patent number: 7935310Abstract: Devices, systems and methods of using same where hybrid substrate materials are provided with a substantially uniform surface to provide uniformity of properties, including interaction with their environments. Uniform surfaces are applied as coatings over, e.g., hybrid metal/silica, metal/polymer, metal/metal surfaces to mask different chemical properties of differing regions of the surface and to afford a protective surface for the hybrid structure.Type: GrantFiled: November 27, 2006Date of Patent: May 3, 2011Assignee: Pacific Biosciences of California, Inc.Inventor: Jonas Korlach
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Patent number: 7932121Abstract: A semiconductor device includes a semiconductor element, a transparent member separated from the semiconductor element by a designated length and facing the semiconductor element, a sealing member sealing an edge surface of the transparent member and an edge part of the semiconductor element, and a shock-absorbing member provided between the edge surface of the transparent member and the sealing member and easing a stress which the transparent member receives from the sealing member or the semiconductor element.Type: GrantFiled: March 29, 2010Date of Patent: April 26, 2011Assignee: Fujitsu Semiconductor LimitedInventor: Naoyuki Watanabe
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Patent number: 7931867Abstract: Devices, systems and methods of using same where hybrid substrate materials are provided with a substantially uniform surface to provide uniformity of properties, including interaction with their environments. Uniform surfaces are applied as coatings over, e.g., hybrid metal/silica, metal/polymer, metal/metal surfaces to mask different chemical properties of differing regions of the surface and to afford a protective surface for the hybrid structure.Type: GrantFiled: October 31, 2007Date of Patent: April 26, 2011Assignee: Pacific Biosciences of California, Inc.Inventor: Jonas Korlach
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Publication number: 20110092023Abstract: A package structure of photodiode and a forming method of the same are provided. The method includes providing a heat-dissipation plate; placing a circuit board on the heat-dissipation plate, the circuit board having an opening exposing a top surface of the heat-dissipation plate and a first contact pad located on a peripheral area of the opening; placing a carrier with a metal cladding surface into the opening, the carrier connecting the top surface of the heat-dissipation plate; placing a photodiode chip on the carrier wherein the bottom area of the photodiode chip is less than the metal cladding surface such that a portion of the metal cladding surface is exposed; and electrically connecting the exposed metal cladding surface to the first contact pad.Type: ApplicationFiled: October 14, 2010Publication date: April 21, 2011Applicant: SOLAPOINT CORPORATIONInventor: Tai-Hui LIU
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Patent number: 7923793Abstract: An image sensor module having a sensor chip closely adhered on a concave surface and a fabrication method thereof are disclosed. The image sensor module includes at least one sensor chip, at least one sensor chip-mounting structure comprising a substrate and a polymer layer formed on the substrate, the polymer layer having an concave surface formed on an upper part thereof by a polymer molding method, so that the sensor chip is bent and bonded on the concave surface, and at least one lens fixed on the at least one sensor chip-mounting structure above the sensor chip.Type: GrantFiled: May 13, 2008Date of Patent: April 12, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Min-seog Choi, Seung-wan Lee, Woon-bae Kim, Eun-sung Lee, Kyu-dong Jung, Che-heung Kim
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Patent number: 7919841Abstract: A structure of an integrated circuit module includes a wiring board, a plurality of integrated circuits and at least one terminating resistance circuit. The wiring board has a mounting region on at least one surface thereof. The plurality of integrated circuits are mounted in the mounting region of the wiring board and spaced from one another in a first direction. The at least one terminating resistance circuit is arranged between at least two adjacent integrated circuits, and coupled to an output of a last of the plurality of integrated circuits.Type: GrantFiled: January 22, 2008Date of Patent: April 5, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Joo Park, Ki-Hyun Ko, Young Yun, Soo-Kyung Kim
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Patent number: 7910934Abstract: Optical analysis system fluidically self-assembled using shape-coded freestanding optoelectronic components and a template having shape-coded recessed binding sites connected by an embedded interconnect network. Also includes methods of manufacture and use for optical analyses.Type: GrantFiled: July 2, 2009Date of Patent: March 22, 2011Assignee: University of WashingtonInventors: Samuel Kim, Babak Amirparviz, Deirdre Meldrum, Ehsan Saeedi
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Patent number: 7910674Abstract: Methods for the addition polymerization of cycloolefins using a cationic Group 10 metal complex and a weakly coordinating anion of the formula: [(R?)zM(L?)x(L?)y]b[WCA]d wherein [(R?)zM(L?)x(L?)y] is a cation complex where M represents a Group 10 transition metal; R? represents an anionic hydrocarbyl containing ligand; L? represents a Group 15 neutral electron donor ligand; L? represents a labile neutral electron donor ligand; x is 1 or 2; and y is 0, 1, 2, or 3; and z is 0 or 1, wherein the sum of x, y, and z is 4; and [WCA] represents a weakly coordinating counteranion complex; and b and d are numbers representing the number of times the cation complex and weakly coordinating counteranion complex are taken to balance the electronic charge on the overall catalyst complex.Type: GrantFiled: June 18, 2003Date of Patent: March 22, 2011Assignee: Promerus, LLCInventors: Larry Funderburk Rhodes, Andrew Bell, Ramakrishna Ravikiran, John C. Fondran, Saikumar Jayaraman, Brian Leslie Goodall, Richard A. Mimna, John-Henry Lipian
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Publication number: 20110062410Abstract: An electronic device comprises a drawn glass tube having opposing ends, a semiconductive material disposed inside of the drawn glass tube, and a first electrode and a second electrode disposed at the opposing ends of the drawn glass tube. A method of making an electrical device comprises disposing a semiconductive material inside of a glass tube, and drawing the glass tube with the semiconductive material disposed therein to form a drawn glass tube. The method of making an electrical device also comprises disposing a first electrode and a second electrode on the opposing ends of the drawn glass tube to form an electric device.Type: ApplicationFiled: September 11, 2009Publication date: March 17, 2011Inventors: Ilia N. IVANOV, John T. SIMPSON
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Publication number: 20110062573Abstract: The MEMS package has a mounting substrate on which one or more transducer chips are mounted wherein the mounting substrate has an opening. A top cover is attached to and separated from the mounting substrate by a spacer forming a housing enclosed by the top cover, the spacer, and the mounting substrate and accessed by the opening. Electrical connections are made between the one or more transducer chips and the mounting substrate and/or between the one or more transducer chips and the top cover. A bottom cover can be mounted on a bottom surface of the mounting substrate wherein a hollow chamber is formed between the mounting substrate and the bottom cover, wherein a second opening in the bottom cover is not aligned with the first opening. Pads on outside surfaces of the top and bottom covers can be used for further attachment to printed circuit boards. The top and bottom covers can be a flexible printed circuit board folded under the mounting substrate.Type: ApplicationFiled: November 8, 2010Publication date: March 17, 2011Inventors: Wang Zhe, Chong Ser Choong
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Publication number: 20110062571Abstract: An optical device for an integrated circuit device, includes a laminated substrate having a through-passage and a tubular frame in which an optical lens is mounted, the tubular frame having an end part inserted or integrated in the through-passage of the laminated substrate. A integrated circuit device includes an optical device and an integrated circuit die carried by the laminated substrate and having an active optical area placed in front of the optical lens.Type: ApplicationFiled: September 11, 2009Publication date: March 17, 2011Applicant: ST-ERICSSON SAInventor: Nedyalko Slavov
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Patent number: 7906372Abstract: A wirebond protector has an elongated shape that corresponds to the elongated array of wirebonds along the edge of a microelectronic device that connect a semiconductor die to electrical conductors on a substrate. In making the microelectronic device with wirebond protection, wirebonds are first formed in the conventional manner The wirebond protector is then attached to the device in an orientation in which it extends along the array of wirebonds to at least partially cover the wirebonds.Type: GrantFiled: July 9, 2008Date of Patent: March 15, 2011Assignee: Avago Technologies Fiber IP (Singapore) Pte. LtdInventor: David J. K. Meadowcroft
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Patent number: 7901972Abstract: Provided is a method of manufacturing a camera module, the camera module including a housing that includes one or more lenses which are sequentially fixed and coupled and of which the focus does not need to be adjusted; a holder assembly that is coupled to a lower end portion of the housing; and a main substrate that is coupled to a lower end portion of the holder assembly.Type: GrantFiled: October 28, 2008Date of Patent: March 8, 2011Assignee: Samsung Electro-Mechanics Co., Ltd.Inventor: Min Chul Go
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Patent number: 7898070Abstract: The invention provides an image sensor package and method for fabricating the same. The image sensor package comprises a first substrate comprising a sensor device thereon and a hole therein. A bonding pad comprising a first opening is formed on an upper surface of the first substrate. A second substrate comprising a spacer element with a second opening therein is disposed on the first substrate. A conductive plug is formed in the hole and passes through the first and second openings to the second substrate to electrically contact with the bonding pad. A conductive layer is formed on a lower surface of the first substrate and electrically connects to the conductive plug. A solder ball is formed on the conductive layer and electrically connects to the bonding pad by the conductive plug. The image sensor package further comprises a second substrate bonding to the first substrate. The image sensor package is relatively less thick, thus, the dimensions thereof are relatively reduced.Type: GrantFiled: August 19, 2009Date of Patent: March 1, 2011Assignee: VisEra Technologies Company LimitedInventors: Jui-Ping Weng, Jang-Cheng Hsieh, Tzu-Han Lin, Pai-Chun Peter Zung
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Patent number: 7893514Abstract: An image sensor package, a method of manufacturing the same, and an image sensor module including the image sensor package are provided. In the image sensor package, an image sensor chip is installed onto a depression of a transmissive substrate. An adhesive bonds the image sensor chip to the transmissive substrate and seals an Active Pixel Sensor (APS) on the image sensor chip, protecting it from fine particle contamination. An IR cutting film is disposed on the transmissive substrate to minimize the height of the image sensor package. The image sensor package is electrically connected to external connection pads in the depression. Consequently, the image sensor package has a minimum height, is not susceptible to particle contamination, and does not require expensive alignment processes during manufacturing.Type: GrantFiled: July 31, 2007Date of Patent: February 22, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Woon-Seong Kwon, Yong-Hwan Kwon, Un-Byoung Kang, Chung-Sun Lee, Hyung-Sun Jang
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Patent number: 7888176Abstract: In one or more embodiments, a method of producing a stacked integrated circuit assembly includes providing a substrate having a top surface with at least one substrate connection pad. A first flip chip integrated circuit (FFIC) is disposed above the substrate, and a second flip chip integrated circuit (SFIC) is disposed above the FFIC. The FFIC may be disposed between the substrate and the SFIC. The method includes making at least one solder connection between the substrate connection pad and the FFIC and at least one solder connection between the FFIC and the SFIC.Type: GrantFiled: September 10, 2009Date of Patent: February 15, 2011Assignee: Raytheon CompanyInventors: Tse E. Wong, Samuel D. Tonomura, Stephen E. Sox, Timothy E. Dearden, Clifton Quan, Polwin C. Chan, Mark S. Hauhe
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Patent number: 7883916Abstract: A complementary metal-oxide-semiconductor (CMOS) image sensor comprises a first photosensitive diode comprising a first semiconductor material is formed in a first semiconductor substrate. A second photosensitive diode comprising a second semiconductor material, which has a different light detection wavelength range than the first semiconductor material, is formed in a second semiconductor substrate. Semiconductor devices for holding and detecting charges comprising a sensing circuit of the CMOS image sensor may also be formed in the second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are bonded so that the first photosensitive diode is located underneath the second photosensitive diode. The vertical stack of the first and second photosensitive diodes detects light in the combined detection wavelength range of the first and second semiconductor materials. Sensing devices may be shared between the first and second photosensitive diodes.Type: GrantFiled: May 30, 2008Date of Patent: February 8, 2011Assignee: International Business Machines CorporationInventors: Jeffrey P. Gambino, Daniel N. Maynard, Kevin N. Ogg, Richard J. Rassel, Raymond J. Rosner
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Patent number: 7875528Abstract: A method, system and program product for bonding two circuitry-including semiconductor substrates, and a related stage, are disclosed. In one embodiment, a method of bonding two circuitry-including substrates includes: providing a first stage for holding a first circuitry-including substrate and a second stage for holding a second circuitry-including substrate; identifying an alignment mark on each substrate; determining a location and a topography of each alignment mark using laser diffraction; creating an alignment model for each substrate based on the location and topography the alignment mark thereon; and bonding the first and second circuitry-including substrates together while aligning the first and second substrate based on the alignment model.Type: GrantFiled: February 7, 2007Date of Patent: January 25, 2011Assignee: International Business Machines CorporationInventors: Douglas C. La Tulipe, Jr., Steven E. Steen, Anna W. Topol
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Publication number: 20110012248Abstract: A method for producing a capping wafer for a sensor having at least one cap includes: production of a contacting via extending through the wafer, and, temporally subsequent thereto, filling of the contacting via with an electrically conductive material.Type: ApplicationFiled: October 20, 2008Publication date: January 20, 2011Inventors: Frank Reichenbach, Franz Laermer, Silvia Kronmueller, Andreas Scheurle
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Patent number: 7868336Abstract: According to the present invention, protrusions 4 are formed on electrodes 3 of semiconductor elements 6, and an optical member 7 is secured on the semiconductor element 6 with an adhesive 8 so as to be pressed onto the protrusions 4.Type: GrantFiled: November 4, 2008Date of Patent: January 11, 2011Assignee: Panasonic CorporationInventors: Hiroaki Fujimoto, Yoshihiro Tomita
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Patent number: 7863105Abstract: An image sensor package comprises a substrate, a chip mounted over the substrate. A molding material is formed surrounding the chip to expose a micron lens area, wherein the molding material includes via structure passing there through. A protection layer is formed on the micro lens area to prevent the micro lens. A redistributed conductive layer is formed over the molding material to connect to a pad of the chip. Metal pads are formed on via structure as connecting points with PCB. A cover layer is formed over the substrate to isolate the metal pads.Type: GrantFiled: May 8, 2008Date of Patent: January 4, 2011Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Jui-Hsien Chang
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Patent number: 7858446Abstract: A sensor-type semiconductor package and a fabrication method thereof are provided. The fabrication method of the sensor-type semiconductor package includes steps of: providing a wafer having sensor chips; attaching light-permeable bodies to the sensor chips, wherein each light-permeable body has a covering layer and an adhesive layer; singulating the wafer so as to obtain a plurality of separated sensor chips with the light-permeable bodies attached thereon; attaching and electrically connecting the separated sensor chips to a substrate module having substrates, forming an encapsulant encapsulating the sensor chips and the light-permeable bodies; cutting the encapsulant along edges of the light-permeable bodies to a depth at least corresponding the bottom edges of the covering layers; removing the covering layers with the encapsulant mounted thereon to expose the light-permeable bodies; and cutting between the substrates to obtain a plurality of sensor-type semiconductor packages.Type: GrantFiled: November 2, 2007Date of Patent: December 28, 2010Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chien-Ping Huang, Tse-Wen Chang, Chang-Yueh Chan, Cheng-Yi Chang
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Patent number: 7858438Abstract: A semiconductor device has a chip, a first bump electrode, a conductive wire and a second bump electrode. The chip has at least one contact pad, and the first bump electrode is formed on the contact pad. The conductive wire is disposed on an active surface of the chip and electrically connected to the first bump electrode. The second bump electrode is formed on the conductive wire, and the second bump electrode is not disposed over any contact pad of the chip. In addition, a method for packaging a chip and an IC package are also disclosed.Type: GrantFiled: June 13, 2007Date of Patent: December 28, 2010Assignee: Himax Technologies LimitedInventors: Chien-Ru Chen, Ying-Lieh Chen
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Patent number: 7855424Abstract: A method for packaging a semiconductor device includes following steps. First, a first substrate including at least one first pattern is provided. At least one semiconductor device is disposed on the surface of the first substrate. Next, a spacer with at least one aperture and at least one through hole is provided. Then, the first pattern is aimed at the through hole to connect the first substrate and the spacer, so that the semiconductor device is positioned correspondingly to the aperture. Afterwards, a second substrate including at least one second pattern is provided. Thereon, the second pattern is aimed at the through hole, so that the second substrate is connected to the spacer correspondingly.Type: GrantFiled: November 30, 2006Date of Patent: December 21, 2010Assignee: Advanced Semiconductor Engineering, Inc.Inventor: Chain-Hau Hsu
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Patent number: 7854366Abstract: A method of mounting a conductive ball according to the present invention includes the steps of, disposing a mask on a substrate including connection pads, the mask having opening portions corresponding to the connection pad, supplying conductive balls on the mask, arranging the conductive balls on the connection pad of the substrate through the opening portions of the mask by moving the conductive balls to one end side of the mask by ball moving member (a brush), and removing excess conductive balls remaining on a region of the mask where the opening portions are provided, by bonding the excess conductive balls to a ball removal film (adhesive film).Type: GrantFiled: August 8, 2008Date of Patent: December 21, 2010Assignee: Shinko Electric Industries Co., Ltd.Inventors: Hideaki Sakaguchi, Kiyoaki Iida
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Patent number: 7846754Abstract: A high power Light Emitting Diode (LED) package and a method of producing the same. The high power LED package according to the present invention includes a plurality of light emitting diode chips, a first lead frame with the light emitting diode chips mounted thereon, and a second lead frame disposed at a predetermined interval from the first lead frame. The LED package also includes a package body fixing the first and second lead frames and bonding wires for electrically connecting the plurality of LED chips with upward-inclined inner side walls thereof and a second reflecting part surrounding the entire plurality of LED chips with an upward-inclined inner side wall thereof.Type: GrantFiled: August 27, 2009Date of Patent: December 7, 2010Assignee: Samsung LED Co., Ltd.Inventors: Kyung Seob Oh, Jae Ky Roh, Jung Kyu Park, Jong Hwan Baek, Seung Hwan Choi
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Publication number: 20100295178Abstract: A first wiring pattern is formed on a surface of a first support plate; a semiconductor chip is disposed on the first wiring pattern; and electrode terminals of the semiconductor chip are electrically connected to the first wiring pattern at required positions. Post electrodes connected to a second wiring pattern of a wiring-added post electrode component integrally connected by a second support plate are collectively fixed and electrically connected to the first wiring pattern formed on the first support plate at predetermined positions. After sealing with resin, the first and second support plates are separated; a glass substrate is affixed on a front face side; and external electrodes connected to the second wiring pattern are formed on a back face side.Type: ApplicationFiled: January 16, 2009Publication date: November 25, 2010Inventors: Masamichi Ishihara, Hirotaka Ueda
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Patent number: 7829190Abstract: An anisotropic electrically conducting interconnect is disclosed in which an adhesive comprising particles having a breakable coating of at least one electrically nonconductive material is compressed between a first contact and a second contact. Compression to two contacts breaks the breakable coating exposing an electrically conducting material which makes contact with the first and second contacts. The electrically conducting material may be a metal conductor or a two-part reactive conductive resin/catalyst system. Also disclosed are processes for making such electrical interconnects and adhesives for use in making electrical interconnect.Type: GrantFiled: August 25, 2005Date of Patent: November 9, 2010Assignee: Micron Technology, Inc.Inventors: Chad A. Cobbley, Steve W. Heppler
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Patent number: 7824945Abstract: A method for making micro-electromechanical system devices includes: (a) forming a sacrificial layer on a device wafer; (b) forming a plurality of loop-shaped through-holes in the sacrificial layer so as to form the sacrificial layer into a plurality of enclosed portions; (c) forming a plurality of cover caps on the sacrificial layer such that the cover caps respectively enclose the enclosed portions of the sacrificial layer; (d) forming a device through-hole in each of active units of the device wafer so as to form an active part suspended in each of the active units; and (e) removing the enclosed portions of the sacrificial layer through the device through-holes in the active units of the device wafer.Type: GrantFiled: October 2, 2008Date of Patent: November 2, 2010Assignee: Asia Pacific Microsystems, Inc.Inventors: Tso-Chi Chang, Mingching Wu
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Patent number: 7811861Abstract: An image sensing device and packaging method thereof is disclosed. The packaging method includes the steps of a) providing an image sensing module, having a light-receiving region exposed, on a first substrate; b) forming a plurality of first contacts around the light-receiving region on the image sensing module; c) providing a second substrate, having a plurality of second contacts corresponding to the plurality of first contacts and an opening for allowing the light-receiving region to be exposed while the second substrate is placed over the image sensing module, the plurality of second contacts being disposed around the opening; d) connecting the plurality of first contacts and the plurality of second contacts; and e) disposing a transparent lid above the light-receiving region, on a side of the second substrate which is opposite to the plurality of second contacts.Type: GrantFiled: August 1, 2008Date of Patent: October 12, 2010Assignee: Tong Hsing Electronic Industries Ltd.Inventors: Chi-Chih Huang, Chih-Yang Hsu
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Patent number: 7807505Abstract: Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods are disclosed herein. A method for packaging microfeature devices in accordance with an embodiment of the invention can include releasably attaching a plurality of first known good microelectronic dies to a carrier substrate in a desired arrangement. In several embodiments, for example, the first dies can be releasably attached to an attachment feature on the carrier substrate. The method can also include attaching one or more second known good microelectronic dies to the individual first dies in a stacked configuration to form a plurality of stacked devices. The method further includes at least partially encapsulating the stacked devices and separating the stacked devices from each other.Type: GrantFiled: August 30, 2005Date of Patent: October 5, 2010Assignee: Micron Technology, Inc.Inventors: Warren M. Farnworth, Alan G. Wood