Having Light Transmissive Window Patents (Class 438/116)
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Patent number: 11515347Abstract: An image sensor module comprises an image sensor having a light sensing area, a cover glass for covering the light sensing area, a dam between the image sensor and the cover glass, which surrounds the light sensing area, and has an outer wall and an inner wall, where a cross-section of the inner wall parallel to the surface of the light sensing area of the image sensor forms a sawtooth pattern and/or, where a cross-section of the inner wall orthogonal to the surface of the light sensing area of the image sensor forms an inclined surface.Type: GrantFiled: January 20, 2020Date of Patent: November 29, 2022Assignee: OmniVision Technologies, Inc.Inventors: Wei-Feng Lin, En-Chi Li, Chi-Chih Huang
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Patent number: 11145777Abstract: An optical sensor module includes a first frame set, a second frame set and a housing which partially covers the first frame set and the second frame set. The first frame set has a first chip-mounting frame and a first wiring frame. The first chip-mounting frame has a first chip-mounting section, and a first conductive lead. At least one first indentation is formed on the first chip-mounting section. The second frame set has a second chip-mounting frame and a second wiring frame. The second chip-mounting frame has a second chip-mounting section and a second conductive lead. At least one second indentation is formed on the second chip-mounting section.Type: GrantFiled: January 9, 2020Date of Patent: October 12, 2021Assignees: LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORPORATIONInventors: Chen-Hsiu Lin, Shih-Chung Huang, Bo-Jhih Chen
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Patent number: 10937927Abstract: A group III nitride semiconductor light-emitting element includes a single crystal substrate and an element layer. The element layer includes an n-type layer, an active layer, and a p-type layer formed on the upper surface of the single crystal substrate in this order, and has a composition represented by the composition formula AlXGaYIn1-X-YN (0?X?1.0, 0?Y?1.0, 0?X+Y?1.0). The thickness of the single crystal substrate is at least 80 ?m. The area of the upper surface of the substrate is larger than the area of the bottom surface of the substrate.Type: GrantFiled: December 15, 2017Date of Patent: March 2, 2021Assignee: STANLEY ELECTRIC CO., LTDInventor: Toshiyuki Obata
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Patent number: 10636717Abstract: A fingerprint sensor package, including a sensing side for sensing fingerprint information and a separate connection side for electrically connecting the fingerprint sensor package to a host device, is disclosed. The fingerprint sensor package can also include a sensor integrated circuit facing the sensing side and substantially surrounded by a fill material. The fill material includes vias at peripheral locations around the sensor integrated circuit. The fingerprint sensor package can further include a redistribution layer on the sensing side which redistributes connections of the sensor integrated circuit to the vias. The connections can further be directed through the vias to a ball grid array on the connection side. Some aspects also include electrostatic discharge traces positioned at least partially around a perimeter of the connection side. Methods of manufacturing are also disclosed.Type: GrantFiled: September 5, 2017Date of Patent: April 28, 2020Assignee: Amkor Technology, Inc.Inventors: Ronald Patrick Huemoeller, David Bolognia, Robert Francis Darveaux, Brett Arnold Dunlap
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Patent number: 10627088Abstract: A light source module according to an embodiment includes a substrate, a plurality of light emitting device packages disposed on the substrate, a plurality of driving devices disposed on the substrate, and a connection terminal part disposed on the substrate, wherein an interval between both ends of the substrate and the connection terminal part is equal to or greater than an interval between the light emitting device package adjacent to the both ends of the substrate and the both ends of the substrate. The light source module is advantageous to slimming and thinning and has an advantage where a design of arrangement of a light emitting device package is free.Type: GrantFiled: January 19, 2016Date of Patent: April 21, 2020Assignee: LG INNOTEK CO., LTD.Inventor: Jae O Kwak
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Patent number: 9735135Abstract: There is provided an optical sensor package including a semiconductor base layer. A first surface of the semiconductor base layer is formed with a pixel array, a plurality of solder balls and an optical component such that when the optical sensor package is assembled with a substrate, the optical component is accommodated in an accommodation throughhole of the substrate so as to reduce the total thickness.Type: GrantFiled: December 4, 2014Date of Patent: August 15, 2017Assignee: PIXART IMAGING (PENANG) SDN. BHD.Inventors: Hun-Kwang Lee, Sai-Mun Lee, Yik-Leong Chong
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Patent number: 9653434Abstract: The invention relates to a light-emitting diode arrangement having the following: a preferably heat-conductive substrate (2); a printed circuit board (5) which is arranged on the substrate (2), a recess (9) being provided in the printed circuit board (5); and at least one light-emitting diode chip (3) which is arranged on the substrate (2) and in the recess (9), said recess (9) being at least partly filled with at least one matrix material which preferably has a color-converting material (8).Type: GrantFiled: November 15, 2012Date of Patent: May 16, 2017Assignee: TRIDONIC GMBH & CO KGInventors: Gerd Muehlbacher, Stefan Kerber, Gavin Brydon
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Patent number: 9287476Abstract: A method of manufacturing a light emitting device having a resin package which provides an optical reflectivity equal to or more than 70% at a wavelength between 350 nm and 800 nm after thermal curing, and in which a resin part and a lead are formed in a substantially same plane in an outer side surface, includes a step of sandwiching a lead frame provided with a notch part, by means of an upper mold and a lower mold, a step of transfer-molding a thermosetting resin containing a light reflecting material in a mold sandwiched by the upper mold and the lower mold to form a resin-molded body in the lead frame and a step of cutting the resin-molded body and the lead frame along the notch part.Type: GrantFiled: August 16, 2013Date of Patent: March 15, 2016Assignee: NICHIA CORPORATIONInventors: Hirofumi Ichikawa, Masaki Hayashi, Shimpei Sasaoka, Tomohide Miki
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Patent number: 9054279Abstract: A plastic housing is arranged on a carrier element and is provided with a recess in which an optoelectronic component is arranged. On the side facing away from the carrier element, the recess has an opening to the outside which can be provided with a transparent cover. One or more structures can be provided on the plastic housing in order to orient the cover and/or optical components relative to the optoelectronic component.Type: GrantFiled: January 9, 2008Date of Patent: June 9, 2015Assignee: OSRAM Opto Semiconductors GmbHInventors: Georg Bogner, Stefan Gruber, Thomas Zeiler, Markus Kirsch
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Patent number: 9035439Abstract: The present embodiments provide surface mount devices and/or systems. In some embodiments, the surface mount devices comprise a casing having a recess formed extending at least partially into said casing; and first and second leads each of which is at least partially encased by said casing and each of which has a portion exposed through said recess, wherein at least one of said first and second leads has one or more size reduction features in its said exposed portion that reduces the surface area to provide an increased surface bonding area to said casing around said lead.Type: GrantFiled: January 28, 2010Date of Patent: May 19, 2015Assignee: Cree Huizhou Solid State Lighting Company LimitedInventors: Wong Xuan, Xie Jian Hui, Cheng Siu Cheong
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Patent number: 9029968Abstract: An optical sensor element is mounted in a package which includes a glass substrate having a cavity, and a glass lid substrate bonded to the other substrate to close the cavity. The glass substrate with the cavity has metalized wiring patterns on front and rear surfaces thereof, and a through hole filled with metal to form a through-electrode interconnecting the wiring patterns on the front and rear surfaces. A metalized wiring pattern on the rear surface of the glass lid substrate is electrically connected to the wiring pattern on the front surface of the other substrate with an adhesive containing conductive particles. The glass lid substrate is made either of glass having a filter function or glass having a light shielding property with an opening therethrough filled with glass having a filter function.Type: GrantFiled: November 14, 2012Date of Patent: May 12, 2015Assignee: Seiko Instruments Inc.Inventors: Koji Tsukagoshi, Hitoshi Kamamori, Sadao Oku, Hiroyuki Fujita, Keiichiro Hayashi
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Publication number: 20150102478Abstract: Semiconductor packages and methods for forming a semiconductor package are presented. The semiconductor package includes a package substrate having a die region on a first surface thereof. The package includes a die having a sensing element. The die is disposed in the die region and is electrically coupled to contact pads disposed on the first surface of the package substrate by insulated wire bonds. A cap is disposed over the first surface of the package substrate. The cap and the first surface of the package substrate define an inner cavity which accommodates the die and the insulated wire bonds. The insulated wire bonds are directly exposed to an environment through at least one access port of the package.Type: ApplicationFiled: October 10, 2013Publication date: April 16, 2015Applicant: United Test and Assembly Center Ltd.Inventors: Nathapong SUTHIWONGSUNTHORN, John Ducyao BELERAN, Serafin Padilla PEDRON, JR.
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Patent number: 8999743Abstract: A solar cell module is manufactured by forming silicone coating films (2, 2) on panels (1a, 1b), placing a solar cell matrix (3) on the silicone coating film on panel (1a), providing a seal member (4) consisting of a base seal member (4a) of butyl rubber and protrusive seal segments (4b) of butyl rubber on a peripheral region of panel (1a), mating the two panels together such that the seal member (4) may abut against a peripheral region of panel (1b), and the solar cell matrix (3) may be sandwiched between the silicone coating films (2), and compressing and heating the mated panels (1a, 1b) in vacuum for establishing a seal around the solar cell matrix (3).Type: GrantFiled: July 1, 2014Date of Patent: April 7, 2015Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Tomoyoshi Furihata, Hiroto Ohwada, Naoki Yamakawa, Masahiro Hinata
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Patent number: 8975150Abstract: A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material so as to cover the semiconductor element; and a via, a wiring layer, an insulation layer, an external terminal, and a solder resist are then formed. The transparent board is then peeled from the semiconductor device through the use of the release material. A chip can thereby be mounted with high precision, there is no need to provide a positioning mark during mounting of the chip on the substrate in the manufacturing process, and the substrate can easily be removed. As a result, a semiconductor device having high density and a thin profile can be manufactured at low cost.Type: GrantFiled: July 25, 2011Date of Patent: March 10, 2015Assignee: Renesas Electronics CorporationInventors: Kentaro Mori, Shintaro Yamamichi, Hideya Murai, Takuo Funaya, Masaya Kawano, Takehiko Maeda, Kouji Soejima
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Patent number: 8970034Abstract: Semiconductor assemblies, structures, and methods of fabrication are disclosed. A coating is formed on an electrically conductive pillar. The coating, which may be formed from at least one of a silane material and an organic solderability protectant material, may bond to a conductive material of the electrically conductive pillar and, optionally, to other metallic materials of the electrically conductive pillar. The coating may also bond to substrate passivation material, if present, or to otherwise-exposed surfaces of a substrate and a bond pad. The coating may be selectively formed on the conductive material. Material may not be removed from the coating after formation thereof and before reflow of the solder for die attach. The coating may isolate at least the conductive material from solder, inhibiting solder wicking or slumping along the conductive material and may enhance adhesion between the resulting bonded conductive element and an underfill material.Type: GrantFiled: May 9, 2012Date of Patent: March 3, 2015Assignee: Micron Technology, Inc.Inventor: Jaspreet S. Gandhi
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Patent number: 8946711Abstract: An organic light-emitting display device including: a substrate; a plurality of pixels each including a first electrode, a second electrode, and an organic emission layer interposed between the first electrode and the second electrode; and a black matrix-containing neutral density (ND) film formed in a direction in which light is emitted from the plurality of pixels.Type: GrantFiled: February 7, 2012Date of Patent: February 3, 2015Assignee: Samsung Display Co., Ltd.Inventor: Jang-Seok Ma
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Patent number: 8945959Abstract: A method for manufacturing an LED (light emitting diode) is disclosed wherein a metal substrate is provided. A chip fastening area with a depression and two wire fixing areas on the first metal substrate are defined on the metal substrate. The chip fastening area and the wire fixing areas are separated by a plurality of first grooves. An LED chip is provided in the depression of the chip fastening area and electrically connected to the wire fixing areas by wires. An encapsulant is formed to cover and connect the chip fastening area and the wire fixing areas. Portions of the metal substrate except the chip fastening area and the wire fixing areas are removed.Type: GrantFiled: June 17, 2013Date of Patent: February 3, 2015Assignee: Advanced Optoelectronic Technology, Inc.Inventors: Pin-Chuan Chen, Chao-Hsiung Chang, Hsin-Chiang Lin
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Patent number: 8940584Abstract: A semiconductor package including a package substrate having a chip mounting region and a peripheral region and including a ground layer formed in the peripheral region, first solder balls on the package substrate in the chip mounting region, second solder balls on the ground layer, at least one semiconductor chip stacked on the package substrate in the chip mounting region, and a package cap covering the semiconductor chip and contacting the package substrate in the peripheral region may be provided. The package cap is electrically connected to the second solder balls. Methods of fabricating the semiconductor package are also provided.Type: GrantFiled: May 8, 2014Date of Patent: January 27, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Tongsuk Kim, Jangwoo Lee, Heeseok Lee, Kyoungsei Choi
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Patent number: 8928147Abstract: Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substract, a semiconductor chip by which the flip chip was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.Type: GrantFiled: July 22, 2014Date of Patent: January 6, 2015Assignee: Renesas Electronics CorporationInventors: Eiji Hayashi, Kyo Go, Kozo Harada, Shinji Baba
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Patent number: 8927341Abstract: An object of the invention is to provide a method for producing a conductive member having low electrical resistance, and the conductive member is obtained using a low-cost stable conductive material composition that does not contain an adhesive. A method for producing a semiconductor device in which silver or silver oxide provided on a surface of a base and silver or silver oxide provided on a surface of a semiconductor element are bonded, includes the steps of arranging a semiconductor element on a base such that silver or silver oxide provided on a surface of the semiconductor element is in contact with silver or silver oxide provided on a surface of the base, and bonding the semiconductor element and the base by applying heat having a temperature of 200 to 900° C. to the semiconductor device and the base.Type: GrantFiled: January 28, 2014Date of Patent: January 6, 2015Assignee: Nichia CorporationInventors: Masafumi Kuramoto, Satoru Ogawa, Miki Niwa
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Patent number: 8916418Abstract: A disclosed surface-emitting laser module includes a surface-emitting laser formed on a substrate to emit light perpendicular to its surface, a package including a recess portion in which the substrate having the surface-emitting laser is arranged, and a transparent substrate arranged to cover the recess portion of the package and the substrate having the surface-emitting laser such that the transparent substrate and the package are connected on a light emitting side of the surface-emitting laser. In the surface-emitting laser module, a high reflectance region and a low reflectance region are formed within a region enclosed by an electrode on an upper part of a mesa of the surface-emitting laser, and the transparent substrate is slanted to the surface of the substrate having the surface-emitting laser in a polarization direction of the light emitted from the surface-emitting laser determined by the high reflectance region and the low reflectance region.Type: GrantFiled: March 16, 2011Date of Patent: December 23, 2014Assignee: Ricoh Company, Ltd.Inventors: Toshihiro Ishii, Satoru Sugawara, Yoshihiro Ohba, Kazuhiro Harasaka, Shunichi Sato, Kazuhiko Adachi
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Patent number: 8912049Abstract: Each LED in an array of LEDs mounted on a submount wafer has at least a first semiconductor layer exposed and connected to a first electrode of each LED. The submount wafer has a first metal portion bonded to the first electrode of each LED for providing an energization current to each LED. The submount wafer also has a second metal portion running along and proximate to the first metal portion but not electrically connected to the first metal portion. The second metal portion may be interdigitated with the first metal portion. The second metal portion is connected to a bias voltage. When the wafer is immersed in an electrically conductive solution for electrochemical (EC) etching of the exposed first semiconductor layer, the solution electrically connects the second metal portion to the first metal portion for biasing the first semiconductor layer during the EC etching.Type: GrantFiled: October 10, 2011Date of Patent: December 16, 2014Assignee: Koninklijke Philips N.V.Inventor: Yajun Wei
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Patent number: 8889441Abstract: The invention provides a wafer-bonded semiconductor device wherein warpage generated when wafers are bonded is reduced at a low cost ad through a simple process. In a method for manufacturing a wafer-bonded semiconductor device by bonding a first wafer substrate and a second wafer substrate together, the method of the invention includes a first step of forming in advance bonding members having a bonding function when heated on the wafer-bonded surface sides of the first wafer substrate and the second wafer substrate, respectively; a second step of supplying flux paste containing two or more kinds of powdery materials having reactivity to the surfaces of the bonding members formed in the first step; and a third step of causing excitation to have the flux paste supplied in the second step start reacting.Type: GrantFiled: October 27, 2010Date of Patent: November 18, 2014Assignee: Hitachi, Ltd.Inventors: Toshiaki Takai, Yukio Sakigawa
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Patent number: 8877557Abstract: An organic light emitting display device is manufactured by: preparing a target substrate that includes sub-pixel areas (each having a thin film transistor) and pixel defining areas (each having a conductive layer) between the sub-pixel areas; preparing an ionized deposition material by vaporizing and ionizing a deposition material; applying a ground voltage to one of the sub-pixel areas while applying a voltage having a same polarity as the ionized deposition material to the neighboring ones of the sub-pixel areas and to the pixel defining areas; and depositing the ionized deposition material on the one of the sub-pixel areas to form an organic thin layer while the one of the sub-pixel areas is polarized by an electric field generated by the voltage being applied to the conductive layer of the pixel defining areas.Type: GrantFiled: December 14, 2012Date of Patent: November 4, 2014Assignee: Samsung Display Co., Ltd.Inventor: Geum Jong Roh
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Patent number: 8847243Abstract: A semiconductor package includes a transmissive support plate and includes at least one elongate hole. An integrated circuit semiconductor device is mounted on a rear face of the support plate. The semiconductor device includes first and second optical elements oriented towards the rear face of the support plate, where the first and second optical elements are placed on either side of the elongate hole. An encapsulation material made of an opaque material encapsulates the semiconductor device and fills the elongate hole so as to form an optical insulation partition between the first and second optical elements. A cavity is left, however, between each optical element and a rear face of the support plate.Type: GrantFiled: March 29, 2012Date of Patent: September 30, 2014Assignee: STMicroelectronics (Grenoble 2) SASInventors: Romain Coffy, Emmanuelle Vigier-Blanc
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Patent number: 8846428Abstract: A method for manufacturing a light emitting diode chip includes the following steps: providing an epitaxial structure having an epitaxial layer; forming a first electrode and a second electrode on the epitaxial layer; coating an inert layer on the epitaxial structure, the first electrode and the second electrode continuously; annealing the first electrode and the second electrode; and removing the inert layer coated on the first electrode and the second electrode to expose the first electrode and the second electrode.Type: GrantFiled: July 16, 2013Date of Patent: September 30, 2014Assignee: Advanced Optoelectronic Technology, Inc.Inventors: Ya-Chi Lien, Tzu-Chien Hung
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Patent number: 8846422Abstract: A method for manufacturing an LED package structure is disclosed wherein a substrate with a first electrode, a second electrode and a connecting layer is provided. A photoresist coating is provided to cover the substrate, the first electrode, the second electrode and the connecting layer. A portion of the photoresist coating is removed to define a groove corresponding to the connecting layer. A metal layer is formed in the groove to join the connecting layer. A remaining portion of the photoresist coating is removed and a concave is formed and surrounded by the metal layer. A reflective layer is formed on an inside surface of the concave to join the metal layer to form a reflective cup. An LED die is mounted in the reflective cup and electrically connects with the first and second electrodes.Type: GrantFiled: December 14, 2012Date of Patent: September 30, 2014Assignee: Advanced Optoelectronic Technology, Inc.Inventors: Pin-Chuan Chen, Hsin-Chiang Lin, Lung-Hsin Chen
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Publication number: 20140264809Abstract: This disclosure provides systems, methods and apparatus for manufacturing display devices having electronic components mounted within a display device package. In one aspect, the electronic component connects to the exterior of the display device through pads that run below a seal that holds a substrate and a backplate of the display device together. In another aspect the electronic components also connect to an electromechanical device within the display device, as well as connecting to pads that are external to the display device.Type: ApplicationFiled: June 2, 2014Publication date: September 18, 2014Applicant: QUALCOMM MEMS Technologies, Inc.Inventors: Ravindra V. Shenoy, Marc Maurice Mignard
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Patent number: 8835199Abstract: A light emitting package comprising a support hosting at least one light emitting diode. A light transmissive dome comprised of a silicone including a phosphor material positioned to receive light emitted by the diode. A glass cap overlies said dome.Type: GrantFiled: July 21, 2011Date of Patent: September 16, 2014Assignee: GE Lighting Solutions, LLCInventors: Boris Kolodin, Anirudha R. Deshpande
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Patent number: 8829543Abstract: A semiconductor light emitting device including a first type doped semiconductor layer, a light emitting layer, a second type doped semiconductor layer, and a reflection layer is provided. The first type doped semiconductor layer has a mesa portion and a depression portion. The light emitting layer is disposed on the mesa portion and has a first surface, a second surface and a first side surface connecting the first surface with the second surface. The second type doped semiconductor layer is disposed on the light emitting layer and has a third surface, a fourth surface and a second side surface connecting the third surface with the fourth surface. Observing from a viewing direction parallel to the light emitting layer, the reflection layer covers at least part of the first side surface and at least part of the second side surface. A flip chip package device is also provided.Type: GrantFiled: March 6, 2013Date of Patent: September 9, 2014Assignee: Genesis Photonics Inc.Inventors: Yun-Li Li, Chih-Ling Wu, Yi-Ru Huang, Yu-Yun Lo
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Patent number: 8796115Abstract: A light-emitting diode arrangement comprising a plurality of semiconductor chips which are provided for emitting electromagnetic radiation from their front side and which are fixed by their rear side—opposite the front side—on a first main face of a common carrier body, wherein the semiconductor chips consist of a respective substrateless semiconductor layer stack and are fixed to the common carrier body without an auxiliary carrier, and to a method for producing such a light-emitting diode arrangement.Type: GrantFiled: April 5, 2012Date of Patent: August 5, 2014Assignee: OSRAM Opto Semiconductors GmbHInventors: Jörg Erich Sorg, Stefan Gruber, Siegfried Herrmann, Berthold Hahn
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Publication number: 20140166762Abstract: Composite cards formed in accordance with the invention include a security layer comprising a hologram or diffraction grating formed at, or in, the center, or core layer, of the card. The hologram may be formed by embossing a designated area of the core layer with a diffraction pattern and depositing a thin layer of metal on the embossed layer. Additional layers may be selectively and symmetrically attached to the top and bottom surfaces of the core layer. A laser may be used to remove selected portions of the metal formed on the embossed layer, at selected stages of forming the card, to impart a selected pattern or information to the holographic region. The cards may be ‘lasered’ when the cards being processed are attached to, and part of, a large sheet of material, whereby the “lasering” of all the cards on the sheet can be done at the same time and relatively inexpensively.Type: ApplicationFiled: February 19, 2014Publication date: June 19, 2014Inventor: JOHN HERSLOW
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Patent number: 8754423Abstract: Embodiments provide a light emitting device package including a package body, at least one electrode pattern placed on the package body, at least one light emitting device electrically connected to the electrode pattern, a heat dissipation member inserted into the package body to thermally come into contact with the light emitting device, and a anti-fracture layer placed on the heat dissipation member. The anti-fracture layer vertically overlaps with at least a partial peripheral region of the heat dissipation member.Type: GrantFiled: September 24, 2013Date of Patent: June 17, 2014Assignee: LG Innotek Co., Ltd.Inventors: Byung Mok Kim, Bo Hee Kang, Ha Na Kim, Hiroshi Kodaira, Yuichiro Tanda, Satoshi Ozeki
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Patent number: 8748228Abstract: A semiconductor package including a package substrate having a chip mounting region and a peripheral region and including a ground layer formed in the peripheral region, first solder balls on the package substrate in the chip mounting region, second solder balls on the ground layer, at least one semiconductor chip stacked on the package substrate in the chip mounting region, and a package cap covering the semiconductor chip and contacting the package substrate in the peripheral region may be provided. The package cap is electrically connected to the second solder balls. Methods of fabricating the semiconductor package are also provided.Type: GrantFiled: August 17, 2012Date of Patent: June 10, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Tongsuk Kim, Jangwoo Lee, Heeseok Lee, Kyoungsei Choi
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Patent number: 8742559Abstract: To suppress the reduction in reliability of a resin-sealed semiconductor device. A first cap (member) and a second cap (member) with a cavity (space formation portion) are superimposed and bonded together to form a sealed space. A semiconductor including a sensor chip (semiconductor chip) and wires inside the space is manufactured in the following way. In a sealing step of sealing a joint part between the caps, a sealing member is formed of resin such that an entirety of an upper surface of the second cap and an entirety of a lower surface of the first cap are respectively exposed. Thus, in the sealing step, the pressure acting in the direction of crushing the second cap can be decreased.Type: GrantFiled: March 14, 2012Date of Patent: June 3, 2014Assignee: Renesas Electronics CorporationInventor: Noriyuki Takahashi
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Patent number: 8741692Abstract: A method for forming semiconductor devices with wafer-level packaging (WLP) includes providing a silicon-on-insulator (SOI) substrate, forming a mask on a silicon layer of the SOI substrate, etching the silicon layer through openings in the mask to form elements initially bonded to but later released from an insulator layer of the SOI substrate, bonding a support substrate to the silicon layer, depositing metal over through holes in the support substrate to contact the silicon layer, and singulating the semiconductor devices from the bonded SOI substrate and the support substrate. The support substrate defines depressions opposite the elements so the elements are not bonded to the support substrate. Each semiconductor device includes a hermetically sealed package having a portion of the SOI substrate and a portion of the support substrate.Type: GrantFiled: September 15, 2011Date of Patent: June 3, 2014Assignee: Advanced NuMicro Systems, Inc.Inventor: Yee-Chung Fu
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Patent number: 8742323Abstract: A semiconductor module including a semiconductor chip having a light receiving device formed at a front thereof and a light permeable cover having a front, a back, and a side. The light permeable cover is disposed opposite to the front of the semiconductor chip such that the front of the semiconductor chip is covered by the back of the light permeable cover. The light permeable cover is provided at the outer circumferential region of the front thereof and at the side thereof with a light shielding layer. It is possible to prevent the incidence of unnecessary light from the side of the light permeable cover of a CSP and to easily adjust the distance between a lens and the front of the semiconductor chip within tolerance.Type: GrantFiled: November 6, 2009Date of Patent: June 3, 2014Assignee: LAPIS Semiconductor Co., Ltd.Inventor: Yoshinori Shizuno
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Patent number: 8735932Abstract: An LED includes a compound semiconductor structure having first and second compound layers and an active layer, first and second electrode layers atop the second compound semiconductor layer and connected to respective compound layers. An insulating layer is coated in regions other than where the first and second electrode layers are located. A conducting adhesive layer is formed atop the non-conductive substrate, connecting the same to the first electrode layer and insulating layer. Formed on one side surface of the non-conductive substrate and adhesive layer is a first electrode connection layer connected to the conducting adhesive layer. A second electrode connection layer formed on another side surface is connected to the second electrode layer. By forming connection layers on respective side surfaces of the light-emitting device, manufacturing costs can be reduced.Type: GrantFiled: October 5, 2011Date of Patent: May 27, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-hyung Kim, Cheol-soo Sone, Jong-in Yang, Sang-yeob Song, Si-hyuk Lee
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Publication number: 20140124917Abstract: A method for alignment of a first substrate coupled to a second substrate includes determining an inclination angle for the first substrate or the second substrate due to warpage. The method includes determining a joint height difference based on the inclination angle and configuring a size for one or more bond pads based on the joint height difference.Type: ApplicationFiled: November 2, 2012Publication date: May 8, 2014Applicant: FUJITSU LIMITEDInventors: Michael G. Lee, Chihiro Uchibori
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Patent number: 8704337Abstract: In one embodiment, a method for manufacturing a semiconductor device includes following steps. An aperture is formed in an interlayer insulating film formed on a semiconductor wafer apart from an integrated circuit portion by etching process. The interlayer insulating film has a dielectric constant smaller than a silicon oxide film (SiO2), and the width of the aperture is larger than a dicing region. A resin layer is embedded in the aperture. An adhesive layer is formed on the interlayer insulating film and the resin layer. The semiconductor wafer is attached to a glass substrate using the adhesive layer by Face Down method. The semiconductor wafer, the resin layer, and the adhesive layer on a dicing region are cut by blade dicing. The semiconductor wafer and the glass substrate adhered to the semiconductor wafer are cut into pieces by the blade dicing of the glass substrate under the dicing region.Type: GrantFiled: September 13, 2010Date of Patent: April 22, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Eiji Takano, Hideo Numata, Kazumasa Tanida
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Patent number: 8679898Abstract: An object of the invention is to provide a method for producing a conductive member having low electrical resistance, and the conductive member is obtained using a low-cost stable conductive material composition that does not contain an adhesive. A method for producing a semiconductor device in which silver or silver oxide provided on a surface of a base and silver or silver oxide provided on a surface of a semiconductor element are bonded, includes the steps of arranging a semiconductor element on a base such that silver or silver oxide provided on a surface of the semiconductor element is in contact with silver or silver oxide provided on a surface of the base, and bonding the semiconductor element and the base by applying heat having a temperature of 200 to 900° C. to the semiconductor device and the base.Type: GrantFiled: January 22, 2010Date of Patent: March 25, 2014Assignee: Nichia CorporationInventors: Masafumi Kuramoto, Satoru Ogawa, Miki Niwa
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Publication number: 20140035609Abstract: A probe card is provided. The probe card includes a probe module and a first carrier board. The probe module has a plurality of probes. The probe module is disposed on the first carrier board. The first carrier board is at least partially light-transmitted and has a plurality of vias and a plurality of conductive fillers. The vias are filled with the conductive fillers, respectively. The probe module is electrically connected to the conductive fillers. With the first carrier board being partially light-transmitted, not only is it feasible to simplify the steps of registering the probe card and a device under test, but it is also feasible for an inspector to inspect the contact between the probe card and the device under test synchronously.Type: ApplicationFiled: July 30, 2013Publication date: February 6, 2014Inventor: JUNG-TANG HUANG
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Publication number: 20140028969Abstract: Methods to form a device whereon flexible component elements are attached upon three-dimensional surfaces are described. In some aspects, the present invention includes incorporating flexible semiconductor devices onto three-dimensional surfaces with electrical contacts. In some aspects, the formed device may be incorporated in an ophthalmic device.Type: ApplicationFiled: July 19, 2013Publication date: January 30, 2014Applicant: Johnson & Johnson Vision Care, Inc.Inventors: Randall B. Pugh, James Daniel Riall, Daniel B. Otts, Adam Toner, Frederick A. Flitsch
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Patent number: 8633507Abstract: An LED includes a base, a first lead and a second lead mounted to the base, a light emitting chip electrically connected to the first lead and the second lead, and an encapsulant sealing the chip. The first lead and the second lead each include a first beam and a second beam connected to each other. Each of the first beam and the second beam has two opposite ends protruding beyond two opposite lateral faces of the base, respectively, for electrically connecting with a circuit board.Type: GrantFiled: August 27, 2012Date of Patent: January 21, 2014Assignee: Advanced Optoelectronic Technology, Inc.Inventors: Hsin-Chiang Lin, Pin-Chuan Chen
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Patent number: 8624371Abstract: Packaging assemblies for optically interactive devices and methods of forming the packaging assemblies in an efficient manner that eliminates or reduces the occurrence of process contaminants. In a first embodiment, a transparent cover is attached to a wafer of semiconductor material containing a plurality of optically interactive devices. The wafer is singulated, and the optically interactive devices are mounted on an interposer and electrically connected with wire bonds. In a second embodiment, the optically interactive devices are electrically connected to the interposer with back side conductive elements. In a third embodiment, the optically interactive devices are mounted to the interposer prior to attaching a transparent cover. A layer of encapsulant material is formed over the interposer, and the interposer and encapsulant material are cut to provide individual packaging assemblies. In a fourth embodiment, the optically interactive devices are mounted in a preformed leadless chip carrier.Type: GrantFiled: April 19, 2013Date of Patent: January 7, 2014Assignee: Round Rock Research, LLCInventors: Todd O. Bolken, Chad A. Cobbley
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Patent number: 8617927Abstract: A method and apparatus for mounting microelectronic chips to a thermal heat sink. The chips are arranged in a desired configuration with their active faces all facing a common direction and with their active faces defining a common planar surface for all of said chips. A metallic material is applied to the chip, preferably by electroplating to backsides of the chips, the metallic material being electro-formed thereon and making void-free contact with the backsides of the chips.Type: GrantFiled: November 29, 2011Date of Patent: December 31, 2013Assignee: HRL Laboratories, LLCInventors: Alexandros D. Margomenos, Miroslav Micovic
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Patent number: 8587118Abstract: Provided is a light emitting device package. The light emitting device package comprises a housing, first and second lead frames, and a light emitting device. The housing comprises a front opening and side openings. The first and second lead frames pass through the housing to extend to an outside. A portion of each lead frame being exposed through the front opening. The light emitting device is in the front opening and electrically connected to the first and second lead frames. A protrusion protruding in a direction of the side opening is formed on an inner surface of the side opening.Type: GrantFiled: June 19, 2008Date of Patent: November 19, 2013Assignee: LG Innotek Co., Ltd.Inventors: Sung Min Kong, Myung Gi Kim, Hyeong Seok Im
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Patent number: 8586422Abstract: A semiconductor device is made by providing a semiconductor die having an optically active area, providing a leadframe or pre-molded laminated substrate having a plurality of contact pads and a light transmitting material disposed between the contact pads, attaching the semiconductor die to the leadframe so that the optically active area is aligned with the light transmitting material to provide a light transmission path to the optically active area, and disposing an underfill material between the semiconductor die and leadframe. The light transmitting material includes an elevated area to prevent the underfill material from blocking the light transmission path. The elevated area includes a dam surrounding the light transmission path, an adhesive ring, or the light transmission path itself can be the elevated area. An adhesive ring can be disposed on the dam. A filler material can be disposed between the light transmitting material and contact pads.Type: GrantFiled: March 13, 2012Date of Patent: November 19, 2013Assignee: STATS ChipPAC, Ltd.Inventors: Zigmund R Camacho, Henry D Bathan, Lionel Chien Hui Tay, Amel Senosa Trasporto
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Patent number: 8563350Abstract: The present invention discloses a wafer level image sensor packaging structure and a manufacturing method for the same. The manufacturing method includes the following steps: providing a silicon wafer with image sensor chips, providing a plurality of transparent lids, allotting one said transparent lid on top of the corresponding image sensor chip, and carrying out a packaging process. The manufacturing method of the invention has the advantage of having a simpler process, lower cost, and higher production yield rate. The encapsulation compound arranges on the first surface of the image sensor chip and covers the circumference of the transparent lid to avoid the side light leakage as traditional chip scale package (CSP). Thus, the sensing performance of the wafer level image sensor packaging structure can be enhanced.Type: GrantFiled: November 16, 2010Date of Patent: October 22, 2013Assignee: Kingpak Technology Inc.Inventors: Hsiu-Wen Tu, Han-Hsing Chen, Chung-Hsien Hsin, Ming-Hui Chen
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Patent number: 8563963Abstract: The present invention relates to a light-emitting diode die package. The LED die package includes a semiconductor base, at least two electrodes disposed on an electrode mounting surface of the semiconductor base, an insulation layer formed on the electrode-mounting surface and provided with two through holes for exposing the electrodes, a conductor-forming layer formed on the insulation layer and provided with two conductor-mounting holes in communication with the through holes, and conductor units formed within the through holes and the conductor-mounting holes in a manner electrically connected to the corresponding electrodes. The LED die package further includes a covering layer formed on a surface of the LED die opposite to the electrode-mounting surface and extending to an outer surface of the LED die. The covering layer is made of transparent material doped with phosphor powder.Type: GrantFiled: September 27, 2010Date of Patent: October 22, 2013Assignee: Evergrand Holdings LimitedInventors: Yu-Nung Shen, Tsung-Chi Wang