Incorporating Resilient Component (e.g., Spring, Etc.) Patents (Class 438/117)
  • Patent number: 9837738
    Abstract: An exemplary miniature support has upper and lower spaced-apart engagement surfaces each having at least a portion that are parallel to each other. Two supports each with an end supporting the upper engagement surface and another end supporting the lower engagement surface. The two supports have a spring-like property so that the upper and lower engagement surfaces can repeatedly move between an uncompressed state when not engaged to provide an interconnection and a compressed state when engaged between two opposing boards to provide an interconnection between the boards. The connector is preferably made using 3-D printing and may be integrally made as part of a board also made using the same 3-D printing. The support may have upper and lower engagement surfaces and at least one of the at least two supports that are conductive to establish connectivity between the upper and lower engagement surfaces.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: December 5, 2017
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Charles M. Jackson, Elizabeth T. Kunkee
  • Patent number: 9818625
    Abstract: Stacked semiconductor die assemblies with thermal spacers and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a thermally conductive casing defining a cavity, a stack of first semiconductor dies within the cavity, and a second semiconductor die stacked relative to the stack of first dies and carried by a package substrate. The semiconductor die assembly further includes a thermal spacer disposed between the package substrate and the thermally conductive casing. The thermal spacer can include a semiconductor substrate and plurality of conductive vias extending through the semiconductor substrate and electrically coupled to the stack of first semiconductor dies, the second semiconductor die, and the package substrate.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: November 14, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Jian Li, Steven K. Groothuis, Michel Koopmans
  • Patent number: 9412689
    Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: August 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Cheng Lin, Chung-Shi Liu, Kuei-Wei Huang, Cheng-Ting Chen, Wei-Hung Lin, Ming-Da Cheng
  • Patent number: 9293442
    Abstract: A first package is bonded to a second package with a structural member located between the first package and the second package for structural support. In an embodiment the structural member is a plate or one or more conductive balls. Once the structural member is in place, the first package is bonded to the second package.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: March 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: An-Jhih Su, Hsien-Wei Chen
  • Patent number: 9209081
    Abstract: A semiconductor grid array package has a first housing member with a cavity that has a cavity floor and cavity walls. A semiconductor die is affixed to the cavity floor. A second housing member is molded to the first housing member and covers an interface surface of the die. Electrically conductive runners are mounted to an external surface of the second housing member. The runners have a wire contacting area and an external connector contacting area. Bond wires are selectively bonded to the external connection pads of the semiconductor die and selectively connected to the wire contacting area of the runners. External electrical connectors are mounted to a designated external connector contacting area.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: December 8, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Fui Yee Lim, Weng Foong Yap
  • Patent number: 9209051
    Abstract: In one embodiment the mounting apparatus mounts an upper chip on a lower chip, and thermally presses the upper chip with the lower chip. The mounting apparatus includes a first movement part for mounting the upper chip on the lower chip and preliminarily bonding by thermal pressing, and a second movement part for mainly bonding the plurality of upper chips preliminarily bonded with the plurality of lower chips for a longer time. The second movement part thermally presses the upper chips preliminarily bonded on the lower chip in a state that the upper chips are adsorbed on an adsorption surface parallel to a loading surface of the lower chip on which the upper chips are loaded.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: December 8, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yukimori Yoshiaki, Kajinami Masato, Ueyama Shinji
  • Patent number: 9147637
    Abstract: A module includes a DCB substrate and a discrete device mounted on the DCB substrate, wherein the discrete device comprises a leadframe, a semiconductor chip mounted on the leadframe and an encapsulation material covering the semiconductor chip.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: September 29, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Roland Rupp, Daniel Domes
  • Patent number: 9034696
    Abstract: A microelectronic assembly or package can include first and second support elements and a microelectronic element between inwardly facing surfaces of the support elements. First connectors and second connectors such as solder balls, metal posts, stud bumps, or the like face inwardly from the respective support elements and are aligned with and electrically coupled with one another in columns. Dielectric reinforcing collars are provided on outer surfaces of the first connectors, second connectors or both, and an encapsulation separates pairs of coupled connectors from one another and may fill spaces between support elements.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: May 19, 2015
    Assignee: Invensas Corporation
    Inventors: Ilyas Mohammed, Belgacem Haba
  • Publication number: 20150123261
    Abstract: An electric power converter that can easily be assembled is provided. An electric power converter includes a semiconductor stacking unit, a frame and a spring unit. The semiconductor stacking unit has a configuration in which the semiconductor modules and coolers are stacked. The spring unit is inserted between one end of the semiconductor stacking unit in a stacking direction, and a support provided on the frame, and fixes the semiconductor stacking unit while applying pressure thereto. The spring unit is provided with a first plate, a second plate, and a coil spring sandwiched between the first and second plates. A recess is provided in the first plate so as to have a gap between the first plate and the end surface of the semiconductor stacking unit. A penetrating passage through which the entire spring unit passes along a bottom of the recess is provided in the spring unit.
    Type: Application
    Filed: January 23, 2012
    Publication date: May 7, 2015
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Ryouji Hironaka, Hitoshi Imura
  • Patent number: 9024421
    Abstract: A semiconductor power module includes at least two sub modules. The sub modules include at least one respective transistor having a collector, an emitter, and a gate. The module includes a connection arrangement having a collector terminal unit for connecting the collectors of the at least two sub modules collectively to external circuit components, at least two emitter terminal units for connecting the respective emitters of the at least two sub modules individually to external circuit components, and at least two gate terminal units for connecting the respective gates of the at least two sub modules individually to external circuit components.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: May 5, 2015
    Assignee: ABB Research Ltd
    Inventors: Didier Cottet, Gunnar Asplund, Stefan Linder
  • Patent number: 9018742
    Abstract: An electronic device includes a semiconductor chip. A contact element, an electrical connector, and a dielectric layer are disposed on a first surface of a conductive layer facing the semiconductor chip. A first conductive member is disposed in a first recess of the dielectric layer. The first conductive member electrically connects the contact element of the semiconductor chip with the conductive layer. A second conductive member is disposed in a second recess of the dielectric layer. The second conductive member electrically connects the conductive layer with the electrical connector.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: April 28, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ivan Nikitin, Joachim Mahler
  • Patent number: 9006035
    Abstract: A fabrication method of manufacturing a package a plurality of electronic components in an encapsulation body, firstly, mounting the plurality of electronic components and one ends of a plurality of metal resilient units on a substrate. After that, the plurality of electronic components and the plurality of metal resilient units are encapsulated on the substrate to form an encapsulation body with another ends of the plurality of metal resilient units exposed on an exterior surface of the encapsulation body. Then etching remaining epoxy resin on the other ends of the plurality of metal resilient units.
    Type: Grant
    Filed: November 17, 2013
    Date of Patent: April 14, 2015
    Assignee: Shunsin Technology (Zhong Shan) Limited
    Inventor: Jun-Yi Xiao
  • Patent number: 8999765
    Abstract: Embodiments of the present description include methods for attaching a microelectronic device to a microelectronic substrate with interconnection structures after disposing of an underfill material on the microelectronic device, wherein filler particles within the underfill material may be repelled away from the interconnection structures prior to connecting the microelectronic device to the microelectronic structure. These methods may include inducing a charge on the interconnection structures and may include placing the interconnection structures between opposing plates and producing a bias between the opposing plates after depositing the underfill material on the interconnection structures.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: April 7, 2015
    Assignee: Intel Corporation
    Inventors: Manish Dubey, Rajendra C. Dias, Yonghao Xiu, Arjun Krishnan, Yiqun Bai, Purushotham Kaushik Muthur Srinath
  • Patent number: 8987889
    Abstract: An integrated electromagnetic interference (EMI) shield for a semiconductor module package. The integrated EMI shield includes a plurality of wirebond springs electrically connected between a ground plane in the substrate of the package and a conductive layer printed on the top of the package mold compound. The wirebond springs have a defined shape that causes a spring effect to provide contact electrical connection between the tops of the wirebond springs and the conductive layer. The wirebond springs can be positioned anywhere in the module package, around all or some of the devices included in the package, to create a complete EMI shield around those devices.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: March 24, 2015
    Assignee: Skyworks Solutions, Inc.
    Inventors: Patrick Lawrence Welch, Yifan Guo
  • Patent number: 8963324
    Abstract: In a semiconductor device, a semiconductor module is pressed against a cooler by a spring member. The spring member is compressed by a beam member that is connected with a strut fixed to the cooler. The cooler has a pressed part in which the semiconductor module is pressed, and a strut fixing part to which the strut is fixed. The strut fixing part has higher rigidity than the pressed part.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: February 24, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Takato Sato, Yukio Onishi, Hiroyuki Kono, Hiroaki Yoshizawa, Toshio Watari, Hiromi Yamasaki
  • Patent number: 8963124
    Abstract: At least first and second Si1-xGex (0?x?1) layers are formed on an insulating film. At least first and second material layers are formed correspondingly to the at least first and second Si1-xGex (0?x?1) layers. A lattice constant of the first Si1-xGex (0?x?1) layer is matched with a lattice constant of the first material layer. A lattice constant of the second Si1-xGex (0?x?1) layer is matched with a lattice constant of the second material layer.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: February 24, 2015
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Masanobu Miyao, Hiroshi Nakashima, Taizoh Sadoh, Ichiro Mizushima, Masaki Yoshimaru
  • Patent number: 8956915
    Abstract: Provided is a semiconductor device including a flexible circuit board which includes a first external electrode provided on a first face and second and third external electrodes provided on a second face; a plurality of memory devices and passive components; a supporter which is provided with a groove on one face; and a computing processor device. The memory devices and the passive components are connected to the first external electrode, the one face of the supporter is bonded on the first face of the flexible circuit board so that the groove houses the memory devices and the passive components. The flexible circuit board is bent along a perimeter of the supporter to be wrapped around a side face and another face of the supporter. On the flexible circuit board, the second external electrode is provided on the second face which is opposite to the first external electrode, and the third external electrode is provided on the second face which is bent to the another face of the supporter.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: February 17, 2015
    Assignees: NEC Corporation, NEC AccessTechnica Ltd.
    Inventors: Takao Yamazaki, Shinji Watanabe, Shizuaki Masuda, Katsuhiko Suzuki
  • Patent number: 8936967
    Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: January 20, 2015
    Assignee: Intel Corporation
    Inventors: Chuan Hu, Shawna M. Liff, Gregory S. Clemons
  • Patent number: 8928114
    Abstract: A discrete Through-Assembly Via (TAV) module includes a substrate, and vias extending from a surface of the substrate into the substrate. The TAV module is free from conductive features in contact with one end of each of the conductive vias.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hua Chen, Chen-Shien Chen, Ching-Wen Hsiao
  • Publication number: 20140374912
    Abstract: Standard solder-based interconnect structures are utilized as mechanical fasteners to attach an IC die in a “flip-chip” orientation to a support structure (e.g., a package base substrate or printed circuit board). Electrical connections between the support structure and the IC die are achieved by curved micro-springs that are disposed in peripheral regions of the IC die and extend through a gap region separating the upper structure surface and the processed surface of the IC die. The micro-springs are fixedly attached to one of the support structure and the IC die, and have a free (tip) end that contacts an associated contact pad disposed on the other structure/IC die. Conventional solder-based connection structures (e.g., solder-bumps/balls) are disposed on “dummy” (non-functional) pads disposed in a central region of the IC die. After placing the IC die on the support structure, a standard solder reflow process is performed to complete the mechanical connection.
    Type: Application
    Filed: June 24, 2013
    Publication date: December 25, 2014
    Inventor: John C. Knights
  • Patent number: 8883563
    Abstract: A microelectronic assembly or package can include first and second support elements and a microelectronic element between inwardly facing surfaces of the support elements. First connectors and second connectors such as solder balls, metal posts, stud bumps, or the like face inwardly from the respective support elements and are aligned with and electrically coupled with one another in columns. The first connectors, the second connectors or both may be partially encapsulated prior to electrically coupling respective pairs of first and second connectors in columns. A method may include arranging extremities of first connectors or second connectors in a temporary layer before forming the partial encapsulation.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: November 11, 2014
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed
  • Patent number: 8865526
    Abstract: A semiconductor device mountable to a substrate is provided. The device includes a semiconductor package having at least one semiconductor die, an electrically conductive attachment region, and a packaging material in which is embedded the semiconductor die and a first portion of the electrically conductive attachment region contacting the die. A metallic shell encloses the embedded semiconductor die and the first portion of the electrically conductive attachment region.
    Type: Grant
    Filed: April 10, 2013
    Date of Patent: October 21, 2014
    Assignee: Vishay General Semiconductor LLC
    Inventors: Ta-Te Chou, Yong-Qi Tian, Xian Li
  • Patent number: 8860042
    Abstract: A light component includes a printed circuit board and a plurality of lighting emitting diodes (LEDs). The printed circuit board has a metal substrate. The LEDs are disposed on the printed circuit board, wherein two opposite edges of the metal substrate protrude out and are bent towards the LEDs to form two metal clamps.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: October 14, 2014
    Assignee: Lextar Electronics Corporation
    Inventors: Xin-Lin Zhou, Chen-Yi Su
  • Patent number: 8851358
    Abstract: One plate-like member and the other plate-like member to be aligned with each other are provided with guide holes and guide portions to be received in the guide holes, respectively. The plate-like members are aligned appropriately, and in a state in which this alignment is held, the guide portions are formed on land portions provided on the other plate-like member so as to be aligned with the guide holes. Accordingly, regardless of presence/absence or size of a process error in the guide holes, the guide portions appropriate to the respective guide holes can be formed. Consequently, by aligning the guide portions with the guide holes, the plate-like members can be aligned appropriately without relative fine adjustment between the members.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: October 7, 2014
    Assignee: Kabushiki Kaisha Nihon Micronics
    Inventors: Tomokazu Saito, Seito Moriyama
  • Publication number: 20140252576
    Abstract: A semiconductor device has a packaging structure in which a top surface of a semiconductor chip 1 is electrically connected to a conductive member 4 through a deformation absorption layer 2a and a joining layer 3a and a bottom surface thereof is electrically connected to a conductive member 5 through a deformation absorption layer 2b and a joining layer 3b. Each of the deformation absorption layers 2a and 2b includes a nano-structure layer 7 arranged at a center of a thickness direction and plate layers 6 and 8 of two layers with the nano-structure layer 7 therebetween. The nano-structure layer 7 has a structure in which a plurality of nano-structures 9 having a size of 1 ?m or less are two-dimensionally arranged and thermal stress due to a thermal deformation difference of each member forming the semiconductor device is absorbed by deformation of the nano-structures 9.
    Type: Application
    Filed: October 31, 2011
    Publication date: September 11, 2014
    Applicant: Hitachi, Ltd.
    Inventors: Hisashi Tanie, Hiroshi Shintani, Naotaka Tanaka
  • Patent number: 8829671
    Abstract: An electrical interconnect between terminals on an IC device and contact pads on a printed circuit board (PCB). The electrical interconnect includes a substrate with a first surface having a plurality of openings arranged to correspond to the terminals on the IC device. A compliant material is located in the openings. A plurality of first conductive traces extend along the first surface of the substrate and onto the compliant material. The compliant material provides a biasing force that resists flexure of the first conductive traces into the openings. Vias extending through the substrate are electrically coupled the first conductive traces. A plurality of second conductive traces extend along the second surface of the substrate and are electrically coupled to a vias. The second conductive traces are configured to electrical couple with the contact pads on the PCB.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: September 9, 2014
    Assignee: Hsio Technologies, LLC
    Inventor: James Rathburn
  • Patent number: 8803185
    Abstract: A light emitting diode package and a method of fabricating the same. The package includes a light emitting diode chip having a first surface and a second surface opposing the first surface, a metal frame (or TAB tape) having leads connected to the light emitting diode chip, and a light-pervious encapsulant encapsulating the light emitting diode chip, wherein the second surface of the chip is exposed from the first light-pervious encapsulant. The metal frame (or TAB tape) connects the light emitting diode chip to an external circuit board. The LED package does not need wire-bonding process. A method of fabricating a light emitting diode package is also provided.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: August 12, 2014
    Inventors: Peiching Ling, Vivek B. Dutta
  • Publication number: 20140220422
    Abstract: The present invention provides electronic systems, including device arrays, comprising functional device(s) and/or device component(s) at least partially enclosed via one or more fluid containment chambers, such that the device(s) and/or device component(s) are at least partially, and optionally entirely, immersed in a containment fluid. Useful containment fluids for use in fluid containment chambers of electronic devices of the invention include lubricants, electrolytes and/or electronically resistive fluids. In some embodiments, for example, electronic systems of the invention comprise one or more electronic devices and/or device components provided in free-standing and/or tethered configurations that decouple forces originating upon deformation, stretching or compression of a supporting substrate from the free standing or tethered device or device component.
    Type: Application
    Filed: March 15, 2013
    Publication date: August 7, 2014
    Inventors: John A. ROGERS, Sheng XU, Jonathan FAN
  • Patent number: 8766427
    Abstract: An RF-power device includes a semiconductor substrate having a plurality of active regions arranged in an array. Each active region includes one or more RF-power transistors. The active regions are interspersed with inactive regions for reducing mutual heating of the RF-power transistors in separate active regions. The devices also includes at least one impedance matching component located in one of the inactive regions of the substrate.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: July 1, 2014
    Assignee: NXP, B.V.
    Inventor: Marnix Bernard Willemsen
  • Patent number: 8766107
    Abstract: Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of making and using such PCBs that include layers of laminate; at least one via hole traversing the layers of laminate, and a via conductor contained within the via hole, the via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a metal having a conductivity lower than the conductivity of copper.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Moises Cases, Tae Hong Kim, Rohan U. Mandrekar, Nusrat I. Sherali
  • Patent number: 8748230
    Abstract: An integrated electromagnetic interference (EMI) shield for a semiconductor module package. The integrated EMI shield includes a plurality of wirebond springs electrically connected between a ground plane in the substrate of the package and a conductive layer printed on the top of the package mold compound. The wirebond springs have a defined shape that causes a spring effect to provide contact electrical connection between the tops of the wirebond springs and the conductive layer. The wirebond springs can be positioned anywhere in the module package, around all or some of the devices included in the package, to create a complete EMI shield around those devices.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: June 10, 2014
    Assignee: Skyworks Solutions, Inc.
    Inventors: Patrick L. Welch, Yifan Guo
  • Patent number: 8742579
    Abstract: A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer. A polymer pillar is formed over the first conductive layer. A second conductive layer is formed over the polymer pillar to create a conductive pillar with inner polymer core. A semiconductor die or component is mounted over the substrate. An encapsulant is deposited over the semiconductor die or component and around the conductive pillar. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The sacrificial substrate and adhesive layers are removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first interconnect structure. The second interconnect structure is electrically connected to the conductive pillar.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: June 3, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Byung Tai Do, Shuangwu Huang
  • Patent number: 8735184
    Abstract: A device includes a semiconductor die having a surface, a plurality of proximity connectors proximate to the surface, and a circuit coupled to at least one of the plurality of proximity connectors. The semiconductor die is configured to communicate voltage-mode signals through capacitive coupling using one or more of the plurality of proximity connectors. The circuit also includes a filter with a capacitive-summing junction to equalize the signals.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: May 27, 2014
    Assignee: Oracle International Corporation
    Inventors: Ronald Ho, Robert D. Hopkins, William S. Coates, Robert J. Drost
  • Patent number: 8716847
    Abstract: Flow diverting structures for preferentially impeding, redirecting or both impeding and redirecting the flow of flowable encapsulant material, such as molding compound, proximate a selected surface or surfaces of a semiconductor die or dice during encapsulation are disclosed. Flow diverting structures may be included in or associated with one or more portions of a lead frame, such as a paddle, tie bars, or lead fingers. Flow diverting structures may also be inserted into a mold in association with semiconductor dice carried on non-lead frame substrates, such as interposers and circuit boards, to preferentially impede, redirect or both impede and redirect the flow of molding compound flowing between and over the semiconductor dice.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: May 6, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Stephen L. James
  • Patent number: 8689436
    Abstract: An align fixture for aligning an electronic component having a receptacle adapted to receive the electronic component and having a first abutting section and a second abutting section, the align fixture further having a first elastic unit and a second elastic unit, the first abutting section is flexibly mounted via the first elastic unit, and the second abutting section is flexibly mounted via the second elastic unit, and the first abutting section and the second abutting section are together adapted to floatingly engage the electronic component.
    Type: Grant
    Filed: August 17, 2010
    Date of Patent: April 8, 2014
    Assignee: Multitest Elektronische Systeme GmbH
    Inventors: Thomas Hofmann, Helmut Scheibenzuber
  • Patent number: 8685778
    Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) cavity includes forming a first sacrificial cavity layer over a lower wiring layer. The method further includes forming a layer. The method further includes forming a second sacrificial cavity layer over the first sacrificial layer and in contact with the layer. The method further includes forming a lid on the second sacrificial cavity layer. The method further includes forming at least one vent hole in the lid, exposing a portion of the second sacrificial cavity layer. The method further includes venting or stripping the second sacrificial cavity layer such that a top surface of the second sacrificial cavity layer is no longer touching a bottom surface of the lid, before venting or stripping the first sacrificial cavity layer thereby forming a first cavity and second cavity, respectively.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Christopher V. Jahnes, Anthony K. Stamper
  • Patent number: 8658911
    Abstract: Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of making and using such PCBs that include layers of laminate; at least one via hole traversing the layers of laminate, and a via conductor contained within the via hole, the via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a metal having a conductivity lower than the conductivity of copper.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: February 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Moises Cases, Tae Hong Kim, Rohan U. Mandrekar, Nusrat I. Sherali
  • Publication number: 20140030852
    Abstract: An integrated electromagnetic interference (EMI) shield for a semiconductor module package. The integrated EMI shield includes a plurality of wirebond springs electrically connected between a ground plane in the substrate of the package and a conductive layer printed on the top of the package mold compound. The wirebond springs have a defined shape that causes a spring effect to provide contact electrical connection between the tops of the wirebond springs and the conductive layer. The wirebond springs can be positioned anywhere in the module package, around all or some of the devices included in the package, to create a complete EMI shield around those devices.
    Type: Application
    Filed: January 14, 2013
    Publication date: January 30, 2014
    Applicant: SKYWORKS SOLUTIONS, INC.
    Inventor: SKYWORKS SOLUTIONS, INC.
  • Publication number: 20140027890
    Abstract: A package that electrically connects an integrated circuit to a printed circuit board includes a frame and a package body that encases a portion of the frame and the integrated circuit. The frame includes a mounting region that is connected to the printed circuit board, and a cantilevering region that cantilevers away from the mounting region. The cantilevering region retains the integrated circuit in a flexible fashion.
    Type: Application
    Filed: July 27, 2013
    Publication date: January 30, 2014
    Applicant: Integrated Device Technology Inc.
    Inventor: Ajay K. Ghai
  • Patent number: 8637789
    Abstract: The present invention relates to a process for producing a metallized textile surface having one or more articles needing or generating electric current. A formulation having at least one metal powder is applied as a component atop a textile surface patternedly or uniformly. At least one article needing or generating electric current is fixed in at least two locations where formulation was applied. A further metal is deposited on the textile surface.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: January 28, 2014
    Assignee: BASF SE
    Inventors: Rene Lochtman, Norbert Wagner, Jürgen Kaczun, Jürgen Pfister, Antonino Raffaele Addamo, Ralf Nörenberg
  • Patent number: 8614514
    Abstract: Standard ribbon bonds are utilized as clamp-like mechanical fasteners to attach an IC die in a “flip-chip” orientation to a support structure (e.g., a package base substrate or printed circuit board). Electrical connections between the support structure and the IC die are achieved by curved micro-springs that extend through an air-gap region separating the upper structure surface and the active surface of the IC die. The micro-springs have an anchor portion fixedly attached to one of the support structure and the IC die, and a free (tip) end that is in nonattached contact with an associated contact pad disposed on the other of the support structure and the IC die. Once the IC die is placed on the support structure, the ribbon bonds are formed between the support structure and the IC die using conventional wedge bonder, but the ribbon bonds connected to the non-active surface of the IC die.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: December 24, 2013
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Vernon Powers, Eugene M. Chow
  • Patent number: 8610265
    Abstract: An electrical interconnect for providing a temporary interconnect between terminals on an IC device and contact pads on a printed circuit board (PCB). The electrical interconnect includes a substrate with a first surface having a plurality of openings arranged to correspond to the terminals on the IC device. A compliant material is located in the openings. A plurality of conductive traces extend along the first surface of the substrate and onto the compliant material. The compliant material provides a biasing force that resists flexure of the conductive traces into the openings. Conductive structures are electrically coupled to the conductive traces over the openings. The conductive structures are adapted to enhance electrical coupling with the terminals on the IC device. Vias electrically extending through the substrate couple the conductive traces to PCB terminals located proximate a second surface of the substrate.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: December 17, 2013
    Assignee: Hsio Technologies, LLC
    Inventor: James Rathburn
  • Patent number: 8604609
    Abstract: A semiconductor package includes a curved body and a plurality of semiconductor die. The curved body includes first and second opposing end regions and an intermediate center region. The curved body has a first inflection point at the center region, a second inflection point at the first end region and a third inflection point at the second end region. The center region has a convex curvature with a minimal extremum at the first inflection point, the first end region has a concave curvature with a maximal extremum at the second inflection point and the second end region has a concave curvature with a maximal extremum at the third inflection point. The plurality of semiconductor die are attached to an upper surface of the curved body between the maximal extrema.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: December 10, 2013
    Assignee: Infineon Technologies AG
    Inventors: Anwar A. Mohammed, Soon Ing Chew, Donald Fowlkes, Alexander Komposch, Benjamin Pain-Fong Law, Michael Opiz Real
  • Patent number: 8592946
    Abstract: An anisotropic wet etch of a semiconductor layer generates facets joined by a ridge running along the center of a pattern in a dielectric hardmask layer on the semiconductor layer. The dielectric hardmask layer is removed and a conformal masking material layer is deposited. Angled ion implantation of Ge, B, Ga, In, As, P, Sb, or inert atoms is performed parallel to each of the two facets joined by the ridge causing damage to implanted portions of the masking material layer, which are removed selective to undamaged portions of the masking material layer along the ridge and having a constant width. The semiconductor layer and a dielectric oxide layer underneath are etched selective to the remaining portions of the dielectric nitride. Employing remaining portions of the dielectric oxide layer as an etch mask, the gate conductor layer is patterned to form gate conductor lines having a constant width.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: November 26, 2013
    Assignee: International Business Machines Corporation
    Inventor: Huilong Zhu
  • Patent number: 8581378
    Abstract: Terminals (2b, 2c) are divided into two along a common boundary, coatings (10, 11) most suitable for two conductive bonding materials (5, 6) to be used are exposed on the terminals (2b, 2c), the most suitable one of the coatings (10, 11) is selected, and the corresponding conductive bonding material (5, 6) is bonded onto the coating. Thus it is possible to improve the reliability of bonding and easily reduce a bonding resistance while suppressing a decrease in the reliability of a semiconductor element 3.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: November 12, 2013
    Assignee: Panasonic Corporation
    Inventors: Toshiyuki Yokoe, Chie Fujioka, Daichi Kumano
  • Patent number: 8581422
    Abstract: A semiconductor module includes a semiconductor device, a first conductive member, a second conductive member, a cylinder, and a cover. The first conductive member is in contact with a first electrode of the semiconductor device. The second conductive member is in contact with a second electrode of the semiconductor device. The cylinder encompasses the semiconductor device and is fixed to the first conductive member, and a first thread groove is formed on the cylinder. A second thread groove is formed on the cover. The cover is fixed to the cylinder by an engagement of the second thread groove with the first thread groove. The semiconductor device and the second conductive member are fixed by being sandwiched between the first conductive member and the cover. The second conductive member includes a portion extending from inside to outside the cylinder by penetrating an outer peripheral wall of the cylinder.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: November 12, 2013
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Masaki Aoshima
  • Patent number: 8575954
    Abstract: Based upon a layout of a semiconductor wafer comprising a plurality of integrated circuits at pre-defined locations, each integrated circuit comprising a set of electrical connection pads, a probe chip contactor is established, having a unit standard cell on the probe side of the probe chip to correspond to each of the arranged integrated circuits. The unit standard cell is stepped and repeated for the probe side of the probe chip contactor, to establish a wafer scale standard cell layout. The opposite contact side of the probe chip contactor is connectable to a central structure, e.g. a Z-block or PC board, typically comprising a fixed array of vias with fixed X, Y, and Z locations. The routing of contact side of the probe chip contactor is preferably routed automatically, such as implemented on one or more computers, to provide electrical connections between the substrate through vias and the Z-block through vias.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: November 5, 2013
    Assignee: Advantest (Singapore) Pte Ltd
    Inventors: Fu Chiung Chong, William R. Bottoms, Erh-Kong Chieh, Nim Cho Lam
  • Patent number: 8571405
    Abstract: A silicon MEMS device can have at least one solder contact formed thereupon. The silicon MEMS device can be configured to be mounted to a circuit board via the solder contact(s). The silicon MEMS device can be configured to be electrically connected to the circuit board via the solder contact(s).
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: October 29, 2013
    Assignee: DigitalOptics Corporation MEMS
    Inventor: Roman C. Gutierrez
  • Patent number: 8564117
    Abstract: The present invention is an apparatus for integrating multiple devices. The apparatus includes a substrate having a first via and a second via, a semiconductor chip positioned on a top portion of the substrate and positioned between the first via and the second via, first and second bumps positioned on the semiconductor chip, and an interposer wafer having a first interposer spring assembly and a second interposer spring assembly, the first interposer spring assembly having a first interposer spring and a first electrical connection attached to the first interposer spring, and the second interposer spring assembly having a second interposer spring and a second electrical connection attached to the second interposer spring.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: October 22, 2013
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventors: Sang Won Yoon, Koji Shiozaki
  • Patent number: 8531042
    Abstract: A processing technique facilitating the fabrication of the integrated circuit with microsprings at different vertical positions relative to a surface of a substrate is described. During the fabrication technique, microsprings are lithographically defined on surfaces of a first substrate and a second substrate. Then, a hole is created through a first substrate. Moreover, the integrated circuit may be created by rigidly mechanically coupling the two substrates to each other such that the microsprings on the surface of the second substrate are within a region defined at least in part by an edge around the hole. Subsequently, photoresist that constrains the microsprings on the surfaces of the two substrates may be removed. In this way, microsprings at the different vertical positions can be fabricated.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: September 10, 2013
    Assignee: Oracle America, Inc.
    Inventors: Robert J. Drost, John E. Cunningham, Ashok V. Krishnamoorthy