Abstract: The present application relates to a chip heat dissipating structure, a chip structure, a circuit board and a supercomputing device, and the chip heat dissipating structure includes a metal layer, where the metal layer is covered on the chip. By adding a metal layer on the top of the chip, the heat sink may be soldered onto the metal layer through a solder layer, so that the heat sink is fixed to the top of the chip; the main component of the solder layer is metal tin, and the metal layer has a higher thermal conductivity than an epoxy resin material mounted on a traditional heat sink, thereby solving a problem of the heat dissipation bottleneck of a resin material in the chip, thus improving a heat dissipation effect of the chip and preventing a large amount of heat from damaging the chip.

Abstract: A semiconductor device includes a first carrier, a first external contact, a second external contact, and a first semiconductor die. The first semiconductor die has a first main face, a second main face opposite to the first main face, a first contact pad disposed on the first main face, a second contact pad disposed on the second main face, a third contact pad disposed on the second main face, and a vertical transistor. The first semiconductor die is disposed with the first main face on the first carrier. A clip connects the second contact pad and the second external contact. A first wire is connected with the first external contact. The first wire is disposed at least partially under the clip.

Abstract: A semiconductor device includes an integrated circuit, first conductive features, second conductive features, a package structure, and an encapsulant. The integrated circuit has an active surface and a rear surface opposite to the active surface. The first conductive features surround the integrated circuit. The second conductive features are stacked on the first conductive features. The package structure is disposed on the second conductive features and the rear surface of the integrated circuit. The encapsulant laterally encapsulates the integrated circuit, the first conductive features, the second conductive features, and the package structure.

Abstract: A method includes attaching an integrated circuit die adjacent to a first substrate, the integrated circuit die comprising: an active device in a second substrate; a pad adjacent to the second substrate; and a first dielectric layer adjacent to the second substrate, the first dielectric layer comprising a polyimide with an ester group; forming an encapsulant around the integrated circuit die; and removing the first dielectric layer.

Abstract: A method includes attaching a die to a thermal compression bonding (TCB) head through vacuum suction, wherein the die comprises a plurality of conductive pillars, attaching a first substrate to a chuck through vacuum suction, wherein the first substrate comprises a plurality of solder bumps, contacting a first conductive pillar of the plurality of conductive pillars to a first solder bump of the plurality of solder bumps, wherein contacting the first conductive pillar to the first solder bump results in a first height between a topmost surface of the first conductive pillar and a bottommost surface of the first solder bump, and adhering the first solder bump to the first conductive pillar to form a first joint, wherein adhering the first solder bump to the first conductive pillar comprises heating the TCB head.

Abstract: Cables, cable connectors, and support structures for cantilever package and/or cable attachment may be fabricated using additive processes, such as a coldspray technique, for integrated circuit assemblies. In one embodiment, cable connectors may be additively fabricated directly on an electronic substrate. In another embodiment, seam lines of cables and/or between cables and cable connectors may be additively fused. In a further embodiment, integrated circuit assembly attachment and/or cable attachment support structures may be additively formed on an integrated circuit assembly.

Abstract: Apparatuses relating generally to a microelectronic package having protection from electromagnetic interference are disclosed. In an apparatus thereof, a platform has an upper surface and a lower surface opposite the upper surface and has a ground plane. A microelectronic device is coupled to the upper surface of the platform. Wire bond wires are coupled to the ground plane with a pitch. The wire bond wires extend away from the upper surface of the platform with upper ends of the wire bond wires extending above an upper surface of the microelectronic device. The wire bond wires are spaced apart from one another to provide a fence-like perimeter to provide an interference shielding cage. A conductive layer is coupled to at least a subset of the upper ends of the wire bond wires for electrical conductivity to provide a conductive shielding layer to cover the interference shielding cage.

Abstract: The present application provides a semiconductor package with air gaps for reducing capacitive coupling between conductive features and a method for manufacturing the semiconductor package. The semiconductor package includes a first semiconductor structure and a second semiconductor structure bonded with the first semiconductor structure. The first semiconductor structure has a first bonding surface. The second semiconductor structure has a second bonding surface partially in contact with the first bonding surface. A portion of the first bonding surface is separated from a portion of the second bonding surface, a space between the portions of the first and second bonding surfaces is sealed and forms an air gap in the semiconductor package.

Abstract: A semiconductor apparatus includes an interconnect substrate having a first major surface, a first semiconductor device having a second major surface and mounted to the interconnect substrate, the second major surface opposing the first major surface, a second semiconductor device having a third major surface and a fourth major surface and mounted to the first semiconductor device, the third major surface opposing the first major surface, the fourth major surface opposing the second major surface, a through hole formed through the interconnect substrate at a position overlapping the second semiconductor device in a plan view taken in a thickness direction of the interconnect substrate, and a heatsink member disposed in contact with part of the third major surface, at least a part of the first major surface, and at least a part of a sidewall surface of the through hole.

Abstract: The present disclosure provides a fan-out packaging structure and a method for fabricating the fan-out packaging. The fan-out packaging structure includes a first redistribution layer, a second redistribution layer, metal connecting posts, a semiconductor chip, a first filling layer, a first packaging layer, a stacked chip package, a passive element, a second filling layer, a second packaging layer, and metal bumps. By means of the present disclosure, various chips having different functions can be integrated into one packaging structure, thereby improving the integration of the fan-out packaging structure. By means of the first redistribution layer, the second redistribution layer, and the metal connecting posts, a three-dimensional vertical stacked packaging is achieved.

Abstract: A manufacturing method for a chip packaging structure, comprising: arranging a metal heat dissipation layer on a substrate comprising at least one flange on its side surface; forming a sealing pin located on an upper surface of the flange, so that the metal heat dissipation layer, the flange and the sealing pin form a cavity for accommodating an encapsulant; attaching a chip structure on an upper surface of the metal heat dissipation layer using an adhesive layer; forming the encapsulant encapsulating an upper surface of the substrate, the metal heat dissipation layer and the chip structure, the sealing pin extends to a periphery of the upper surface of the encapsulant; performing a mechanical or chemical treatment, to make electrode connecting structures on an upper layer of the chip structure exposed outside the first encapsulant; arranging a pin layer for electrically coupling to and covering the electrode connection structures.

Abstract: A package structure includes a substrate, a semiconductor device and an adhesive layer. The semiconductor device is disposed on the substrate, wherein an angle ? is formed between one sidewall of the semiconductor device and one of sides of the substrate, 0°<?<90°. The adhesive layer surrounds the semiconductor device on the substrate and at least continuously disposed at two of the sides of the substrate, wherein the adhesive layer has a first opening misaligned with a corner of the semiconductor device closest to the first opening.

Abstract: Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, an interconnect structure includes dielectric layers, a conductive layer disposed in the dielectric layers, and a via layer disposed in the dielectric layers proximate the conductive layer. An underball metallization (UBM) layer is disposed in the dielectric layers proximate the via layer. A first connector coupling region is disposed in the via layer and the UBM layer. A via layer portion of the first connector coupling region is coupled to a first contact pad in the conductive layer. A second connector coupling region is disposed in the UBM layer. The second connector coupling region is coupled to a conductive segment in the UBM layer and the via layer. The second connector coupling region is coupled to a second contact pad in the conductive layer by the conductive segment.

Abstract: An electronic device includes a metal member and a connected member. A metal connecting layer is provided between a lower-side surface of the metal member and an upper-side surface of the connected member, to connect the metal member and the connected member to each other. The metal connecting layer includes at least one of metal films, each of which is made of gold or gold alloy. A thickness of the metal connecting layer in an opposing area between the metal member and the connected member is smaller than a flatness of each of the lower-side surface and the upper-side surface. A rust-preventing film is formed on a side wall of the metal member in such a way that the rust-preventing film extends from an outer periphery of the metal connecting layer to a position away from the outer periphery by a predetermined distance.

Abstract: Each of a supporting-terminal-equipped capacitor chip and a mounted structure thereof includes a capacitor chip and first and second supporting terminals that each have electric conductivity. A maximum diameter size of the first supporting terminal when viewed in an axial direction is larger than a maximum length size of a portion of a first outer electrode on a second main surface in a length direction. A maximum diameter size of the second supporting terminal when viewed in the axial direction is larger than a maximum length size of a portion of a second outer electrode on the second main surface in the length direction.

Abstract: A heat dissipation apparatus includes a heat dissipation substrate, a heat dissipation component, and a plurality of heat dissipation fins disposed on a first side of the heat dissipation substrate. The heat dissipation fins are configured to dissipate heat on the heat dissipation substrate. A first surface of the heat dissipation component is fastened on a second side of the heat dissipation substrate. There is a gap between a side surface of the heat dissipation component and the heat dissipation substrate, and a second surface of the heat dissipation component is used to be attached to a first to-be-heat-dissipated component, to dissipate heat on the first to-be-heat-dissipated component. An area that is on the second side of the heat dissipation substrate is used to be attached to another to-be-heat-dissipated component. Heating power of the first to-be-heat-dissipated component is greater than heating power of the another to-be-heat-dissipated component.

Abstract: Improved electrically conductive guide plates for vertical probe arrays are provided by patterning a thin metal layer disposed on an insulating substrate. Holes passing through the guide plate for guiding probes can be electrically connected or isolated from each other in any pattern according to the deposition of the metal. Such structures can include several distinct ground and/or voltage planes. Furthermore, passive electrical components can be included in the guide plate, by patterning of the deposited metal and/or by integration of passive electrical components with the deposited metal traces.

Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

Abstract: Probes are connected to the space transformer via multiple carrier plates. Electrical contacts from the probes to the space transformer are by way of spring tail features on the probes that connect to the space transformer and not to the carrier plates. In other words, the carrier plates are purely mechanical in function. This configuration can significantly reduce probe array fabrication time relative to sequential placement of individual probes on the space transformer. Multiple probe carrier plates can be populated with probes in parallel, and the final sequential assembly of carrier plates onto the space transformer has a greatly reduced operation count. Deviations of the space transformer from flatness can be compensated for.

Abstract: According to one embodiment, a semiconductor memory includes a plurality of conductors stacked with insulators being interposed therebetween and a pillar through the plurality of conductors. The pillar includes a first columnar section, a second columnar section, and a joint portion between the first columnar section and the second columnar section. The pillar comprises portions that cross the respective conductors and that each function as part of a transistor. The plurality of conductors include a first conductor. The first conductor is closest to the joint portion among the plurality of conductors through the second columnar section, and includes a bending portion formed along the joint portion.

Abstract: A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.

Abstract: An exemplary miniature support has upper and lower spaced-apart engagement surfaces each having at least a portion that are parallel to each other. Two supports each with an end supporting the upper engagement surface and another end supporting the lower engagement surface. The two supports have a spring-like property so that the upper and lower engagement surfaces can repeatedly move between an uncompressed state when not engaged to provide an interconnection and a compressed state when engaged between two opposing boards to provide an interconnection between the boards. The connector is preferably made using 3-D printing and may be integrally made as part of a board also made using the same 3-D printing. The support may have upper and lower engagement surfaces and at least one of the at least two supports that are conductive to establish connectivity between the upper and lower engagement surfaces.

Abstract: Stacked semiconductor die assemblies with thermal spacers and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a thermally conductive casing defining a cavity, a stack of first semiconductor dies within the cavity, and a second semiconductor die stacked relative to the stack of first dies and carried by a package substrate. The semiconductor die assembly further includes a thermal spacer disposed between the package substrate and the thermally conductive casing. The thermal spacer can include a semiconductor substrate and plurality of conductive vias extending through the semiconductor substrate and electrically coupled to the stack of first semiconductor dies, the second semiconductor die, and the package substrate.

Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

Abstract: A first package is bonded to a second package with a structural member located between the first package and the second package for structural support. In an embodiment the structural member is a plate or one or more conductive balls. Once the structural member is in place, the first package is bonded to the second package.

Abstract: In one embodiment the mounting apparatus mounts an upper chip on a lower chip, and thermally presses the upper chip with the lower chip. The mounting apparatus includes a first movement part for mounting the upper chip on the lower chip and preliminarily bonding by thermal pressing, and a second movement part for mainly bonding the plurality of upper chips preliminarily bonded with the plurality of lower chips for a longer time. The second movement part thermally presses the upper chips preliminarily bonded on the lower chip in a state that the upper chips are adsorbed on an adsorption surface parallel to a loading surface of the lower chip on which the upper chips are loaded.

Abstract: A semiconductor grid array package has a first housing member with a cavity that has a cavity floor and cavity walls. A semiconductor die is affixed to the cavity floor. A second housing member is molded to the first housing member and covers an interface surface of the die. Electrically conductive runners are mounted to an external surface of the second housing member. The runners have a wire contacting area and an external connector contacting area. Bond wires are selectively bonded to the external connection pads of the semiconductor die and selectively connected to the wire contacting area of the runners. External electrical connectors are mounted to a designated external connector contacting area.

Abstract: A module includes a DCB substrate and a discrete device mounted on the DCB substrate, wherein the discrete device comprises a leadframe, a semiconductor chip mounted on the leadframe and an encapsulation material covering the semiconductor chip.

Abstract: A microelectronic assembly or package can include first and second support elements and a microelectronic element between inwardly facing surfaces of the support elements. First connectors and second connectors such as solder balls, metal posts, stud bumps, or the like face inwardly from the respective support elements and are aligned with and electrically coupled with one another in columns. Dielectric reinforcing collars are provided on outer surfaces of the first connectors, second connectors or both, and an encapsulation separates pairs of coupled connectors from one another and may fill spaces between support elements.

Abstract: An electric power converter that can easily be assembled is provided. An electric power converter includes a semiconductor stacking unit, a frame and a spring unit. The semiconductor stacking unit has a configuration in which the semiconductor modules and coolers are stacked. The spring unit is inserted between one end of the semiconductor stacking unit in a stacking direction, and a support provided on the frame, and fixes the semiconductor stacking unit while applying pressure thereto. The spring unit is provided with a first plate, a second plate, and a coil spring sandwiched between the first and second plates. A recess is provided in the first plate so as to have a gap between the first plate and the end surface of the semiconductor stacking unit. A penetrating passage through which the entire spring unit passes along a bottom of the recess is provided in the spring unit.

Abstract: A semiconductor power module includes at least two sub modules. The sub modules include at least one respective transistor having a collector, an emitter, and a gate. The module includes a connection arrangement having a collector terminal unit for connecting the collectors of the at least two sub modules collectively to external circuit components, at least two emitter terminal units for connecting the respective emitters of the at least two sub modules individually to external circuit components, and at least two gate terminal units for connecting the respective gates of the at least two sub modules individually to external circuit components.

Abstract: An electronic device includes a semiconductor chip. A contact element, an electrical connector, and a dielectric layer are disposed on a first surface of a conductive layer facing the semiconductor chip. A first conductive member is disposed in a first recess of the dielectric layer. The first conductive member electrically connects the contact element of the semiconductor chip with the conductive layer. A second conductive member is disposed in a second recess of the dielectric layer. The second conductive member electrically connects the conductive layer with the electrical connector.

Abstract: A fabrication method of manufacturing a package a plurality of electronic components in an encapsulation body, firstly, mounting the plurality of electronic components and one ends of a plurality of metal resilient units on a substrate. After that, the plurality of electronic components and the plurality of metal resilient units are encapsulated on the substrate to form an encapsulation body with another ends of the plurality of metal resilient units exposed on an exterior surface of the encapsulation body. Then etching remaining epoxy resin on the other ends of the plurality of metal resilient units.

Abstract: Embodiments of the present description include methods for attaching a microelectronic device to a microelectronic substrate with interconnection structures after disposing of an underfill material on the microelectronic device, wherein filler particles within the underfill material may be repelled away from the interconnection structures prior to connecting the microelectronic device to the microelectronic structure. These methods may include inducing a charge on the interconnection structures and may include placing the interconnection structures between opposing plates and producing a bias between the opposing plates after depositing the underfill material on the interconnection structures.

Abstract: An integrated electromagnetic interference (EMI) shield for a semiconductor module package. The integrated EMI shield includes a plurality of wirebond springs electrically connected between a ground plane in the substrate of the package and a conductive layer printed on the top of the package mold compound. The wirebond springs have a defined shape that causes a spring effect to provide contact electrical connection between the tops of the wirebond springs and the conductive layer. The wirebond springs can be positioned anywhere in the module package, around all or some of the devices included in the package, to create a complete EMI shield around those devices.

Abstract: At least first and second Si1-xGex (0?x?1) layers are formed on an insulating film. At least first and second material layers are formed correspondingly to the at least first and second Si1-xGex (0?x?1) layers. A lattice constant of the first Si1-xGex (0?x?1) layer is matched with a lattice constant of the first material layer. A lattice constant of the second Si1-xGex (0?x?1) layer is matched with a lattice constant of the second material layer.

Abstract: In a semiconductor device, a semiconductor module is pressed against a cooler by a spring member. The spring member is compressed by a beam member that is connected with a strut fixed to the cooler. The cooler has a pressed part in which the semiconductor module is pressed, and a strut fixing part to which the strut is fixed. The strut fixing part has higher rigidity than the pressed part.

Abstract: Provided is a semiconductor device including a flexible circuit board which includes a first external electrode provided on a first face and second and third external electrodes provided on a second face; a plurality of memory devices and passive components; a supporter which is provided with a groove on one face; and a computing processor device. The memory devices and the passive components are connected to the first external electrode, the one face of the supporter is bonded on the first face of the flexible circuit board so that the groove houses the memory devices and the passive components. The flexible circuit board is bent along a perimeter of the supporter to be wrapped around a side face and another face of the supporter. On the flexible circuit board, the second external electrode is provided on the second face which is opposite to the first external electrode, and the third external electrode is provided on the second face which is bent to the another face of the supporter.

Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.

Abstract: A discrete Through-Assembly Via (TAV) module includes a substrate, and vias extending from a surface of the substrate into the substrate. The TAV module is free from conductive features in contact with one end of each of the conductive vias.

Abstract: Standard solder-based interconnect structures are utilized as mechanical fasteners to attach an IC die in a “flip-chip” orientation to a support structure (e.g., a package base substrate or printed circuit board). Electrical connections between the support structure and the IC die are achieved by curved micro-springs that are disposed in peripheral regions of the IC die and extend through a gap region separating the upper structure surface and the processed surface of the IC die. The micro-springs are fixedly attached to one of the support structure and the IC die, and have a free (tip) end that contacts an associated contact pad disposed on the other structure/IC die. Conventional solder-based connection structures (e.g., solder-bumps/balls) are disposed on “dummy” (non-functional) pads disposed in a central region of the IC die. After placing the IC die on the support structure, a standard solder reflow process is performed to complete the mechanical connection.

Abstract: A microelectronic assembly or package can include first and second support elements and a microelectronic element between inwardly facing surfaces of the support elements. First connectors and second connectors such as solder balls, metal posts, stud bumps, or the like face inwardly from the respective support elements and are aligned with and electrically coupled with one another in columns. The first connectors, the second connectors or both may be partially encapsulated prior to electrically coupling respective pairs of first and second connectors in columns. A method may include arranging extremities of first connectors or second connectors in a temporary layer before forming the partial encapsulation.

Abstract: A semiconductor device mountable to a substrate is provided. The device includes a semiconductor package having at least one semiconductor die, an electrically conductive attachment region, and a packaging material in which is embedded the semiconductor die and a first portion of the electrically conductive attachment region contacting the die. A metallic shell encloses the embedded semiconductor die and the first portion of the electrically conductive attachment region.

Abstract: A light component includes a printed circuit board and a plurality of lighting emitting diodes (LEDs). The printed circuit board has a metal substrate. The LEDs are disposed on the printed circuit board, wherein two opposite edges of the metal substrate protrude out and are bent towards the LEDs to form two metal clamps.

Abstract: One plate-like member and the other plate-like member to be aligned with each other are provided with guide holes and guide portions to be received in the guide holes, respectively. The plate-like members are aligned appropriately, and in a state in which this alignment is held, the guide portions are formed on land portions provided on the other plate-like member so as to be aligned with the guide holes. Accordingly, regardless of presence/absence or size of a process error in the guide holes, the guide portions appropriate to the respective guide holes can be formed. Consequently, by aligning the guide portions with the guide holes, the plate-like members can be aligned appropriately without relative fine adjustment between the members.

Abstract: A semiconductor device has a packaging structure in which a top surface of a semiconductor chip 1 is electrically connected to a conductive member 4 through a deformation absorption layer 2a and a joining layer 3a and a bottom surface thereof is electrically connected to a conductive member 5 through a deformation absorption layer 2b and a joining layer 3b. Each of the deformation absorption layers 2a and 2b includes a nano-structure layer 7 arranged at a center of a thickness direction and plate layers 6 and 8 of two layers with the nano-structure layer 7 therebetween. The nano-structure layer 7 has a structure in which a plurality of nano-structures 9 having a size of 1 ?m or less are two-dimensionally arranged and thermal stress due to a thermal deformation difference of each member forming the semiconductor device is absorbed by deformation of the nano-structures 9.

Abstract: An electrical interconnect between terminals on an IC device and contact pads on a printed circuit board (PCB). The electrical interconnect includes a substrate with a first surface having a plurality of openings arranged to correspond to the terminals on the IC device. A compliant material is located in the openings. A plurality of first conductive traces extend along the first surface of the substrate and onto the compliant material. The compliant material provides a biasing force that resists flexure of the first conductive traces into the openings. Vias extending through the substrate are electrically coupled the first conductive traces. A plurality of second conductive traces extend along the second surface of the substrate and are electrically coupled to a vias. The second conductive traces are configured to electrical couple with the contact pads on the PCB.

Abstract: A light emitting diode package and a method of fabricating the same. The package includes a light emitting diode chip having a first surface and a second surface opposing the first surface, a metal frame (or TAB tape) having leads connected to the light emitting diode chip, and a light-pervious encapsulant encapsulating the light emitting diode chip, wherein the second surface of the chip is exposed from the first light-pervious encapsulant. The metal frame (or TAB tape) connects the light emitting diode chip to an external circuit board. The LED package does not need wire-bonding process. A method of fabricating a light emitting diode package is also provided.

Abstract: The present invention provides electronic systems, including device arrays, comprising functional device(s) and/or device component(s) at least partially enclosed via one or more fluid containment chambers, such that the device(s) and/or device component(s) are at least partially, and optionally entirely, immersed in a containment fluid. Useful containment fluids for use in fluid containment chambers of electronic devices of the invention include lubricants, electrolytes and/or electronically resistive fluids. In some embodiments, for example, electronic systems of the invention comprise one or more electronic devices and/or device components provided in free-standing and/or tethered configurations that decouple forces originating upon deformation, stretching or compression of a supporting substrate from the free standing or tethered device or device component.

Abstract: Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of making and using such PCBs that include layers of laminate; at least one via hole traversing the layers of laminate, and a via conductor contained within the via hole, the via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a metal having a conductivity lower than the conductivity of copper.