Abstract: A semiconductor device is provided having a single-piece clip that interlocks into a lead frame using one or more forks on the clip that mate with one or more corresponding slots in the lead frame. A semiconductor die is mounted to a pad of the lead frame and the clip couples the die to a conductive lead of the lead frame. The interlocking coupling forms a lever that allows adjustment of a position of the clip relative to a region of the semiconductor die. Interference between the clip fork and a slot corresponding to the clip fork confines the lever motion or pivoting of the clip relative to the mounted semiconductor die. The coupling between the clip fork and the slot furthermore confines motion of the clip in each of a first dimension and a second dimension relative to a position of the lead frame.

Abstract: An integrated circuit lid fixture and methods of using the same are provided. In one aspect, an integrated circuit lid fixture is provided that includes a base that has a plurality of pillars. Each of the plurality of pillars has a surface for supporting a substrate that may be removably seated thereon. The surfaces of the plurality of pillars have a first footprint at least as large as a footprint of the substrates to be placed thereon. A plate is provided for applying a compressive force to an integrated circuit lid positioned on any of the substrates removably seated on the pillars.

Abstract: Formation of a plurality of conductive connectors of an integrated circuit package is described. The conductive connectors made with a conductive elastomer material and formed using an interposer that includes a plurality of the conductive connectors linked together.

Abstract: Semiconductor devices,-semiconductor wafers, and semiconductor modules are provided: wherein the semiconductor device has a small warp; damages at chip edge and cracks in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility. The semiconductor device 17 comprising: a semiconductor chip 64; a porous stress relaxing layer 3 provided on the plane, whereon circuits and electrodes are formed, of the semiconductor chip; a circuit layer 2 provided on the stress relaxing layer and connected to the electrodes; and external terminals 10 provided on the circuit layer; wherein an organic protecting film 7 is formed on the plane, opposite to the stress relaxing layer, of the semiconductor chip, and respective side planes of the stress relaxing layer, the semiconductor chip 6, and the protecting film 7 are exposed outside on a same plane.

Abstract: Methods for processing at least one die which comprises an integrated circuit. In one example of a method of the invention, an identification code is applied to a carrier. A singulated die is deposited into the carrier which holds the singulated die. The singulated die comprises an integrated circuit. The identification code may be applied to the carrier before or after depositing the singulated die into the carrier. The carrier may be used in testing the singulated die and may include a plurality of singulated die or just one singulated die. In another example of a method of the invention, an identification code is applied to a die. The die is deposited into a carrier which holds the die. The die comprises an integrated circuit, and the carrier holds the die in singulated form. Typically the die is placed in the carrier without any packaging which may protect the die. The identification code may be applied to the die before or after it is deposited into the carrier.

Abstract: A method for electrically testing a semiconductor wafer during integrated-circuit fabrication process, the method including: (i) providing a scanning charged-particle microscope (SCPM), having a defined scanning plane and operative, while in any one mechanical state, to scan a surface in the scanning plane within a two-dimensional scanning window, which has a given maximum size; (ii) providing in association with any layer of the wafer, it being a test layer, one or more test structures, each test structure including normally conductive areas within a normally non-conductive background in one or more layers, which include said test layer, the conductive areas formed as one or more patterns; the patterns in said test layer include one or more clusters of mutually isolated pads; each pad is conductively connected with a corresponding distinct point on the patterns and all the pads in any one cluster are sized and arranged so that at least a significant portion of each pad falls within a common window whose size

Abstract: The present invention provides a COF flexible printed wiring board whose insulating layer is not melt-adhered to a heating tool, to thereby enhance reliability and productivity of a semiconductor chip mounting line, and also provides a method of producing the COF flexible printed wiring board. The COF flexible printed wiring board contains an insulating layer, a wiring pattern, on which a semiconductor chip being mounted, formed of a conductor layer provided on at least one side of the insulating layer and a releasing layer, wherein the releasing layer is formed from a releasing agent containing at least one species selected from a silane compound and silica sol and is provided on a surface of the insulating layer, which is opposite to the mounting side of the semiconductor chip.

Abstract: A spring contact for establishing electrical contact between a lead element of an IC device and a substrate. The spring contact generally comprises a contact portion and a base portion. The contact portion, which generally comprises a coil-type compression spring, is configured to engage and resiliently bias against a lead element of the IC device. The spring contact is disposed in a mating aperture formed in the substrate. The base portion of the spring contact is configured to secure the spring contact within the mating aperture and to establish electrical contact with the substrate. A plurality of such spring contacts and mating apertures may be arranged on the substrate in an array corresponding to the pin-out of the IC device. A clamping element secures the IC device to the substrate and biases the IC device against the spring contacts.

Abstract: An electronic component includes at least one semiconductor chip, which has an active chip top side with contact areas and has a chip rear side arranged on a carrier top side of a circuit carrier. The circuit carrier and the chip top side are covered by a common rewiring layer having external contact areas at a different level. The different level is matched to a common level of external contact top sides by means of different heights of in part compliant external contacts.

Abstract: A semiconductor package having a substrate mounted die. The die configured having active circuit components and a top surface having bond pads electrically connected with circuitry of the die. The bond pads commonly being formed above active circuit components. The bond pads being electrically interconnected with wire bonds to establish intra-chip electrical connection between circuitry of the die. Methods of forming such packages are also disclosed.

Abstract: Interconnect assemblies and methods for forming and using them. In one example of the invention, an interconnect assembly comprises a substrate, a resilient contact element and a stop structure. The resilient contact element is disposed on the substrate and has at least a portion thereof which is capable of moving to a first position, which is defined by the stop structure, in which the resilient contact element is in mechanical and electrical contact with another contact element. In another example of the invention, a stop structure is disposed on a first substrate with a first contact element, and this stop structure defines a first position of a resilient contact element, disposed on a second substrate, in which the resilient contact element is in mechanical and electrical contact with the first contact element. The stop structure may be formed as a sheet with openings and applied to an unsingulated semiconductor wafer with resilient contacts located in the openings.

Abstract: A semiconductor component has a lower semiconductor element and an upper semiconductor element. A contact-making region is provided between the lower and the upper semiconductor element that makes contact with an upper side of the lower semiconductor element and an underside of the upper semiconductor element. The contact-making region is formed on appropriate extensions of those bonding wires that are used as electrical terminals of the contact-making region.

Abstract: Electronic assemblies and methods for forming assemblies are described. One embodiment includes a method of forming an electronic assembly, including forming a plurality of first solder bumps on one of a substrate and an interposer. The substrate and interposer are positioned so that the first solder bumps are located between the substrate and the interposer. A gap control structure is positioned between the substrate and the interposer. A first reflow operation that reflows and then solidifies the first solder bumps is performed. The first reflow operation couples the interposer to the substrate. A plurality of second solder bumps are formed on one of the interposer and a die. The interposer and die are positioned so that the second solder bumps are located between the interposer and the die. A second reflow operation that reflows and then solidifies the second solder bumps is performed. The second reflow operation couples the die to the interposer.

Abstract: An integrated circuit package which may include the dispense of a second encapsulant material (or fillet) different from the first underfill material on an integrated circuit package which may include an integrated circuit that is mounted to a substrate. The package may further have a first underfill material and a second underfill material that are attached to the integrated circuit and the substrate. The second encapsulant material may be tailored to inhibit cracking of the epoxy itself that propagates into the substrate during thermo-mechanical loading.

Abstract: This invention provides a solution to increase the yield strength and fatigue strength of miniaturized springs, which can be fabricated in arrays with ultra-small pitches. It also discloses a solution to minimize adhesion of the contact pad materials to the spring tips upon repeated contacts without affecting the reliability of the miniaturized springs. In addition, the invention also presents a method to fabricate the springs that allow passage of relatively higher current without significantly degrading their lifetime.

Abstract: A seconductor device (50) includes a semiconductor die (20) having a first surface (14) for forming electronic circuitry. A coating layer (16) formed on a second surface (15) of the semiconductor die has a color that contrasts with the color of the semiconductor die. The coating layer is patterned to expose a portion of the second surface to reveal information pertaining to the semiconductor device. The coating layer is patterned by directing a radiation beam (30) such as a laser to selectively remove material from the coating layer.

Abstract: A submember for electrical device is disclosed. Said submember is mounted on a chip of electrical device. An embodiment for the submember comprised of an insulator and a plurality of conductive elements, wherein the conductive elements embedded in the insulator and a portion of conductive element exposed to the insulator for electrical connection, then (i). the reliability of submember is enhanced; (ii). the material of insulator enables to be saved; and (iii). the thickness of submember is thinner and the heat dissipation of chip enhanced; moreover, a portion of the conductive element may be protruding the insulator for avoiding a short-circuited problem of conductive wire, moreover, the conductive element may be staircase-shaped, then, not only the reliability of submember is enhanced, but the short circuit problem of conductive wire is also avoided; the conductive element may further include an extending portion, furthermore, the conductive element may be placed in a cavity as required.

Abstract: Process for the formation of a spatial chip arrangement having several chips (32, 36, 37, 38, 39) arranged in several planes and electrically connected to one another, in which the chips are connected via their peripheral connection surfaces (33) to assigned conducting paths (23) of a conducting-path structure (24, 25) arranged on at least one carrier substrate (21, 22) by the chips being arranged transverse to the longitudinal extent of the carrier substrate.

Abstract: A semiconductor light emitting device is packaged by forming a sealed compartment enclosing the device, at least one of the walls of the sealed compartment being formed of an elastomeric material. The elastomeric material is then penetrated with a needle and a quantity of softer material is injected through the needle into the sealed compartment. In some embodiments, a coaxial needle or two needles are used, one needle to inject the softer material and one needle to vent air from the compartment.

Abstract: The thermal interface structure of the present invention is suited for use in a non-referenced die system between a heat source and heat sink spaced up to 300 mils apart and comprises a plurality of layers including a core body of high conductivity metal or metal alloy having opposite sides, a soft thermal interface layer disposed on one side of the core body for mounting against the heat sink and a thin layer of a phase change material disposed on the opposite side of the core body for mounting against the heat source wherein the surface area dimension (footprint) of the core body is substantially larger than the surface area of the heat source upon which the phase change material is mounted to minimize the thermal resistance between the heat source and the heat sink and wherein said soft thermal interface layer is of a thickness sufficient to accommodate a variable spacing between the heat source and the heat sink of up to 300 mils.

Abstract: A thin film processing method for processing the thin film by irradiating an optical beam to the thin film. A unit of the irradiation of the optical beam includes a first and a second optical pulse irradiation to the thin film, and the unit of the irradiation is carried out repeatedly to process the thin film. The first and the second optical pulse have pulse waveforms different from each other. Preferably, a unit of the irradiation of the optical beam includes the a first optical pulse irradiated to the thin film and a second optical pulse irradiated to the thin film starting substantially simultaneous with the first optical pulse irradiation. In this case, the relationship between the first and the second optical pulse satisfies (the pulse width of the first optical pulse)<(the optical pulse of the second optical pulse) and (the irradiation intensity of the first optical pulse)?(the irradiation intensity of the second optical pulse).

Abstract: Temporary connections to spring contact elements extending from an electronic component such as a semiconductor device are made by urging the electronic component, consequently the ends of the spring contact elements, vertically against terminals of an interconnection substrate, or by horizontally urging terminals of an interconnection substrate against end portions of the spring contact elements. A variety of terminal configurations are disclosed.

Abstract: Methods of de-fluorinating a wafer surface after damascene processing and prior to photoresist removal are disclosed, as is a related structure. In one embodiment, the method places the wafer surface in a chamber and exposes the wafer surface to a plasma from a source gas including at least one of nitrogen (N2) and/or hydrogen (H2) at a low power density or ion density. The exposing step removes the chemisorbed and physisorbed fluorine residue present on the wafer surface (and chamber), and improves ultra low dielectric (ULK) interconnect structure robustness and integrity. The exposing step is operative due to the efficacy of hydrogen and nitrogen radicals at removing fluorine-based species and also due to the presence of a minimal amount of ion energy in the plasma. The low power density nitrogen and/or hydrogen-containing plasma process enables negligible ash/adhesion promoter interaction and reduces integration complexity during dual damascene processing of low-k OSG-based materials.

Abstract: A method for making an IC package preferably includes providing a mold including first and second mold portions, and wherein the first mold portion carries a mold protrusion defining an IC-contact surface with peripheral edges and a bleed-through retention channel positioned inwardly from the peripheral edges. The method also preferably includes closing the first and second mold portions around the IC and injecting encapsulating material into the mold to encapsulate the IC and make the IC package having an exposed portion of the IC adjacent the mold protrusion. Morever, the bleed-through retention channel retains any encapsulating material bleeding beneath the peripheral edges of the IC contact surface, and prevents the encapsulating material from reaching further onto the exposed portion of the IC. The method may also include releasing the IC package with the exposed portion from the mold.

Abstract: A method of manufacturing a package is disclosed. The manufacturing method includes the steps of providing a substrate having an opening, disposing a metal slice on a bottom surface of the substrate to cover the opening and bond pads on the bottom surface of the substrate, disposing a die on the metal slice inside the opening or above the top surface of the substrate outside the opening, forming a number of bond wires between the top surface of the die and the top surface of the substrate to electrically connect the die to the substrate, forming an encapsulating mold compound to cover the die, the bond wires, and a part of the top surface of the substrate, removing a part of the metal slice to form a metal heat slug thermally connected to the die and to expose the bond pads, and forming a number of solder balls on the exposed bond pads.

Abstract: Numerous embodiments of a heat spreader, comprised of a plurality of downset legs, which provides a simple and lower cost method of forming a heat spreader as compared to conventional methods are disclosed, as well as novel apparatus and methods for attaching the heat spreader to a substrate and a secondary device to the heat spreader, are disclosed.

Abstract: A method of making a microelectronic assembly buying restraining a substrate in a fixture at room temperature, placing a flip chip on the substrate so that conductive bumps on the flip chip are aligned with contact pads on the substrate, heating the flip chip, the substrate and the fixture to reflow the conductive bumps on the flip chip, cooling the flip chip, substrate and fixture to solidify the conductive bumps and to mount the flip chip to the substrate, depositing an underfill between the flip chip and the substrate, curing the underfill by heating the flip chip, substrate, underfill and fixture to an elevated temperature, and removing the flip chip mounted substrate from the fixture.

Abstract: An apparatus in one example includes a compliant component for supporting an electrical interface component that serves to electrically and mechanically couple a die with a separate layer. In one example, the compliant component, upon relative movement between the die and the separate layer, serves to promote a decrease in stress in one or more of the die and the separate layer. The apparatus in another example includes a compliant component for supporting an electrical interface component that serves to create an electrical connection between a die and a separate layer. The compliant component, upon relative movement between the die and the separate layer, serves to promote maintenance of the electrical connection.

Abstract: AS conductive patterns 11A to 11D are formed burying in a insulating resin 10 and a conductive foil 20 is formed being half-etched, thickness of the device is made thin. As an electrode for radiation 11D is provided, a semiconductor device superior in radiation is provided.

Abstract: According to one embodiment of the invention, a method includes providing a semiconductor chip, providing a substrate, forming a plurality of cantilevered springs outwardly from either the semiconductor chip or the substrate, engaging the cantilevered springs with respective contact pads on either the semiconductor chip or the substrate with a fixture, encapsulating the semiconductor chip and cantilevered springs with a molding, and curing the molding.

Abstract: A method of manufacturing a plurality of semiconductor chip packages and the resulting chip package assemblies. The method includes providing a circuitized substrate having terminals and leads. A first microelectronic element is arranged with the substrate and contacts on the microelectronic element are connected to the substrate. A conductive member is placed on top of the first microelectronic element and is used to support a second microelectronic element. The second microelectronic element is arranged with the conductive member in a top and bottom position. The second microelectronic element is then also connected by leads from contacts on the second microelectronic element to pads and terminals on the circuitized substrate. The conductive member is then connected to a third pad or set of pads on the substrate. An encapsulant material may be deposited so as to encapsulate the leads and at least one surface of the microelectronic elements.

Abstract: A flexible, compliant layer of a single low modulus material for connecting a chip die directly to a circuit card without encapsulation. The flexible compliant layer provides stress relief caused by CTE thermal mismatch in chip die and circuit card. An array of copper plated vias are formed in said compliant layer with each via terminating on opposing surfaces of the layer in copper pads. Rather than copper, other metals, such as gold or nickel, may also be used. An array of holes may be positioned between said array of vias to provide additional resiliency. The plated vias may be angled with respect to said opposing surfaces to allow additional vertical and horizontal stress relief. Connection of the pads on one surface to high melt C-4 solder balls or columns on a chip die results in solder filled vias. Low melt solder connection of the pads on the other surface to a circuit card allows non-destructive rework of the cards.

Abstract: A heat dissipating element (e.g., a heat sink) is held in an initial position closer to a heat generating structure (e.g., a microprocessor) and in a subsequent position farther from the microprocessor. A thermal interface material (e.g., a thermal grease) spans the gap, but is not held under compression, between the heat sink and the microprocessor.

Abstract: The invention involves a method of packaging and interconnecting four power transistor dies to operate at a first frequency without oscillation at a second frequency higher than the first frequency but lower than a cutoff frequency of the transistors. The method comprises mounting the dies on a substrate with a lower side (drain) of each die electrically and thermally bonded to a first area of a conductive layer on the substrate; electrically connecting a source of each die to a second area of the conductive layer on the substrate; and electrically connecting a gate of each die to a third, common interior central area of the conductive layer on the substrate via separate electrical leads.

Abstract: A semiconductor mounting arrangement inclusive of a heat sink member enabling desirable resistance to physical impact damage to the semiconductor device, the heat sink and the printed circuit board supporting the semiconductor device and the heat sink. The heat sink is fabricated of thermally and electrically conductive metal such as copper and captured by metallic interconnection such as soldering to conductors of the printed circuit board. Efficient thermal and electrical conductivity between semiconductor device and heat sink are achieved also by metallic interconnection such as soldering intermediate the semiconductor device and the heat sink. Desirable semiconductor device performance under extreme electrical and physical force transient loading conditions are disclosed.

Abstract: A method and apparatus for assembling laser diode arrays. The invention includes the use of vacuum forces and a bi-metallic clip to place a diode array and substrate in proper alignment, and to maintain that alignment while solder pre-forms are melted in an oven to accomplish a mass fusion of the assembly.

Abstract: A new type of high-Q variable capacitor includes a substrate, a first electrically conductive layer fixed to the substrate, a dielectric layer fixed to a portion of the electrically conductive layer, and a second electrically conductive layer having an anchor portion and a free portion. The anchor portion is fixed to the dielectric layer and the free portion is initially fixed to the dielectric layer, but is released from the dielectric layer to become separated from the dielectric layer, and wherein an inherent stress profile in the second electrically conductive layer biases the free portion away from the dielectric layer. When a bias voltage is applied between the first electrically conductive layer and the second electrically conductive layer, electrostatic forces in the free portion bend the free portion towards the first electrically conductive layer, thereby increasing the capacitance of the capacitor.

Abstract: A circuit module including at least one Application Specific Integrated Circuit (ASIC) and a plurality of Vertical Cavity Surface-Emitting Laser (VCSEL) array modules is built using a standard ceramic or organic Multi-Chip Module (MCM) package substrate, resulting is a high density device with a small footprint. Interconnection between the electronic devices and the VCSEL array modules is accomplished using standard integrated circuit packaging technology and flexible connectors. Optical connections from the VCSEL arrays to fiber optic cables are made possible by integrating industry-standard optical connectors onto the package. Optical receiver and transceiver modules may also be incorporated into the circuit module.

Abstract: We disclose a technique to generate stretched solder columns (bumps) at the wafer level, suitable for wafer level packaging. This is accomplished through use of using two wafers—the standard (functional) wafer that contains the integrated circuits and a master (dummy) wafer on whose surface is provided an array of solder bumps that is the mirror image of that on the functional wafer. After suitable alignment, both sets of solder bumps are melted and then slowly brought together till they merge. Then, as they cool, they are slowly pulled apart thereby stretching the merged solder columns. Once the latter have fully solidified, they are separated from the master wafer only.

Abstract: A method of manufacturing a semiconductor package including a substrate for mounting and fixing a semiconductor ship thereon and a connecting pattern, includes providing the substrate with an elongate opening formed therein, fixing the semiconductor chip with its surface mounted on the substrate and with its electrode being aligned within the elongate opening, and electrically an electrode of the semiconductor chip to the connecting pattern via wires through the elongate opening. The elongate opening and the wires then are sealed with resin.

Abstract: Methods for processing at least one die which comprises an integrated circuit. In one example of a method of the invention, an identification code is applied to a carrier. A singulated die is deposited into the carrier which holds the singulated die. The singulated die comprises an integrated circuit. The identification code may be applied to the carrier before or after depositing the singulated die into the carrier. The carrier may be used in testing the singulated die and may include a plurality of singulated die or just one singulated die. In another example of a method of the invention, an identification code is applied to a die. The die is deposited into a carrier which holds the die. The die comprises an integrated circuit, and the carrier holds the die in singulated form. Typically the die is placed in the carrier without any packaging which may protect the die. The identification code may be applied to the die before or after it is deposited into the carrier.

Abstract: The present invention provides a method for connecting an integrated circuit to a substrate, which has the following steps: provision of a first electrical contact structure on a first main area of the integrated circuit; provision of a corresponding second electrical contact structure on an upper side of the substrate; at least one of the first and second electrical contact structures having elastic elevations; attachment of a second main area of the integrated circuit to a frame structure; placement of the first electrical contact structure onto the second electrical contact structure, so that the two are in electrical contact; and attachment of the frame structure to the substrate in such a way that the elastic elevations are under compressive stress. The invention likewise provides a corresponding circuit arrangement.

Abstract: Coupling components to an underlying substrate using a composition of a polymer and magnetic material particles. Upon applying the composition between the component and the printed circuit board, the composition may be subjected to a magnetic field to align the magnetic material particles into a conductive path between the component and the underlying substrate. At the same time the polymer-based material may be cured or otherwise solidified to affix the conductive path formed by the magnetic material particles.

Abstract: A method for producing a corrosion-resistant channel in a wetted path of a silicon device enables such device to be used with corrosive compounds, such as fluorine. A wetted path of a MEMS device is coated with either (1) an organic compound resistant to attack by atomic fluorine or (2) a material capable of being passivated by atomic fluorine. The device is then exposed to a gas that decomposes into active fluorine compounds when activated by a plasma discharge. One example of such a gas is CF4, an inert gas that is easier and safer to work with than volatile gases like ClF3. The gas will passivate the material (if applicable) and corrode any exposed silicon. The device is tested in such a manner that any unacceptable corrosion of the wetted path will cause the device to fail. If the device operates properly, the wetted path is deemed to be resistant to corrosion by fluorine or other corrosive compounds, as applicable.

Abstract: Methods are disclosed for fabricating spring structures that minimize helical twisting by reducing or eliminating stress anisotropy in the thin films from which the springs are formed through manipulation of the fabrication process parameters and/or spring material compositions. In one embodiment, isotropic internal stress is achieved by manipulating the fabrication parameters (i.e., temperature, pressure, and electrical bias) during spring material film information to generate the tensile or compressive stress at the saturation point of the spring material. Methods are also disclosed for tuning the saturation point through the use of high temperature or the incorporation of softening metals. In other embodiments, isotropic internal stress is generated through randomized deposition (e.g., pressure homogenization) or directed deposition techniques (e.g., biased sputtering, pulse sputtering, or long throw sputtering). Cluster tools are used to separate the deposition of release and spring materials.

Abstract: A semiconductor device in a computer system is disclosed that includes a die having an active surface bearing integrated circuitry, the die including a plurality of bond pads thereon at least some of which are connected to the integrated circuitry and having at least one electrically conductive wire bond made between first and second bond pads of the plurality of bond pads for providing external electrical connection between the two bond pads.

Abstract: An integrated circuit package comprises a cavity for housing an integrated circuit (IC) and an antenna provided as part of the package that is located substantially outside the cavity. The antenna may be located on the floor of the IC package that lies in the region outside of the IC cavity. Alternatively, the antenna may be located on the upper or lower surface of the lid sealing the IC package. The antenna may be placed in the floor or on a surface of the IC lid by forming depressions in the floor or lid surface and depositing conductive material in the depressions. The conductive material deposition may be by sputtering, evaporation, or other known physical or chemical deposition method. Antennas formed in the upper surface of an IC lid may be coupled to a pin of the IC package so that the antenna may be electrically coupled to a transceiver component on the IC within the package.

Abstract: A test probe includes a conductive trace with a bumped terminal, the bumped terminal includes a jagged contact surface and a cavity that face in opposite directions, and the contact surface includes a plated metal. The contact surface is jagged due to particles which may protrude, be covered or dislodged. Preferably, the test probe includes an elastomer that fills the cavity so that the bumped terminal is compliant. The test probe is well-suited for pressure contact with semiconductor chips, BGA packages and other electronic devices.

Abstract: A wired circuit board that can control characteristic impedance at connection points between wires of a suspension board with circuit and terminal portions of the wired circuit board connected thereto with a simple structure, to improve signal transmission efficiency even for fine pitch wiring or for high frequency signal. To provide this wired circuit board, a relay flexible wiring circuit board 1 is formed by a first wired circuit board 14 comprising a first metal substrate 16, a first insulating base layer 17, a first conductor layer 18 and a first insulating cover layer 19 which is substantially identical in layer structure with the suspension board with circuit 3 and a second wired circuit board 15 connected with the first wired circuit board 14 for connecting with a control circuit board 4.

Abstract: An interconnection element and a method of forming an interconnection element. In one embodiment, the interconnection element includes a first structure and a second structure coupled to the first structure. The second structure coupled with the first material has a spring constant greater than the spring constant of the first structure alone. In one embodiment, the interconnection element is adapted to be coupled to an electronic component tracked as a conductive path from the electronic component. In one embodiment, the method includes forming a first (interconnection) structure coupled to a substrate to define a shape suitable as an interconnection in an integrated circuit environment and then coupling, such as by coating, a second (interconnection) structure to the first (interconnection) structure to form an interconnection element.