Abstract: A method of manufacturing a core substrate having an electronic component, including providing a core substrate having a first surface and a second surface on an opposite side of the first surface, forming a through hole extending from the first surface to the second surface in the core substrate, attaching an adhesive tape to the second surface of the core substrate such that the through hole formed in the core substrate is closed on the second surface, attaching an electronic component to the adhesive tape inside the through hole, filling the through hole with a filler, and removing the adhesive tape from the second surface of the core substrate.

Abstract: Embodiments of microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the fabrication method includes printing a patterned die attach material onto the backside of a wafer including an array of non-singulated microelectronic die each having an interior keep-out area, such as a central keep-out area. The die attach material, such as a B-stage epoxy, is printed onto the wafer in a predetermined pattern such that the die attach material does not encroaching into the interior keep-out areas. The wafer is singulated to produce singulated microelectronic die each including a layer of die attach material. The singulated microelectronic die are then placed onto leadframes or other package substrates with the die attach material contacting the package substrates. The layer of die attach material is then fully cured to adhere an outer peripheral portion of the singulated microelectronic die to its package substrate.

Abstract: A printed circuit board assembly and method of assembly in which underfill is placed between a chip and substrate to support the chip. A trench is formed in the upper layer of the printed circuit board to limit the flow of the underfill and in particular to limit the underfill from contact with adjacent components so that the underfill does not interfere with adjacent components on the printed circuit board assembly.

Abstract: A method includes bonding a carrier over a top die. The method further includes curing an underfill disposed between a substrate and the top die. The method further includes applying a force over the carrier during the curing. The method further includes removing the carrier from the top die.

Abstract: Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.

Abstract: An adhesive for a semiconductor, comprising an epoxy resin, a curing agent, and a compound having a group represented by the following formula (1): wherein R1 represents an electron-donating group.

Abstract: A packaging substrate and a semiconductor package using the packaging substrate are provided. The packaging substrate includes: a substrate body having a die attach area, a circuit layer formed around the die attach area and having a plurality of conductive traces each having a wire bonding pad, and a surface treatment layer formed on the wire bonding pads. Therein, only one of the conductive traces is connected to an electroplating line so as to prevent cross-talk that otherwise occurs between conductive traces due to too many electroplating lines in the prior art.

Abstract: A semiconductor package includes a baseplate having a die attach region and a peripheral region, a transistor die having a first terminal attached to the die attach region, and a second terminal and a third terminal facing away from the baseplate, and a frame including an electrically insulative member having a first side attached to the peripheral region of the baseplate, a second side facing away from the baseplate, a first metallization at the first side of the insulative member and a second metallization at the second side of the insulative member. The insulative member extends outward beyond a lateral sidewall of the baseplate. The first metallization is attached to the part of the first side which extends outward beyond the lateral sidewall of the baseplate. The first and second metallizations are electrically connected at a region of the insulative member spaced apart from the lateral sidewall of the baseplate.

Abstract: The adhesive sheet of the invention comprises a resin composition containing (A) a high-molecular-weight component, (B1) a thermosetting component having a softening point of below 50° C., (B2) a thermosetting component having a softening point of between 50° C. and 100° C. and (C) a phenol resin having a softening point of no higher than 100° C., the composition containing 11 to 22 mass % of the (A) high-molecular-weight component, 10 to 20 mass % of the (B1) thermosetting component having a softening point of below 50° C., 10 to 20 mass % of the (B2) thermosetting component having a softening point of between 50° C. and 100° C. and 15 to 30 mass % of the phenol resin having a softening point of no higher than 100° C., based on 100 mass % of the resin composition.

Abstract: Provided is a semiconductor device including a flexible circuit board which includes a first external electrode provided on a first face and second and third external electrodes provided on a second face; a plurality of memory devices and passive components; a supporter which is provided with a groove on one face; and a computing processor device. The memory devices and the passive components are connected to the first external electrode, the one face of the supporter is bonded on the first face of the flexible circuit board so that the groove houses the memory devices and the passive components. The flexible circuit board is bent along a perimeter of the supporter to be wrapped around a side face and another face of the supporter. On the flexible circuit board, the second external electrode is provided on the second face which is opposite to the first external electrode, and the third external electrode is provided on the second face which is bent to the another face of the supporter.

Abstract: An apparatus for performing communication control includes a control module implemented with at least one integrated circuit (IC) whose package includes a plurality of sets of terminals, each set of the plurality of sets of terminals corresponding to one of a plurality of sub-modules of the control module, and within the sets of terminals, a set of terminals corresponding to a specific sub-module of the sub-modules include a power-input terminal arranged to input power from outside the control module. For example, on a printed circuit board (PCB) of the apparatus, arrangement of some modules is similar to that of some contact pads associated to the sets of terminals. In another example, the control module includes a power distribution system including at least one power distribution wire. In another example, a PCB within the apparatus includes at least one signal transmission wire and at least one set of co-plane ground wires.

Abstract: A method of fabricating a microelectronic package can include mounting a microelectronic element to a substrate with a joining material. The mounting can include bonding a front surface of the microelectronic element to a first surface of the substrate with a joining material, and joining contacts arranged within a contact-bearing region of the front surface of the microelectronic element with corresponding substrate contacts at the substrate first surface, the joining creating electrical contact between the microelectronic element and the substrate. The method can also include forming an underfill between the substrate first surface and the contact-bearing region of the front surface of the microelectronic element, the underfill reinforcing the joints between the contacts and the substrate contacts, the joining material having a Young's modulus less than 75% of a Young's modulus of the underfill.

Abstract: The present invention enables additional processes required for forming vertical wiring and rewiring in a double face package (DFP) or a wafer level chip size package (WLCSP) to be implemented through use of a component for vertical wiring and rewiring, to thereby simplify the manufacturing process and reduce cost. An electronic component for interconnection is incorporated into an electronic device package in which a circuit element including a semiconductor chip is disposed and which has external electrodes connected to the circuit element via vertical interconnects and horizontal interconnects.

Abstract: To enhance the reliability of a semiconductor device. The semiconductor device includes a wiring substrate having a plurality of bonding fingers (terminal) formed on a chip-mounting surface, a semiconductor chip mounted on the wiring substrate, a plurality of wires having a ball part and a stitch part respectively. The bonding fingers have a first bonding finger to which the stitch part of the first wire is coupled respectively, and the second bonding finger to which a ball part of the second wire is coupled. In addition, in plan view, the second bonding finger is arranged at a position different from the arrangement of a plurality of first bonding fingers, and the width of the second bonding finger is larger than the width of the first bonding finger.

Abstract: An adhesive for a semiconductor, containing an epoxy resin, a curing agent, and a fluxing agent comprising a compound having a group represented by the following formula (1-1) or (1-2): wherein R1 represents an electron-donating group; and a plurality of R1 may be identical or different from each other.

Abstract: There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process.

Abstract: Embodiments provide a method of forming a chip package. The method may include attaching at least one chip on a carrier, the chip including a plurality of chip pads on a surface of the chip opposite to the carrier; depositing a first adhesion layer on the carrier and on the chip pads of the chip, the first adhesion layer including tin or indium; depositing a second adhesion layer on the first adhesion layer, the second adhesion layer including a silane organic material; and depositing a lamination layer or an encapsulation layer on the second adhesion layer and the chip.

Abstract: A wiring substrate includes an adhesive layer, a wiring layer, and a support substrate. The adhesive layer includes a first surface and a second surface that is opposite to the first surface. The wiring layer is formed on the first surface of the adhesive layer. The support substrate is formed on the second surface of the adhesive layer. The wiring layer is partially exposed in a through hole extending through the adhesive layer and the support substrate in a thicknesswise direction. The support substrate is adhered to the adhesive layer in a removable manner.

Abstract: An electronic component package includes a substrate having a first surface, an electronic component mounted to the substrate, traces on the first surface, a terminal on the first surface, and a solder mask on the first surface. The solder mask includes a solder mask opening exposing the terminal. An electrically conductive coating and/or conductive coating feature is formed on the solder mask and extends into the solder mask opening to contact and be electrically connected to the terminal. The conductive coating may be grounded to shield the electronic component from electromagnetic interference (EMI). Further, the conductive coating provides a ground plane for the traces facilitating impedance matching of signals on the traces. In addition, the conductive coating has a high thermal conductivity thus enhancing heat dissipation from the electronic component.

Abstract: A multi-die package includes a first semiconductor die and a second semiconductor die each having an upper surface with a plurality of bond pads positioned thereon. The multi-die package also includes a plurality of bonding wires each coupling one of the bond pads on the upper surface of the first semiconductor die to a corresponding one of the bond pads on the upper surface of the second semiconductor die. A bonding wire of the plurality of bonding wires includes a first portion extending upward from one of the second plurality of bond pads substantially along a z-axis and curving outward substantially along x and y axes in a direction towards the first semiconductor die. The bonding wire also includes a second portion coupled to the first portion and extending from the first portion downward to one of the first plurality of bond pads on the upper surface of the first semiconductor die.

Abstract: A semiconductor package including a package substrate having a chip mounting region and a peripheral region and including a ground layer formed in the peripheral region, first solder balls on the package substrate in the chip mounting region, second solder balls on the ground layer, at least one semiconductor chip stacked on the package substrate in the chip mounting region, and a package cap covering the semiconductor chip and contacting the package substrate in the peripheral region may be provided. The package cap is electrically connected to the second solder balls. Methods of fabricating the semiconductor package are also provided.

Abstract: A package structure includes a thin chip substrate, a stabilizing material layer, a chip and a filling material. A first circuit metal layer of the substrate is inlaid into a dielectric layer and a co-plane is defined by the first circuit metal layer and the dielectric layer and is exposed from the dielectric layer. The bonding pads of the substrate are on the co-plane, have a height higher than the co-plane and connected to the first circuit metal layer. The stabilizing material layer is provided on two sides of the co-plane to define a receiving space for accommodating the chip. The filling material is injected into the receiving space to fasten the pins of the chip securely with bonding pads. Since no plastic molding is required, a total thickness of the package structure and the cost is reduced. The stabilizing material layer prevents the substrate from warping and distortion.

Abstract: Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member, a first die attached to the support member, and a second die attached to the first die in a stacked configuration. The device can also include an attachment feature between the first and second dies. The attachment feature can be composed of a dielectric adhesive material. The attachment feature includes (a) a single, unitary structure covering at least approximately all of the back side of the second die, and (b) a plurality of interconnect structures electrically coupled to internal active features of both the first die and the second die.

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a first semiconductor wafer and a second semiconductor wafer bonded via a hybrid bonding structure, and the hybrid bonding structure includes a first conductive material embedded in a polymer material and a second conductive material embedded in a second polymer material. The first conductive material of the first semiconductor wafer bonded to the second conductive material of the second semiconductor wafer and the first polymer material of the first semiconductor wafer is bonded to the second polymer material of the second semiconductor wafer. The semiconductor device structure further includes at least one through substrate via (TSV) extending from a bottom surface of the second semiconductor wafer to a top surface of the first semiconductor wafer.

Abstract: A substrate includes a first wiring substrate, a second wiring substrate, and an adhesive sheet. The first wiring substrate includes a number of first connecting pads and a first penetrating room. The second wiring substrate includes a number of second connecting pads. The adhesive sheet includes a number of through holes and a second penetrating room. The through holes are filled with a conducting material. The adhesive sheet and the first wiring substrate are orderly pressed on the second wiring substrate. The conducting material is connected to the first connecting pads and the second connecting pads. The first penetrating room of the first wiring substrate and the second penetrating room of the adhesive sheet cooperatively form a receiving recess.

Abstract: A semiconductor device has a semiconductor wafer with a plurality of semiconductor die separated by a non-active region. The semiconductor die can be circular or polygonal with three or more sides. A plurality of bumps is formed over the semiconductor die. A portion of semiconductor wafer is removed to thin the semiconductor wafer. A wafer ring is mounted to mounting tape. The semiconductor wafer is mounted to the mounting tape within the wafer ring. The mounting tape includes translucent or transparent material. A penetrable layer is applied over the bumps formed over the semiconductor wafer. An irradiated energy from a laser is applied through the mounting tape to the non-active region to form a modified region within the non-active region. The semiconductor wafer is singulated along the modified region to separate the semiconductor die.

Abstract: A light-emitting structure comprises a semiconductor light-emitting element which includes a first connection point and a second connection point. The light-emitting structure further includes a first electrode electrically connected to the first connection point, and a second electrode electrically connected the second connection point. The first electrode and the second electrode can form a concave on which the semiconductor light-emitting element is located.

Abstract: An LED manufacturing method includes following steps: providing an LED die; providing an electrode layer having a first section and a second section electrically insulated from the first section, and arranging the LED die on the second section wherein an electrically conductive material electrical connects a bottom of the LED die with second section; forming a transparent conductive layer to electrically connect a top of the LED die with the first section; providing a base and coating an outer surface of the base with a layer of electrically conductive material, defining a continuous gap in the electrically conductive material to divide the electrically conductive material into a first electrode part, and a second electrode part, arranging the electrode layer on the base so that the first section contacts the first electrode part, and the second section contacts the second electrode part.

Abstract: A coreless package structure and a method for manufacturing same includes the steps of providing a supporting substrate comprising an etching resist layer and a copper foil. A groove is defined in the copper foil and a plurality of contact pads are formed on the surface of the copper foil. A chip including a plurality of electrode pads is received in the groove and a packaging layer is formed on a side of the copper foil. An insulating layer and a conductive pattern layer are formed on the packaging layer in that order, the conductive pattern layer being electrically connected to the contact pads and the electrode pads by a plurality of conductive bumps. Finally, the etching resist layer and the copper foil are removed to obtain a coreless package structure.

Abstract: A method of forming a semiconductor package includes forming an interconnecting structure on an adhesive layer, wherein the adhesive layer is on a carrier. The method further includes placing a semiconductor die on a surface of the interconnecting structure. The method further includes placing a package structure on the surface of the interconnecting structure, wherein the semiconductor die fits in a space between the interconnecting structure and the package structure. The method further includes performing a reflow to bond the package structure to the interconnecting structure.

Abstract: A method for fabricating a substrate having transferable chiplets includes forming a photo-sensitive adhesive layer on a process side of a source substrate including active components or on a patterned side of a transparent intermediate substrate. The intermediate substrate is brought into contact with the source substrate to adhere the active components on the process side to the patterned side of the intermediate substrate via the photo-sensitive adhesive layer therebetween. Portions of the source substrate opposite the process side thereof are removed to singulate the active components. Portions of the photo-sensitive adhesive layer are selectively exposed to electromagnetic radiation through the intermediate substrate to alter an adhesive strength thereof. Portions of the photo-sensitive adhesive layer having a weaker adhesive strength are selectively removed to define breakable tethers comprising portions of the adhesive layer having a stronger adhesive strength.

Abstract: Method for bonding of a plurality of chips onto a base wafer which contains chips on the front, the chips being stacked in at least one layer on the back of the base wafer and electrically conductive connections are established between the vertically adjacent chips, with the following steps: a) fixing of the front of the base wafer on a carrier, b) placing at least one layer of chips in defined positions on the back of the base wafer, and c) heat treatment of the chips on the base wafer fixed on the carrier, characterized in that prior to step c) at least partial separation of the chips of the base wafer into separated chip stack sections of the base after takes place.

Abstract: A light emitting device having a structure in which oxygen and moisture are prevented from reaching light emitting elements, and a method of manufacturing the same, are provided. Further, the light emitting elements are sealed by using a small number of process steps, without enclosing a drying agent. The present invention has a top surface emission structure. A substrate on which the light emitting elements are formed is bonded to a transparent sealing substrate. The structure is one in which a transparent second sealing material covers the entire surface of a pixel region when bonding the two substrates, and a first sealing material (having a higher viscosity than the second sealing material), which contains a gap material (filler, fine particles, or the like) for protecting a gap between the two substrates, surrounds the pixel region. The two substrates are sealed by the first sealing material and the second sealing material.

Abstract: A method of making a semiconductor assembly that includes a semiconductor device, a heat spreader, an adhesive and a build-up circuitry is disclosed. The heat spreader includes a bump, a base and a flange. The bump defines a cavity. The semiconductor device is mounted on the bump at the cavity, electrically connected to the build-up circuitry and thermally connected to the bump. The bump extends from the base into an opening in the adhesive, the base extends vertically from the bump opposite the cavity and the flange extends laterally from the bump at the cavity entrance. The build-up circuitry includes a dielectric layer and conductive traces on the semiconductor device and the flange. The conductive traces provide signal routing for the semiconductor device.

Abstract: Provided are a double-sided adhesive tape, semiconductor packages, and methods of fabricating the packages. A method of fabricating semiconductor packages includes providing a double-sided adhesive tape on a top surface of a carrier, the double-sided adhesive tape including a first adhesive layer and a second adhesive layer stacked on the first adhesive layer, the first adhesive layer of the double-sided adhesive tape being in contact with the top surface of the carrier, adhering active surfaces of a plurality of semiconductor chips onto the second adhesive layer of the double-sided adhesive tape, separating the first adhesive layer from the second adhesive layer such that the second adhesive layer remains on the active surfaces of the semiconductor chips, patterning the second adhesive layer to form first openings that selectively expose the active surfaces of the semiconductor chips, and forming first conductive components on the second adhesive layer to fill the first openings.

Abstract: A method, and apparatus resulting from the method, for fabricating a circuit board suitable for mounting electronic components. The method includes drilling a plurality of through-holes in a plurality of dielectric sheets, forming a conductive film on at least one side of each of the plurality of dielectric sheets, and substantially filling each of the plurality of through holes with a conductive material. The conductive material is both electrically and thermally uninterrupted from a first face to a second face of each of the plurality of dielectric sheets. The plurality of dielectric sheets are then sequentially mounted, one atop another, to form the circuit board. The sequential mounting step is performed after the steps of drilling the plurality of through-holes, forming the conductive layer, and substantially filling the plurality of through-holes.

Abstract: A method of manufacturing an electronic system. One embodiment provides a semiconductor chip having a first main face and a second main face opposite to the first main face. A mask is applied to the first main face of the semiconductor chip. A compound is applied to the first main face of the semiconductor chip. The compound includes electronically conductive particles. The semiconductor chip is coupled to a carrier with the compound facing the carrier.

Abstract: An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface, where the first surface of the insulating layer is less than 10 microns below an upper plane of the integrated circuit assembly. An active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the active layer and formed on the second surface of the insulating layer, and is also electrically connected to a printed circuit board. A method of fabricating an integrated circuit assembly includes coupling a handle wafer to the active layer of a semiconductor-on-insulator wafer, removing the substrate of the semiconductor-on-insulator, forming a bond pad connecting to the active layer on the exposed insulator surface, bonding the bond pad to a printed circuit board using a solder bump, and removing the handle wafer.

Abstract: A method of forming solder-less printed wiring boards includes attaching a electronic components to a workpiece using an adhesive material. A mold material is added to partially cover the electronic components to form a sub-assembly including the electronic components attached to the mold material and a planar surface on the workpiece side. At least tops of the electronic components extend beyond a height of the mold material. The adhesive material is removed to separate the workpiece and sub-assembly. A first prepreg dielectric is attached to the planar surface of the mold material. First vias are formed in the first prepreg dielectric to expose bondable contacts of the electronic components. The first vias are filled with electrically conductive plugs to provide connections to the bondable contacts of the electronic components. A circuit layer is formed on a surface of the first prepreg dielectric to provide contact to the first plugs.

Abstract: A method for temporary connection of a product substrate to a carrier substrate comprised of the steps of: applying an interconnect layer to a product substrate receiving side of the carrier substrate in an interconnect surface section of the product substrate receiving side, applying an antiadhesion layer with low adhesion force to one interconnect side of the product substrate in an antiadhesion surface section of the interconnect side, the antiadhesion surface section corresponding to the interconnect surface section, in terms of area, wherein a receiving space is formed which is bordered by the interconnect layer and the carrier substrate as well as the product substrate and the antiadhesion layer accommodating structures which are provided on the interconnect side of the product substrate and which project from the interconnect side, aligning the product substrate relative to the carrier substrate and bonding of the interconnect layer to the antiadhesion layer on one contact surface.

Abstract: A method of attaching a die to a carrier using a temporary attach material is disclosed. The method comprises attaching the temporary attach material between a surface of the die and a surface of the carrier. The temporary attach material attaches the die to the carrier. The method comprises bonding at least one connector to the die and the carrier. The connector includes a first end bonded to the carrier and a second end bonded to the die. The method further comprises encapsulating at least a portion of the die and at least a portion of the at least one connector by an encapsulation material.

Abstract: A semiconductor package assembly process that includes attaching one or more dies to a substrate; applying an adhesive material on a periphery of the substrate by an adhesive dispenser having a stamp-type dispensing head; applying a thermal interface material (TIM) on a top surface of the die by a TIM dispenser having a stamp-type dispensing head; and positioning a lid over the one or more dies and placing the lid on top of the adhesive material and the TIM by a lid carrier to encapsulate the one or more dies.

Abstract: An embodiment provides a chip package including a substrate, a cavity extending downward from an upper surface of the substrate, a metal layer overlying the substrate and conformally covering a sidewall and a bottom portion of the cavity, a chip having an upper surface and located on the metal layer in the cavity, wherein the upper surface is not lower than an upper surface of the metal layer outside of the cavity, and the protective layer covering the chip.

Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed on contact pads disposed over its active surface. An encapsulant is formed over the semiconductor die. An interconnect structure is formed over the semiconductor die and encapsulant. The semiconductor die is mounted to a translucent tape with the bumps embedded in the translucent tape. The translucent tape has layers of polyolefin, acrylic, and polyethylene terephthalate. A back surface of the semiconductor die undergoes backgrinding to reduce die thickness. The tape undergoes UV curing. A laminate layer is formed over the back surface of the semiconductor die. The laminate layer undergoes oven curing. The laminate layer is laser-marked while the tape remains applied to the bumps. The tape is removed after laser-marking the laminate layer. Alternately, the tape can be removed prior to laser-marking. The tape reduces die warpage during laser-marking.

Abstract: In a manufacturing method for layered chip packages, a layered substructure with at least one additional package joined thereto is used to produce a plurality of layered chip packages. The layered substructure includes a plurality of main bodies to be separated from each other later. Each main body includes: a main part having top and bottom surfaces and including a plurality of layer portions stacked on each other; and a plurality of main terminals disposed on at least one of the top and bottom surfaces of the main part. The additional package includes an additional semiconductor chip and at least one additional terminal that is electrically connected to the additional semiconductor chip and in contact with at least one of the plurality of main terminals.

Abstract: A method of fabricating a semiconductor device includes attaching a semiconductor substrate to a carrier using a carrier fixing layer, where the semiconductor substrate including a plurality of semiconductor chips. The method further includes forming gaps between adjacent ones of the chips. The gaps may be formed using one or more chemicals or light which act to remove portions of the semiconductor substrate to expose the carrier fixing layer. Additional portions of the carrier fixing layer are then removed to allow for removal of the chips from the carrier.

Abstract: A structure for a semiconductor component is provided having a bi-layer capping coating integrated and built on supporting layer to be transferred. The bi-layer capping protects the layer to be transferred from possible degradation resulting from the attachment and removal processes of the carrier assembly used for layer transfer. A wafer-level layer transfer process using this structure is enabled to create three-dimensional integrated circuits.

Abstract: A method for producing a semiconductor device, including a semiconductor chip, for improving production efficiency and the flexibility of production design is provided.

Abstract: Methods and devices for packaging integrated circuits. A packaged device may include an integrated circuit, a first packaging component including a patterned surface, and a second packaging component. The patterned surface of the first packaging component may be adhesively coupled to a surface of the second packaging component or a surface of the integrated circuit. The integrated circuit may be at least partially enclosed between the first and second packaging components. A packaging method may include patterning a surface of a packaging component of an integrated circuit package. The surface of the packaging component may be for adhesively coupling to a second component to at least partially enclose an integrated circuit in the integrated circuit package.

Abstract: A method (30) of forming a semiconductor package (20) entails applying (56) an adhesive (64) to a portion (66) of a bonding perimeter (50) of a base (22), with a section (68) of the perimeter (50) being without the adhesive (64). A lid (24) is placed on the base (22) so that a bonding perimeter (62) of the lid (24) abuts the bonding perimeter (50) of the base (22). The lid (24) includes a cavity (25) in which dies (38) mounted to the base (22) are located. A gap (70) is formed without the adhesive (64) at the section (68) between the base (22) and the lid (24). The structure vents from the gap (70) as air inside the cavity (25) expands during heat curing (72). Following heat curing (72), another adhesive (80) is dispensed in the section (68) to close the gap (70) and seal the cavity (25).