Abstract: A method for manufacturing a semiconductor device includes placing a sheet containing a fibrous material having at least one outer surface having a metal on a semiconductor chip-mounting region of a substrate; forming a bonding layer containing a fusible metal on the semiconductor chip-mounting region; placing a semiconductor chip on the semiconductor chip-mounting region; and bonding the semiconductor chip to the semiconductor chip-mounting region with the fusible metal-containing bonding layer by heating.

Abstract: On an epitaxy substrate (1), a layer structure (5, 6, 7) provided for light-emitting diodes or other optoelectronic components using thin-film technology is produced and provided with a first connecting layer (2), which comprises one or a plurality of solder materials. A second connecting layer (3) is applied over the whole area on a carrier (10) and permanently connected to the first connecting layer (2) by means of a soldering process.

Abstract: Methods for minimizing component shift during soldering are described. One such method includes forming a pedestal pad having a preselected shape on a substrate, forming at least one intervening layer on the substrate, the at least one intervening layer including a layer including a solidifying accelerant, and a layer including a solder, the solder layer having a preselected shape about the same as the preselected shape of the pedestal pad, positioning the component on the at least one intervening layer, and heating the solder to a predetermined process temperature, wherein the pedestal pad is configured to remain a solid during the heating the solder to the predetermined process temperature, and wherein the solidifying accelerant is configured to accelerate a solidification of the solder after the heating the solder to the predetermined process temperature.

Abstract: A method of forming a semiconductor device includes an integrated circuit (IC) die which is provided with a substrate with surfaces. At least one through substrate via (TSV) is formed through the substrate to a protruding integral tip that includes sidewalls and a distal end. A metal layer is formed on the bottom surface of the IC die, and the sidewalls and the distal end of the protruding integral tips. Completing fabrication of at least one functional circuit including at least one ground pad on the top surface of the semiconductor, wherein the ground pad is coupled to said TSV.

Abstract: There is provided a method that allows semiconductor chips to be obtained from a semiconductor wafer at high yield, while sufficiently inhibiting generation of chip cracks and burrs. The method for manufacturing a semiconductor chip comprises a step of preparing a laminated body having a semiconductor wafer, an adhesive film for a semiconductor and dicing tape laminated in that order, the semiconductor wafer being partitioned into multiple semiconductor chips and notches being formed from the semiconductor wafer side so that at least a portion of the adhesive film for a semiconductor remains uncut in its thickness direction, and a step of stretching out the dicing tape in a direction so that the multiple semiconductor chips are separated apart, to separate the adhesive film for a semiconductor along the notches. The adhesive film for a semiconductor has a tensile breaking elongation of less than 5% and the tensile breaking elongation of less than 110% of the elongation at maximum load.

Abstract: A process for the production of a MWT silicon solar cell comprising the steps: (1) providing a p-type silicon wafer with (i) holes forming vias between the front-side and the back-side of the wafer and (ii) an n-type emitter extending over the entire front-side and the inside of the holes, (2) applying a conductive metal paste to the holes of the silicon wafer to provide at least the inside of the holes with a metallization, (3) drying the applied conductive metal paste, and (4) firing the dried conductive metal paste, whereby the wafer reaches a peak temperature of 700 to 900° C., wherein the conductive metal paste has no or only poor fire-through capability and comprises (a) at least one particulate electrically conductive metal selected from the group consisting of silver, copper and nickel and (b) an organic vehicle.

Abstract: A method generates at least one electrical connection from at least one electronic component, which is positioned on a substrate inside an encapsulation, to outside the encapsulation. The functional capability of the electrical connection is to be provided at ambient temperatures greater than 140° C. and in the event of large power losses and extreme environmental influences. A reactive nanofilm, having targeted reaction, which can be triggered exothermically by laser, is used to produce hermetically sealed electrical connections. Using the nanofilm, an output of an electrical connection and a contact of the electrical connection to at least one further electrical contact can be provided.

Abstract: A plurality of FPGA dice is disposed upon a semiconductor substrate. In order both to connect thousands of signal interconnect lines between the plurality of FPGA dice and to supply the immense power required, it is desired that the substrate construction include two different portions, each manufactured using incompatible processes. The first portion is a signal interconnect structure containing a thin conductor layers portion characterized as having a plurality of thin, fine-pitch conductors. The second portion is a power connection structure that includes thick conductors and vertical through-holes. The through-holes contain conductive material and supply power to the FPGA dice from power bus bars located at the other side of the semiconductor substrate. The portions are joined at the wafer level by polishing the wafer surfaces within a few atoms of flatness and subsequent cleaning. The portions are then fusion bonded together or combined using an adhesive material.

Abstract: Preparation methods of forming packaged semiconductor device, specifically for flip-chip vertical power device, are disclosed. In these methods, a vertical semiconductor chip is flip-chip attached to a lead frame and then encapsulated with plastic packing materials. Encapsulated chip is then thinned to a predetermined thickness. Contact terminals connecting the chip with external circuit are formed by etching at least a bottom portion of the lead frame connected.

Abstract: A method of forming a microball grid array includes adhering a microball precursor material to a transfer medium under conditions to reflect a selective charge pattern. The method includes transferring the microball precursor material from the transfer medium across a gap and to an integrated circuit substrate under conditions to reflect the selective charge pattern. The method includes achieving the microball grid array without the aid of a mask.

Abstract: Described herein are stackable semiconductor device packages and related stacked package assemblies and methods. In one embodiment, a manufacturing method includes: (1) providing a substrate including contact pads disposed adjacent to an upper surface of the substrate; (2) applying an electrically conductive material to form conductive bumps disposed adjacent to respective ones of the contact pads; (3) electrically connecting a semiconductor device to the upper surface of the substrate; (4) applying a molding material to form a molded structure covering the conductive bumps and the semiconductor device; (5) forming a set of cutting slits extending partially through the molded structure and the conductive bumps to form truncated conductive bumps; and (6) reflowing the truncated conductive bumps to form reflowed conductive bumps.

Abstract: Metal particles are applied to a metal foil. A semiconductor chip is placed over the metal foil with contact elements of the semiconductor chip facing the metal particles. The metal particles are heated and the metal foil is structured after heating the metal particles.

Abstract: A semiconductor device has a semiconductor die mounted over a surface of a substrate. A mold underfill dispensing needle has a width substantially equal to a width of the semiconductor die. The dispensing needle is placed in fluid communication with a side of the semiconductor die. A mold underfill is deposited from an outlet of the dispensing needle evenly across a width of the semiconductor die into an area between the semiconductor die and substrate without motion of the dispensing needle. The dispensing needle has a shank and the outlet in a T-configuration. The dispensing needle can have a plurality of pole portions between a shank and the outlet. The dispensing needle has a plate between a shank and the outlet. The outlet has an upper edge with a length substantially equal to or greater than a length of a lower edge of the outlet.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead having a horizontal ridge at a lead top side; forming a connection layer having an inner pad and an outer pad directly on the lead top side, the inner pad having an inner pad bottom surface; mounting an integrated circuit over the inner pad; applying a molding compound, having a molding bottom surface, over the integrated circuit, the inner pad, and the outer pad; and applying a dielectric directly on the molding bottom surface and the inner pad bottom surface.

Abstract: The present invention relates to a combi-card which can be used in a contact-type or noncontact-type fashion and a method for manufacturing the same. More particularly, this invention relates to a combi-card and a method for making the same, in which an inlay layer on which an antenna terminal made of a coil or conductive fiber is formed and a COB (chip on board) on which ACF (anisotropic conductor film) is applied, are pre-treated by a heating head and the like, the COB is attached to an antenna coil insertion layer, and an upper printing sheet with a protection film, and a lower printing sheet with a protection film, which are cut out to be suitable for the COB shape, are stacked to construct a combi-card.

Abstract: An assembly and method of making same are provided. The assembly can include a first component including a dielectric region having an exposed surface, a conductive pad at the surface defined by a conductive element having at least a portion extending in an oscillating or spiral path along the surface, and a an electrically conductive bonding material joined to the conductive pad and bridging an exposed portion of the dielectric surface between adjacent segments. The conductive pad can permit electrical interconnection of the first component with a second component having a terminal joined to the pad through the electrically conductive bonding material. The path of the conductive element may or may not overlap or cross itself.

Abstract: A method includes allowing a work piece having a solder bump to contact a bond head; heating the bond head until the solder bump is melted; and conducting a cooling media into the bond head to cool the solder bump and to solidify the solder bump.

Abstract: A method of manufacturing an integrated circuit packaging system includes: providing an inner lead and an outer lead, the inner lead having an inner peripheral side with a non-linear contour; forming a bump contact, having a groove in and a mesa from the inner lead or the outer lead, the groove adjacent to the mesa; mounting a first device adjacent to the inner lead; connecting a second device to the mesa; and forming an encapsulation material over the first device, the inner lead, and the outer lead and covering the second device.

Abstract: In a light-emitting apparatus using a silicone resin as a sealant of its light-emitting element, it is intended to prevent discoloration of its lead frame. A light-emitting element fixed to a lead frame is sealed with a sealed portion formed by a silicone resin. An average spin-spin relaxation time of the silicone resin is equal to or smaller than 100 microseconds at 25° C. at a resonance frequency of 25 MHz.

Abstract: In one or more embodiments, a method comprising applying thermo compression to a package assembly including a lid, a die, and a package substrate to assemble the package assembly is disclosed. The method may include assembling the package assembly without coupling a biasing mechanism to the lid. Heat may be applied to a bond head coupled with a pick and place tool. Heat may be applied to a bond stage coupled to a carrier for holding the package assembly during processing. An adhesive applied to the lid or package substrate may be allowed to at least partially cure. The method may further include, in an oven, reflowing a thermal interface material (TIM) coupled to the lid and the die, curing the TIM, and/or curing the adhesive, without using clips.

Abstract: It is provided a contacting method when a plurality of films to be peeled are laminating. Reduction of total layout area, miniaturization of a module, weight reduction, thinning, narrowing a frame of a display device, or the like can be realized by sequentially laminating a plurality of films to be peeled which are once separately formed over a plastic film or the like. Moreover, reliable contact having high degree of freedom is realized by forming each layer having a connection face of a conductive material and by patterning with the use of a photomask having the same pattern.

Abstract: An integrated circuit package comprises a molding compound covering a semiconductor die. A healing substance is on the surface of the semiconductor die at an interface of the molding compound and the semiconductor die. The healing compound comprises a catalyst and a plurality of microcapsules containing a sealing compound. If the molding compound becomes delaminated from the semiconductor die the microcapsules rupture and spill the sealing compound. When the sealing compound is spilled and contacts the catalyst the sealing compound and catalyst polymerize and fasten the molding compound to the semiconductor die.

Abstract: A process of forming a semiconductor integrated circuit that includes the steps of: forming at least a first element having a first pattern of conductive material and including a polymer layer surrounding the conductive material, forming at least a second element having a second pattern of conductive material and including a polymer layer surrounding the conductive material, positioning the first element relative to the second element, and bonding the polymer layer of the first and second elements at a temperature below a melting temperature of the conductive materials of the first and second elements wherein the conductive material of the first element contacts the conductive material of the second element and is maintained in position by the bonded polymer layers.

Abstract: A system for bonding electrical devices using an electrically conductive adhesive to adhere the electrical devices together, the system comprising: an ultrasonic transducer to generate an ultrasonic vibration; and an ultrasonic to thermal energy apparatus operatively attached to and covering an operational end of the ultrasonic transducer, the ultrasonic to thermal energy apparatus damping the ultrasonic vibration to minimize ultrasonic vibration transmitted to a first electrical device and causing the conversion of the ultrasonic vibration to a heating pulse which is conducted through the first electrical device to the adhesive; wherein the adhesive is softened by the heating pulse to bond the electrical devices together.

Abstract: In one aspect of the present invention, a method of LED die-bonding includes coating the back side of an LED chip with a magnetic material, placing the LED chip in a packaging cup such that the back side of the LED chip is in contact with the bottom of the packaging cup, applying a magnetic field in a region near the bottom of the packaging cup so as to exert a magnetic force on the LED chip via the magnetic material coated on the back side of the LED chip, thereby holding the LED chip in place against the bottom of the packaging cup, while the magnetic field is applied, bonding one end of a first conductive wire to an anode of the LED and the other end of the first conductive wire to a first electrode, and bonding one end of a second conductive wire to a cathode of the LED and the other end of the second conductive wire to a second electrode, where the first electrode and the second electrode are attached to the packaging cup, and filling the packaging cup with an epoxy, and curing the epoxy.

Abstract: A method of manufacture of an integrated circuit package system that includes: providing an electrical interconnect system including an inner lead-finger system and an outer lead-finger system; stacking a first device, a second device, and a third device between and over the electrical interconnect system; connecting the first device and the second device to the inner lead-finger system; and connecting the third device to the outer lead-finger system.

Abstract: A wiring structure having a wiring-terminal-connection adhesive that includes a curing agent capable of generating a free radical upon heating, a radically polymerizable substance and silicone particles.

Abstract: This invention provides a wiring-terminal-connecting adhesive comprising a curing agent capable of generating a free radical upon heating, a radically polymerizable substance and silicone particles, and a wiring-terminal-connecting method and a wiring structure which make use of such an adhesive.

Abstract: The radiation performance of a resin sealed semiconductor package is enhanced and further the fabrication yield thereof is enhanced. A drain terminal coupled to the back surface drain electrode of a semiconductor chip is exposed at the back surface of an encapsulation resin section. Part of the following portion and terminal is exposed at the top surface of the encapsulation resin section: the first portion of a source terminal coupled to the source pad electrode of the semiconductor chip and a gate terminal coupled to the gate pad electrode of the semiconductor chip. The remaining part of the second portion of the source terminal and the gate terminal is exposed at the back surface of the encapsulation resin section. When this semiconductor device is manufactured, bonding material and a film member are placed between the drain terminal and the semiconductor chip.

Abstract: A metal tab die attach paddle (DAP) disposed between the lead frame and a power device die in a power device package reduces the stress exerted on the semiconductor power device die caused by the different coefficients of thermal expansion (CTE) of the semiconductor power device die and the lead frame. In addition the power device package substantially prevents impurities from penetrating into the power device package by increasing the surface creepage distance of a sealant resulting from the metal tab DAP and an optional swaging of the lead frame.

Abstract: An electronic device can include a first die having a first terminal at a first front side, and a second die having a second terminal at a second front side and a through via. In one aspect, a process of forming the electronic device includes supplying a second substrate including a die location of the second die. The process can also include attaching the second substrate to a handling substrate and singulating the second die from the second substrate before removing the handling substrate. In another aspect, the handling substrate can include a rigid substrate. The process can include orienting the front side of the first die and a back side of the second substrate front-to-back with respect to each other. In yet another aspect, the first terminal is electrically connected to the through via and the second terminal. In one embodiment, the electronic device can include a third die.

Abstract: A no-lead electronic package including a heat spreader and method of manufacturing the same. This method includes the steps of selecting a matrix or mapped no-lead lead frame with die receiving area and leads for interconnect; positioning an integrated circuit device within the central aperture and electrically interconnecting the integrated circuit device to the leads; positioning a heat spreader in non-contact proximity to the integrated circuit device such that the integrated circuit device is disposed between the leads and the heat spreader; and encapsulating the integrated device and at least a portion of the heat spreader and leads in a molding resin.

Abstract: An RFID tag manufacturing method is including application process in which a heat-curable adhesive is applied to an area where a circuit chip is placed on a base to which antennae are wired so as to be connected with the circuit chip, placement process in which the circuit chip is placed where the adhesive is applied, and thereby the circuit chip is connected with the antennae, covering process in which the circuit chip placed on the base is covered with a sheet member having an adhesive layer on its surface, such that the adhesive layer faces the base, and heat and pressure applying process in which pressure is applied to the sheet member toward the base, and heat and pressure are applied to the circuit chip from above the sheet member, thereby curing the adhesive and fixing the circuit chip and the sheet member on the base.

Abstract: An embedded electronic component semiconductor package structure and a packaging process thereof are provided. By providing two or more preformed building blocks, the electronic component can be assembled to the joined building blocks to obtain the embedded component semiconductor package structure.

Abstract: A method that in one embodiment is useful in bonding a first substrate to a second substrate includes forming a layer including metal over the first substrate. The layer including metal in one embodiment surrounds a semiconductor device, which can be a micro electromechanical system (MEMS) device. On the second substrate is formed a first layer comprising silicon. A second layer comprising germanium and silicon is formed on the first layer. A third layer comprising germanium is formed on the second layer. The third layer is brought into contact with the layer including metal. Heat (and pressure in some embodiments) is applied to the third layer and the layer including metal to form a mechanical bond material between the first substrate and the second substrate in which the mechanical bond material is electrically conductive. In the case of the mechanical bond surrounding a semiconductor device such as a MEMS, the mechanical bond can be particularly advantageous as a hermetic seal for protecting the MEMS.

Abstract: A method of bonding a semiconductor structure to a substrate to effect both a mechanical bond and a selectively patterned conductive bond, comprising the steps of mechanically bonding a semiconductor structure to a substrate by means of a bonding layer; providing gaps in the bonding layer generally corresponding to a desired conductive bond pattern; providing vias though the substrate generally positioned at the gaps in the bonding layer; causing electrically conductive material to contact the semiconductor structure exposed through the vias. A device made in accordance with the method is also described.

Abstract: A mounted body (100) of the present invention includes: a semiconductor element (10) having a surface (10a) on which element electrodes (12) are formed and a rear surface (10b) opposing the surface (10a); and a mounting board (30) on which wiring patterns (35) each having an electrode terminal (32) are formed. The rear surface (10b) of the semiconductor element (10) is in contact with the mounting board (30), and the element electrodes (12) of the semiconductor element (10) are connected electrically to the electrode terminals (32) of the wiring pattern (35) formed on the mounting board (30) via solder connectors (20) formed of solder particles assembled into a bridge shape. With this configuration, fine pitch connection between the element electrodes of the semiconductor element and the electrode terminals of the mounting board becomes possible.

Abstract: There are provided an adhesive for connecting a circuit to be interposed between substrates having circuit electrodes thereon opposed to each other and to electrically connect the circuit electrodes on the substrates opposed to each other to the pressurizing direction under pressure, wherein the adhesive contains a compound having an acid equivalent of 5 to 500 KOH mg/g, and an adhesive for connecting a circuit to be interposed between substrates having circuit electrodes opposed to each other and to electrically connect the electrodes on the substrate opposed to each other to the pressurizing direction under pressure, wherein the adhesive comprises a first adhesive layer and a second adhesive layer, and a glass transition temperature of the first adhesive layer after pressure connection is higher than the glass transition temperature of the second adhesive layer after pressure connection.

Abstract: The present invention enables improvement of bonding reliability of the conductive adhesive interposed between a semiconductor chip and a die pad portion. Provided is a semiconductor device, in which a silicon chip is mounted over the die pad portion integrally formed with a drain lead, has a source pad over the main surface and a drain electrode of a power MOSFET over the back side, and is bonded onto the die pad portion via an Ag paste. In the device, a source lead and the source pad are electrically coupled via an Al ribbon. Over the back surface of the silicon chip, an Ag nanoparticle coated film is formed, while another Ag nanoparticle coated film is formed over the die pad portion and lead (drain lead and source lead).

Abstract: Disclosed herein are a die package and a method of manufacturing the die package. A solder layer is formed on a lower surface of a die. The die is self-aligned and attached to a support plate using surface tension between the solder layer and a metal layer of the support plate, thus reducing attachment lead time of the die.

Abstract: An active matrix substrate includes a first substrate, a driving integrated circuit chip mounted on the first substrate with an anisotropic electrically conductive layer, and an insulating member. The insulating member isolates a terminal from a wiring and a bump electrode that are adjacent to the terminal portion and isolates a bump electrode facing the terminal portion from a bump electrode and a wiring that are adjacent to the bump electrode.

Abstract: To prevent formation of entrapped underfill material between solder balls and bonding bumps, fast temperature ramping is employed during a chi assembly after application of an underfill material prior to bonding. Voids formed within the underfill material are subsequently removed by curing the underfill material in a pressurized environment. Temperature cycling on the underfill material is limited during the bonding process in order to maintain viscosity of the underfill material prior to the cure process in the pressurized environment. Further, the underfill material is subjected to the pressurized environment until the cure process is complete to prevent re-formation of voids. The cure process can be a constant temperature or a multi-temperature process including temperature ramping. Further, the cure process can be a constant pressure process or a pressure cycling process that accelerates removal of the voids.

Abstract: A chip-scale semiconductor device package includes a die, an insulating substrate having a through hole, a first metal layer, a second metal layer, and an insulating layer. The first metal layer is on a first surface of the insulating substrate and a first side of the through hole. The insulating layer is overlaid on a second surface of the insulating substrate and surrounds a second side of the through hole. The second metal is on the insulating layer and the second side of the through hole. The die is in the through hole and includes a first electrode and a second electrode. The first electrode is electrically connected to the first metal layer, and the second electrode is electrically connected to the second metal layer.

Abstract: An integrated circuit package stacking system includes: forming a flexible substrate by: providing an insulating material, forming a stacking pad on the insulating material, forming a coupling pad on the insulating material, and forming a trace between the stacking pad and the coupling pad; providing a package substrate; coupling an integrated circuit to the package substrate; and applying a conductive adhesive on the package substrate for positioning the flexible substrate over the integrated circuit and coupling the flexible substrate on the conductive adhesive.

Abstract: In a method for manufacturing an electronic device an integrated circuit (1) is arranged between two layers (2, 3) of a substrate, said integrated circuit (1) having at least one contacting surface, a hole (4) is formed in at least one substrate layer (3) above said at least one contacting surface, a conductive structure (5) is formed on a surface of said at least one substrate layer (3) facing away from the integrated circuit (1) and said conductive structure (5) is connected to said contacting surface by means of said hole (4).

Abstract: The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to contact or metallization processing. Contacts and bonding pads may then be fabricated after the TSVs are already in place, which allows the TSV to be more dense and allows more freedom in the overall TSV design. By providing a denser connection between TSVs and bonding pads, individual wafers and dies may be bonded directly at the bonding pads. The conductive bonding material, thus, maintains an electrical connection to the TSVs and other IC components through the bonding pads.

Abstract: An integrated conformal electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed on a plurality of encapsulated modules by attaching a plurality of modules (30-33) to a process carrier (1) using a double side adhesive tape (2), and then sequentially depositing an insulating layer (15) and a conductive shielding layer (16) before encapsulating the modules with a molding compound (17). After removing the adhesive tape (2) to expose a surface of the encapsulated modules, a multi-layer circuit substrate (100) is formed over the exposed surface, where the circuit substrate includes shielding via structures (101-112) that are aligned with and electrically connected to the conductive shielding layer (16), thereby encircling and shielding the circuit module(s).

Abstract: A liquid crystal display device (100) includes a glass substrate (110) having an LSI chip (130) and an FPC board (140) mounted thereon. A component ACF (150a) made of a single sheet is used to further mount discrete electronic components such as stabilizing capacitors (150) on the glass substrate (110). The component ACF (150a) has a size that covers not only a region where the discrete electronic components are to be mounted, but also the top surfaces of the LSI chip (130) and the FPC board (140) which are mounted first. By thus using the large component ACF (150a), a positional constraint upon adhering the component ACF (150a) to the glass substrate (110) is eliminated, reducing the area of a region where the discrete electronic components are mounted. By this, a board module miniaturized by reducing the area of a region where discrete electronic components are mounted is provided.

Abstract: Some embodiments include methods of assembling integrated circuit packages in which at least two different conductive layers are formed over a bond pad region of a semiconductor die, and in which a conductive projection associated with an interposer is bonded through a gold ball to an outermost of the at least two conductive layers. The conductive layers may comprise one or more of silver, gold, copper, chromium, nickel, palladium, platinum, tantalum, titanium, vanadium and tungsten. In some embodiments, the bond pad region may comprise aluminum, an inner of the conductive layers may comprise nickel, an outer of the conductive layers may comprise gold, the conductive projection associated with the interposer may comprise gold; and the thermosonic bonding may comprise gold-to-gold bonding of the interposer projection to a gold ball, and gold-to-gold bonding of the outer conductive layer to the gold ball. Some embodiments include integrated circuit packages.

Abstract: A method of assembling an electronic device and electronic packages therefrom. A die attach adhesive precursor is placed between a top surface of a workpiece and an IC die. The die attach adhesive precursor includes metal particles, a first plurality of first microcapsules having a polymerizable material inside, and a second plurality of second microcapsules having a polymerization agent inside to form a first polymer upon rupture of first and second microcapsules. A force sufficient to rupture at least a portion of the first plurality of first microcapsules and at least a portion of the second plurality of second microcapsules is applied to form a self-healing die attach adhesive wherein the first polymer binds the plurality of metal particles and the remaining microcapsules and secures the IC die to the top surface of the workpiece. The self-healing die attach adhesive generally includes at least 90 vol. % metal.