Abstract: A method of forming a silicon (Si) via in vertically stacked wafers is provided with a contact plug extending from selected metallic lines of a top wafer and an etch stop layer formed prior to the contact plug. Such a method comprises selectively etching through the silicon (Si) of the top wafer until stopped by the etch stop layer to form the Si via; depositing an oxide layer to insulate a sidewall of the Si via; forming a barrier layer on the oxide layer and on the bottom of the Si via; and depositing a conduction metal into the Si via to provide electrical connection between active IC devices located on vertically stacked wafers and an external interconnect.

Abstract: An electronic device and fabrication of an electronic device. One embodiment provides applying a paste including electrically conductive particles to a surface of a semiconductor wafer. The semiconductor wafer is singulated with the electrically conductive particles for obtaining a plurality of semiconductor chips. At least one of the plurality of semiconductor chips is placed over a carrier with the electrically conductive particles facing the carrier. The electrically conductive particles are heated until the at least one semiconductor chip adheres to the carrier.

Abstract: In a stacking semiconductor device in which a first-layer and a second-layer semiconductor devices are stacked and bonded with a solder, warpage occurs due to a difference in thermal expansion coefficient of constituent members or a difference in elastic modulus of individual members. Therefore, between the first-layer and the second-layer semiconductor devices are provided an external connection terminal of solder and a thermosetting resin, and the stacking semiconductor device is heated at 150 to 180° C., which are the temperatures of preheating for reflow of the solder, for 30 to 90 seconds. Thereby the warpage of the first-layer semiconductor device is reduced and the thermosetting resin is cured completely in this state. Then, the temperature is raised to a reflow temperature of the solder and solder bonding using the external connection terminal is performed. Thereby, the bonding reliability of a solder-bonded portion of the stacking semiconductor device is considerably improved.

Abstract: The invention claimed is a packaged semiconductor device with dual exposed surfaces and a method of manufacturing the device. A thermal clip and one or multiple source pads are exposed on opposite ends of the device through a nonconductive molding material used to package the device. The thermal clip and source pad can be either top or bottom-exposed. The gate, source and drain leads are exposed through the molding material, and all leads are coplanar with the bottom-exposed surface. The device can have multiple semiconductor dies or various sized dies while still having a single, constant footprint. The method of manufacturing requires attaching the semiconductor die to a thermal clip, and then attaching the die with the attached thermal clip to a lead frame. The resulting device is then molded, marked, trimmed and singulated, in this order, creating a packaged semiconductor device with dual exposed surfaces.

Abstract: A semiconductor device includes a substrate having a substrate wiring, a semiconductor chip provided on the substrate, a first electrical conductor electrically connecting the semiconductor chip and the substrate wiring, and an electrically conductive pad provided on the substrate. The semiconductor device further includes a wiring member electrically connected to the electrically conductive pad and serving as a wiring path different from the substrate wiring.

Abstract: A semiconductor package includes a leadframe which is cup-shaped and holds a semiconductor die. The leadframe is in electrical contact with a terminal on one side of the die, and the leads of the leadframe are bent in such a way that portions of the leads are coplanar with the other side of the die, which also contains one or more terminals. A plastic capsule is formed around the leadframe and die.

Abstract: A semiconductor device (100) comprises a first resin substrate (101) on which a first semiconductor chip (125) is mounted a surface thereof; a second resin substrate (111) on which a second semiconductor chip (131) is mounted on a surface thereof; and a resin base material (109), joined to a front surface of the first resin substrate (101) and to a back surface of the second resin substrate (111), so that these surfaces are electrically connected. The resin base material (109) is disposed in a circumference of the first resin substrate (101) in the surface of the first resin substrate (101). Further, the first semiconductor chip (125) is disposed in a space section provided among the first resin substrate (101), the second resin substrate (111) and the resin base material (109) in the surface of the first resin substrate (101).

Abstract: A circuit structure may be formed in a substrate having a face and an open trench, where one or more chips are to be mounted. At least one bridge may extend across an intermediate portion of the trench, and optionally, may divide the trench into sections. A conductive adhesive layer may be applied to the substrate face and, if included, the bridge. One or more circuit chips may be mounted on the adhesive layer, with at least one edge of one circuit chip adjacent to the trench. Alternatively or additionally, an adhesive layer may be applied to a base of a chip and then mounted to the substrate face, in like fashion. The trench may accommodate excess adhesive flowing out from under the one or more chips, while the bridge retains the adhesive across the width of the trench. If the adhesive is conductive, this provides continuity of the conductive layer on the face of the substrate across the trench.

Abstract: A method for fabricating a semiconductor component with through interconnects can include the steps of providing a semiconductor substrate with substrate contacts, and forming openings from a backside of the substrate aligned with the substrate contacts. The method can also include the steps of providing an interposer substrate (or alternately a second semiconductor substrate), forming projections on the interposer substrate (or on the second semiconductor substrate), and forming conductive vias in the projections. The method can also include the steps of placing the projections in physical contact with the openings, and placing the conductive vias in electrical contact with the substrate contacts. The method can also include the steps of bonding the conductive vias to the substrate contacts, and forming terminal contacts on the interposer substrate (or alternately on one of the semiconductor substrates) in electrical communication with the conductive vias.

Abstract: A semiconductor device that improves adhesion between a resin and a die pad and prevents cracking of the resin includes: a semiconductor chip; a die pad on which the semiconductor chip is mounted; a bonding agent for bonding the semiconductor chip to the die pad; a plurality of inner leads provided at the outer periphery of the die pad; outer leads extending from the inner leads; bonding wires connecting the inner leads to the semiconductor chip mounted on the die pad; and a resin for sealing the inner leads, the die pad, the semiconductor chip, the bonding agent and the bonding wires. The bonding agent is further disposed in all or part of a margin of the die pad at a peripheral portion where the semiconductor chip is mounted, and a plurality of dimples are formed in the surface of the bonding agent in the die pad margin.

Abstract: In an electronic apparatus, a busbar assembly is composed of busbars made of at least one previously selected metal material. Each of the busbars has one surface. A solder joint is made of an alloy of previously selected metal materials and placed on the one surface of at least one busbar. The solder joint is changed from a molten state to a solid state to thereby mechanically and electrically connect an electronic component to the one surface of the at least one busbar. The at least one previously selected metal material of the at least one busbar and the previously selected metal materials of the alloy of the solder joint determine that a contact angle of the molten solder joint to the one surface of the at least one busbar is within an angular range of 40 to 60 degrees.

Abstract: Disclosed are semiconductor die packages, methods of making them, and systems incorporating them. An exemplary package comprises a first substrate, a second substrate, a semiconductor die disposed between the first and second substrates, and an electrically conductive member disposed between the first and second substrates. The semiconductor die has a conductive region at its first surface that is electrically coupled to a first conductive region of the first substrate, and another conductive region at its second surface that is electrically coupled to a first conductive region of the second substrate. The conductive member is electrically coupled between the first conductive region of the second substrate and a second electrically conductive region of the first substrate. This configuration enables terminals on both surfaces of the semiconductor die to be coupled to the first substrate.

Abstract: A method of forming a wall structure in a microelectronic assembly includes selectively depositing a flowable material on an upper surface of a first element in the microelectronic assembly, positioning a molding surface in contact with the deposited flowable material and controlling a distance between the upper surface of the first element and the molding surface with one or more objects positioned between the upper surface and the molding surface.

Abstract: A procedure of packaging an electronic component is provided, comprising the following steps: step A for mount at which a conductor and a chip are temporarily mounted on a carrier removable, and next step B for encapsulation at which the conductor and the chip are encapsulated with colloid and mounted and then removed from the carrier so that the chipset after modeled without any substrate may be mounted for decreasing the costs of substrate use and design and the probability of damage of the substrate an chip due to the thermal expansion and increasing the yield factor of a finished product.

Abstract: The present invention enables improvement of bonding reliability of the conductive adhesive interposed between a semiconductor chip and a die pad portion. Provided is a semiconductor device, in which a silicon chip is mounted over the die pad portion integrally formed with a drain lead, has a source pad over the main surface and a drain electrode of a power MOSFET over the back side, and is bonded onto the die pad portion via an Ag paste. In the device, a source lead and the source pad are electrically coupled via an Al ribbon. Over the back surface of the silicon chip, an Ag nanoparticle coated film is formed, while another Ag nanoparticle coated film is formed over the die pad portion and lead (drain lead and source lead).

Abstract: A circuit connection structure that exhibits excellent adhesiveness between a heat resistant resin film and a circuit adhesive member, even under high temperature and high humidity, is provided by introducing a chemically stable functional group into the heat resistant resin film by additional surface treatment to improve adhesiveness. In a circuit connection structure, a semiconductor substrate and a circuit member are adhered by a circuit adhesive member sandwiched therewith. First circuit electrode on the semiconductor substrate and second circuit electrode on the circuit member are connected electrically by conductive particles in the circuit adhesive member. A surface modification is given to the semiconductor substrate by plasma treatment using gas containing nitrogen, ammonia and the like. Therefore, the heat resistant resin film on the semiconductor substrate and the circuit adhesive member are firmly adhered for a long period of time even under high temperature and high humidity.

Abstract: An apparatus and method for a low voltage drop and thermally enhanced integrated circuit (IC) package are described. A substantially planar substrate having a plurality of contact pads on a first surface is electrically connected through the substrate to a plurality of solder ball pads on a second surface of the substrate. An IC die having a first surface is mounted to the first surface of the substrate. The IC die has a plurality of I/O pads electrically connected to the plurality of contact pads on the first surface of the substrate. A heat sink assembly is coupled to a second surface of the IC die and to a first contact pad on the first surface of the substrate to provide a thermal path from the IC die to the first surface of the substrate. The heat sink assembly can also provide an electrical path from the IC die to the first surface of the substrate. The heat sink assembly may have one or two heat sink elements to provide thermal and/or electrical connectivity between the IC die and the substrate.

Abstract: A manufacturing method of a semiconductor device includes providing an adhesive on a supporting board, the supporting board being where a semiconductor element is to be mounted; providing a member configured to block flow of the adhesive on a first main surface of the semiconductor element, the semiconductor element having a second main surface where an outside connection terminal is provided; mounting the semiconductor element on a part of the supporting board where the adhesive is provided by pressing the semiconductor element via the member.

Abstract: The present invention relates to a semiconductor packaging method. The method comprises (S1) applying a die adhesive to an upper surface of a member through screen-printing; (S2) B-stage curing the member having the die adhesive; (S3) attaching a die on the B-stage cured die adhesive; (S4) wire-bonding the die to the member; and (S5) encapsulating the outside of the resultant, after the B-stage curing process of the step S2, a degree of cure of the die adhesive shows a decrease in heat capacity by 80 to 100%, and the step S3 is performed such that the die adhesive maintains an adhesive strength of 10 kgf/cm2 or more at normal temperature after the die attaching.

Abstract: A method is provided for forming peripheral contacts between a die and a substrate. In accordance with the method, a die (305) is provided which has first and second opposing major surfaces, wherein the first major surface is attached to a substrate (303) having a first group (323) of contact pads disposed thereon, and wherein the second major surface has a second group (311) of contact pads disposed thereon. An electrically conductive pathway (326) is formed between the first and second groups of contacts with an electrically conductive polymeric composition.

Abstract: An integrated circuit package system comprising: providing a substrate; coupling an integrated circuit to the substrate; mounting a shielding element around the integrated circuit; applying a conductive shielding layer on the shielding element; and coupling a system interconnect to the shielding element.

Abstract: A method and apparatus for underfilling a gap between a semiconductor die or device and a substrate, where the semiconductor die or device is electrically connected to the substrate so that an active surface of the semiconductor die is facing a top surface of the substrate with the gap therebetween. A silane layer is applied to the active surface of the semiconductor die, the upper surface of the substrate, and/or both to increase the surface tension thereon. The increased surface tension thereby allows the underfill material to fill the gap via capillary action in a lesser flow time more effectively, and therefore, is more efficient than conventional underfilling methods.

Abstract: An integrated circuit chip has one or more electrically conductive nano-fibers formed on one or more contact pads of the integrated circuit chip. The one or more electrically conductive nano-fibers are configured to provide an adhesive force by intermolecular forces and establish an electrical connection with one or more contact pads disposed on the surface of a chip package.

Abstract: A tape adhesive type material is directionally conductive. According to an example embodiment of the present invention, carbon nanotubes (212, 214, 216, 218) are configured in a generally parallel arrangement in a tape base type material (210). The carbon nanotubes conduct (e.g., electrically and/or thermally) in their generally parallel direction and the tape base type material inhibits conduction in a generally lateral direction. In some implementations, the tape base material is arranged between integrated circuit components (220, 230), with the carbon nanotubes making a conductive connection there between. This approach is applicable to coupling a variety of components together, such as integrated circuit dies (flip chip and conventional dies) to package substrates, to each other and/or to leadframes.

Abstract: A flip chip mounting method which is applicable to the flip chip mounting of a next-generation LSI and high in productivity and reliability as well as a method for connecting substrates are provided. A circuit board 10 having a plurality of connecting terminals 11 and a semiconductor chip 20 having a plurality of electrode terminals 21 are disposed in mutually facing relation and a resin 13 containing conductive particles 12 and a gas bubble generating agent is supplied into the space therebetween. In this state, the resin 13 is heated to generate gas bubbles 30 from the gas bubble generating agent contained in the resin 13. The resin 13 is pushed toward the outside of the generated gas bubbles 30 by the growth thereof. The resin 13 pushed to the outside is self-assembled in the form of columns between the respective terminals of the circuit board 10 and the semiconductor chip 20.

Abstract: A packaged semiconductor device (a wafer-level chip scale package) containing a conductive adhesive material as an electrical interconnect route between the semiconductor die and a patterned conductive substrate is described. The patterned conductive substrate acts not only as a substrate, but also as a redistribution layer that converts the dense pad layout of the die to a larger array configuration of the solder balls in the circuit board. Using the invention allows the formation of a lower priced chip scale package that also overcomes the restriction of the die size used in die-sized chip packages and the input-output pattern that can be required by the printed circuit board. Thus, the invention can provide a familiar pitch (i.e., interface) to the printed circuit board for any small die.

Abstract: A method and apparatus for handling and positioning half plated balls for socket application in ball grid array packages. The half plated balls, comprising a first side adapted to be soldered and a second side adapted to establish reliable solderless electrical contact, are embedded in a soft foil, with a common orientation. The soft foil is positioned on a clam-receiving tool and a vacuumed caved cover clam is fitted on the balls and then pushed to cut and separate the polymer sheet from the copper ball surface. The vacuumed caved cover clam is then lifted with the oriented copper balls entrapped inside and the vacuumed caved cover clam places the entrapped balls on the laminate pads, with a deposit of low melt alloy. The air vacuum is deactivated and the cover is lifted, leaving the balls positioned on the pads while the soldering process is initiated and solder joints are formed to fix the balls.

Abstract: A method for encapsulating a component by using a chamber in which there is a vacuum or controlled atmosphere, positioning a continuous sealing seam made of a metal or a metal alloy on a wettable surface previously placed on a substrate including at least one component and extending around the periphery of the component(s), positioning a package on the sealing seam, and raising the temperature inside the chamber to fuse the material that constitutes the sealing seam, thereby causing the package to drop onto the substrate and form a leaktight, hermetic seal between the package and the substrate.

Abstract: A method of manufacturing a semiconductor device uses a substrate on which an interconnect pattern is formed and on which a protective film is formed to include an opening and to cover the interconnect pattern in a region other than the opening. The method includes: attaching an adhesive sheet to an area including the opening and a boundary between the opening and the protective film so that a void is formed due to a level difference between the interconnect pattern and the substrate; softening the adhesive sheet by heating; and causing a semiconductor chip to adhere to the substrate through the adhesive sheet. The protective film includes a groove which connects with the opening, the adhesive sheet is attached except a part of the groove, and the void is discharged through the groove by heating and softening the adhesive sheet.

Abstract: The present invention realizes a semiconductor device of high reliability which allows metal terminals which have a uniform height, are flat and smooth to be formed under low load and at low costs and to be mounted with low damage. The electrodes 5 and the insulating film 6 are both formed of materials having the property that they are solid and do not exhibit the adhesiveness at room temperature and exhibit the adhesiveness at a temperature not lower than a first temperature and cure at a temperature not lower than a second temperature higher than the first temperature. The surfaces of the electrodes 5 and the insulating film 6 of a semiconductor chip 1a are planarized in continuously flat with a hard cutting tool, as of diamond or others.

Abstract: A method for making a composite integrated device includes providing a first integrated device having a substrate, an overlying interconnect region, and a contact, wherein the contact electrically contacts the interconnect region and is at a surface of the first integrated device. The method further includes forming a sidewall spacer along a sidewall of a first opening in a first dielectric layer, located over the surface of the integrated device, and providing a deformable metal feature adjacent to the sidewall spacer and in the first opening. The method further includes providing a second integrated device having a substrate, an overlying interconnect region, a contact, and a second dielectric layer surrounding the contact of the second integrated device. The method further includes contacting the contact of the second integrated device with the deformable metal feature and pressing the first dielectric layer against the second dielectric layer.

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include placing an anisotropic conductive layer comprising at least one compliant conductive sphere on at least one interconnect structure disposed on a first substrate, applying pressure to contact the compliant conductive spheres to the at least one interconnect structure, removing a portion of the anisotropic conductive layer to expose at least one of the compliant conductive spheres; and then attaching a second substrate to the anisotropic conductive layer.

Abstract: A method of making a semiconductor chip assembly includes mechanically attaching a semiconductor chip to a routing line, forming a thermal conductor on the chip, forming an encapsulant that covers the chip and the thermal conductor, grinding the encapsulant without grinding the thermal conductor or the chip and then grinding the encapsulant and the thermal conductor without grinding the chip such that the encapsulant and the thermal conductor are laterally aligned.

Abstract: A method of forming multiple bonds on an electronic device includes heating first bonding metals at a predetermined temperature to form a first bond comprising a first melting temperature above the predetermined temperature. The first bond and second bonding metals are then heated at the predetermined temperature to form a second bond comprising a second melting temperature above the predetermined temperature.

Abstract: A semiconductor sensor device is electrically coupled to an object. An attachment member attaches the semiconductor sensor device to the object. The attachment member comprises a first conductive contact region and a second conductive contact region. An insulating portion is electrically isolates the semiconductor sensor device from the first conductive contact region and second conductive contact region.

Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.

Abstract: A method of constructing an RFID unit can include using a protective layer to hold an integrated circuit chip module to a substrate layer with an antenna unit while a conductive adhesive has not yet fully set.

Abstract: A semiconductor die is attached to a packaging substrate by a patterned layer of conductive metal that includes voids. The voids provide a space into which the metal may expand when heated in order to avoid placing mechanical stress on the bonds caused by mismatches in the thermal coefficients of thermal expansion of the die, the conductive metal bond layer and the substrate. An additional coating of conductive metal may be flowed over the bond lines to reinforce the bonds.

Abstract: The invention provides a method of fabricating a micromachined structure, and in particular to a method of forming a micro-electro-mechanical system (MEMS) structure. A thin silicon cantilevered or suspended structure used to make micromachined structures is first formed from a SOI wafer or a bulk silicon wafer, followed by formation of the micromachined structures by semiconductor manufacturing techniques.

Abstract: An integrated circuit die includes a circuit surface and a back surface opposite the circuit surface. An underbump metallurgy is formed on a back surface. A layer of solder is formed on the underbump metallurgy.

Abstract: A method of constructing an RFID unit can include using a protective layer to hold an integrated circuit chip module to a substrate layer with an antenna unit while a conductive adhesive has not yet fully set.

Abstract: Provided is a method for manufacturing a semiconductor package. In the method, a wafer for a cap substrate is provided. The wafer for the cap substrate includes a plurality of vias and via electrodes on a lower surface. A wafer for a device substrate is provided. The wafer for the device substrate includes a circuit unit and a connection electrode on an upper surface. The wafer for the cap substrate and the wafer for the device substrate are primarily bonded by a medium of a primary adhesive. A trench is formed to expose the upper surface of the wafer for the device substrate to an outside along an outer edge of the primary adhesive. A secondary bonding operation is performed by a medium of a secondary adhesive to electrically connect the via electrode and the connection electrode. The wafer for the device substrate is diced along a virtual cut line.

Abstract: A semiconductor package with a semiconductor chip having under bump metallizations (UBMs) on a first surface and a substrate having open vias. The substrate is attached to the semiconductor chip with the UBMs in alignment with the open vias. An encapsulant surrounds the semiconductor chip and the substrate and a conductor fills the open vias to form external package connections. A method of forming a semiconductor package having external package connections includes providing a semiconductor chip having under bump metallizations (UBMs) on a first surface; attaching the first surface of the semiconductor chip to a substrate, the UBMs of the semiconductor chip being in alignment with open vias formed in the substrate; encapsulating the semiconductor chip and the substrate; and filling with open vias with a conductor to form the external package connections.

Abstract: A method of packaging a semiconductor die (20). The method comprises mounting a semiconductor die (20) to a die attach pad (34) on a carrier (10) and electrically coupling an electrode (36) of the semiconductor die (20) and a contact pad (16) on the carrier (10) with a clip (54) carried by a sacrificial substrate (58). The method further comprises removing the sacrificial substrate (58) to release the clip (54). The method may be extended to accommodate a carrier (10) having multiple device regions (12, 13) each with a die attach pad (34) and a contact pad (16) for mounting multiple semiconductor die (20).

Abstract: A semiconductor package substrate with embedded chip and a fabrication method thereof are provided. A first insulating layer is applied on a metallic board, and formed with at least one opening for exposing a portion of the metallic board. At least one semiconductor chip is mounted on the exposed portion of the metallic board. A support plate is mounted on the first insulating layer, and formed with a through cavity at a position corresponding to the opening of the first insulating layer, for receiving the chip in the through cavity. A second insulating layer is applied on the chip and the support plate. Insulating materials of the insulating layers fill a gap between the chip and the support plate. A circuit layer is formed on the second insulating layer, wherein the circuit layer is electrically connected to the chip by conductive structures formed in the second insulating layer.

Abstract: A semiconductor die assembly comprising a semiconductor die with bond pads, a plurality of leads which extend across the semiconductor die and terminates over their respective bond pads, and an alpha barrier preferably positioned between the leads and the semiconductor die. Electrical connection is made between the leads and their respective bond pads by a strip of anisotropically conductive elastomeric material, preferably a multi-layer laminate consisting of alternating parallel sheets of a conductive foil and an insulating elastomer wherein the laminate layers are oriented perpendicular to both the bond pad and the lead, positioned between the leads and the bond pads. A burn-in die according to the present invention is also disclosed.

Abstract: The present invention is directed to a new bonding pad structure having a rugged contact interface that makes it more difficult for a crack to grow from the peripheral edge of the bonding pad. The rugged contact interface also helps to accumulate more solder paste on the edge of the bonding pad, increase the thickness of the solder layer near the pad edge and prevent the pad edge from being oxidized and turning into a crack initiation point.

Abstract: Underfill compounds including electrically charged filler elements, microelectronic devices having underfill compounds including electrically charged filler elements, and methods of disposing underfill including electrically charged filler elements on microelectronic devices are disclosed herein. In one embodiment, a microelectronic device includes a microelectronic component, a plurality of electrical couplers carried by the microelectronic component, and an underfill layer covering at least a portion of the electrical couplers. The underfill layer comprises a binder and a plurality of electrically charged filler elements in the binder. The underfill layer can include a first zone having a first concentration of electrically charged filler elements and a second zone having a second concentration of electrically charged filler elements different than the first concentration.

Abstract: A fabric type semiconductor device package is provided. The fabric type semiconductor device package comprises a fabric type printed circuit board comprising a fabric and a lead unit formed by patterning a conductive material on the fabric, a semiconductor device comprising an electrode unit bonded to the lead unit of the fabric type printed circuit board, and a molding unit for sealing the fabric type printed circuit board and the semiconductor device. In the fabric type semiconductor device package according to the present invention, a fabric type printed circuit board formed of fabric is used so that a feeling of an alien substance can be minimized. The fabric type semiconductor device package can be easily installed. The productivity of the fabric type semiconductor device package can be improved.

Abstract: The invention is based on the discovery that a certain polyester compounds are useful as b-stageable adhesives for the microelectonic packaging industry. The polyester compounds described herein contain ring-opening or ring-forming polymerizable moieties and therefore exhibit little to no shrinkage upon cure. In addition, there are provided well-defined b-stageable adhesives useful in stacked die assemblies. In particular, there are provided assemblies wherein the b-stageable adhesive encapsulates a portion of the wiring members contained within the bondline gap between the stacked die.