Abstract: In a semiconductor device functioning as a three-dimensional device composed of two semiconductor chips bonded to each other, the back surface of the upper semiconductor chip is polished, the entire side surfaces of the upper semiconductor chip are covered with a resin layer, or the center portion of the upper semiconductor chip is formed to be thicker than the peripheral portion thereof. This suppresses the occurrence of a package crack and improves the reliability of the semiconductor device.

Abstract: A semiconductor device according to this invention, wherein two semiconductor chips are sealed by one resin body using two lead frames, includes a wide part extending in the width direction of dam bars, the width of one dam bar being narrower than the width of another dam bar, and the two lead frames are joined by welding outside the resin body after sealing them with resin.

Abstract: A lead frame has an array of mounting portions connected by joint bars, and each of the mounting portions has an island serving as an external connection terminal and a plurality of lead terminals extending from the island and serving as external connection terminals for a semiconductor chip to be mounted on an adjacent island along the array. An electrically conductive paste is applied to the island, and a semiconductor chip is mounted on the island. Then, the semiconductor chip is electrically connected to the lead terminals by wires. A resin layer is deposited over the semiconductor chip, a principal surface of the island, and principle surfaces the lead terminals, while leaving opposite surfaces of the island and the lead terminals exposed. A region surrounding the island and the lead terminals electrically connected to the island is cut off into a package.

Abstract: A multi-part lead frame die assembly is disclosed including a die bonded to a die paddle. A second lead frame including leads is superimposed and bonded onto the first lead frame. Also disclosed is a method for fabricating the multi-part lead frame assembly which utilizes equipment designed for single lead frame processing. If desired, the materials for the multi-part lead frame may be dissimilar.

Abstract: A stackable Ball Grid Array (BGA) semiconductor chip package and a fabrication method thereof increases reliability and mount density of a semiconductor package. The stackable BGA semiconductor chip package includes a supporting member that includes a supporting plate and a supporting frame formed on edges of the supporting plate. Conductive patterns are formed in and extend through the supporting member. First metal traces are formed on a bottom of the supporting plate and the first metal traces are connected to first ends of the conductive patterns in the supporting member. Second metal traces are attached to an upper surface of a semiconductor chip, and the semiconductor chip is attached to the supporting member. The second metal traces are connected to bond pads of the chip, and to upper ends of the conductive patterns in the supporting member. A plurality of conductive balls are then attached to exposed portions of the first and/or the second metal traces.

Abstract: A semiconductor package which includes: a semiconductor integrated circuit having chip pads formed thereon; interconnection bumps overlying on the chip pads; a patterned metal layer connecting to the interconnection bumps; a first dielectric layer under the patterned metal layer; a second dielectric layer overlying on the patterned metal layer; and terminal pads connecting to the patterned metal layer. The semiconductor package can further include external terminals connecting to the terminal pads, a third dielectric layer filling a gap between the first dielectric layer and the semiconductor integrated circuit.

Abstract: The invention provides a manufacturing process for making chip-size semi-conductor packages (“CSPs”) at the wafer-level without the added size, cost, and complexity of substrates in the packages or the need to overmold them with plastic. One embodiment of the method includes the provision of a semiconductor wafer with opposite top and bottom surfaces and a plurality of dies integrally defined therein. Each die has an electronic device formed in a top surface thereof, and one or more electrically conductive vias extending therethrough that electrically connect the electronic device to the bottom surface of the die. The openings for the vias are formed ablatively with a laser and plated through with a conductive material. In a BGA form of the CSP, the vias connects the electronic device to lands on the bottom surface of the die. The lands may each have a bump of a conductive metal, e.g., solder, attached to it that functions as an input-output terminal of the CSP.

Abstract: A hybrid semiconductor package is formed from a die having two opposed elongate die edges with conductive bond pads arranged transversely relative to the rows of outer leads. A first portion of inner leads is off-die wire bonded to some of the bond pads, and a second portion of inner leads is insulatively attached as LOC leads between the bond pads along the opposed die edges. The hybrid package results in shorter inner leads of increased pitch enabling improved line yield at wire bond and encapsulation, as well as improved electrical performance, particularly for packages with very small dice.

Abstract: A lead-frame-based chip-scale package (CSP) structure and a method of manufacturing the same are proposed. The proposed CSP structure is characterized in the use of a specially-designed lead frame having an inner-lead part and an outer-lead part, with each inner lead being formed with a deformed portion. During the encapsulation process, an epoxy molding compound (EMC) is formed to encapsulate the semiconductor die and the inner-lead part. By the proposed CSP structure, both sides of the inner-lead part can be wrapped by the EMC due to it being raised by the deformed portion to within the EMC. As a result, during the lead-singulation process, the inner-head part can be firmly supported in position, thereby reducing the occurrence of micro cracks in the EMC above the inner-lead part that would otherwise occur in the prior art.

Abstract: On a semiconductor material body housing an electronic device a peripheral region of semiconductor material and at least one pad are initially formed. The peripheral region is connected to a first terminal of the electronic device and extends on at least one peripheral portion of the semiconductor material body. The pad is insulated from the semiconductor material body and is electrically connected to a second terminal of the electronic device. The semiconductor material body is fixed to a support body formed by a blank belonging to a reel. The pad is connected by a wire to an electrode formed by the blank. Next, a connection region is formed on the peripheral region and surrounds, at least partially, the semiconductor material body and the support body. The connection region is advantageously obtained by galvanic growth.

Abstract: A leadframe for use in the assembly of integrated circuit chips comprising a base metal structure having an adherent layer of nickel covering said base metal; an adherent film of palladium on said nickel layer; and an adherent layer of palladium on said palladium film, selectively covering areas of said leadframe suitable for bonding wire attachment and solder attachment.

Abstract: Leads are connected between first and second elements so that a first end of each lead is connected to the first element and a second end of each lead is connected to the second element. and the elements are moved away from one another so as to bend the leads towards a vertically-extensive disposition. The direction of each lead, prior to the movement step, is represented by a lead direction vector from the first end of the lead to the second end of the same lead. At least some of these lead direction vectors are non-parallel with at least some other lead direction vectors, but the various lead direction vectors have components in a common direction. During the vertical movement step, the first element is moved in a horizontal direction of motion in this common direction, thereby moving the first end of each lead horizontally toward the second end of that lead, so as to provide or maintain slack in the leads.

Abstract: To enable readily forming the etching stop layer of a lead frame with multilayer structure by plating without using a large-scale device, enhance adhesive strength between the etching stop layer and an adjacent metal layer and prevent peeling caused by deterioration caused by the invasion of a chemical between the etching stop layer and each adjacent metal layer from occurring, an etching stop layer is formed by nickel or a nickel alloy in a method of manufacturing a lead frame at least provided with an etching process for selectively etching metal layers using an etching stop layer as an etching stopper in a state in which a thick metal layer is formed on one side of the etching stop layer as an intermediate layer and a thin metal layer is formed on the other side and a process for etching the etching stop layer using the metal layers on both sides as a mask.

Abstract: A resin sealing type semiconductor device, a manufacturing method thereof and a packaging structure thereof are capable of downsizing the semiconductor device and attaining high-density packaging. For this, the resin sealing type semiconductor device with leads exposed in an outer surface, is provided with spot leads adhered to a circuit forming surface of a semiconductor element with an insulating adhesive tape interposed therebetween, each independently regularly arrayed, and exposed to outside with the semiconductor element disposed inside.

Abstract: A packaged power semiconductor device (24) with voltage isolation between a metal backside (34) and the terminals (38) of the device. A direct-bonded copper (“DBC”) substrate (28) is used to provide electrical isolation and good thermal transfer from the device to a heatsink. A power semiconductor die (26) is soldered or otherwise mounted to a first metal layer (30) of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. The leads and die may be soldered to the DBC substrate in a single operation. In one embodiment, over 3,000 Volts of isolation is achieved. In another embodiment, the packaged power semiconductor device conforms to a TO-247 outline.

Abstract: A flip chip assembly, and methods of forming the same, including a single or multi-layer substrate having a plurality of via holes in which pre-formed strips or leads inside the via holes serve as the connections between the semiconductor device and substrate circuitry. The assembling steps include attaching an integrated circuit (IC) chip having a plurality of input/output terminal pads to a rigid or flexible substrate having a plurality of leads extending from the patterned circuitry traces and hanging inside a plurality of via holes. The via holes are aligned with and expose the terminal pads. After attachment, an electrically conductive material connects the leads to the IC terminal pads through electrolytic plating, electroless (chemical) plating or solder re-flow processes. The conductive material provides mechanical support as well as electrical continuity between the IC chip and the circuitry of the substrate.

Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.

Abstract: An insulating substrate (1) has insulative ceramic layers (2, 3) laid one upon another, an intermediate layer (4) made of a material that is different from a material of the ceramic layers and arranged between adjacent ones of the ceramic layers to join the adjacent ceramic layers to each other, a first conductive layer (5) joined to the top surface of a top one of the ceramic layers, and a second conductive layer (6) joined to the bottom surface of a bottom one of the ceramic layers. Even if any one of the ceramic layers has strength lower than design strength and causes a breakage due to, for example, thermal stress, the remaining ceramic layers are sound to secure a specified breakdown voltage for the insulating substrate.

Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.

Abstract: The present invention relates to a packaged semiconductor comprising:

Abstract: A leadless semiconductor package mainly comprises a semiconductor chip disposed on a die pad and electrically connected to a plurality of leads arranged around the die pad. There are a plurality of tie bars connected to the die pad. The lower surface of each lead has an indentation formed corresponding to one of the bottom edges of the package. The semiconductor chip, the leads and the tie bars are encapsulated in a package body wherein the lower surface of each lead is exposed from the bottom surface of the package except the indentation thereof.

Abstract: A method for forming a semiconductor device includes providing a lead frame which has a die pad and a plurality of leads extending toward the outside of the die pad, mounting a semiconductor chip on the die pad, defining a plurality of inner leads by cutting a predetermined cut portion on each of the leads located around the semiconductor chip, and bonding a wire between the inner leads and the semiconductor chip. Accordingly, an applicable lead frame is provided for several sizes of a semiconductor chip.

Abstract: A dual-dies packaging structure is provided. The dual-dies packaging structure includes a lead frame, which further includes a die pad and several lead legs, in which the die pad includes an upper surface and a lower surface. A first die, having several first bonding pads, is fixed on the upper surface of the die pad by, for example, gluing it. The first bonding pads remain exposed. A second die, having several second bonding pads, is fixed on the lower surface by, for example, gluing it. The second bonding pads remain exposed. A bumping redistribution structure layer is located on the second die so as to redistribute each of the second bonding pads to a pseudo-bonding pad. Each pseudo-bonding pad has its proper location with respect to the first bonding pads. Thus, when several bonding wires are used to bond the first bonding pads and the pseudo-bonding pads to the lead legs, bonding wires can be regularly and simply put on without crossing or entangling to each other.

Abstract: The semiconductor device comprises: a tub for supporting a semiconductor chip; a sealing body formed by sealing the semiconductor chip with a resin; a plurality of leads made of a copper alloy, exposed to the back face of the sealing body, and having a soldered layer on the exposed mounted face; and wires for connecting the pads of the semiconductor chip and the corresponding leads. In the manufacture method, the sealing body is polished, after resin-molded, at its back face with a brush to form the two widthwise edge portions, as exposed from the back face of the sealing body, of the lead into rounded faces, and the mounted face of the lead including the rounded faces is protruded at its central portion from the back face of the sealing body thereby to improve the connection reliability at the packaging time.

Abstract: A tapeless micro-leadframe has a plurality of preload extension tabs protruding from a flat base for integrated circuit packaging, to reduce the possibility of undesirable leakage or bleeding of mold flash.

Abstract: A lead frame made from Ni, a Ni alloy, Cu, a Cu alloy, Fe or an Fe alloy, comprising an inner lead part with a surface treatment layer of Ag or a Ag-containing alloy and an outer lead part with a surface treatment layer of an alloy containing Ag and Sn, wherein the latter surface treatment layer has a brightness of not less than 0.6 and Sn has the body-centered tetragonal lattice with the crystal orientation indices of from 1.5 to 5 at the (220) plane, not more than 0.9 at the (211) plane and not less than 0.5 at the (200) plane. The surface treatment layer is plated with utilization of a plating solution which contains one or more selected from alkane sulfonic acid, alkanol sulfonic acid and sulfamine acid as the acid component, one or more of tin methane-sulfonate and SnO as a tin salt, and one or more slected from silver methane-sulfonate, Ag2O and AgO as a silver salt.

Abstract: Semiconductor packages having a thin structure capable of easily discharging heat from a semiconductor chip included therein, and methods for fabricating such semiconductor packages, are disclosed.

Abstract: A chip of semiconductor material is fixed to a supporting area of a film of insulating material. Electrical interconnecting elements join metallized areas of the chip to the ends of metal strips which form the terminals of the device. To obtain devices with numerous terminals without approaching the dimensional limits imposed by the manufacture of the terminal frames, the interconnecting elements include electrically conductive tracks formed on the film of insulating material. The electrical connection between the ends of the terminals and the tracks is made by strips of anisotropic conductive material.

Abstract: A semiconductor device includes a two-part, coplanar, interdigitated decoupling capacitor formed as a part of the conductive lead frame. For down-bonded dice, the die attach paddle is formed as the interdigitated member. Alternatively, an interdigitated capacitor may be placed as a LOC type lead frame member between electrical bond pads on the die. The capacitor sections comprise Vcc and Vss bus bars.

Abstract: The invention encompasses a board-on-chip package comprising an insulative substrate having circuitry thereon and an opening therethrough. A semiconductive-material-comprising die is adhered to the substrate and electrically connected to the circuitry with a plurality of electrical interconnects extending through the opening. A metal foil is in physical contact with at least a portion of the die. The invention also encompasses a method of forming a plurality of board-on-chip packages. An insulative substrate is provided. Such substrate has a repeating circuitry pattern thereon, and a plurality of openings therethrough. The openings are in a one-to-one correspondence with individual of the repeated circuitry patterns. A plurality of semiconductive-material-comprising dies are adhered to the substrate. Circuitry supported by the dies is electrically connected with the circuitry on the substrate utilizing a plurality of electrical interconnects extending through the openings.

Abstract: Methods for forming substantially chip scale packages and the resulting structures. The methods comprise applying an adhesive on an active surface of a semiconductor chip to form a patterned adhesive layer on a portion of the active surface. A leadframe having leads with inner lead ends and outer lead ends is provided. The inner lead ends of the leads are aligned proximate to the adhesive-free area and the leads are attached to the adhesive layer on the active surface of the semiconductor chip. The outer lead ends are oriented to form a footprint which is not substantially larger than the dimensions of the semiconductor chip.

Abstract: A semiconductor device including a substantially flat leadframe that includes a die attach area on a surface of the leadframe. A die including solder bumps is placed thereon and a plurality of columns surround at least a portion of the periphery of the die attach area. The die is positioned within the die attach area and the columns have a height substantially equal to the solder bumps and the die on the leadframe.

Abstract: The present invention relates to a die pad of a leadframe. The die pad is used for receiving a die. The die and the die pad are connected by a solder paste. The die pad comprises a plurality of slots. The slots extend through the die pad. A restrictive region is defined by the slots such that the solder paste is restricted within the restrictive region. The die is positioned on the restrictive region. Because of the cohesion of the solder paste, the solder paste does not flow into the slots. Therefore, the solder paste does not flow and expand everywhere during the heating process. The solder paste is restricted within the restrictive region so that the die on the solder paste does not drift so as to increase the packaging quality.

Abstract: Methods for forming substantially chip scale packages and the resulting structures. The methods comprise applying an adhesive on an active surface of a semiconductor chip to form a patterned adhesive layer on a portion of the active surface. A leadframe having leads with inner lead ends and outer lead ends is provided. The inner lead ends of the leads are aligned proximate to the adhesive-free area and the leads are attached to the adhesive layer on the active surface of the semiconductor chip. The outer lead ends are oriented to form a footprint which is not substantially larger than the dimensions of the semiconductor chip.

Abstract: A hybrid semiconductor device comprises four identical semiconductor diode chips each having top and bottom surfaces. Each chip is mounted on a respective mounting pad all of which lie in a common plane and, for ease of assembly, the four chips are mounted in identical top to bottom orientation, e.g., bottom surface down and electrically connected to the mounting pads. In one embodiment, the mounting pads for the chips and terminals for the device are integral with leads of a single (“component”) lead frame and various electrical connectors for the chips comprise bonding wires or stamped metal jumpers added to the workpiece after the chips are mounted on the lead frame. The metal jumpers can be provided on a separate “jumper” lead frame used in cooperation with the component lead frame, or the jumpers can comprise portions of leads of the single component lead frame. Printed circuit boards embodiments are also disclosed.

Abstract: Methods for forming substantially chip scale packages and the resulting structures. The methods comprise applying an adhesive on an active surface of a semiconductor chip to form a patterned adhesive layer on a portion of the active surface. A leadframe having leads with inner lead ends and outer lead ends is provided. The inner lead ends of the leads are aligned proximate to the adhesive-free area and the leads are attached to the adhesive layer on the active surface of the semiconductor chip. The outer lead ends are oriented to form a footprint which is not substantially larger than the dimensions of the semiconductor chip.

Abstract: The present invention controls attachment of a first semiconductor material, such as a semiconductor die, to a second semiconductor material, such as a bond pad, substrate, or the like. A placement tool is used to pick up the first semiconductor material and move it to a defined position above the top surface of the second semiconductor material. The second semiconductor material will have an adhesive, such as epoxy, applied to its top surface. From the defined position above the second semiconductor material, the placement tool is allowed to fall for an amount of time previously determined to result in an adhesive layer of a defined thickness, within precise tolerances. The adhesive thickness is often referred to as bond line thickness (BLT) when bonding a semiconductor die to a bond pad, substrate, or the like.

Abstract: A multichip semiconductor assembly comprising a semiconductor chip stack comprising first and second chips, each having an active surface including an integrated circuit and a plurality of input/output contact pads; a leadframe for interconnecting semiconductor integrated circuits having a plurality of leads, portions of said leads comprising undulating patterns and a surface metallurgy for promoting solder wetting, said leadframe being disposed between said first and second chips, and said active surface of said first chip positioned in front of said active surface of said second chip; and connections between each of said contact pads of said first chip to one of said leads, respectively, and between each of said contact pads of said second chip to one of said leads, respectively, said connections comprising solder balls, whereby the connections to at least one of said leads are common between said first and second chips.

Abstract: A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.

Abstract: The present invention is to provide a effective method for packing an electronic device including steps of: (a) putting an electronic device having a plurality of pins in a frame having a plurality of connecting members corresponding to said plurality of pins; (b) electrically connecting the plurality of pins of the electronic device with the corresponding connecting members; (c) mounting a fixing member on the electronic device to fix the electronic device with respect to the frame to form a semi-product; and(d) packing the semi-product with the fixing member.

Abstract: A method of manufacturing a semiconductor device which includes a semiconductor chip and a plastic package of a thermosetting polymer, including the steps of performing an ultraviolet cleaning process on the bottom surface of the semiconductor chip and, encapsulating the semiconductor chip through a molding process. The thermosetting polymer of the plastic package fully or partially covers the bottom surface of the semiconductor chip.

Abstract: A leadframe configuration for a semiconductor device has a die attach paddle with paddle support bars. In addition, clamp tabs extend outwardly from lesser supported locations of the paddle to underlie a conventional lead clamp. The clamp tabs are formed as an integral part of the paddle. Normal clamping during die attach and wire bonding operations prevents paddle movement and enhances integrity of the die bond and wire bonds.

Abstract: A leadframe including offsets extending from a major plane thereof The offsets extend from the major plane at a non-perpendicular angle thereto. Preferably, the angle of extension, relative to the major plane, is about 45 degrees or less. The offsets may extend upwardly and/or downwardly from the major plane. The offsets of the present invention are useful for preventing warpage, bowing, skewing, or other distortions of a packaged semiconductor device including same when subjected to high temperatures or changes in temperature.

Abstract: A semiconductor device package is formed with a lead frame including a plurality of lead members positioned in an array, and a semiconductor die is secured to the lead frame. At least one pair of bus bars is connected to the lead frame and positioned over the semiconductor die, with the bus bars including a plurality of inner-digitized bond fingers. The inner-digitized bond fingers are formed from a series of alternating projections and recesses on each bus bar. A plurality of bond wires electrically couples the lead members to the semiconductor die. Other bond wires electrically couple the inner-digitized bond fingers of the bus bars to the semiconductor die. The bond wires attached to the inner-digitized bond fingers have a substantially uniform loop height and length, providing for easier manufacture and inspection of the semiconductor device package.

Abstract: A semiconductor device has a semiconductor chip fixedly mounted on an island and a bonding wire connecting a bonding pad on the semiconductor chip to a lead terminal whose end is positioned near the island. The semiconductor chip and the bonding wire are encased by a molded resin. The bonding wire includes a first extension ascending substantially vertically from the bonding pad, a second extension extending substantially horizontally from the first extension, and a third extension descending substantially vertically from the second extension. A bend between the second and third extensions is disposed outwardly of an end of the semiconductor chip.

Abstract: A method of manufacturing semiconductor components (200, 400, 700) includes assembling, packaging, and testing the semiconductor components (200, 400, 700) while the semiconductor components (200, 400, 700) are mounted on an adhesive layer (220). The method of can also keep the semiconductor components (200, 400, 700) mounted on the adhesive layer (220) between each of the assembling, packaging, and testing steps.

Abstract: Providing a method of producing a semiconductor device wherein semiconductor element are sealed with a resin by using the same lead and other means regardless of the specifications of the semiconductor elements, and a semiconductor device which can be reduced in size and weight and has good heat dissipation performance and high-frequency performance. The semiconductor devices can be produced by mounting a plurality of the semiconductor elements on the lead frame having leads disposed substantially parallel to each other, sealing the whole with a resin, and cutting off the individual semiconductor devices.

Abstract: Barrier structures are included within the packaging material of a packaged semiconductor device, such barrier structures including barrier bodies which overlie the die-die pad assembly of the device on either side thereof. The barrier bodies act as baffles which limit diffusion of moisture through the packaging material into the area of the die-die pad assembly of the device, the barrier bodies including apertures therethrough which control such diffusion in a manner that avoids delamination problems in the area of the die-die pad assembly, meanwhile also avoiding undesirable trapping of gas within the packaging material.

Abstract: There is provided a solid-state image sensing device, having: a semiconductor chip having an effective area used for image sensing; a sealing plate provided opposedly to the semiconductor chip; inner leads arranged between an outside portion of the effective area of the semiconductor chip and the sealing plate, and connected electrically to the semiconductor chip; and a sealant in contact with the end portion and the side face on the effective area side of the inner leads.

Abstract: A process of manufacturing a multi-chip semiconductor module includes: providing a substrate having opposite first and second surfaces, a plurality of conductive vias that extend through the first and second surfaces, a circuit layout patterned on the first surface of the substrate and connected electrically to the conductive vias, and a chip-receiving opening formed therein; mounting a contact pad surface of a first semiconductor chip on the first surface of the substrate such that the first semiconductor chip has a first set of contact pads registered with the chip-receiving opening, and a second set of contact pads around the chip-receiving opening, and connecting electrically the second set of contact pads of the first semiconductor chip to the circuit layout; disposing an adhesive layer having opposite first and second adhesive surfaces and a plurality of windows that extend through the first and second adhesive surfaces inside the chip-receiving opening, and adhering the second adhesive surface of the a