Abstract: Improvement is affected in uniformizing the thickness of a tape carrier package having a semiconductor chip in which bonding pads are disposed in such a way that the bonding pads are arranged concentratedly on one side of the semiconductor chip.

Abstract: In a lead frame with a reinforcing ring surrounding a semiconductor element which are electrically connected to leads through electrodes is integrally formed through suspending portions, reinforcing portions for reinforcing the suspending portions are provided on the suspending portions. Upon application of a lead frame forming technique in which a laminate plate of three or more layers is used as a base, and inner leads are formed at one side while outer leads are formed by the surface layer at the other side, the lead frame is formed by forming a ring in place of outer leads, for example. A semiconductor package is formed by mounting the lead frame on a semiconductor chip.

Abstract: Disclosed is a semiconductor device which comprises a semiconductor element having a plurality of electrodes, a plurality of external electrodes disposed around the periphery of the semiconductor element, a fine wire electrically connected between at least one of surfaces of each of the plural external electrodes and at least one of the plural electrodes of the semiconductor element, and an encapsulating resin which encapsulates the semiconductor element, the plural external electrodes, and the fine wires and whose external shape is a rectangular parallelepiped, wherein a bottom surface of the semiconductor element and a bottom surface of each of the plural external electrode are exposed from a bottom surface of the encapsulating resin and a top surface of the semiconductor element and a top surface of each of the plural external electrode are located substantially coplanar with each other.

Abstract: An integrated circuit package (50) may include an integrated circuit chip (22) having an integrated circuit (14). A lead frame (28) may be opposite the integrated circuit chip (22). The lead frame (28) may include at least one lead (30) electrically coupled to the integrated circuit (14) by a connector (42). The lead (30) may be within a periphery (32) of the integrated circuit chip (22). An encapsulant (44) may cover the integrated circuit (14), the connector (42) and a portion of the lead frame (28). A remaining portion of the lead frame (28) may be exposed from the encapsulant (44).

Abstract: The present invention is directed to a method of attaching a leadframe to a singulated good die using a wet film adhesive applied in a predetermined pattern on the active surface of the good die, the lead finger of a leadframe, or both. By applying the adhesive only to identified good dice, time and material are saved over a process that applies adhesive to the entire wafer. By attaching the leadframe to the good die with a wet film, it is possible to remove the leadframe from the good die for rework if the good die subsequently tests unacceptable.

Abstract: A method of manufacturing a leadless semiconductor chip package comprises the steps of: attaching a semiconductor die onto a die pad of a lead frame, wherein the lead frame comprises a plurality of leads arranged about the periphery of the die pad and each lead has a notch formed at the to-be-punched position thereof; wire bonding the inner ends of the leads to bonding pads on the semiconductor die; sucking a film against a lower part of a molding die; closing and clamping the molding die in a manner that the semiconductor die is positioned in a cavity of the molding die and the lead frame is disposed against the film; transferring a hardenable molding compound into the cavity; hardening the molding compound; opening the molding die to take out the molded product; and punching the molded product along the notches of the leads thereby making the singulation process more convenient and correct.

Abstract: A lead frame for a semiconductor chip package includes a frame body and at least two chip-receiving windows formed in the frame body. Each chip-receiving window receives a respective integrated circuit chip therein. A plurality of internal connection leads are formed on the frame body adjacent to the chip-receiving windows, and are connected electrically to bonding pads on the integrated circuit chips in the chip-receiving windows such that internal electrical connection among the integrated circuit chips can be established via the internal connection leads., A plurality of external connection leads are formed on the frame body adjacent to at least one of the chip-receiving windows, and are connected electrically to the bonding pads on the integrated circuit chip in the adjacent chip-receiving window.

Abstract: A semiconductor die assembly comprising a semiconductor die with bond pads, a plurality of leads which extends across the semiconductor die and terminates over its respective bond pads, and an alpha barrier preferably positioned between the leads and the semiconductor die. Electrical connection is made between the leads and their respective bond pads by a strip of anisotropically conductive elastomeric material, preferably a multi-layer laminate consisting of alternating parallel sheets of a conductive foil and an insulating elastomer wherein the laminate layers are oriented perpendicular to both the bond pad and the lead, positioned between the leads and the bond pads. A burn-in die according to the present invention is also disclosed.

Abstract: A semiconductor device which includes a semiconductor chip mounted on a die pad having first and second surfaces opposite to each other with the semiconductor chip mounted on the first surface, and one or a plurality of electrode terminals having third and fourth surfaces opposite to each other and spaced a distance from the die pad and electrically connected with the semiconductor chip through a corresponding wire with the wire being connected to the third surface. Further, a sealing resin encloses the die pad and the electrode terminal. A surface of the die pad opposite to the surface on which the second and fourth surfaces of the die pad and the electrode terminal, respectively, is exposed to an outside of the sealing resin.

Abstract: A semiconductor integrated circuit device, and method of manufacturing the same, having a conventional-type lead frame with the die paddle removed. In particular, the die paddle is replaced with a section of tape that is supported by the ends of the lead fingers. The semiconductor die is attached to the tape so that it may be wire bonded to the lead fingers. The tape contains at least one slot to allow for expansion and/or contraction of the tape due to various temperatures experienced during the manufacturing process so that the tape does not wrinkle or warp to alter the position of the die.

Abstract: Leadless plastic chip carriers are formed from a matrix of lead frames provided in a section of a metal strip. Each lead frame in the matrix includes a die-attach pad and multiple leads disposed in close proximity to the die-attach pad. After a semiconductor die is attached to each of the die-attach pad and wire-bonded, the leadless plastic chip carriers are formed by providing a plastic encapsulation which exposes the bottom sides of the die-attach pad and the leads. The bottom sides of the leads serve as solder pads to be used for attaching the leadless plastic chip carrier to a printed circuit board.

Abstract: In the present semiconductor device, a chip with an LSI circuit is secured to a board 3 (with the chip flipped) so as to be level. The LSI circuit on the chip is specified to operate normally only when the chip is level. Further, the back of the chip is processed so as to give stress to the chip. The chip has a reduced thickness of 50 &mgr;m or less (alternatively 30 &mgr;m to 50 &mgr;m). Therefore, when the chip is detached from the board, it deforms and is no longer level due to the stress, which prohibits the LSI circuit from operating normally. This way, the present semiconductor device ensures that no analysis can be conducted on the LSI circuit once the chip is detached.

Abstract: A package substrate suitable for use with a ball grid array according to the invention includes an electrically and thermally conductive heat sink having a top surface and a bottom surface, the heat sink having a slot formed therethrough which opens onto the top and bottom surfaces. A dielectric layer is formed on the bottom surface of the heat sink proximate the slot, preferably directly thereon without an intervening adhesive layer. A circuit is selectively formed in a circuit pattern on the dielectric layer. An electrically resistive soldermask is disposed on the dielectric layer and the circuit, which soldermask has openings therethrough which expose bond pads of the circuit. Such a substrate according to the invention permits the integrated circuit die to be mounted over the slot in the manner of a lead-on-chip package, but provides bond pads to which solder balls can be mounted in order to form a ball grid array.

Abstract: A memory TCP loaded with four chips (1-bank 16-bit type) is constructed by a tape of one two-layer wiring layer structure, four chips mounted to this tape, etc. Common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side. The common signal terminals on the two sides are electrically connected to each other common signal wiring. Further, in a DIMM in which this memory TCP is mounted to front and rear sides of a substrate, plural external terminals are formed on one long side of the rectangular substrate, and the memory TCP is mounted such that the independent signal terminal of the memory TCP is arranged along an arranging direction of these external terminals.

Abstract: A memory TCP loaded with four chips (1-bank 16-bit type) is constructed by a tape of one two-layer wiring layer structure, four chips mounted to this tape, etc. Common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side. The common signal terminals on the two sides are electrically connected to each other common signal wiring. Further, in a DIMM in which this memory TCP is mounted to front and rear sides of a substrate, plural external terminals are formed on one long side of the rectangular substrate, and the memory TCP is mounted such that the independent signal terminal of the memory TCP is arranged along an arranging direction of these external terminals.

Abstract: Metal bond pads are formed over active circuitry in a semiconductor chip in a reliable and cost effective manner. According to an example embodiment of the present invention, a metal bond pad is formed over circuitry in the semiconductor chip. A metal layer is formed over the circuitry and the metal bond pad, and a diffusion barrier layer is formed between the metal layer and the metal bond pad. In this manner, additional metal can be formed on the pad site using only one additional mask step, and thicker metal at the pad site improves the reliability of the chip by providing for a metal cushion at the pad useful in subsequent wire bonding processes.

Abstract: A film carrier tape and laminated multi-chip semiconductor device incorporating the same and method thereof wherein a plurality of chip semiconductor devices are laminated onto a substrate. Each chip semiconductor device includes a film carrier tape having leads, a semiconductor chip electrically connected to the leads, a heat sink mounted to a surface of the chip, and a connector for mounting the heat sink, the connector being electrically connected to the leads of the film carrier tape. The film carrier tape includes a carrier member having a metallic layer superposed thereon which is etched so as to form the leads and the heat sink.

Abstract: A method is proposed for forming a constricted-mouth dimple structure on a lead-frame die pad for an integrated circuit (IC) package. This method can help secure the molded compound of the integrated circuit package more firmly in position to the die pad so that the molded compound would be less likely subjected to delamination. This method is charaterized in the use of a stamping process to punch on a selected part of the die pad that is located around the mouth of an originally-formed inwardly-tapered dimple structure, thereby narrowing the mouth of the inwardly-tapered dimple structure, resulting in the forming of the intended constricted-mouth dimple structure. Since this method requires only an additional stamping process to narrow the originally-formed inwardly-tapered dimple structure, it is much easier and more cost-effective to implement than the prior art.

Abstract: A method of forming a semiconductor memory device comprises the steps of providing a semiconductor die, forming a temporary protective material over a surface of the die, and attaching the die to a first lead frame portion. Next, a protective material is contacted with a second lead frame portion and, subsequently, the second lead frame portion is electrically connected with the second lead frame portion with bond pads on the first surface of the die with bond wires. Subsequent to electrically connecting the die and the second lead frame portion the protective material is removed.

Abstract: A conductive plastic lead frame and method of manufacturing same suitable for use in IC packaging. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.

Abstract: A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.

Abstract: A process is provided for the fabrication of a plastic molded type semiconductor device in which a die pad is formed to have a smaller area than a semiconductor chip to be mounted on a principal surface of the die pad and the semiconductor chip and die pad are sealed with a plastic mold.

Abstract: A method for manufacturing a semiconductor chip (15) which is bonded on a die pad (13) of a leadframe, and inner leads (12) are electrically connected to electrode pads of the semiconductor chip (15) with metal fine wires (16). The die pad (13), semiconductor chip (15) and inner leads are molded with a resin encapsulant (17). However, no resin encapsulant (17) exists on the respective back surfaces of the inner leads (12), which protrude downward from the back surface of the resin encapsulant (17) so as to be external electrodes (18).

Abstract: The present invention is related to a method for manufacturing lead frames and a lead frame material including an intermediate layer and a top layer. The intermediate layer is composed of a layer of nickel-cobalt alloy having 5 to 30 wt. % of cobalt and a thickness of 3 to 20 microinches and a layer of nickel or nickel alloy having a thickness of 10 to 80 microinches. The intermediate layer can inhibit the diffusion of the base metal to the surface of the leads. The top layer consisting of gold or gold alloy, which is composed of gold and at least one metal selected from the group consisting of palladium, silver, tin and copper and has at least 60 weight percent gold, has a thickness of 0.1 to 5 microinches.

Abstract: A package is disclosed in which deterioration of insulating encapsulation resin attributable to the generation of heat at source wires caused by an increase in a drain current is prevented. Specifically, there is provided a semiconductor package including a header made of metal, a semiconductor chip forming a power MOSFET secured on the header, an encapsulation element made of insulating resin covering the semiconductor chip, header and the like, a suspended lead contiguous with the header protruding from one side surface of the encapsulation element, a source lead and a gate lead protruding in parallel from one side surface of the encapsulation element, and wires positioned in the encapsulation element for connecting electrodes on the upper surface of the semiconductor chip and the source and gate leads. The source lead is constituted by a plurality of leads in parallel with each other, and the ends of the leads are coupled into one coupling portion in the encapsulation element.

Abstract: A semiconductor die assembly employing a voltage reference plane structure electrically isolated from, but in immediate proximity to, leads of a lead frame to which the die is electrically connected. A non-conductive adhesive or an adhesively-coated dielectric film is used to position the voltage reference plane on the leads. The voltage reference plane is electrically connected to a ground or other reference potential pin of the die through a connection to one of the leads. The assembly is encapsulated, preferably by transfer-molding of a filled polymer. More than one discrete voltage reference plane structure may be employed, for example, when the package is of an LOC configuration with two rows of leads, each having a voltage reference plane secured thereto, or a single voltage reference plane including major portions adhered to leads and interposed connection portions may be applied to all of the leads of an assembly.

Abstract: A method for fabricating semiconductor components, such as BGA packages, chip scale packages, and multi chip modules, includes the steps of cutting decals from ribbons of adhesive tape, and then attaching a semiconductor die to a substrate using the decals. A system for performing the method includes a tape cutting apparatus configured to cut the decals from the tape without wasted tape, and then to apply the cut decals to the substrate. A first finished dimension (e.g., width) of the decals is determined by a width of the tape, and a second finished dimension (e.g., length) of the decals is determined by indexing the tape through a selected distance. The tape cutting apparatus includes cutters configured to move through guide openings to cut and apply the decals to the substrate. The guide openings align the tape to the cutters, and also align the cut decals to the substrate. The system also includes a substrate handling apparatus configured to index and position the substrate relative to the guide openings.

Abstract: A hybrid lead frame having leads for conventional lead-to-I/O wire bonding, and leads for power and ground bussing that extend over a surface of the semiconductor die are provided where the leads for bussing are held in place by lead-lock tape to prevent bending and/or other movement of the bussing leads during manufacturing. More specifically, the lead-lock tape is transversely attached across a plurality of bussing leads proximate to and outside of the position where the die is to be attached.

Abstract: A process for manufacturing a semiconductor device assembly including a semiconductor device having a plurality of bond pads on the active surface thereof and a lead frame having a portion of the plurality of lead fingers of the lead frame located below the semiconductor device in a substantially horizontal plane and another portion of the plurality of lead fingers of the lead frame located substantially in the same horizontal plane as the active surface of the semiconductor device. Both pluralities of lead fingers of the lead frame having their ends being located substantially adjacent the peripheral sides of the semiconductor device, rather than at the ends thereof.

Abstract: In construction of a plastic molded semiconductor package provided with a heat sink and electrically conductive leads attached to the periphery of the heat sink, a conventional electrically insulating, adhesive bonding tape is replaced by a non-adhesive insulating sheet and support bars are locally provided in a lead frame between the leads. For uniting the leads to the heat sink, the support bars are fixed to the heat sink whilst sandwiching the insulating sheet. Elimination of the adhesive bonding tape greatly reduces intrusion of contaminants into the package, simplifies the production process and lowers the production cost.

Abstract: A semiconductor device of this invention has an LOC (Lead On Chip) structure, and a protective film consisting of a thermoplastic (thermosetting) resin material such as a thermoplastic (thermosetting) polyimide resin or a thermoplastic (thermosetting) polyamide resin is formed on the surface of a semiconductor chip having a DRAM. The lower surface of a lead frame is positioned to the upper surface of the semiconductor chip, on which the protective film is formed, and the upper surface of the semiconductor chip is bonded and fixed to the lower surface of the distal end portion of an inner lead with only the protective film interposed therebetween such that bonding pads appear between opposing bus bars. According to this invention, the protective film serves not only as an &agr;-ray protective film but also as an insulating material and an adhesive material.

Abstract: A resin-sealed LOC type semiconductor device includes semiconductor chip having a circuit surface on which electrodes are formed. Leads are arranged with their distal ends overlapping the semiconductor chip, electrically connected to the respective electrodes. A lead fixing resin layer is interposed between the semiconductor chip and the leads to fix them. A sealing resin layer coats the semiconductor chip and the lead to over them. The diameter of filler contained in the lead fixing resin layer is about {fraction (1/10)} to ⅕ the diameter of filler contained in the sealing resin layer, and is about {fraction (1/10)} the width of a gap between each lead and the semi conductor chip.

Abstract: An integrated circuit is provided having an alignment feature integral with the lead frame. The integrated circuit includes a lead frame coupled with a semiconductor die, and is partially encapsulated in insulating material. The lead frame has the alignment feature therein. The alignment feature includes a cut out on the lead frame taking the form of a semi-circle, protuberance, apertures, or slots. Alternatively, the alignment feature includes a removably coupled tab. After testing of the integrated circuit has been completed, the alignment tab is removed from the integrated circuit. The alignment feature can also be provided on a heat spreader which is attached to a side of or within the lead frame package.

Abstract: A process is provided for the fabrication of a plastic molded type semiconductor device in which a die pad is formed to have a smaller area than a semiconductor chip to be mounted on a principal surface of the die pad and the semiconductor chip and die pad are sealed with a plastic mold.

Abstract: An integrated circuit package includes a semiconductor chip, a plurality of wired pins, and at least one non-wired pin. The size of the non-wired pin is minimized, or the non-wired pin is eliminated, in order to increase the lead pin spacing. The increase in lead pin spacing prevents electrostatic discharge failure in an integrated circuit package due to electrostatic stressing of the non-wired pin.

Abstract: A lead frame to support a semiconductor die within an encapsulating package. The lead frame includes a first rail and a second rail in a first plane, with the second rail parallel to and spaced apart from the first rail by more than the length of the package. A first bar and a second bar are connected perpendicularly to the first and second rails, with the second bar spaced apart from the first bar by more than the width of the package. A lead is connected perpendicularly to the first bar with an unconnected lead end extending toward the second bar and located to extend under the supported semiconductor die. A first support tab is connected perpendicularly to the first rail with a first unconnected tab end extending toward the second rail and located to extend under the supported semiconductor die. A second support tab is connected perpendicularly to the second rail with a second unconnected tab end extending toward the first rail and located to extend under the supported semiconductor die.

Abstract: A semiconductor device includes a two-part, coplanar, interdigitated decoupling capacitor formed as a part of the conductive lead frame. For down-bonded dice, the die attach paddle is formed as the interdigitated member. Alternatively, an interdigitated capacitor may be placed as a LOC type lead frame member between electrical bond pads on the die. The capacitor sections comprise Vcc and Vss bus bars.

Abstract: A semiconductor apparatus includes a thin film belt-like insulating tape having a plurality of predetermined wire patterns thereon, and a plurality of IC chips that are provided on a surface of the insulating tape at uniform spaces in a lengthwise direction and electrically connected with the wire patterns, and further includes thick film reinforcing tapes with sprocket holes for transport use provided at uniform spaces, the reinforcing tapes being provided on both side portions of the insulating tape, in the lengthwise direction.

Abstract: The present invention relates to a bump formation method, comprising the steps of providing a mask, in which a plurality of openings have been formed corresponding to a plurality of electrode pads, to a substrate provided with this plurality of electrode pads, filling the openings with a solder paste, and heat treating the solder paste. The solder paste contains a solder powder. This solder powder is one that contains no more than 10 wt % particles whose diameter is greater than the thickness of the mask and no more than 1.5 times this thickness. Preferably, this solder powder is one that contains no more than 10 wt % particles whose diameter is greater than 40% of the diameter of the openings, or one that contains no more than 30 wt % particles whose diameter is 40 to 100% the thickness of the mask.

Abstract: The present invention provides a hybrid chip package that utilizes a high-speed BGA structure and a plurality of flexible and reliable QFP leads. More specifically, the QFP leads are attached to a peripheral region of a substrate to surround the attached BGA structure and replace solder bumps of a conventional BGA structure that would typically flack or crack during operational cycles to create an electrical open between the conventional BGA package and the attached printed circuit board.

Abstract: A method for packaging a semiconductor device (23) to form a semiconductor component (10). A die attach material (17) is disposed on a flange (11). A semiconductor chip (23) is bonded to the die attach material (17). After disposing the die attach material (17) on the flange (11), an insulator material (28) is coupled to the flange (11). A leadframe (32) is coupled to the semiconductor chip (23) via a plurality of wirebonds (36). The wirebonds (36) and the semiconductor chip (23) are protected by a lid (37).

Abstract: A multi-chip semiconductor package using a lead-on-chip lead frame. The lead-on-chip package places two or more lead-on-chip dice into one package that are either attached to their own lead-on-chip lead frame or are mounted to the same lead-on-chip lead frame and subsequently wire bonded to provide electrical connection from the dice to the lead frame while in substantially the same arrangement without requiring the assembly of the multiple semiconductor dice and lead frame to be flipped for additional wire bonding attachment of the dice to the lead frame.

Abstract: Metal bond pads are formed over active circuitry in a semiconductor chip in a reliable and cost effective manner. According to an example embodiment of the present invention, a metal bond pad is formed over circuitry in the semiconductor chip. A metal layer is formed over the circuitry and the metal bond pad, and a photoresist mask is patterned over the metal layer. The metal layer is etched and the portion of the metal layer not masked with the photoresist is removed. In this manner, additional metal can be formed on the pad site using only one additional mask step, and the thicker metal at the pad site improves the reliability of the chip by providing for a metal cushion at the pad useful in subsequent wire bonding processes.

Abstract: A method for forming a package of plastic material for a semiconductor electronic device having heat sink fully embedded within the package plastic case, is of the type which provides for forming the plastic case within a mold on whose interior a heat sink has been placed which has a first major surface to be insulated by means of a plastic material layer with a first thickness, whereon a metal leadframe and at least one semiconductor material die having an electronic circuit formed thereon have been fixed, and a second major surface opposite from the first and to be insulated by means of a plastic material layer with a second thickness, thinner than said first thickness; and at least one supporting element adapted to be positioned inside the mold cavity facilitating properly spacing the second surface of the heat sink out from a facing wall of the mold cavity during the process of introducing the plastic material for molding.

Abstract: The invention relates to a semiconductor device formed by using a film carrier tape and having a package size that is close to the chip size, and also to a semiconductor device and a making method therefor which facilitates the injection of resin for sealing. A film carrier tape 32 comprises a plurality of connection leads (24); portions defining holes (29, 31) formed by punching out connection portions, where any one of the connection leads (24) are connected together, and by punching out an intersection portion; and portions defining rectangular holes (11, 15). Resin is injected through rectangular holes (11, 15), rectangular holes (12, 14) stop the spreading of the resin, and holes (29, 31) allow air to escape from the resin.

Abstract: A method for fabricating an integrated circuit chip includes the steps of:

Abstract: Resin sealed lead frames are processed by modular processing work stations related in number to a plurality of steps used in processing the lead or leads of the resin sealed lead frame. The work stations are separate modules which are detachably interconnected, whereby the number of modules can be exactly correlated to the number of steps actually required for processing the lead or leads of the resin sealed lead frame. As required, modules can be added or omitted. The resin sealed lead frame is sequentially advanced through the modules in steps corresponding to at least two pitches, whereby one pitch is defined as the on-center spacing between two neighboring products on the lead frame. Such feed advance permits performing at least two processing steps simultaneously. Thus, the method for processing the resin sealed lead frame and the apparatus therefore are adaptable to a change in the type of processing and to the production volume.

Abstract: A semiconductor package provided with a reinforcing plate on the side of the lead joined face of which a chip housing concave portion is formed, a semiconductor chip housed and fixed in the chip housing concave portion of this reinforcing plate, a plurality of leads joined and held on the lead joined face of the reinforcing plate, the inner lead section of which is joined to the semiconductor chip via a bump and in the outer lead section of which a protruded electrode is formed, a solder resist film formed on the lead except the bump formed area and the electrode formed area of this lead and a polyimide film formed on the side of the inner lead section of the lead on the solder resist film and the manufacturing method are disclosed and hereby, the quality of the semiconductor package with ultra-multipin structure is stabilized.

Abstract: In a plastic packaged semiconductor device, a chip support formed on the same lead frame as leads is disposed so as to extend over the surface of a semiconductor element, the chip support is bonded and fixed to the surface of a polyimide wafer coat on the semiconductor element by means of an insulating tape, the leads are brought into contact with the polyimide wafer coat on the semiconductor element without being fixed, the leads and the electrodes of the semiconductor element are connected by means of gold wires, and these are packaged by a packaging material. Generation of crack in the sealing material thereby prevented, and the thickness of the plastic packaged semiconductor device is reduced.

Abstract: A semiconductor package having outer leads which are not protruded from the package but only exposed to outside. The semiconductor package comprises a semiconductor chip which is formed with a plurality of bond pads at a central portion of its bottom surface, a lead frame including leads connected to bond pads for input/output of the bond pads respectively and bus bars connected to power supplying pads of the bond pads, insulation adhesives for attaching inner leads of the leads and inner leads of the bus bars to a bottom surface of the semiconductor chip formed with the bond pads, metal wires for electrically connecting the inner leads of the leads and the inner leads of the bus bars to the bond pads respectively, and a molding compound enveloping the semiconductor chip assembly with outer leads of the lead frame exposed to outside. The adhesive tapes are removed after a molding procedure.