Encapsulating Patents (Class 438/127)
  • Patent number: 10763194
    Abstract: A semiconductor package includes a lead frame, a die, a discrete electrical component, and electrical connections. The lead frame includes leads and a die pad. Some of the leads include engraved regions that have recesses therein and the die pad may include an engraved region or multiple engraved regions. Each engraved region is formed to contain and confine a conductive adhesive from flowing over the edges of the engraved leads or the die pad. The boundary confines the conductive adhesive to the appropriate location on the engraved lead or the engraved die pad when being placed on the engraved regions. By utilizing a lead frame with engraved regions, the flow of the conductive adhesive or the wettability of the conductive adhesive can be contained and confined to the appropriate areas of the engraved lead or engraved die pad such that a conductive adhesive does not cause cross-talk between electrical components within a semiconductor package or short circuiting within a semiconductor package.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: September 1, 2020
    Assignees: STMICROELECTRONICS, INC., STMICROELECTRONICS PTE LTD
    Inventors: Rennier Rodriguez, Bryan Christian Bacquian, Maiden Grace Maming, David Gani
  • Patent number: 10756051
    Abstract: The present disclosure provides a wafer-level packaging method and a package structure. The wafer-level packaging method includes: providing a device wafer that contains a plurality of first chips, that each first chip contains a first electrode exposed at a wafer front surface of the device wafer; providing a plurality of second chips, that each second chip contains a second electrode exposed at a chip front surface of the each second chip, and a surface opposite to the chip front surface is a chip back surface; bonding the chip back surface of the each second chip to a portion of the wafer front surface of the device wafer between adjacent first chips of the plurality of first chips; forming insulating sidewalls on sidewalls of the plurality of second chips; and forming a conductive layer conformally covering the chip front surface, each insulating sidewall, and the wafer front surface.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 25, 2020
    Assignee: Ningbo Semiconductor International Corporation
    Inventors: Hailong Luo, Clifford Ian Drowley
  • Patent number: 10756064
    Abstract: The present disclosure provides a method for manufacturing a semiconductor package, including providing a carrier, forming an insulating layer over the carrier, forming a first semiconductor die layer over the insulating layer, debonding the carrier from the insulating layer, and exposing the conductive contact from the insulating layer by an etching operation. Forming the first semiconductor die layer over the insulating layer includes forming a shallow trench in the insulating layer, forming a conductive contact in the shallow trench, and placing a first semiconductor die over the insulating layer.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Feng-Cheng Hsu, Jui-Pin Hung, Shin-Puu Jeng
  • Patent number: 10730746
    Abstract: A method for manufacturing a micromechanical inertial sensor, including: forming a movable MEMS structure in a MEMS wafer; connecting a cap wafer to the MEMS wafer; forming an access opening into the cavity, the access opening to the cavity being formed from two opposing sides; a defined narrow first access opening being formed from one side of the movable MEMS structure and a defined wide second access opening being formed from a surface of the MEMS wafer, the second access opening being formed to be wider in a defined manner than the first access opening; and closing the first access opening while enclosing a defined internal pressure in the cavity.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: August 4, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Jochen Reinmuth, Martin Rambach
  • Patent number: 10720415
    Abstract: A display device is provided. The display device includes a substrate having a first surface and a second surface opposite to the first surface, a plurality of light-emitting units disposed on the first surface of the substrate, and a plurality of conductive structures extending into the substrate from the second surface of the substrate. The plurality of conductive structures are electrically connected to the plurality of light-emitting units.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: July 21, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: Wei-Cheng Chu, Ming-Fu Jiang, Chia-Cheng Liu, Chih-Yuan Lee
  • Patent number: 10714403
    Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package comprises a carrier, a first patterned conductive layer, an interconnection structure, a first semiconductor device, an encapsulant, a second patterned conductive layer, and a passivation layer. The carrier has a first surface and a second surface opposite to the first surface. The first patterned conductive layer is adjacent to the first surface of the carrier. The interconnection structure is disposed on the first patterned conductive layer and electrically connected to the first patterned conductive layer. The first semiconductor device is disposed on the interconnection structure and electrically connected to the interconnection structure. The encapsulant is disposed on the first patterned conductive layer and encapsulates the semiconductor device and the interconnection structure.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: July 14, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 10714455
    Abstract: IC package assemblies including a molding compound in which an IC chip surface is recessed relative to the molding compound. Thickness of the IC chip may be reduced relative to its thickness during the molding process. Another IC chip, heat spreader, etc. may then occupy the resultant recess framed by the molding compound to achieve a fine stacking pitch. In some embodiments, a package-on-package (PoP) assembly includes a center-molded IC chip flip-chip-bonded to a first package substrate. A second substrate to which a second IC chip is flip-chip bonded is then electrically coupled to the first substrate by through-molding vias. Within the PoP assembly, the second IC chip may be disposed back-to-back with the center-molded IC chip so as to occupy the recess framed by the molding compound.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: July 14, 2020
    Assignee: Intel IP Corporation
    Inventors: Georg Seidemann, Klaus Reingruber
  • Patent number: 10658334
    Abstract: Package structures and methods for forming the same are provided. The method includes providing a first integrated circuit die and forming a redistribution structure over the first integrated circuit die. The method also includes forming a base layer over the redistribution structure. The base layer has first and second openings. The first openings are wider than the second openings. The method further includes forming first bumps over the redistribution structure. The first bumps have a lower portion filling the first openings. In addition, the method includes bonding a second integrated circuit die to the redistribution structure through second bumps having a lower portion filling the second openings. There is a space between the second integrated circuit die and the base layer. The method also includes forming a molding compound layer over the base layer. The molding compound layer fills the space and surrounds the first and second bumps.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Jen Cheng, Yu-Chih Huang, Chih-Hua Chen, Yu-Feng Chen, Hao-Yi Tsai
  • Patent number: 10651051
    Abstract: A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Robert L. Sankman, John S. Guzek
  • Patent number: 10651337
    Abstract: The present disclosure relates to a method for manufacturing a semiconductor light emitting device, a semiconductor device including the supporting substrate, and a method for manufacturing the supporting substrate, in which the method includes: providing a first substrate having a first face and a second face opposite to the first face; forming a groove in the first substrate in a direction from the first face to the second face; forming a conducting part in the groove; bonding a second substrate to the first face of the first substrate; and forming, on the second face, a first conducting pad to be in electrical communication with the conducting part.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: May 12, 2020
    Inventor: Sang Jeong An
  • Patent number: 10636741
    Abstract: A printed wiring board includes a core substrate, and a build-up layer formed on the substrate. The substrate includes core material, third conductor layer, fourth conductor layer, and through-hole conductors. The build-up layer is formed on the core material and third conductor layer and includes insulating layers, first conductor layers, and via conductors. The build-up layer has central area and outer peripheral area such that the via conductors include central area via conductors and outer peripheral area via conductors, diameter of central area via conductor is smaller than diameter of outer peripheral area via conductor, the outermost first conductor layer includes first pads to mount first electronic component and second pads to mount second electronic component, the first and second pads are connected to each other via the central via conductors, and the lowermost insulating layer does not have the via conductors in the central area of the build-up layer.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: April 28, 2020
    Assignee: IBIDEN CO., LTD.
    Inventor: Yoji Sawada
  • Patent number: 10600762
    Abstract: Some embodiments include an apparatus having a first chip and a second chip. Each of the first and second chips comprises a multilevel wiring structure and a redistribution wiring layer over the multilevel wiring structure. The redistribution wiring layers include redistribution wiring and pads electrically coupled to the redistribution wiring. The first chip is mounted above the second chip so that the redistribution wiring layer of the first chip faces the redistribution wiring layer of the second chip. The pad of the first chip faces the pad of the second chip, and is vertically spaced from the pad of the second chip by an intervening insulative region. The redistribution wiring of the second chip is electrically coupled to the redistribution wiring of the first chip through a bonding region.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: March 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Dai Sasaki, Mitsuaki Katagiri, Satoshi Isa
  • Patent number: 10553558
    Abstract: A semiconductor device includes a memory component, which is a semiconductor component (a semiconductor chip or a semiconductor package), to be mounted over an upper surface of a wiring substrate. In addition, in the upper surface, a distance between the memory component and a first substrate side of the upper surface is smaller than a distance between the memory component and a second substrate side of the upper surface. In addition, in the upper surface, a dam portion is formed between the memory component and the first substrate side.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: February 4, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Yosuke Katsura, Yusuke Tanuma
  • Patent number: 10532379
    Abstract: A mechanical structure comprising a stack including an active substrate and at least one actuator designed to generate vibrations at the active substrate, the stack comprises an elementary structure for amplifying the vibrations: positioned between the actuator and the active substrate, the structure designed to transmit and amplify the vibrations; and comprising at least one trench, located between the actuator and the active substrate. A method for manufacturing the structure comprising the use of a temporary substrate is provided.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: January 14, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS (CROLLES 2) SAS, UNIVERSITÉ GRENOBLE ALPES
    Inventors: Fabrice Casset, Skandar Basrour, Cédrick Chappaz, Jean-Sébastien Danel
  • Patent number: 10529652
    Abstract: A single chip integrated circuit (IC) package includes a die pad, and a spacer ring on the die pad defining a solder receiving area. A solder body is on the die pad within the solder receiving area. An IC die is on the spacer ring and is secured to the die pad by the solder body within the solder receiving area. Encapsulating material surrounds the die pad, spacer ring, and IC die. For a multi-chip IC package, a dam structure is on the die pad and defines multiple solder receiving areas. A respective solder body is on the die pad within a respective solder receiving area. An IC die is within each respective solder receiving area and is held in place by a corresponding solder body. Encapsulating material surrounds the die pad, dam structure, and plurality of IC die.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: January 7, 2020
    Assignee: STMICROELECTRONICS PTE LTD
    Inventor: Wing Shenq Wong
  • Patent number: 10515901
    Abstract: A method includes dispensing sacrificial region over a carrier, and forming a metal post over the carrier. The metal post overlaps at least a portion of the sacrificial region. The method further includes encapsulating the metal post and the sacrificial region in an encapsulating material, demounting the metal post, the sacrificial region, and the encapsulating material from the carrier, and removing at least a portion of the sacrificial region to form a recess extending from a surface level of the encapsulating material into the encapsulating material.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai
  • Patent number: 10515912
    Abstract: Substrateless integrated circuit (IC) packages having a die with direct diagonal connections, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, an IC package may include: a die having a face with a plurality of contacts thereon, a dielectric layer in contact with the face, and a conductive pathway extending diagonally through the dielectric layer and coupling to an individual contact of the plurality of contacts on the die. In some embodiments, a conductive pathway may fan out to translate the contacts from a more dense layout to a less dense layout. In some embodiments, a conductive pathway may fan in to translate the contacts from a less dense layout to a more dense layout. In some embodiments, the dielectric layer and the conductive pathway may extend beyond the footprint of the die on one or more edges.
    Type: Grant
    Filed: September 24, 2017
    Date of Patent: December 24, 2019
    Assignee: Intel Corporation
    Inventors: Min Suet Lim, Jiun Hann Sir, Eng Huat Eh Goh, Mooi Ling Chang
  • Patent number: 10490525
    Abstract: Techniques for high speed handling of ultra-small chips (e.g., micro-chips) by selective laser bonding and/or debonding are provided. In one aspect, a method includes: providing a first wafer including chips bonded to a surface thereof; contacting the first wafer with a second wafer, the second wafer including a substrate bonded to a surface thereof, wherein the contacting aligns individual chips with bonding sites on the substrate; and debonding the individual chips from the first wafer using a debonding laser having a small spot size of about 0.5 ?m to about 100 ?m, and ranges therebetween. A system is also provided that has digital cameras, a motorized XYZ-axis stage, and a computer control system configured to i) control a spot size of the at least one laser source and ii) adjust a positioning of the sample to align individual chips with a target area of the laser.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: November 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Qianwen Chen, Bing Dang, Russell Budd, Bo Wen, Li-Wen Hung, Jae-Woong Nah, John Knickerbocker
  • Patent number: 10461123
    Abstract: A light emitting device, includes: a substrate; a light emitting element on the substrate, the light emitting element having a first end portion and a second end portion arranged in a longitudinal direction; one or more partition walls disposed on the substrate, the one or more partition walls being spaced apart from the light emitting element; a first reflection electrode adjacent the first end portion of the light emitting element; a second reflection electrode adjacent the second end portion of the light emitting element; a first contact electrode connected to the first reflection electrode and the first end portion of the light emitting element; an insulating layer on the first contact electrode, the insulating layer having an opening exposing the second end portion of the light emitting element and the second reflection electrode to the outside; and a second contact electrode on the insulating layer.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: October 29, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dae Hyun Kim, Jong Hyuk Kang, Joo Yeol Lee, Hyun Deok Im, Hyun Min Cho
  • Patent number: 10396049
    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip, wherein the first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pad, the semiconductor chip includes a passivation layer having an opening exposing at least a portion of the connection pad, the redistribution layer of the second interconnection member is connected to the connection pad through a via, and the via covers at least a portion of the passivation layer.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: August 27, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Min Ban, Han Kim, Kyung Moon Jung
  • Patent number: 10361122
    Abstract: A method includes forming a metal seed layer on a dielectric layer, and forming a patterned mask over the metal seed layer. An opening in the patterned mask is over a first portion of the dielectric layer, and the patterned mask overlaps a second portion of the dielectric layer. The method further includes plating a metal region in the opening, removing the patterned mask to expose portions of the metal seed layer, etching the exposed portions of the metal seed layer, performing a plasma treatment on a surface of the second portion of the dielectric layer, and performing an etching process on the surface of the second portion of the dielectric layer.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: July 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun Chen Hsieh, Hui-Jung Tsai, Hung-Jui Kuo, Chen-Hua Yu
  • Patent number: 10269721
    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant filling at least portions of spaces between walls of the through-hole and side surfaces of the semiconductor chip; and a second interconnection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip through vias, wherein the side surface of the semiconductor chip has a step portion.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: April 23, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Sang Jin Lee, Dong Hun Lee
  • Patent number: 10256300
    Abstract: A semiconductor device includes: an active layer that is located in an SOI substrate, and in which an element included in a circuit is formed; a buried insulation layer that is located in the SOI substrate, and is in contact with the active layer; a deep trench isolation (DTI) region that is formed in the active layer to surround a whole formation region of the element in plan view, and extends from an upper surface to a lower surface of the active layer; and a first conductive film formed above the element. The DTI region has a first hole inside, and a film thickness of the first conductive film is greater than a thickness of the active layer.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: April 9, 2019
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Shinya Natsume, Masaki Inoue, Mitsuo Tanaka
  • Patent number: 10229858
    Abstract: Conductive paths through a dielectric are described that have a high aspect ratio for semiconductor devices. In one example, a semiconductor device package has a semiconductor substrate having circuitry formed on the substrate. A plurality of conductive connection pads are on the semiconductor substrate to connect to the circuitry. A post is on each of a subset of the connection pads, the posts being formed of a conductive material. A dielectric layer is over the semiconductor substrate including over the connection pads and the posts. Filled vias are over each connection pad that is not of the subset and over each post of the subset of the connection pads and a connector is over each filled via.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: March 12, 2019
    Assignee: Intel IP Corporation
    Inventors: Thorsten Meyer, Andreas Wolter
  • Patent number: 10179730
    Abstract: Disclosed examples include sensor apparatus and integrated circuits having a package structure with an internal cavity and an opening that connects of the cavity with an ambient condition of an exterior of the package structure, and an electronic sensor structure mechanically supported by wires in the cavity and including a sensing surface exposed to the cavity to sense the ambient condition of an exterior of the package structure.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: January 15, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Barry Jon Male, Benjamin Cook, Robert Alan Neidorff, Steve Kummerl
  • Patent number: 10163855
    Abstract: An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various electronic devices, and methods of making thereof, that comprise a permanently coupled carrier that enhances reliability of the electronic devices.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: December 25, 2018
    Assignee: Amkor Technology, Inc.
    Inventors: Jong Sik Paek, Doo Hyun Park
  • Patent number: 10161022
    Abstract: A metal composition suitable for originating a joint by means of welding with a borosilicate glass for a solar collector. The composition, expressed in weight percentage, comprises the following alloy elements: Ni Co Mn Si C Ti Zr Ta Ti + Zr + Ta 28-31 15-18 ?0.5 ?0.3 ?0.05 ?0.30 ?0.30 ?0.30 ?0.40 and it is such that 45.5?(Ni+Co)?46.5, and that (Ti+Ta+Zr)?4×C, the remaining part being made up of iron, apart from the inevitable impurities. Additionally, a metal ring made of the metal composition described above and suitable for originating a metal-glass joint by means of welding; the metal-glass joint thus obtained; and the tubular solar collector thus obtained.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: December 25, 2018
    Assignee: ARCHIMEDE SOLAR ENERGY SRL
    Inventors: Federico Ruffini, Claudio Raggi, Stefano Fortunati, Learco Cagiola, Antonio De Luca
  • Patent number: 10163662
    Abstract: A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: December 25, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Cheng-Chia Chiang, Don-Son Jiang, Lung-Yuan Wang, Shih-Hao Tung, Shu-Huei Huang
  • Patent number: 10159154
    Abstract: A method of making a multilayered, fusion bonded circuit structure. A first circuitry layer is attached to a first major surface of a first LCP substrate. A plurality of first recesses are formed that extend from a second major surface of the first substrate to the first circuitry layer. The first recesses are then plated to form a plurality of first conductive pillars of solid metal that substantially fill the first recesses. A plurality of second recesses are formed in a second LCP substrate corresponding to a plurality of the first conductive pillars. The second recess are plated to form a plurality of second conductive structures that extend between first and second major surfaces of the second substrate. The second major surface of the first substrate is positioned adjacent to the second major surface of the second substrate. The first conductive pillars are aligned with the second conductive structures.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: December 18, 2018
    Assignee: HSIO Technologies, LLC
    Inventor: James Rathburn
  • Patent number: 10134710
    Abstract: A stacked semiconductor package in an embodiment includes a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; and a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package. The first semiconductor package further includes a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin; and a thermal via connected to the conductive layer and located on the first circuit board.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: November 20, 2018
    Assignee: J-DEVICES CORPORATION
    Inventors: Takeshi Miyakoshi, Sumikazu Hosoyamada, Yoshikazu Kumagaya, Tomoshige Chikai, Shingo Nakamura, Hiroaki Matsubara, Shotaro Sakumoto
  • Patent number: 10134719
    Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias and a protection film covering the molding compound and the die. The protection film is formed by a printing process.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Hui Cheng, Jing-Cheng Lin, Po-Hao Tsai
  • Patent number: 10132705
    Abstract: Systems and methods are disclosed for a pressure sensor device. The pressure sensor device includes a header that defines an interior cavity including one or more tether connecting regions. The header further defines an outer portion in communication with the interior cavity; the outer portion includes a plurality of through bores in communication with an exterior portion of the header for insertion of header pins through the header. The pressure sensor device includes a pressure sensor chip disposed within the interior cavity of the header. One or more anchoring tethers are attached to the corresponding one or more tether connecting regions. The pressure sensor chip is free to move within the interior cavity of the header, and the one or more anchoring tethers are in communication with the pressure sensor chip and are configured to limit movement of the pressure sensor chip within the header.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: November 20, 2018
    Assignee: Kulite Semiconductor Products, Inc.
    Inventors: Sorin Stefanescu, Alexander A. Ned, Joseph R. VanDeWeert, Andrew Bemis
  • Patent number: 10112822
    Abstract: A semiconductor device includes a first substrate, a second substrate, an anti-stiction layer and at least one metal layer. The first substrate includes a microelectromechanical systems (MEMS) structure. The second substrate is bonded to the first substrate and disposed over the MEMS structure. The second substrate comprises at least one through hole. The anti-stiction layer is disposed on a surface of the MEMS structure. The at least one metal layer is disposed over the second substrate and covers the at least one through hole of the second substrate.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: October 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Fung Chang, Lien-Yao Tsai, Len-Yi Leu
  • Patent number: 9953952
    Abstract: A semiconductor device includes a carrier, a chip attached to the carrier, a sealant vapor deposited over the chip and the carrier, and encapsulation material deposited over the sealed chip and the sealed carrier.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: April 24, 2018
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Michael Juerss, Stefan Landau
  • Patent number: 9892999
    Abstract: A method for producing wafer level packaging using an embedded leadframe strip and the resulting device are provided. Embodiments include placing dies into a mold with an active side of each die facing a surface of the mold; placing a leadframe strip on the mold, wherein the leadframe strip includes etched and half etched portions positioned between each die; placing a mold cover over the mold and dies; and adding mold compound in spaces between the dies and mold cover.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: February 13, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Richard S. Graf, Sudeep Mandal, Kibby Horsford
  • Patent number: 9865493
    Abstract: A plating jig that can form a metal plating film simultaneously on both surfaces of a semiconductor wafer by one plating process. The plating jig includes a base section and a cover section that can hold a substrate to be plated, and a center section that holds the substrate between the base section and cover section; the base section, the cover section and the center section each having an annular portion having an opening at a center thereof; seal packings each having a conductive ring disposed thereon being attached to each of facing surfaces of the annular portions of the base section and the cover section; the substrate to be plated being disposed inside the opening of the center section; and the substrate to be plated being held from front and back surfaces thereof with the seal packings attached to the cover section and the center section.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: January 9, 2018
    Assignee: JCU CORPORATION
    Inventors: Junichiro Yoshioka, Takashi Murayama
  • Patent number: 9842787
    Abstract: The present disclosure relates to an electronic element package and a method of manufacturing the same. The electronic element package includes a substrate, an element disposed on the substrate, and a cap enclosing the element. One of the substrate and the cap includes a groove, the other of the substrate and the cap includes a protrusion engaging with the groove. A first metal layer and a second metal layer form a metallic bond with each other in a space between the groove and the protrusion.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: December 12, 2017
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Pil Joong Kang, Kwang Su Kim, Ji Hye Nam, Jeong Il Lee, Jong Hyeong Song, Yun Sung Kang, Seung Joo Shin, Nam Jung Lee
  • Patent number: 9821998
    Abstract: In a microelectromechanical system (MEMS) device, a CMOS die is affixed to a die-mounting surface and wire-bonded to electrically conductive leads, and a MEMS die is stacked on and electrically coupled to the CMOS die in a flip-chip configuration. A package enclosure envelopes the MEMS die, CMOS die and wire bonds, and exposes respective regions of the electrically conductive leads.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: November 21, 2017
    Assignee: SiTime Corpoaration
    Inventors: Pavan Gupta, Aaron Partridge, Markus Lutz
  • Patent number: 9812422
    Abstract: An apparatus including a die; and a build-up carrier including alternating layers of conductive material and dielectric material disposed on a device side of the die and dielectric material embedding a portion of a thickness dimension of the die; and a plurality of carrier contact points disposed at a gradation between the device side of the die and the embedded thickness dimension of the die and configured for connecting the carrier to a substrate. A method including disposing a die on a sacrificial substrate with a device side of the die opposite the sacrificial substrate; forming a build-up carrier adjacent a device side of a die, wherein the build-up carrier includes a dielectric material defining a gradation between the device side of the die and a backside of the die, the gradation including a plurality of carrier contact points; and separating the die and the carrier from the sacrificial substrate.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: November 7, 2017
    Assignee: Intel Corporation
    Inventors: Toong Erh Ooi, Bok Eng Cheah, Nitesh Nimkar
  • Patent number: 9793188
    Abstract: The present invention relates generally to the field of semiconductor devices, including solar cells, and compositions and methods for processing semiconductor devices, passivation of semiconductor surfaces, semiconductor etching and anti-reflective coatings for semiconductor devices.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: October 17, 2017
    Inventor: Arjun Mendiratta
  • Patent number: 9704768
    Abstract: It is an object of the present invention to achieve reduced faults in manufacturing steps and increased reliability by relieving electric field strength of a surface of a power semiconductor chip. The present invention includes: a power semiconductor chip disposed on an insulating substrate; wiring connected to a surface conductor pattern in an element region of the power semiconductor chip; a low dielectric constant film disposed between the wiring and the peripheral region; and a sealing material formed so as to cover the insulating substrate, the power semiconductor chip, the wiring, and the low dielectric constant film. The low dielectric constant film has a dielectric constant lower than that of the sealing material.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: July 11, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yasuto Kawaguchi
  • Patent number: 9698135
    Abstract: A method for forming a package structure is provided. The method includes forming a plurality of conductive columns over a carrier substrate and forming an interfacial layer over sidewalls and tops of the conductive columns. The method also includes disposing a semiconductor die over a planar portion of the interfacial layer. The method further includes forming a molding compound to partially or completely encapsulate the semiconductor die, the conductive columns, and the interfacial layer such that the molding compound is in direct contact with the interfacial layer.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: July 4, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jing-Cheng Lin, Po-Hao Tsai
  • Patent number: 9699908
    Abstract: A component-embedded board includes a multilayer board obtained by stacking resin layers and an electronic component in the multilayer board having terminal electrodes on at least one principal face. The resin layers include a first resin layer having a space to accommodate the electronic component and at least one first interlayer connector formed by solidifying a conductive paste outside each of at least three sides of a principal face of the electronic component and a second resin layer having second and third interlayer connectors formed by solidifying a conductive paste. At least one second interlayer connector is positioned outside the three sides of the principal face. The third interlayer connectors are joined to the terminal electrodes. The first resin layer and the second resin layer are adjacent to each other in a stacking direction within the multilayer board. The first interlayer connector and the second interlayer connector are joined.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: July 4, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takahiro Baba, Yuki Wakabayashi
  • Patent number: 9673171
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: providing a semiconductor die having semiconductor die contacts; depositing an insulation layer on the semiconductor die including the semiconductor die contacts exposed; applying a conductive layer on the semiconductor die contacts and the insulation layer; and coupling system interconnects to the conductive layer for electrically connecting the semiconductor die to the system interconnects.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: June 6, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: HeeJo Chi, HeeSoo Lee, Omin Kwon
  • Patent number: 9666500
    Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: May 30, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Pandi C. Marimuthu, Kang Chen, Hin Hwa Goh, Yu Gu, Il Kwon Shim, Rui Huang, Seng Guan Chow, Jianmin Fang, Xia Feng
  • Patent number: 9666501
    Abstract: A semiconductor device including a die pad having a front surface made of Cu; a semiconductor chip disposed so as to be opposed to the front surface of the die pad; a bonding layer provided between the die pad and the semiconductor chip; and a plurality of leads disposed around the die pad, wherein the die pad and the plurality of leads make up a lead frame in cooperation with each other, a cavity is fabricated on the surface of the plurality of leads, and a projecting portion is fabricated next to the cavity.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: May 30, 2017
    Assignee: ROHM CO., LTD.
    Inventor: Motoharu Haga
  • Patent number: 9633923
    Abstract: There are provided an electronic device module capable of increasing a degree of integration by mounting electronic components on both surfaces of a board, and a manufacturing method thereof. The electronic device module includes a board having mounting electrodes formed on both surfaces thereof, a plurality of electronic devices mounted on the mounting electrodes, a molded portion sealing the electronic devices, at least one connection wire having one end bonded to one surface of the board and the other end exposed to the outside of the molded portion, and an external connection terminal coupled to the other end of the connection wire.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: April 25, 2017
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Do Jae Yoo, Jae Hyun Lim, Sun Ho Kim
  • Patent number: 9633834
    Abstract: A method for forming a coating layer includes spraying coating material having a first flowability onto a substrate; performing a first spin coating process with a first spin speed to form an initial coating layer; and performing a first baking process to the initial coating layer to form a first material layer having a second flowability and a second material layer having a third flowability. The third flowability is less than the first flowability but larger than the second flowability, which is less than the first flowability. Further, the method includes performing a second spin coating process with a second spin speed to drive the coating material in the second material layer flowing on the surface of the first material layer to form a third material layer with a uniform thickness, and performing a second baking process to form a final coating layer on the substrate.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: April 25, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Guowei Zhang
  • Patent number: 9617353
    Abstract: A method for protecting an electrical or electronic device against liquid damage, the method comprising a preliminary step of applying a continuous power plasma to the electrical or electronic device, followed by exposing the device to pulsed plasma comprising a compound of formula (I) where R1, R2 and R3 are independently selected from hydrogen, alkyl, haloalkyl or aryl optionally substituted by halo; and R4 is a group X—R5 where R5 is an alkyl or haloalkyl group and X is a bond; a group of formula C(O)O(CH2)nY where n is an integer of from 1 to 10 and Y is a bond or a sulphonamide group; or a group (O)pR6(O)q(CH2)t where R6 is aryl optionally substituted by halo, p is 0 or 1, q is 0 or 1 and t is 0 or an integer of from 1 to 10, provided that where q is 1, t is other than 0, for a sufficient period of time to allow a polymeric layer to form on the surface of the electrical or electronic device.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: April 11, 2017
    Assignee: PZi Limited
    Inventor: Stephen Coulson
  • Patent number: 9607937
    Abstract: An interposer to form a frame around a bottom chip bonded to a package substrate and to standoff a top chip or package for clearance of the bottom chip. The interposer has pins arrayed on a first side which are soldered to the package substrate for reduced interposer z-height and pads arrayed on a second side to which the top package (chip) is bonded. During assembly, the interposer pins may be pressed against pre-soldered pads and the solder reflowed to join the interposer to the package substrate. A top package (chip) is then joined to an opposite side of the interposer to integrate the first and second chips.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: March 28, 2017
    Assignee: Intel Corporation
    Inventors: Nicholas R. Watts, Tao Wu