Encapsulating Patents (Class 438/127)
  • Patent number: 11444035
    Abstract: A semiconductor device has a substrate. A first component and second component are disposed over the substrate. The first component includes an antenna. A lid is disposed over the substrate between the first component and second component. An encapsulant is deposited over the substrate and lid. A conductive layer is formed over the encapsulant and in contact with the lid. A first portion of the conductive layer over the first component is removed using laser ablation.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: September 13, 2022
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: ChangOh Kim, KyoWang Koo, SungWon Cho, BongWoo Choi, JiWon Lee
  • Patent number: 11410965
    Abstract: An electronic device having a first component carrier and an electronic component which is surface mounted on or embedded within the first component carrier. The electronic device further has a second component carrier. The first component carrier together with the electronic component is at least partially embedded within the second component carrier.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: August 9, 2022
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventor: Mikael Tuominen
  • Patent number: 11404289
    Abstract: Underfill materials with graded moduli for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, the underfill material between a semiconductor die and a package substrate includes a matrix material, first filler particles with a first size distribution, and second filler particles with a second size distribution different than the first size distribution. Centrifugal force may be applied to the underfill material to arrange the first and second filler particles such that the underfill material may form a first region having a first elastic modulus and a second region having a second elastic modulus different than the first elastic modulus. Once the underfill material is cured, portions of conductive pillars coupling the semiconductor die with the package substrate may be surrounded by the first region, and conductive pads of the package substrate may be surrounded by the second region.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: August 2, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Jungbae Lee, Chih Hong Wang
  • Patent number: 11387177
    Abstract: A package structure and a method for forming the same are provided. The package structure includes a die, a first molding surrounding the die, a first redistribution layer (RDL), an interposer disposed over the first RDL, a second molding surrounding the interposer, a first via, and a second RDL. The first RDL includes a first dielectric layer disposed over the die and the first molding, and a first interconnect structure surrounded by the first dielectric layer and electrically connected to the die. The interposer is electrically connected to the die through the first interconnect structure. The first via extends through and within the second molding and is adjacent to the interposer. The second RDL includes a second dielectric layer disposed over the interposer and the second molding, and a second interconnect structure surrounded by the second dielectric layer and electrically connected to the via and the interposer.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: July 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chin-Her Chien, Po-Hsiang Huang, Cheng-Hung Yeh, Tai-Yu Wang, Ming-Ke Tsai, Yao-Hsien Tsai, Kai-Yun Lin, Chin-Yuan Huang, Kai-Ming Liu, Fong-Yuan Chang, Chin-Chou Liu, Yi-Kan Cheng
  • Patent number: 11348853
    Abstract: A semiconductor device according to an embodiment includes a metal plate, a semiconductor chip, an insulating substrate provided between the metal plate and the semiconductor chip, a frame body surrounding the insulating substrate, a mesh-shaped sheet provided between the metal plate and the frame body, an adhesive agent provided between the metal plate and the frame body, and a sealing material being surrounded by the frame body and covering the semiconductor chip and the insulating substrate.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: May 31, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Yuuichi Fujita
  • Patent number: 11309522
    Abstract: A first product may be provided that comprises a substrate having a first surface, a first side, and a first edge where the first surface meets the first side; and a device disposed over the substrate, the device having a second side, where at least a first portion of the second side is disposed within 3 mm from the first edge of the substrate. The first product may further comprise a first barrier film that covers at least a portion of the first edge of the substrate, at least a portion of the first side of the substrate, and at least the first portion of the second side of the device.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: April 19, 2022
    Assignees: UNIVERSAL DISPLAY CORPORATION, THE TRUSTEES OF PRINCETON UNIVERSITY
    Inventors: Prashant Mandlik, Ruiqing Ma, Jeffrey Silvernail, Julia J. Brown, Lin Han, Sigurd Wagner, Luke Walski
  • Patent number: 11257688
    Abstract: A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: February 22, 2022
    Assignee: Intel Corporation
    Inventors: Robert L. Sankman, John S. Guzek
  • Patent number: 11251102
    Abstract: A semiconductor module may include a substrate including a first region and a second region, a first chip mounted in the first region, a second chip and passive devices mounted in the second region, and a heat dissipation layer being in contact with a top surface of the first chip. The heat dissipation layer may be provided on top surfaces and side surfaces of the first chip, the second chip and the passive devices.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: February 15, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yunhyeok Im, Youngsang Cho
  • Patent number: 11189501
    Abstract: A manufacturing method a chip package structure. The carrier board includes a substrate and a stainless steel layer sputtered on the substrate. The substrate has multiple first cavities and at least one second cavity. The stainless steel layer conformally covers the first cavities and the second cavity to define multiple third cavities and at least one fourth cavity. Conductive blocks fill the third cavities. At least one metal layer covers the stainless steel layer, the conductive blocks, and the fourth cavity to define at least one fifth cavity. At least one chip is disposed inside the fifth cavity. At least one circuit structure layer is formed on the carrier board. A patterned circuit layer of the circuit structure layer is electrically connected with multiple electrodes of the chip. The carrier board and the circuit structure layer are separated to expose the conductive blocks and the metal layer.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: November 30, 2021
    Inventor: Chung W. Ho
  • Patent number: 11183437
    Abstract: In some examples, a circuit package includes a packaging, and a circuit device in the packaging, where the packaging comprises a first EMC having a first coefficient of thermal expansion (CTE), and a second EMC having a second CTE higher than the first CTE. The second EMC is on the first EMC that has gelled over time.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: November 23, 2021
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chien-Hua Chen, Michael W. Cumbie, Stephen Farrar
  • Patent number: 11177456
    Abstract: The present application discloses a method of fabricating a display substrate. The method includes forming a mother substrate on a support substrate; cutting the mother substrate to separate a portion of the mother substrate from a remainder of the mother substrate, thereby forming a base substrate; and subsequent to cutting the mother substrate, forming an encapsulating layer on the base substrate for encapsulating the display substrate.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: November 16, 2021
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Tao Wang
  • Patent number: 11177196
    Abstract: A lead frame is provided with a die pad portion, a first lead portion, a second lead portion, and an extension portion extending from a corner portion neighborhood of the die pad portion to the outside of the die pad portion. The first lead portion has a first terminal portion and a first lead post portion positioned on a side closer to the die pad portion relative to the first terminal portion and electrically connected to the first terminal portion. The second lead portion has a second terminal portion, a third terminal portion positioned between the first terminal portion and the second terminal portion, and a second lead post portion positioned on a side closer to the die pad portion relative to the second terminal portion and the third terminal portion and electrically connected to the second terminal portion and the third terminal portion.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: November 16, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Keisuke Tabira, Kenpei Nakamura, Mitsuaki Matsuse, Hiroaki Furihata
  • Patent number: 11152068
    Abstract: In some examples, an integrated circuit comprises a first plate, a second plate, and a dielectric layer disposed between the first and second plates, the first and second plates and the dielectric layer forming a vertical capacitor, wherein the first and second plates and the dielectric layer of the vertical capacitor are disposed on an isolation region of the integrated circuit.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: October 19, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xiang-Zheng Bo, Patrick R. Smith, Douglas T. Grider
  • Patent number: 11147166
    Abstract: Disclosed is a method for producing a semiconductor device including a circuit board having a flexible resin layer that encapsulates a circuit component. The method may include a step of immersing a flexible substrate in an encapsulant, drying the encapsulant, and thereby encapsulating the circuit component with the encapsulant; and a step of curing the encapsulant, and thereby forming a flexible resin layer.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: October 12, 2021
    Assignee: SHOWA DENKO MATERIALS CO., LTD.
    Inventors: Tomoaki Shibata, Hanako Yori, Tomonori Minegishi, Hidenori Abe, Takashi Masuko, Shunsuke Otake
  • Patent number: 11139249
    Abstract: A packaged semiconductor device including a first die attached to a redistribution structure, a second die attached to the first die, and a molding compound surrounding the first die and the second die and a method of forming the same are disclosed. In an embodiment, a method includes forming first conductive pillars over and electrically coupled to a first redistribution structure; attaching a first die to the first redistribution structure, the first die including second conductive pillars; attaching a second die to the first die adjacent the second conductive pillars; encapsulating the first conductive pillars, the first die, and the second die with an encapsulant; forming a second redistribution structure over the encapsulant, the first conductive pillars, the first die, and the second die; and bonding a third die to the first redistribution structure.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: October 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hung-Yi Kuo, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Tsung-Yuan Yu
  • Patent number: 11139164
    Abstract: An electronic device includes: a water impermeable substrate; at least one electronic circuit on the water impermeable substrate; a dielectric encapsulant on the electronic circuit; a capping layer comprising a polymer on the dielectric encapsulant; and a barrier layer on the capping layer, the water impermeable substrate, the dielectric encapsulant, the capping layer, and the barrier layer forming a hermetically sealed micro-cavity.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: October 5, 2021
    Assignee: Raytheon Company
    Inventors: Thomas A. Hanft, Michael A. Moore, John Bedinger
  • Patent number: 11084714
    Abstract: A method for setting a pressure in a cavity formed with the aid of a substrate and a substrate cap, a microelectromechanical system being situated in the cavity, the substrate including a main extension plane. The method includes the following steps: in a first step a clearance is created in the substrate cap, the clearance connecting the cavity to the surroundings, a first clearance end of the clearance being formed on a first surface of the substrate cap that faces away from the cavity, a second clearance end of the clearance being formed on a cavity-side second surface of the substrate cap, the first clearance end and the second clearance end being situated at a distance from one another at least in a first direction which is parallel to the main extension plane; in a second step, after the first step, the clearance is sealed.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: August 10, 2021
    Assignee: Robert Bosch GmbH
    Inventors: Peter Borwin Staffeld, Achim Kronenberger, Rafel Ferre I Tomas
  • Patent number: 11069604
    Abstract: A semiconductor package has a plurality of pillars or portions of a plurality of lead strips, a plurality of semiconductor devices, one or two molding encapsulations and a plurality of electrical interconnections. The semiconductor package excludes a wire. The semiconductor package excludes a clip. A method is applied to fabricate semiconductor packages. The method includes providing a removable carrier; forming a plurality of pillars or a plurality of lead strips; attaching a plurality of semiconductor devices; forming one or two molding encapsulations; forming a plurality of electrical interconnections and removing the removable carrier. The method may further include a singulation process.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: July 20, 2021
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD. GRAND
    Inventors: Xiaotian Zhang, Yan Xun Xue, Long-Ching Wang, Yueh-Se Ho, Zhiqiang Niu
  • Patent number: 11049822
    Abstract: Example embodiments of systems and methods for creating a chip fraud prevention system with a fraud prevention fluid are provided. A chip fraud prevention system includes a device including a chip. The chip may be at least partially encompassed in a chip pocket which contains a fraud prevention fluid. The fraud prevention fluid may be contained in a capsule or implemented as an adhesive. One or more connections may be communicatively coupled to at least one surface of the chip. The one or more connections may be placed in close proximity and/or in contact to the fraud prevention fluid.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: June 29, 2021
    Assignee: CAPITAL ONE SERVICES, LLC
    Inventors: Daniel Herrington, Stephen Schneider, Tyler Maiman
  • Patent number: 11019725
    Abstract: A wiring substrate includes a first insulation layer, a second insulation layer formed on an upper surface of the first insulation layer, an opening extending through the second insulation layer, an adhesive layer formed on a bottom surface in the opening, an electronic component fixed in the opening by the adhesive layer, a filling insulation layer covering an upper surface of the second insulation layer and filling the opening to cover the electronic component, and a wiring layer formed on an upper surface of the filling insulation layer. The adhesive layer includes a base portion covering a lower surface of the electronic component in tight contact and a cover portion covering a side surface of the electronic component in tight contact. The cover portion has a lower filler content ratio than the base portion. The filling insulation layer covers a side surface of the cover portion in tight contact.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: May 25, 2021
    Inventor: Yasuyuki Yamaguchi
  • Patent number: 10971446
    Abstract: A method includes forming a redistribution structure on a carrier, attaching an integrated passive device on a first side of the redistribution structure, attaching an interconnect structure to the first side of the redistribution structure, the integrated passive device interposed between the redistribution structure and the interconnect structure, depositing an underfill material between the interconnect structure and the redistribution structure, and attaching a semiconductor device on a second side of the redistribution structure that is opposite the first side of the redistribution structure.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun Yi Wu, Chen-Hua Yu, Chien-Hsun Chen
  • Patent number: 10916482
    Abstract: A semiconductor wafer has a plurality of semiconductor die distributed over a surface area. The semiconductor die are singulated from the semiconductor wafer. The semiconductor die are mounted to a carrier to form a reconstituted semiconductor wafer. The carrier has a surface area 10-50% larger than the surface area of the semiconductor wafer. The number of semiconductor die mounted to the carrier is greater than a number of semiconductor die singulated from the semiconductor wafer. The reconstituted wafer is mounted within a chase mold. The chase mold is closed with the semiconductor die disposed within a cavity of the chase mold. An encapsulant is dispersed around the semiconductor die within the cavity under temperature and pressure. The encapsulant can be injected into the cavity of the chase mold. The reconstituted wafer is removed from the chase mold. An interconnect structure is formed over the reconstituted wafer.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: February 9, 2021
    Inventors: Yoke Hor Phua, Yung Kuan Hsiao
  • Patent number: 10916511
    Abstract: A method for reducing warpage occurred to a substrate strip after a molding process is provided. First, several dies are mounted on a top surface of a substrate strip. Then, a base having a top surface with a surface curvature is provided, and the top surface of the base is contacted against a bottom surface of the substrate strip to bend the substrate strip. Next, under the status that the top surface of the base is contacted against the bottom surface of the substrate strip, a molding compound is wrapped around each die. Finally, the molding compound is cooled to a room temperature. Accordingly, the molding process is performed on the substrate strip reversely bent in a direction opposite to a warpage direction. Therefore, the warpage originally caused by the molding process is offset by the reverse bending.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: February 9, 2021
    Assignee: KINGPAK TECHNOLOGY INC.
    Inventors: Fu-Chou Liu, Chien-Chen Lee, Ya-Han Chang
  • Patent number: 10910322
    Abstract: A semiconductor device has a substrate. An electrical component is disposed over a surface of the substrate. An encapsulant is deposited over the electrical component and substrate. A portion of the surface of the substrate remains exposed from the encapsulant. A shielding layer is formed over the encapsulant. A portion of the shielding layer is removed to expose the portion of the surface of the substrate.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: February 2, 2021
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: ChangOh Kim, KyoWang Koo, SungWon Cho, BongWoo Choi, JiWon Lee
  • Patent number: 10840170
    Abstract: A semiconductor package substrate, in which a base substrate having an upper surface and a lower surface and formed of a conductive material is filled with resin formed of an insulating material, includes a die pad formed of the conductive material on the upper surface and a lead arranged on the upper surface by being electrically separated from the die pad and comprising a bonding pad that is a wire bonding area. A protrusion protruding toward the lower surface is formed in a central area of the bonding pad. A central thickness of the bonding pad is greater than a peripheral thickness of the bonding pad.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: November 17, 2020
    Assignee: HAESUNG DS CO., LTD.
    Inventors: In Seob Bae, Sung Il Kang
  • Patent number: 10811371
    Abstract: A semiconductor device includes: a semiconductor substrate; a semiconductor layer on the semiconductor substrate; a source electrode and a drain electrode spaced apart from each other on the semiconductor layer; a gate electrode on the semiconductor layer between the source electrode and the drain electrode; and an insulating film covering the semiconductor layer, the source electrode, the drain electrode and the gate electrode, the gate electrode has an eaves structure including a lower electrode joined to the semiconductor layer and an upper electrode provided on the lower electrode and wider than the lower electrode, a principal ingredient of the insulating film is an oxide film where atomic layers are alternately arrayed for each monolayer, and a film thickness of the insulating film that covers the lower electrode of the gate electrode is equal to a film thickness of the insulating film that covers the upper electrode.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: October 20, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Naoto Ando
  • Patent number: 10763194
    Abstract: A semiconductor package includes a lead frame, a die, a discrete electrical component, and electrical connections. The lead frame includes leads and a die pad. Some of the leads include engraved regions that have recesses therein and the die pad may include an engraved region or multiple engraved regions. Each engraved region is formed to contain and confine a conductive adhesive from flowing over the edges of the engraved leads or the die pad. The boundary confines the conductive adhesive to the appropriate location on the engraved lead or the engraved die pad when being placed on the engraved regions. By utilizing a lead frame with engraved regions, the flow of the conductive adhesive or the wettability of the conductive adhesive can be contained and confined to the appropriate areas of the engraved lead or engraved die pad such that a conductive adhesive does not cause cross-talk between electrical components within a semiconductor package or short circuiting within a semiconductor package.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: September 1, 2020
    Assignees: STMICROELECTRONICS, INC., STMICROELECTRONICS PTE LTD
    Inventors: Rennier Rodriguez, Bryan Christian Bacquian, Maiden Grace Maming, David Gani
  • Patent number: 10756064
    Abstract: The present disclosure provides a method for manufacturing a semiconductor package, including providing a carrier, forming an insulating layer over the carrier, forming a first semiconductor die layer over the insulating layer, debonding the carrier from the insulating layer, and exposing the conductive contact from the insulating layer by an etching operation. Forming the first semiconductor die layer over the insulating layer includes forming a shallow trench in the insulating layer, forming a conductive contact in the shallow trench, and placing a first semiconductor die over the insulating layer.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Feng-Cheng Hsu, Jui-Pin Hung, Shin-Puu Jeng
  • Patent number: 10756051
    Abstract: The present disclosure provides a wafer-level packaging method and a package structure. The wafer-level packaging method includes: providing a device wafer that contains a plurality of first chips, that each first chip contains a first electrode exposed at a wafer front surface of the device wafer; providing a plurality of second chips, that each second chip contains a second electrode exposed at a chip front surface of the each second chip, and a surface opposite to the chip front surface is a chip back surface; bonding the chip back surface of the each second chip to a portion of the wafer front surface of the device wafer between adjacent first chips of the plurality of first chips; forming insulating sidewalls on sidewalls of the plurality of second chips; and forming a conductive layer conformally covering the chip front surface, each insulating sidewall, and the wafer front surface.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 25, 2020
    Assignee: Ningbo Semiconductor International Corporation
    Inventors: Hailong Luo, Clifford Ian Drowley
  • Patent number: 10730746
    Abstract: A method for manufacturing a micromechanical inertial sensor, including: forming a movable MEMS structure in a MEMS wafer; connecting a cap wafer to the MEMS wafer; forming an access opening into the cavity, the access opening to the cavity being formed from two opposing sides; a defined narrow first access opening being formed from one side of the movable MEMS structure and a defined wide second access opening being formed from a surface of the MEMS wafer, the second access opening being formed to be wider in a defined manner than the first access opening; and closing the first access opening while enclosing a defined internal pressure in the cavity.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: August 4, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Jochen Reinmuth, Martin Rambach
  • Patent number: 10720415
    Abstract: A display device is provided. The display device includes a substrate having a first surface and a second surface opposite to the first surface, a plurality of light-emitting units disposed on the first surface of the substrate, and a plurality of conductive structures extending into the substrate from the second surface of the substrate. The plurality of conductive structures are electrically connected to the plurality of light-emitting units.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: July 21, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: Wei-Cheng Chu, Ming-Fu Jiang, Chia-Cheng Liu, Chih-Yuan Lee
  • Patent number: 10714455
    Abstract: IC package assemblies including a molding compound in which an IC chip surface is recessed relative to the molding compound. Thickness of the IC chip may be reduced relative to its thickness during the molding process. Another IC chip, heat spreader, etc. may then occupy the resultant recess framed by the molding compound to achieve a fine stacking pitch. In some embodiments, a package-on-package (PoP) assembly includes a center-molded IC chip flip-chip-bonded to a first package substrate. A second substrate to which a second IC chip is flip-chip bonded is then electrically coupled to the first substrate by through-molding vias. Within the PoP assembly, the second IC chip may be disposed back-to-back with the center-molded IC chip so as to occupy the recess framed by the molding compound.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: July 14, 2020
    Assignee: Intel IP Corporation
    Inventors: Georg Seidemann, Klaus Reingruber
  • Patent number: 10714403
    Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package comprises a carrier, a first patterned conductive layer, an interconnection structure, a first semiconductor device, an encapsulant, a second patterned conductive layer, and a passivation layer. The carrier has a first surface and a second surface opposite to the first surface. The first patterned conductive layer is adjacent to the first surface of the carrier. The interconnection structure is disposed on the first patterned conductive layer and electrically connected to the first patterned conductive layer. The first semiconductor device is disposed on the interconnection structure and electrically connected to the interconnection structure. The encapsulant is disposed on the first patterned conductive layer and encapsulates the semiconductor device and the interconnection structure.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: July 14, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 10658334
    Abstract: Package structures and methods for forming the same are provided. The method includes providing a first integrated circuit die and forming a redistribution structure over the first integrated circuit die. The method also includes forming a base layer over the redistribution structure. The base layer has first and second openings. The first openings are wider than the second openings. The method further includes forming first bumps over the redistribution structure. The first bumps have a lower portion filling the first openings. In addition, the method includes bonding a second integrated circuit die to the redistribution structure through second bumps having a lower portion filling the second openings. There is a space between the second integrated circuit die and the base layer. The method also includes forming a molding compound layer over the base layer. The molding compound layer fills the space and surrounds the first and second bumps.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Jen Cheng, Yu-Chih Huang, Chih-Hua Chen, Yu-Feng Chen, Hao-Yi Tsai
  • Patent number: 10651337
    Abstract: The present disclosure relates to a method for manufacturing a semiconductor light emitting device, a semiconductor device including the supporting substrate, and a method for manufacturing the supporting substrate, in which the method includes: providing a first substrate having a first face and a second face opposite to the first face; forming a groove in the first substrate in a direction from the first face to the second face; forming a conducting part in the groove; bonding a second substrate to the first face of the first substrate; and forming, on the second face, a first conducting pad to be in electrical communication with the conducting part.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: May 12, 2020
    Inventor: Sang Jeong An
  • Patent number: 10651051
    Abstract: A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Robert L. Sankman, John S. Guzek
  • Patent number: 10636741
    Abstract: A printed wiring board includes a core substrate, and a build-up layer formed on the substrate. The substrate includes core material, third conductor layer, fourth conductor layer, and through-hole conductors. The build-up layer is formed on the core material and third conductor layer and includes insulating layers, first conductor layers, and via conductors. The build-up layer has central area and outer peripheral area such that the via conductors include central area via conductors and outer peripheral area via conductors, diameter of central area via conductor is smaller than diameter of outer peripheral area via conductor, the outermost first conductor layer includes first pads to mount first electronic component and second pads to mount second electronic component, the first and second pads are connected to each other via the central via conductors, and the lowermost insulating layer does not have the via conductors in the central area of the build-up layer.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: April 28, 2020
    Assignee: IBIDEN CO., LTD.
    Inventor: Yoji Sawada
  • Patent number: 10600762
    Abstract: Some embodiments include an apparatus having a first chip and a second chip. Each of the first and second chips comprises a multilevel wiring structure and a redistribution wiring layer over the multilevel wiring structure. The redistribution wiring layers include redistribution wiring and pads electrically coupled to the redistribution wiring. The first chip is mounted above the second chip so that the redistribution wiring layer of the first chip faces the redistribution wiring layer of the second chip. The pad of the first chip faces the pad of the second chip, and is vertically spaced from the pad of the second chip by an intervening insulative region. The redistribution wiring of the second chip is electrically coupled to the redistribution wiring of the first chip through a bonding region.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: March 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Dai Sasaki, Mitsuaki Katagiri, Satoshi Isa
  • Patent number: 10553558
    Abstract: A semiconductor device includes a memory component, which is a semiconductor component (a semiconductor chip or a semiconductor package), to be mounted over an upper surface of a wiring substrate. In addition, in the upper surface, a distance between the memory component and a first substrate side of the upper surface is smaller than a distance between the memory component and a second substrate side of the upper surface. In addition, in the upper surface, a dam portion is formed between the memory component and the first substrate side.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: February 4, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Yosuke Katsura, Yusuke Tanuma
  • Patent number: 10532379
    Abstract: A mechanical structure comprising a stack including an active substrate and at least one actuator designed to generate vibrations at the active substrate, the stack comprises an elementary structure for amplifying the vibrations: positioned between the actuator and the active substrate, the structure designed to transmit and amplify the vibrations; and comprising at least one trench, located between the actuator and the active substrate. A method for manufacturing the structure comprising the use of a temporary substrate is provided.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: January 14, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS (CROLLES 2) SAS, UNIVERSITÉ GRENOBLE ALPES
    Inventors: Fabrice Casset, Skandar Basrour, Cédrick Chappaz, Jean-Sébastien Danel
  • Patent number: 10529652
    Abstract: A single chip integrated circuit (IC) package includes a die pad, and a spacer ring on the die pad defining a solder receiving area. A solder body is on the die pad within the solder receiving area. An IC die is on the spacer ring and is secured to the die pad by the solder body within the solder receiving area. Encapsulating material surrounds the die pad, spacer ring, and IC die. For a multi-chip IC package, a dam structure is on the die pad and defines multiple solder receiving areas. A respective solder body is on the die pad within a respective solder receiving area. An IC die is within each respective solder receiving area and is held in place by a corresponding solder body. Encapsulating material surrounds the die pad, dam structure, and plurality of IC die.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: January 7, 2020
    Assignee: STMICROELECTRONICS PTE LTD
    Inventor: Wing Shenq Wong
  • Patent number: 10515912
    Abstract: Substrateless integrated circuit (IC) packages having a die with direct diagonal connections, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, an IC package may include: a die having a face with a plurality of contacts thereon, a dielectric layer in contact with the face, and a conductive pathway extending diagonally through the dielectric layer and coupling to an individual contact of the plurality of contacts on the die. In some embodiments, a conductive pathway may fan out to translate the contacts from a more dense layout to a less dense layout. In some embodiments, a conductive pathway may fan in to translate the contacts from a less dense layout to a more dense layout. In some embodiments, the dielectric layer and the conductive pathway may extend beyond the footprint of the die on one or more edges.
    Type: Grant
    Filed: September 24, 2017
    Date of Patent: December 24, 2019
    Assignee: Intel Corporation
    Inventors: Min Suet Lim, Jiun Hann Sir, Eng Huat Eh Goh, Mooi Ling Chang
  • Patent number: 10515901
    Abstract: A method includes dispensing sacrificial region over a carrier, and forming a metal post over the carrier. The metal post overlaps at least a portion of the sacrificial region. The method further includes encapsulating the metal post and the sacrificial region in an encapsulating material, demounting the metal post, the sacrificial region, and the encapsulating material from the carrier, and removing at least a portion of the sacrificial region to form a recess extending from a surface level of the encapsulating material into the encapsulating material.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai
  • Patent number: 10490525
    Abstract: Techniques for high speed handling of ultra-small chips (e.g., micro-chips) by selective laser bonding and/or debonding are provided. In one aspect, a method includes: providing a first wafer including chips bonded to a surface thereof; contacting the first wafer with a second wafer, the second wafer including a substrate bonded to a surface thereof, wherein the contacting aligns individual chips with bonding sites on the substrate; and debonding the individual chips from the first wafer using a debonding laser having a small spot size of about 0.5 ?m to about 100 ?m, and ranges therebetween. A system is also provided that has digital cameras, a motorized XYZ-axis stage, and a computer control system configured to i) control a spot size of the at least one laser source and ii) adjust a positioning of the sample to align individual chips with a target area of the laser.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: November 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Qianwen Chen, Bing Dang, Russell Budd, Bo Wen, Li-Wen Hung, Jae-Woong Nah, John Knickerbocker
  • Patent number: 10461123
    Abstract: A light emitting device, includes: a substrate; a light emitting element on the substrate, the light emitting element having a first end portion and a second end portion arranged in a longitudinal direction; one or more partition walls disposed on the substrate, the one or more partition walls being spaced apart from the light emitting element; a first reflection electrode adjacent the first end portion of the light emitting element; a second reflection electrode adjacent the second end portion of the light emitting element; a first contact electrode connected to the first reflection electrode and the first end portion of the light emitting element; an insulating layer on the first contact electrode, the insulating layer having an opening exposing the second end portion of the light emitting element and the second reflection electrode to the outside; and a second contact electrode on the insulating layer.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: October 29, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dae Hyun Kim, Jong Hyuk Kang, Joo Yeol Lee, Hyun Deok Im, Hyun Min Cho
  • Patent number: 10396049
    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip, wherein the first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pad, the semiconductor chip includes a passivation layer having an opening exposing at least a portion of the connection pad, the redistribution layer of the second interconnection member is connected to the connection pad through a via, and the via covers at least a portion of the passivation layer.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: August 27, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Min Ban, Han Kim, Kyung Moon Jung
  • Patent number: 10361122
    Abstract: A method includes forming a metal seed layer on a dielectric layer, and forming a patterned mask over the metal seed layer. An opening in the patterned mask is over a first portion of the dielectric layer, and the patterned mask overlaps a second portion of the dielectric layer. The method further includes plating a metal region in the opening, removing the patterned mask to expose portions of the metal seed layer, etching the exposed portions of the metal seed layer, performing a plasma treatment on a surface of the second portion of the dielectric layer, and performing an etching process on the surface of the second portion of the dielectric layer.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: July 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun Chen Hsieh, Hui-Jung Tsai, Hung-Jui Kuo, Chen-Hua Yu
  • Patent number: 10269721
    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant filling at least portions of spaces between walls of the through-hole and side surfaces of the semiconductor chip; and a second interconnection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip through vias, wherein the side surface of the semiconductor chip has a step portion.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: April 23, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Sang Jin Lee, Dong Hun Lee
  • Patent number: 10256300
    Abstract: A semiconductor device includes: an active layer that is located in an SOI substrate, and in which an element included in a circuit is formed; a buried insulation layer that is located in the SOI substrate, and is in contact with the active layer; a deep trench isolation (DTI) region that is formed in the active layer to surround a whole formation region of the element in plan view, and extends from an upper surface to a lower surface of the active layer; and a first conductive film formed above the element. The DTI region has a first hole inside, and a film thickness of the first conductive film is greater than a thickness of the active layer.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: April 9, 2019
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Shinya Natsume, Masaki Inoue, Mitsuo Tanaka
  • Patent number: 10229858
    Abstract: Conductive paths through a dielectric are described that have a high aspect ratio for semiconductor devices. In one example, a semiconductor device package has a semiconductor substrate having circuitry formed on the substrate. A plurality of conductive connection pads are on the semiconductor substrate to connect to the circuitry. A post is on each of a subset of the connection pads, the posts being formed of a conductive material. A dielectric layer is over the semiconductor substrate including over the connection pads and the posts. Filled vias are over each connection pad that is not of the subset and over each post of the subset of the connection pads and a connector is over each filled via.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: March 12, 2019
    Assignee: Intel IP Corporation
    Inventors: Thorsten Meyer, Andreas Wolter