Encapsulating Patents (Class 438/127)
  • Patent number: 10361122
    Abstract: A method includes forming a metal seed layer on a dielectric layer, and forming a patterned mask over the metal seed layer. An opening in the patterned mask is over a first portion of the dielectric layer, and the patterned mask overlaps a second portion of the dielectric layer. The method further includes plating a metal region in the opening, removing the patterned mask to expose portions of the metal seed layer, etching the exposed portions of the metal seed layer, performing a plasma treatment on a surface of the second portion of the dielectric layer, and performing an etching process on the surface of the second portion of the dielectric layer.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: July 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun Chen Hsieh, Hui-Jung Tsai, Hung-Jui Kuo, Chen-Hua Yu
  • Patent number: 10269721
    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant filling at least portions of spaces between walls of the through-hole and side surfaces of the semiconductor chip; and a second interconnection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip through vias, wherein the side surface of the semiconductor chip has a step portion.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: April 23, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Sang Jin Lee, Dong Hun Lee
  • Patent number: 10256300
    Abstract: A semiconductor device includes: an active layer that is located in an SOI substrate, and in which an element included in a circuit is formed; a buried insulation layer that is located in the SOI substrate, and is in contact with the active layer; a deep trench isolation (DTI) region that is formed in the active layer to surround a whole formation region of the element in plan view, and extends from an upper surface to a lower surface of the active layer; and a first conductive film formed above the element. The DTI region has a first hole inside, and a film thickness of the first conductive film is greater than a thickness of the active layer.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: April 9, 2019
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Shinya Natsume, Masaki Inoue, Mitsuo Tanaka
  • Patent number: 10229858
    Abstract: Conductive paths through a dielectric are described that have a high aspect ratio for semiconductor devices. In one example, a semiconductor device package has a semiconductor substrate having circuitry formed on the substrate. A plurality of conductive connection pads are on the semiconductor substrate to connect to the circuitry. A post is on each of a subset of the connection pads, the posts being formed of a conductive material. A dielectric layer is over the semiconductor substrate including over the connection pads and the posts. Filled vias are over each connection pad that is not of the subset and over each post of the subset of the connection pads and a connector is over each filled via.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: March 12, 2019
    Assignee: Intel IP Corporation
    Inventors: Thorsten Meyer, Andreas Wolter
  • Patent number: 10179730
    Abstract: Disclosed examples include sensor apparatus and integrated circuits having a package structure with an internal cavity and an opening that connects of the cavity with an ambient condition of an exterior of the package structure, and an electronic sensor structure mechanically supported by wires in the cavity and including a sensing surface exposed to the cavity to sense the ambient condition of an exterior of the package structure.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: January 15, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Barry Jon Male, Benjamin Cook, Robert Alan Neidorff, Steve Kummerl
  • Patent number: 10163855
    Abstract: An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various electronic devices, and methods of making thereof, that comprise a permanently coupled carrier that enhances reliability of the electronic devices.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: December 25, 2018
    Assignee: Amkor Technology, Inc.
    Inventors: Jong Sik Paek, Doo Hyun Park
  • Patent number: 10161022
    Abstract: A metal composition suitable for originating a joint by means of welding with a borosilicate glass for a solar collector. The composition, expressed in weight percentage, comprises the following alloy elements: Ni Co Mn Si C Ti Zr Ta Ti + Zr + Ta 28-31 15-18 ?0.5 ?0.3 ?0.05 ?0.30 ?0.30 ?0.30 ?0.40 and it is such that 45.5?(Ni+Co)?46.5, and that (Ti+Ta+Zr)?4×C, the remaining part being made up of iron, apart from the inevitable impurities. Additionally, a metal ring made of the metal composition described above and suitable for originating a metal-glass joint by means of welding; the metal-glass joint thus obtained; and the tubular solar collector thus obtained.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: December 25, 2018
    Assignee: ARCHIMEDE SOLAR ENERGY SRL
    Inventors: Federico Ruffini, Claudio Raggi, Stefano Fortunati, Learco Cagiola, Antonio De Luca
  • Patent number: 10163662
    Abstract: A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: December 25, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Cheng-Chia Chiang, Don-Son Jiang, Lung-Yuan Wang, Shih-Hao Tung, Shu-Huei Huang
  • Patent number: 10159154
    Abstract: A method of making a multilayered, fusion bonded circuit structure. A first circuitry layer is attached to a first major surface of a first LCP substrate. A plurality of first recesses are formed that extend from a second major surface of the first substrate to the first circuitry layer. The first recesses are then plated to form a plurality of first conductive pillars of solid metal that substantially fill the first recesses. A plurality of second recesses are formed in a second LCP substrate corresponding to a plurality of the first conductive pillars. The second recess are plated to form a plurality of second conductive structures that extend between first and second major surfaces of the second substrate. The second major surface of the first substrate is positioned adjacent to the second major surface of the second substrate. The first conductive pillars are aligned with the second conductive structures.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: December 18, 2018
    Assignee: HSIO Technologies, LLC
    Inventor: James Rathburn
  • Patent number: 10134719
    Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias and a protection film covering the molding compound and the die. The protection film is formed by a printing process.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Hui Cheng, Jing-Cheng Lin, Po-Hao Tsai
  • Patent number: 10132705
    Abstract: Systems and methods are disclosed for a pressure sensor device. The pressure sensor device includes a header that defines an interior cavity including one or more tether connecting regions. The header further defines an outer portion in communication with the interior cavity; the outer portion includes a plurality of through bores in communication with an exterior portion of the header for insertion of header pins through the header. The pressure sensor device includes a pressure sensor chip disposed within the interior cavity of the header. One or more anchoring tethers are attached to the corresponding one or more tether connecting regions. The pressure sensor chip is free to move within the interior cavity of the header, and the one or more anchoring tethers are in communication with the pressure sensor chip and are configured to limit movement of the pressure sensor chip within the header.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: November 20, 2018
    Assignee: Kulite Semiconductor Products, Inc.
    Inventors: Sorin Stefanescu, Alexander A. Ned, Joseph R. VanDeWeert, Andrew Bemis
  • Patent number: 10134710
    Abstract: A stacked semiconductor package in an embodiment includes a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; and a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package. The first semiconductor package further includes a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin; and a thermal via connected to the conductive layer and located on the first circuit board.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: November 20, 2018
    Assignee: J-DEVICES CORPORATION
    Inventors: Takeshi Miyakoshi, Sumikazu Hosoyamada, Yoshikazu Kumagaya, Tomoshige Chikai, Shingo Nakamura, Hiroaki Matsubara, Shotaro Sakumoto
  • Patent number: 10112822
    Abstract: A semiconductor device includes a first substrate, a second substrate, an anti-stiction layer and at least one metal layer. The first substrate includes a microelectromechanical systems (MEMS) structure. The second substrate is bonded to the first substrate and disposed over the MEMS structure. The second substrate comprises at least one through hole. The anti-stiction layer is disposed on a surface of the MEMS structure. The at least one metal layer is disposed over the second substrate and covers the at least one through hole of the second substrate.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: October 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Fung Chang, Lien-Yao Tsai, Len-Yi Leu
  • Patent number: 9953952
    Abstract: A semiconductor device includes a carrier, a chip attached to the carrier, a sealant vapor deposited over the chip and the carrier, and encapsulation material deposited over the sealed chip and the sealed carrier.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: April 24, 2018
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Michael Juerss, Stefan Landau
  • Patent number: 9892999
    Abstract: A method for producing wafer level packaging using an embedded leadframe strip and the resulting device are provided. Embodiments include placing dies into a mold with an active side of each die facing a surface of the mold; placing a leadframe strip on the mold, wherein the leadframe strip includes etched and half etched portions positioned between each die; placing a mold cover over the mold and dies; and adding mold compound in spaces between the dies and mold cover.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: February 13, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Richard S. Graf, Sudeep Mandal, Kibby Horsford
  • Patent number: 9865493
    Abstract: A plating jig that can form a metal plating film simultaneously on both surfaces of a semiconductor wafer by one plating process. The plating jig includes a base section and a cover section that can hold a substrate to be plated, and a center section that holds the substrate between the base section and cover section; the base section, the cover section and the center section each having an annular portion having an opening at a center thereof; seal packings each having a conductive ring disposed thereon being attached to each of facing surfaces of the annular portions of the base section and the cover section; the substrate to be plated being disposed inside the opening of the center section; and the substrate to be plated being held from front and back surfaces thereof with the seal packings attached to the cover section and the center section.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: January 9, 2018
    Assignee: JCU CORPORATION
    Inventors: Junichiro Yoshioka, Takashi Murayama
  • Patent number: 9842787
    Abstract: The present disclosure relates to an electronic element package and a method of manufacturing the same. The electronic element package includes a substrate, an element disposed on the substrate, and a cap enclosing the element. One of the substrate and the cap includes a groove, the other of the substrate and the cap includes a protrusion engaging with the groove. A first metal layer and a second metal layer form a metallic bond with each other in a space between the groove and the protrusion.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: December 12, 2017
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Pil Joong Kang, Kwang Su Kim, Ji Hye Nam, Jeong Il Lee, Jong Hyeong Song, Yun Sung Kang, Seung Joo Shin, Nam Jung Lee
  • Patent number: 9821998
    Abstract: In a microelectromechanical system (MEMS) device, a CMOS die is affixed to a die-mounting surface and wire-bonded to electrically conductive leads, and a MEMS die is stacked on and electrically coupled to the CMOS die in a flip-chip configuration. A package enclosure envelopes the MEMS die, CMOS die and wire bonds, and exposes respective regions of the electrically conductive leads.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: November 21, 2017
    Assignee: SiTime Corpoaration
    Inventors: Pavan Gupta, Aaron Partridge, Markus Lutz
  • Patent number: 9812422
    Abstract: An apparatus including a die; and a build-up carrier including alternating layers of conductive material and dielectric material disposed on a device side of the die and dielectric material embedding a portion of a thickness dimension of the die; and a plurality of carrier contact points disposed at a gradation between the device side of the die and the embedded thickness dimension of the die and configured for connecting the carrier to a substrate. A method including disposing a die on a sacrificial substrate with a device side of the die opposite the sacrificial substrate; forming a build-up carrier adjacent a device side of a die, wherein the build-up carrier includes a dielectric material defining a gradation between the device side of the die and a backside of the die, the gradation including a plurality of carrier contact points; and separating the die and the carrier from the sacrificial substrate.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: November 7, 2017
    Assignee: Intel Corporation
    Inventors: Toong Erh Ooi, Bok Eng Cheah, Nitesh Nimkar
  • Patent number: 9793188
    Abstract: The present invention relates generally to the field of semiconductor devices, including solar cells, and compositions and methods for processing semiconductor devices, passivation of semiconductor surfaces, semiconductor etching and anti-reflective coatings for semiconductor devices.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: October 17, 2017
    Inventor: Arjun Mendiratta
  • Patent number: 9704768
    Abstract: It is an object of the present invention to achieve reduced faults in manufacturing steps and increased reliability by relieving electric field strength of a surface of a power semiconductor chip. The present invention includes: a power semiconductor chip disposed on an insulating substrate; wiring connected to a surface conductor pattern in an element region of the power semiconductor chip; a low dielectric constant film disposed between the wiring and the peripheral region; and a sealing material formed so as to cover the insulating substrate, the power semiconductor chip, the wiring, and the low dielectric constant film. The low dielectric constant film has a dielectric constant lower than that of the sealing material.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: July 11, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yasuto Kawaguchi
  • Patent number: 9698135
    Abstract: A method for forming a package structure is provided. The method includes forming a plurality of conductive columns over a carrier substrate and forming an interfacial layer over sidewalls and tops of the conductive columns. The method also includes disposing a semiconductor die over a planar portion of the interfacial layer. The method further includes forming a molding compound to partially or completely encapsulate the semiconductor die, the conductive columns, and the interfacial layer such that the molding compound is in direct contact with the interfacial layer.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: July 4, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jing-Cheng Lin, Po-Hao Tsai
  • Patent number: 9699908
    Abstract: A component-embedded board includes a multilayer board obtained by stacking resin layers and an electronic component in the multilayer board having terminal electrodes on at least one principal face. The resin layers include a first resin layer having a space to accommodate the electronic component and at least one first interlayer connector formed by solidifying a conductive paste outside each of at least three sides of a principal face of the electronic component and a second resin layer having second and third interlayer connectors formed by solidifying a conductive paste. At least one second interlayer connector is positioned outside the three sides of the principal face. The third interlayer connectors are joined to the terminal electrodes. The first resin layer and the second resin layer are adjacent to each other in a stacking direction within the multilayer board. The first interlayer connector and the second interlayer connector are joined.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: July 4, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takahiro Baba, Yuki Wakabayashi
  • Patent number: 9673171
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: providing a semiconductor die having semiconductor die contacts; depositing an insulation layer on the semiconductor die including the semiconductor die contacts exposed; applying a conductive layer on the semiconductor die contacts and the insulation layer; and coupling system interconnects to the conductive layer for electrically connecting the semiconductor die to the system interconnects.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: June 6, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: HeeJo Chi, HeeSoo Lee, Omin Kwon
  • Patent number: 9666501
    Abstract: A semiconductor device including a die pad having a front surface made of Cu; a semiconductor chip disposed so as to be opposed to the front surface of the die pad; a bonding layer provided between the die pad and the semiconductor chip; and a plurality of leads disposed around the die pad, wherein the die pad and the plurality of leads make up a lead frame in cooperation with each other, a cavity is fabricated on the surface of the plurality of leads, and a projecting portion is fabricated next to the cavity.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: May 30, 2017
    Assignee: ROHM CO., LTD.
    Inventor: Motoharu Haga
  • Patent number: 9666500
    Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: May 30, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Pandi C. Marimuthu, Kang Chen, Hin Hwa Goh, Yu Gu, Il Kwon Shim, Rui Huang, Seng Guan Chow, Jianmin Fang, Xia Feng
  • Patent number: 9633923
    Abstract: There are provided an electronic device module capable of increasing a degree of integration by mounting electronic components on both surfaces of a board, and a manufacturing method thereof. The electronic device module includes a board having mounting electrodes formed on both surfaces thereof, a plurality of electronic devices mounted on the mounting electrodes, a molded portion sealing the electronic devices, at least one connection wire having one end bonded to one surface of the board and the other end exposed to the outside of the molded portion, and an external connection terminal coupled to the other end of the connection wire.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: April 25, 2017
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Do Jae Yoo, Jae Hyun Lim, Sun Ho Kim
  • Patent number: 9633834
    Abstract: A method for forming a coating layer includes spraying coating material having a first flowability onto a substrate; performing a first spin coating process with a first spin speed to form an initial coating layer; and performing a first baking process to the initial coating layer to form a first material layer having a second flowability and a second material layer having a third flowability. The third flowability is less than the first flowability but larger than the second flowability, which is less than the first flowability. Further, the method includes performing a second spin coating process with a second spin speed to drive the coating material in the second material layer flowing on the surface of the first material layer to form a third material layer with a uniform thickness, and performing a second baking process to form a final coating layer on the substrate.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: April 25, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Guowei Zhang
  • Patent number: 9617353
    Abstract: A method for protecting an electrical or electronic device against liquid damage, the method comprising a preliminary step of applying a continuous power plasma to the electrical or electronic device, followed by exposing the device to pulsed plasma comprising a compound of formula (I) where R1, R2 and R3 are independently selected from hydrogen, alkyl, haloalkyl or aryl optionally substituted by halo; and R4 is a group X—R5 where R5 is an alkyl or haloalkyl group and X is a bond; a group of formula C(O)O(CH2)nY where n is an integer of from 1 to 10 and Y is a bond or a sulphonamide group; or a group (O)pR6(O)q(CH2)t where R6 is aryl optionally substituted by halo, p is 0 or 1, q is 0 or 1 and t is 0 or an integer of from 1 to 10, provided that where q is 1, t is other than 0, for a sufficient period of time to allow a polymeric layer to form on the surface of the electrical or electronic device.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: April 11, 2017
    Assignee: PZi Limited
    Inventor: Stephen Coulson
  • Patent number: 9607937
    Abstract: An interposer to form a frame around a bottom chip bonded to a package substrate and to standoff a top chip or package for clearance of the bottom chip. The interposer has pins arrayed on a first side which are soldered to the package substrate for reduced interposer z-height and pads arrayed on a second side to which the top package (chip) is bonded. During assembly, the interposer pins may be pressed against pre-soldered pads and the solder reflowed to join the interposer to the package substrate. A top package (chip) is then joined to an opposite side of the interposer to integrate the first and second chips.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: March 28, 2017
    Assignee: Intel Corporation
    Inventors: Nicholas R. Watts, Tao Wu
  • Patent number: 9577216
    Abstract: The present disclosure relates to the field of organic electroluminescence and provides an OLED display device, a non-contact IC card and a flexible display device. The OLED display device includes a substrate, an encapsulation structure arranged above the substrate, and an OLED arranged between the substrate and the encapsulation structure. A region where an integrated circuit of the display device is bonded is arranged between the substrate and the OLED.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: February 21, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Seiji Fujino, Guodong Huang, Xiaohu Wang
  • Patent number: 9576918
    Abstract: Conductive paths through a dielectric are described that have a high aspect ratio for semiconductor devices. In one example, a plurality of conductive connection pads are formed on a semiconductor substrate to connect to circuitry formed on the substrate. A post is formed on each of a subset of the connection pads, the posts being formed of a conductive material. A dielectric layer is formed over the semiconductor substrate including over the connection pads and the posts. Holes are formed by removing the dielectric layer directly over the posts. The formed holes are filled with a conductive material and a connector is formed over each filled hole.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: February 21, 2017
    Assignee: INTEL IP CORPORATION
    Inventors: Thorsten Meyer, Andreas Wolter
  • Patent number: 9565758
    Abstract: A coating for reducing interaction between a surface and the environment around the surface includes an alkali silicate glass material configured to protect the surface from environmental corrosion due to water or moisture. The alkali silicate glass material is doped with a first element to affect various forms of radiation passing through the coating. The electromagnetic radiation is at least one of ultraviolet, x-ray, atomic (gamma, alpha, beta), and electromagnetic or radio wave radiation. The coating may also be used to protect a solar cell from the environment and UV rays while retransmitting received light as usable light for conversion into electrical energy. The coating may also be used to prevent whisker formation in metal finishes of tin, cadmium, zinc, etc.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: February 7, 2017
    Assignee: Rockwell Collins, Inc.
    Inventors: Nathan P. Lower, Alan P. Boone, Ross K. Wilcoxon, David D. Hillman
  • Patent number: 9558987
    Abstract: Gap-fill methods comprise: (a) providing a semiconductor substrate having a relief image on a surface of the substrate, the relief image comprising a plurality of gaps to be filled; (b) applying a gap-fill composition over the relief image, wherein the gap-fill composition comprises a non-crosslinked crosslinkable polymer, an acid catalyst, a crosslinker and a solvent, wherein the crosslinkable polymer comprises a first unit of the following general formula (I): wherein: R1 is chosen from hydrogen, fluorine, C1-C3 alkyl and C1-C3 fluoroalkyl; and Ar1 is an optionally substituted aryl group that is free of crosslinkable groups; and a second unit of the following general formula (II): wherein: R3 is chosen from hydrogen, fluorine, C1-C3 alkyl and C1-C3 fluoroalkyl; and R4 is chosen from optionally substituted C1 to C12 linear, branched or cyclic alkyl, and optionally substituted C6 to C15 aryl, optionally containing heteroatoms, wherein at least one hydrogen atom is substituted with a functional group
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: January 31, 2017
    Assignees: Dow Global Technologies LLC, Rohm and Haas Electronic Materials LLC, Rohm and Haas Electronic Materials Korea Ltd.
    Inventors: Jae Hwan Sim, Jin Hong Park, Jae-Bong Lim, Jung Kyu Jo, Cheng-Bai Xu, Jong Keun Park, Mingqi Li, Phillip D. Hustad
  • Patent number: 9466554
    Abstract: Some novel features pertain to an integrated device that includes an encapsulation layer, a via structure traversing the encapsulation layer, and a pad. The via structure includes a via that includes a first side, a second side, and a third side. The via structure also includes a barrier layer surrounding at least the first side and the third side of the via. The pad is directly coupled to the barrier layer of the via structure. In some implementations, the integrated device includes a first dielectric layer coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a substrate coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a first die coupled to the substrate, where the encapsulation layer encapsulates the first die. In some implementations, the via includes a portion configured to operate as a pad.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: October 11, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Jae Sik Lee, Hong Bok We, Dong Wook Kim, Shiqun Gu
  • Patent number: 9443829
    Abstract: A semiconductor device has a first interconnect structure. A first semiconductor die has an active surface oriented towards and mounted to a first surface of the first interconnect structure. A first encapsulant is deposited over the first interconnect structure and first semiconductor die. A second semiconductor die has an active surface oriented towards and mounted to a second surface of the first interconnect structure opposite the first surface. A plurality of first conductive pillars is formed over the second surface of the first interconnect structure and around the second semiconductor die. A second encapsulant is deposited over the second semiconductor die and around the plurality of first conductive pillars. A second interconnect structure including a conductive layer and bumps are formed over the second encapsulant and electrically connect to the plurality of first conductive pillars and the first and second semiconductor die.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: September 13, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Reza A. Pagaila
  • Patent number: 9406596
    Abstract: A device comprises a package component comprising a plurality of bumps formed on a first side of the package component, a semiconductor die mounted on the first side of the package component, a dielectric material formed over the first side of the package component, wherein four corners of the top surface of the package component are free from the dielectric material and a top package bonded on the first side of the package component, wherein the semiconductor die is located between the top package and the package component.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: August 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Patent number: 9408306
    Abstract: Systems and methods for a feeding structure for an antenna array are provided. In at least one embodiment, the feeding structure for an antenna array comprises one or more circuit boards with one or more circuits formed thereon, one or more conductive layers wherein the one or more circuit boards are mounted to the one or more conductive layers, and one or more connectors coupled to the one or more circuits through an opening in the one or more conductive layers. Furthermore, the one or more conductive layers are separated by a dielectric from the one or more circuits and the one or more conductive layers contact the one or more circuit boards such that the one or more circuits are isolated from the one or more conductive layers.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: August 2, 2016
    Assignee: Honeywell International Inc.
    Inventors: Nan Wang, Orville Nyhus, Chao Wang
  • Patent number: 9406014
    Abstract: A method for manufacturing a portable data carrier includes the steps of: providing a carrier band having an upper side and a lower side disposed opposite the upper side including a contact field formed with at least one contact area; arranging a semiconductor circuit on the lower side of the carrier band and electroconductively connected with the corresponding contact area; and carrying out an injection molding process on the lower side a potting compound formed around the semiconductor circuit and having outer dimensions according to a portable data carrier standard specification. An injection channel for injecting the potting compound is arranged on a side of the potting compound mold parallel to the lower side, and after the injection of the potting compound a depression remains in the finished data carrier due to the injection channel. A portable data carrier includes the features and is used as a subscriber identity module.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: August 2, 2016
    Assignee: GIESECKE & DEVRIENT GMBH
    Inventors: Bernhard Buttner, Thomas Tarantino, Robert Griesmeier
  • Patent number: 9396998
    Abstract: According to one embodiment, the first resin layer is provided on the first face of the upper layer chip. The first interconnect layer is electrically connected to the upper layer chip. The second resin layer extends into a region outside chip. The region is outer side of a side face of the upper layer chip. The second interconnect layer is provided in the second resin layer. The second interconnect layer is connected to the first interconnect layer and extending into the region outside chip. The lower layer chip is mounted on the surface side of the first resin layer, and is connected to the first interconnect layer. The first sealing resin covers the upper layer chip.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: July 19, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoichiro Kurita, Hirokazu Ezawa, Kazushige Kawasaki, Satoshi Tsukiyama
  • Patent number: 9355944
    Abstract: A semiconductor device includes a lead frame having a die support area and a plurality of inner and outer row leads surrounding the die support area, and a semiconductor die mounted on the die support area and electrically connected to the leads with bond wires. A molding material encapsulates the semiconductor die, the bond wires, and the leads, and defines a package body. The semiconductor device further includes connection bars extending vertically from the leads to a top surface of the package body. The connection bars connect the inner row leads to respective ones of the outer row leads before the molding process is performed.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: May 31, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Peng Liu, Qingchun He, Ping Wu
  • Patent number: 9343576
    Abstract: The present invention provides a thin film forming method. The method includes the steps of: providing a first substrate, of which a surface is covered with a thin film; forming a plurality of openings through the thin film; forming a hollow portion between the first substrate and the thin film by etching the first substrate through the openings; bringing the thin film into contact with a second substrate with a liquid interposed between the thin film and the second substrate; and heating the first substrate and/or the second substrate. In the step of heating, the liquid interposed between the thin film and the second substrate evaporates off, which results in that the thin film is separated from the first substrate and transferred onto the second substrate.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: May 17, 2016
    Assignee: Hiroshima University
    Inventors: Seiichiro Higashi, Kohei Sakaike, Yoshitaka Kobayashi, Shogo Nakamura, Muneki Akazawa
  • Patent number: 9324974
    Abstract: A laser induced thermal imaging apparatus includes a nozzle part disposed over a donor film in a vacuum chamber so as to be spaced apart from the donor film, and configured to spray an inactive gas onto an upper surface of the donor film. Also included is a shielding layer disposed on the upper surface of the donor film to make contact with the donor film and shaped so as to be positioned along a circumference or outer edge of the donor film.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: April 26, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Sam Ho Ihm
  • Patent number: 9318451
    Abstract: A first semiconductor device die is provided having a bottom edge incorporating a notch structure that allows sufficient height and width clearance for a wire bond connected to a bond pad on an active surface of a second semiconductor device die upon which the first semiconductor device die is stacked. Use of such notch structures reduces a height of a stack incorporating the first and second semiconductor device die, thereby also reducing a thickness of a semiconductor device package incorporating the stack.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: April 19, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Tim V. Pham, Michael B. McShane, Perry H. Pelley, Tab A. Stephens
  • Patent number: 9309108
    Abstract: A MEMS microphone packaging method includes the steps of: providing a substrate having a conducting part and a through hole; mounting a processor chip on the substrate and electrically connecting the processor chip to the conducting part; mounting a sensor chip on the substrate over the through hole and adjacent to the processor chip and electrically connecting the sensor chip to the processor chip; and mounting a cover on the substrate over the processor chip and the sensor chip. The cover has a conducting circuit, and the conducting circuit electrically coupled with the conducting part. Thus, the method of the invention can make a flip architecture MEMS microphone, reducing the steps of the packaging process and lowering the degree of difficulty of the manufacturing process and the manufacturing costs.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: April 12, 2016
    Assignee: LINGSEN PRECISION INDUSTRIES, LTD.
    Inventors: Hsien-Ken Liao, Ming-Te Tu
  • Patent number: 9313902
    Abstract: Methods for fabricating conductive structures on and/or in interposing devices and microfeature devices that are formed using such methods are disclosed herein. In one embodiment, a method for fabricating interposer devices having substrates includes forming a plurality of conductive sections on a first substrate in a first pattern. The method continues by forming a plurality of conductive sections on a second substrate in a second pattern. The method further includes constructing a plurality of conductive lines in a common third pattern on both the first substrate and the second substrate. The conductive lines can be formed on the first and second substrates either before or after forming the first pattern of conductive sections on the first substrate and/or forming the second pattern of conductive sections on the second substrate.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: April 12, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Mark S. Johnson
  • Patent number: 9305808
    Abstract: Methods and apparatus for forming a semiconductor device package on an interposer using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, where a micro-bump is used as a vertical connection between a die and the interposer, and a micro-bump line is used as a horizontal connection for signal transmission between different dies above the interposer. The micro-bump lines may be formed at the same time as the formation of the micro-bumps with little or no additional cost.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: April 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yu Lu, Hsien-Pin Hu, Hsiao-Tsung Yen, Tzuan-Horng Liu, Shih-Wen Huang, Shang-Yun Hou, Shin-Puu Jeng
  • Patent number: 9287190
    Abstract: Devices employing semiconductor die having hydrophobic coatings, and related cooling methods are disclosed. A device may include at least one semiconductor die electrically coupled to a substrate by electrical contact elements. During operation the semiconductor die and the electrical contact elements generate heat. By applying hydrophobic coatings to the semiconductor die and the electrical contact elements, a cooling fluid may be used to directly cool the semiconductor die and the electrical contact elements to maintain these components within temperature limits and free from electrical shorting and corrosion. In this manner, the semiconductor die and associated electrical contact elements may be cooled to avoid the creation of damaging localized hot spots and temperature-sensitive semiconductor performance issues.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: March 15, 2016
    Assignee: International Business Machines Corporation
    Inventors: Daniel J. Buvid, Eric J. Campbell, Tyler Jandt, Joseph Kuczynski
  • Patent number: 9287174
    Abstract: A fiber-containing resin substrate for collectively encapsulating a semiconductor-device-mounting surface of a substrate on which semiconductor devices are mounted or a semiconductor-device-forming surface of a wafer on which a semiconductor device is formed, including a resin-impregnated fibrous base material which is obtained by impregnating a fibrous base material with a thermosetting resin and semi-curing or curing the thermosetting resin and has a linear expansion coefficient (ppm/° C.) in an X-Y direction of less than 3 ppm, and an uncured resin layer formed of an uncured thermosetting resin on one side of the resin-impregnated fibrous base material.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: March 15, 2016
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Susumu Sekiguchi, Toshio Shiobara, Hideki Akiba, Tomoaki Nakamura
  • Patent number: 9260298
    Abstract: A stacked MEMS microphone packaging method includes the steps of: providing a substrate having a conducting part and a through hole; affixing a retaining wall to the substrate and forming a conducting circuit in electrical connection with the conducting part; mounting a processor chip and a sensor chip on the substrate to have the sensor chip be disposed at a top side of the through hole; providing a carrier board having a first solder pad and a second solder pad and fixedly mounting the carrier board at the retaining wall and electrically coupled to the first solder pad and the second solder pad. Thus, the method can make a flip architecture MEMS microphone, reducing the steps of the packaging process and lowering the degree of difficulty of the manufacturing process and the manufacturing costs.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: February 16, 2016
    Assignee: LINGSEN PRECISION INDUSTRIES, LTD.
    Inventors: Hsien-Ken Liao, Ming-Te Tu