Abstract: Disclosed is a package that includes a wafer substrate and a metal stack seed layer. The metal stack seed layer includes a titanium thin film outer layer. A resist layer is provided in contact with the titanium thin film outer layer of the metal stack seed layer, the resist layer forming circuitry. A method for manufacturing a package is further disclosed. A metal stack seed layer having a titanium thin film outer layer is formed. A resist layer is formed so as to be in contact with the titanium thin film outer layer of the metal stack seed layer, and circuitry is formed from the resist layer.

Abstract: A method of forming a thinned encapsulated chip structure, wherein the method comprises providing a separation structure arranged within an electronic chip, encapsulating part of the electronic chip by an encapsulating structure, and thinning selectively the electronic chip partially encapsulated by the encapsulating structure so that the encapsulating structure remains with a larger thickness than the thinned electronic chip, wherein the separation structure functions as a thinning stop.

Abstract: To provide a resin composition for sealing an optical semiconductor, which is a raw material for a sealing resin layer having good curability and excellent storage stability; preferably a raw material for a sealing resin layer further having excellent weather resistance. The surface sealant for an optical semiconductor of Embodiment 1 according to the present invention contains epoxy resin (a) having two or more epoxy groups in a molecule, and metal complex (b1) which contains at least one metal ion selected from the group consisting of Zn, Bi, Ca, Al, Cd, La and Zr, a tertiary amine capable of forming a complex with the metal ion and having no N—H bond and an anionic ligand having a molecular weight of 17 to 200, in which the surface sealant has a viscosity of 10 to 10000 mPa·s, as measured by E-type viscometer at 25° C. and 1.0 rpm.

Abstract: A method of making a package substrate having a copper bond pad and a location for receiving a semiconductor die having a remnant of one of a group consisting of HEDP and an HEDP derivative on a top surface of the copper bond pad. The semiconductor die is attached to the substrate. A wirebond connection is attached between the remnant and the semiconductor die.

Abstract: Methods and apparatuses for improved integrated circuit (IC) packages are described herein. In an aspect, an IC device package includes an IC die having a contact pad, where the contact pad is located on a hotspot of the IC die. The hotspot is thermally coupled to a thermal interconnect member. In an aspect, the package is encapsulated in a mold compound. In a further aspect, a heat spreader is attached to the mold compound, and is thermally coupled to the thermal interconnect member. In another aspect, a thermal interconnect member thermally is coupled between the heat spreader and the substrate.

Abstract: Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface, a plurality of side surfaces, and a bond pad defined on the top surface. A layer of encapsulant substantially surrounds the side surfaces of the integrated circuit, the layer of encapsulant having a height substantially equal to a height of the integrated circuit. A bump is spaced apart from the integrated circuit, and a redistribution layer electrically couples the bond pad of the integrated circuit to the bump.

Abstract: Embodiments of the subject application provide for a circuit comprising: a lead frame having a first plurality of exposed terminals, the lead frame defining a plane; a laminate substrate in the plane defined by the lead frame, adjacent to the lead frame, and electrically coupled to the lead frame, the laminate substrate having a first surface including a second plurality of exposed terminals and a second surface opposite the first surface; a first one or more dies mounted on the lead frame and electrically coupled to the lead frame; and a second one or more dies mounted on the second surface of the laminate substrate and electrically coupled to the laminate substrate.

Abstract: A high-frequency module has a multilayer board formed by laminating a plurality of sheets made of a thermoplastic resin material and subjecting the laminated sheets to thermocompression bonding, and an IC chip placed in a cavity provided in the multilayer board. A gap is provided between a side of the IC chip and an inner wall of the cavity. The multilayer board includes a via-hole conductor provided near the inner wall of the cavity for preventing the resin sheets from being softened and flowing into the cavity upon thermocompression bonding.

Abstract: A die has a top surface, and a metal pillar having a portion protruding over the top surface of the die. A sidewall of the metal pillar has nano-wires. The die is bonded to a package substrate. An underfill is filled into the gap between the die and the package substrate.

Abstract: An approach is provided for aligning and leveling a chip package portion. The approach involves filling, at least partially, a reservoir formed between a first sidewall portion having a first slanted surface and a second sidewall portion having a second slanted surface with a fluid. The approach also involves placing a chip package portion into the reservoir. The approach further involves draining the fluid from the reservoir to cause the chip package portion to align with respect to a center of the reservoir. The chip package portion aligns with respect to the center of the reservoir and levels based on a relationship between the chip package portion, an angle of the first slanted surface, an angle of the second slanted surface, and the fluid. The chip package portion is secured in the aligned and leveled state by a molding compound.

Abstract: In one embodiment, a complementary metal-oxide-semiconductor (CMOS) logic device formed with single-walled carbon nanotubes (SWCNTs) includes: at least one p-type metal-oxide-semiconductor (PMOS) thin-film transistor (TFT) formed with the SWCNTs, and at least one n-type metal-oxide-semiconductor (NMOS) TFT formed with the SWCNTs, where each of the at least one PMOS TFT and the at least one NMOS TFT has a gate, a source and a drain. The gate of each of the at least one PMOS TFT and the gate of each of the at least one NMOS TFT is configured to alternatively receive at least one input voltage, and respectively includes a local metallic gate structure formed of a metal. At least one of the drain of the at least one PMOS TFT and the drain of the at least one NMOS TFT is configured to output an output voltage VOUT.

Abstract: A package includes a molding compound, a through-via penetrating through the molding compound, a device die molded in the molding compound, and a buffer layer on and contacting the molding compound. An opening is through the buffer layer to the through-via. The buffer layer has ripples in a plane parallel to an interface between the molding compound and the buffer layer and around a circumference of the opening. Other embodiments contemplate an additional package bonded to the package, and methods for forming the package.

Abstract: A fabrication method of manufacturing a package a plurality of electronic components in an encapsulation body, firstly, mounting the plurality of electronic components and one ends of a plurality of metal resilient units on a substrate. After that, the plurality of electronic components and the plurality of metal resilient units are encapsulated on the substrate to form an encapsulation body with another ends of the plurality of metal resilient units exposed on an exterior surface of the encapsulation body. Then etching remaining epoxy resin on the other ends of the plurality of metal resilient units.

Abstract: A light-emitting device production method includes a positioning step of positioning, in a light-emitting element, a sealing member at least containing a silicone resin semi-cured at a room temperature (T0) by primary cross-linking and a fluorescent material, the silicone resin decreasing in viscosity reversibly in a temperature region between the room temperature (T0) and a temperature lower than a secondary cross-linking temperature (T1), and being totally cured non-reversibly in a temperature region equal to or higher than the secondary cross-linking temperature (T1).

Abstract: An organic light-emitting display and methods of manufacturing the same are disclosed. In one aspect, an organic light-emitting apparatus includes a substrate, a display unit on the substrate, a step compensation layer formed on the display unit and supplementing a step on a surface of the display unit, a first intermediate layer formed on the step compensation layer, and an encapsulation layer formed on the first intermediate layer and sealing the display unit.

Abstract: Provided are a resin composition and a substrate that are capable of being used for producing an electronic device including thin-film transistors having an excellent switching property. The resin composition contains an aromatic polyamide and a solvent dissolving the aromatic polyamide. The resin composition is used to form a layer, and a total light transmittance of the layer in a wavelength of 355 nm is 10% or less. Further, a method of manufacturing the electronic device using such a substrate is also provided.

Abstract: Provided are a resin composition and a substrate that are capable of being used for manufacturing an electronic device having excellent light extraction efficiency. The resin composition contains a crystalline polymer and a solvent dissolving the crystalline polymer. The resin composition is used to form a layer, and a haze value of the layer is 5% or more. Further, a method of manufacturing the electronic device by using such a substrate, and the electronic device are also provided.

Abstract: Embodiments of the present description include methods for attaching a microelectronic device to a microelectronic substrate with interconnection structures after disposing of an underfill material on the microelectronic device, wherein filler particles within the underfill material may be repelled away from the interconnection structures prior to connecting the microelectronic device to the microelectronic structure. These methods may include inducing a charge on the interconnection structures and may include placing the interconnection structures between opposing plates and producing a bias between the opposing plates after depositing the underfill material on the interconnection structures.

Abstract: A process for encapsulating a micro-device in a cavity formed between a first and a second substrate is provided, including producing the micro-device in or on the first substrate; attaching and securing the second substrate to the first substrate, thereby forming the cavity in which the micro-device is placed; producing at least one hole through one of the two substrates, leading into the cavity opposite a portion of the other of the two substrates; depositing at least one getter material portion through the hole on said portion of the other of the two substrates; and hermetically sealing the cavity by closing the hole.

Abstract: Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, having an interposer including at least one topological feature, such as a depression in a surface of the interposer, a die coupled to the surface of the interposer, and an encapsulant material formed over the die and the interposer, and disposed in the at least one depression to resist movement of the encapsulant material relative to the interposer. Other embodiments may be described and claimed.

Abstract: A solar cell module is manufactured by forming silicone coating films (2, 2) on panels (1a, 1b), placing a solar cell matrix (3) on the silicone coating film on panel (1a), providing a seal member (4) consisting of a base seal member (4a) of butyl rubber and protrusive seal segments (4b) of butyl rubber on a peripheral region of panel (1a), mating the two panels together such that the seal member (4) may abut against a peripheral region of panel (1b), and the solar cell matrix (3) may be sandwiched between the silicone coating films (2), and compressing and heating the mated panels (1a, 1b) in vacuum for establishing a seal around the solar cell matrix (3).

Abstract: A method of protecting a semiconductor structure from water and a semiconductor structure formed by the method. The semiconductor structure includes a wide-bandgap semiconductor material in which at least one semiconductor device is formed. The method includes heating the semiconductor structure in a vacuum to a temperature of at least 200° C. to remove water from the semiconductor structure. The method also includes, after the heating of the semiconductor structure, forming a layer comprising a hydrophobic material over the semiconductor structure. The semiconductor structure is kept in the vacuum between the heating of the semiconductor structure and the forming of the layer comprising the hydrophobic material.

Abstract: A system and method for applying an underfill is provided. An embodiment comprises applying an underfill to a substrate and patterning the underfill. Once patterned other semiconductor devices, such as semiconductor dies or semiconductor packages may then be attached to the substrate through the underfill, with electrical connections from the other semiconductor devices extending into the pattern of the underfill.

Abstract: Electronic devices including a semiconductor device package, a substrate, and first and second solder joints. The semiconductor device package includes a die pad, leads and enhancement elements surrounding the die pad, a chip electrically connected to the leads, and a package body encapsulating the chip, portions of the leads, and portions of the enhancement elements, but leaving exposed at least a side surface of each enhancement element. Side surfaces of the enhancement elements and the package body are coplanar. The substrate includes first pads corresponding to the leads and second pads corresponding to the enhancement elements. The first solder joints are disposed between the first pads and the leads. The second solder joints are disposed between the second pads and the enhancement elements. The second solder joints contact side surfaces of the enhancement elements. The surface area of the second pads is greater than the surface area of the corresponding enhancement elements.

Abstract: A method of manufacture of an integrated circuit packaging system comprising: providing a package carrier; mounting an integrated circuit to the package carrier; and forming a perimeter antiwarpage structure on and along a perimeter of the package carrier.

Abstract: Packaging devices, methods of manufacture thereof, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging device includes a substrate including an integrated circuit die mounting region. An underfill material flow prevention feature is disposed around the integrated circuit die mounting region.

Abstract: A single metal layer tape substrate includes a patterned metal layer affixed to a patterned dielectric layer. The dielectric layer is patterned to provide openings exposing lands and bond sites on bond fingers on the land side of the metal layer. The metal layer is patterned to provide circuit traces as appropriate for interconnection with the die (on the die attach side) and with other elements (such as other packages in a multi-package module). Interconnection with a die is made by wire bonding to exposed traces on a die attach side of the metal layer, and bond fingers and lands for access to testing the package are provided on the opposite (land) side of the metal layer.

Abstract: A semiconductor device has a semiconductor die with a first encapsulant disposed over the semiconductor die. A first build-up interconnect structure is formed over the semiconductor die and first encapsulant. The first build-up interconnect structure has a first conductive layer. The first conductive layer includes a plurality of first conductive traces. A second encapsulant is disposed over the semiconductor die and the first build-up interconnect structure. A second build-up interconnect structure is formed over the first build-up interconnect structure and the second encapsulant. The second build-up interconnect structure has a second conductive layer. The second conductive layer includes a plurality of second conductive traces. A distance between the second conductive traces is greater than a distance between the first conductive traces. A passive device is disposed within the first encapsulant and/or the second encapsulant.

Abstract: A semiconductor device has a substrate with a stiffening layer disposed over the substrate. The substrate has a circular shape or rectangular shape. A plurality of semiconductor die is disposed over a portion of the substrate while leaving an open area of the substrate devoid of the semiconductor die. The open area of the substrate devoid of the semiconductor die includes a central area or interstitial locations among the semiconductor die. The semiconductor die are disposed around a perimeter of the substrate. An encapsulant is deposited over the semiconductor die and substrate. The substrate is removed and an interconnect structure is formed over the semiconductor die. By leaving the predetermined areas of the substrate devoid of semiconductor die, the warping effect of any mismatch between the CTE of the semiconductor die and the CTE of the encapsulant on the reconstituted wafer after removal of the substrate is reduced.

Abstract: A method for producing a component with at least one micro-structured or nano-structured element includes applying at least one micro-structured or nano-structured element to a carrier. The element has at least one area configure to make contact and the element is applied to the carrier such that the at least one area adjoins the carrier. The element is enveloped in an enveloping compound and the element-enveloping compound composite is detached from the carrier. A first layer comprising electrically conductive areas is applied to the side of the element-enveloping compound composite that previously adjoined the carrier. At least one passage is introduced into the enveloping compound. A conductor layer is applied to the surface of the passage and at least to a section of the layer comprising the first electrically conductive areas to generate a through contact, which enables space-saving contacting. A component is formed from the method.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead-frame having a metal connector mounted thereon and having a peripheral mounting region; forming an insulation cover on the lead-frame and on the metal connector; connecting an integrated circuit die over the insulation cover; forming a top encapsulation on the integrated circuit die with the peripheral mounting region exposed from the top encapsulation; forming a routing layer, having a conductive land, from the lead-frame; and forming a bottom encapsulation partially encapsulating the routing layer and the insulation cover.

Abstract: Disclosed is a polyimide composition for semiconductor devices, which has a rheological characteristics suited for screen printing and dispense coating, which has an improved wetting property with various coating bases, by which continuous printing of 500 times or more can be attained, with which blisters, cissing and pinholes are not generated after printing and drying or during drying or curing, which can coat a desired area. A method of forming a film in a semiconductor and semiconductors having the film formed by this method as an insulation film, protective film or the like are also disclosed. The composition for semiconductor devices contains a mixed solvent of a first organic solvent (A) and a second organic solvent (B); and a polyimide resin having at least one group selected from the group consisting of alkyl groups and perfluoroalkyl groups in recurring units, and having thixotropic property, the polyimide resin being dissolved in the mixed solvent.

Abstract: A method of making a microelectronic package, and a microelectronic package made according to the method. The method includes: bonding and thermally coupling a plurality of IC dies to an IHS panel to yield a die-carrying IHS panel, and mounting the die-carrying IHS panel onto a substrate panel including a plurality of package substrates by mounting perimeter ribs of the IHS panel to a corresponding pattern of sealant on the substrate panel and by mounting each of the plurality of dies to a corresponding one of the plurality of package substrates to yield a combination including the die-carrying IHS panel mounted to the substrate panel. Other embodiments are also disclosed and claimed.

Abstract: A reconfigured wafer of resin-encapsulated semiconductor packages is obtained by supporting with a resin, thereafter, a grinding process is performed on top and backside surfaces to expose only a bump interconnection electrode on a surface of a semiconductor chip. Further, a chip-scale package is obtained by a dicing process along a periphery of the chip.

Abstract: A semiconductor package with simulated wirebonds. A substrate is provided with a plurality of first pads on a first surface and a plurality of second pads on a second surface. Each of the first pads are electrically coupled to one or more of the second pads. At least one semiconductor device is located proximate the first surface of a substrate. The simulated wirebonds include at least a first dielectric layer selectively printed to create a plurality of recesses, and a conductive material located in the recesses to form first and second contact pads, and electrical traces electrically coupling the first and second contact pads. The first contact pads are electrically coupled to terminals on the semiconductor device and the second contact pads are electrically coupled to the first pads on the first surface of the substrate. An overmolding material seals the semiconductor device and the simulated wirebonds.

Abstract: Disclosed are a flip-chip carrier having individual pad masks (IPMs) and a fabricating method of a MPS-C2 package utilized from the same. The flip-chip carrier primarily comprises a substrate and a plurality of the IPMs. The substrate has a top surface and a plurality of connecting pads on the top surface. The IPMs cover the corresponding connecting pads in one-on-one alignment where each IPM consists of a photo-sensitive adhesive layer on the corresponding connecting pad and a pick-and-place body pervious to light formed on the photo-sensitive adhesive layer. After the photo-sensitive adhesive layers are irradiated by light penetrating through the pick-and-place bodies, the pick-and-place bodies can be pulled out by a pick-and-place process to expose the connecting pads from an encapsulant. The issues of solder bridging and package warpage can easily be solved in conventional MPS-C2 packages.

Abstract: The present invention discloses an adhesive-free method for preparation of micro electro-mechanical structure, comprising forming a micro electro-mechanical structure on a first substrate, forming an enclosing space for immersing liquid on the first or second substrate, and applying pressure to fix the first and second substrate. Before applying the pressure, the assembly including the two substrates is flipped, to make the contact surface immersed by the immersing liquid.

Abstract: A cover glass element can extend to the edges of an electronic device while maintaining the optical flatness and thickness needed for the cover glass. A first glass sheet with the desired thickness and flatness can be thermally bonded to a second glass sheet machined to include an opening to be received by the edges of the electronic device. The resulting three-dimensional cover element forms a uni-body frame that is significantly stiffer than a single sheet of glass, and the larger surface area of the edge provides for enhances pressure distribution, particularly after chemical strengthening, thus enhancing the durability of the electronic device. Further, the thermal bonding process uses lower temperatures than processes such as slumping or pressing, which could potentially affect the flatness and optical clarity of the original sheet glass.

Abstract: A through-holed interposer is provided, including a board body, a conductive gel formed in the board body, and a circuit redistribution structure disposed on the board body. The conductive gel has one end protruding from a surface of the board body, and an area of the protruded end of the conductive gel that is in contact with other structures (e.g., packaging substrates or circuit structures) is increased, thereby strengthening the bonding of the conductive gel and reliability of the interposer.

Abstract: Provided is a method of fabricating a multi-chip stack package. The method includes preparing single-bodied lower chips having a single-bodied lower chip substrate having a first surface and a second surface disposed opposite the first surface, bonding unit package substrates onto the first surface of the single-bodied lower chip substrate to form a single-bodied substrate-chip bonding structure, separating the single-bodied substrate-chip bonding structure into a plurality of unit substrate-chip bonding structures, preparing single-bodied upper chips having a single-bodied upper chip substrate, bonding the plurality of unit substrate-chip bonding structures onto a first surface of the single-bodied upper chip substrate to form a single-bodied semiconductor chip stack structure, and separating the single-bodied semiconductor chip stack structure into a plurality of unit semiconductor chip stack structures.

Abstract: A method of manufacturing a semiconductor device includes providing a transfer foil. A plurality of semiconductor chips is placed on and adhered to the transfer foil. The plurality of semiconductor chips adhered to the transfer foil is placed over a multi-device carrier. Heat is applied to laminate the transfer foil over the multi-device carrier, thereby accommodating the plurality of semiconductor chips between the laminated transfer foil and the multi-device carrier.

Abstract: A chemical vapor deposited film includes silicon atoms, oxygen atoms, carbon atoms, and hydrogen atoms. The chemical vapor deposited film is formed by a plasma CVD method such that the concentration of the oxygen atoms is 10-35% by element.

Abstract: Introducing an underfill material over contact pads on a surface of an integrated circuit substrate; and ablating the introduced underfill material to expose an area of the contact pads using temporally coherent electromagnetic radiation. A method including first ablating an underfill material to expose an area of contact pads on a substrate using temporally coherent electromagnetic radiation; introducing a solder to the exposed area of the contact pads; and second ablating the underfill material using temporally coherent electromagnetic radiation. A method including introducing an underfill material over contact pads on a surface of an integrated circuit substrate; defining an opening in the underfill material to expose an area of the contact pads using temporally coherent electromagnetic radiation; introducing a solder material to the exposed area of the contact pads; and after introducing the solder, removing the sacrificial material.

Abstract: A method for producing an electronic component and an electronic component, having barrier layers for the encapsulation of the component. The method involves providing a substrate (1) with at least one functional layer (22), and an electronic component, applying at least one first barrier layer (3) on the functional layer (22) by way of plasmaless atomic layer deposition (PLALD), and applying at least one second barrier layer (4) on the functional layer (22) by way of plasma-enhanced chemical v0apor deposition (PECVD).

Abstract: A semiconductor device includes a carrier and a semiconductor chip disposed over the carrier. The semiconductor chip has a first surface and a second surface opposite to the first surface, wherein the second surface faces the carrier. Further, the semiconductor device includes a pre-encapsulant covering at least partially the second surface of the semiconductor chip and at least partially a side wall surface of the semiconductor chip. The pre-encapsulant has a thermal conductivity of equal to or greater than 10 W/(m·K) and a specific heat capacity of equal to or greater than 0.2 J/(g·K).

Abstract: Underfill structures useful as pre-applied underfill materials comprise a polymer layer having a first polymer region and a second polymer region, wherein the second polymer region comprises inorganic filler. Electronic assemblies comprising a chip or die and a substrate are formed using such multi-layer structured pre-applied underfill.

Abstract: An electronics assembly includes a semiconductor die assembly, an enclosure affixed to the semiconductor die assembly, the enclosure defining first and second chambers over the semiconductor die assembly, and first and second optical elements mounted in the first and second chambers, respectively. The semiconductor die assembly includes a semiconductor die encapsulated in a molded material, an encapsulation layer located on the top surface of the semiconductor die, and at least one patterned metal layer and at least one dielectric layer over the encapsulation layer. Conductive pillars extend through the encapsulation layer for electrical connection to the semiconductor die. The encapsulation layer blocks optical crosstalk between the first and second chambers. A method is provided for making the electronics assembly.

Abstract: A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.

Abstract: A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.

Abstract: A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.