Using Structure Alterable To Conductive State (i.e., Antifuse) Patents (Class 438/131)
  • Patent number: 10539475
    Abstract: In one embodiment the invention provides an interconnection component operable to interconnect a stretchable sensing component and cable for a sensing circuit. The interconnection component has a flexible circuit board comprising conductive regions to electrically connect to conductive layers of a sensor component overlaying the circuit. The flexible circuit board of one embodiment comprises engagement features to allow the sensor cast over the component to engage the flexible circuit board.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: January 21, 2020
    Assignee: SENSOR HOLDINGS LIMITED
    Inventors: Todd Alan Gisby, Andrew Thomas Wong, Llewellyn Adair Sims Johns
  • Patent number: 10157812
    Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor element formed in or on the semiconductor substrate, a metal layer connected to the semiconductor element, and a passivation film that protects the semiconductor element. The passivation film is formed by alternately stacking a first insulation film that generates compressive stress and has low density and a second insulation film that generates compressive stress and has high density. The first insulation film is disposed in a lowest layer of the passivation film, the lowest layer being nearest to the semiconductor substrate. Each of the first insulation film and the second insulation film is one of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: December 18, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Masayuki Aoike, Atsushi Kurokawa, Atsushi Kobayashi
  • Patent number: 9799663
    Abstract: An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: October 24, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Hsiang-Lan Lung
  • Patent number: 9716032
    Abstract: The present disclosure provides a method for forming a semiconductor device. The semiconductor device includes a first conductive line disposed over a substrate. The first conductive line is located in a first interconnect layer and extends along a first direction. The semiconductor device includes a second conductive line and a third conductive line each extending along a second direction different from the first direction. The second and third conductive lines are located in a second interconnect layer that is different from the first interconnect layer. The second and third conductive lines are separated by a gap that is located over or below the first conductive line. The semiconductor device includes a fourth conductive line electrically coupling the second and third conductive lines together. The fourth conductive line is located in a third interconnect layer that is different from the first interconnect layer and the second interconnect layer.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: July 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Po Tang, Shih-Ming Chang, Ken-Hsien Hsieh, Ru-Gun Liu
  • Patent number: 9646869
    Abstract: Semiconductor devices including at least one diode over a conductive strap. The semiconductor device may include at least one conductive strap over an insulator material, at least one diode comprising a single crystalline silicon material over a conductive material, and a memory cell on the at least one diode. The at least one diode may be formed from a single crystalline silicon material. Methods of forming such semiconductor devices are also disclosed.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: May 9, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Ming Zhang
  • Patent number: 9543577
    Abstract: An electrode in which a silicon layer is provided over a current collector, a thin film layer having a thickness within a certain range is provided on a surface of the silicon layer, and the thin film layer contains fluorine, is used for a power storage device. The thickness of the thin film layer containing fluorine is greater than 0 nm and less than or equal to 10 nm, preferably greater than or equal to 4 nm and less than or equal to 9 nm. The fluorine concentration of the thin film layer containing fluorine is preferably as high as possible, and the nitrogen concentration, the oxygen concentration, and the hydrogen concentration thereof are preferably as low as possible.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: January 10, 2017
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kazutaka Kuriki, Mitsuhiro Ichijo, Toshiya Endo
  • Patent number: 9362158
    Abstract: A one-time programmable (OTP) memory cell is provided, which includes: a well of a first conductivity type; a gate insulating layer formed on the well and including first and second fuse regions; a gate electrode of a second conductivity type formed on the gate insulating layer, the second conductivity type being opposite in electric charge to the first conductivity type; a junction region of the second conductivity type formed in the well and arranged to surround the first and second fuse regions; and an isolation layer formed in the well between the first fuse region and the second fuse region.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: June 7, 2016
    Assignee: MAGNACHIP SEMICONDUCTOR, LTD.
    Inventor: Seong-do Jeon
  • Patent number: 9263450
    Abstract: A one-time programmable (OTP) memory cell is provided, which includes: a well of a first conductivity type; a gate insulating layer formed on the well and including first and second fuse regions; a gate electrode of a second conductivity type formed on the gate insulating layer, the second conductivity type being opposite in electric charge to the first conductivity type; a junction region of the second conductivity type formed in the well and arranged to surround the first and second fuse regions; and an isolation layer formed in the well between the first fuse region and the second fuse region.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: February 16, 2016
    Assignee: Magnachip Semiconductor, Ltd.
    Inventor: Seong-do Jeon
  • Patent number: 9246089
    Abstract: A memory cell according to the present invention comprises a bottom conductor, a doped semiconductor pillar, and a top conductor. The memory cell does not include a dielectric rupture antifuse separating the doped semiconductor pillar from either conductor, or within the semiconductor pillar. The memory cell is formed in a high-impedance state, in which little or no current flows between the conductors on application of a read voltage. Application of a programming voltage programs the cell, converting the memory cell from its initial high-impedance state to a low-impedance state. A monolithic three dimensional memory array of such cells can be formed, comprising multiple memory levels, the levels monolithically formed above one another.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: January 26, 2016
    Assignee: SanDisk 3D LLC
    Inventors: Scott Brad Herner, Andrew Walker
  • Patent number: 9224750
    Abstract: A memory array includes a plurality of ridge-shaped multi-layer stacks extending along a first direction, and a hard mask layer formed on top of the plurality of ridge-shaped multi-layer stacks. The hard mask layer includes a plurality of stripes vertically aligned with the plurality of ridge-shaped multi-layer stacks, respectively, a plurality of bridges connecting adjacent ones of the stripes along a second direction orthogonal to the first direction, and a plurality of hard mask through holes between the plurality of bridges and the plurality of stripes.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: December 29, 2015
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Teng-Hao Yeh, Chih-Wei Hu, Yen-Hao Shih
  • Patent number: 9087691
    Abstract: A MOSFET with a graphene nano-ribbon, and a method for manufacturing the same are provided. The MOSFET comprises an insulating substrate; and an oxide protection layer on the insulating substrate. At least one graphene nano-ribbon is embedded in the oxide protection layer and has a surface which is exposed at a side surface of the oxide protection layer. A channel region is provided in each of the at least one graphene nano-ribbon. A source region and a drain regions are provided in each of the at least one graphene nano-ribbon. The channel region is located between the source region and the drain region. A gate dielectric is positioned on the at least one graphene nano-ribbon. A gate conductor on the gate dielectric. A source and drain contacts contact the source region and the drain region respectively on the side surface of the oxide protection layer.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: July 21, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Qingqing Liang, Zhijiong Luo, Haizhou Yin
  • Patent number: 9076535
    Abstract: A source of charge carriers in thin film transistor-based memory devices is provided for a memory. The source of charge carriers can include a diode having a first and second terminal. A NAND string coupled on a first end via a first switch to a bit line, is coupled on a second end via a second switch to the first terminal of the diode. Separately drivable first and second supply lines are coupled to the first and second terminals, respectively of the diode. Circuitry is included that is coupled to the first and second supply lines, that is configured to bias the first and second supply lines with different bias conditions depending on the mode of operation, including forward bias conditions and reverse bias conditions.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: July 7, 2015
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chih-Wei Hu, Teng-Hao Yeh, Yen-Hao Shih
  • Patent number: 9054305
    Abstract: A nonvolatile memory device includes a plurality of nonvolatile memory elements each having an upper electrode, a variable resistance layer, and a lower electrode; a first insulating layer embedding the plurality of nonvolatile memory elements, and ranging from a lowermost part of the lower electrode to a position higher than an uppermost part of the upper electrode in each of the nonvolatile memory elements; a second insulating layer being formed on the first insulating layer, and having an average size of vacancies larger than an average size of vacancies included in the first insulating layer, or having an average carbon concentration higher than an average carbon concentration of the first insulating layer; and a conductive layer penetrating the second insulating layer and a part of the first insulating layer and being connected to at least one of the upper electrodes included in the nonvolatile memory elements.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: June 9, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Satoru Ito, Yoshio Kawashima, Yukio Hayakawa, Takumi Mikawa
  • Patent number: 9053783
    Abstract: According to one embodiment, in a nonvolatile semiconductor memory device, a first line is disposed on a semiconductor substrate. A first memory cell is disposed on a side opposite to the semiconductor substrate with respect to the first line. A second line intersects with the first line via the first memory cell. A second memory cell is disposed on a side opposite to the semiconductor substrate with respect to the second line. A third line intersects with the second line via the second memory cell. The first memory cell has a first resistance change layer and a first rectification layer. The second memory cell has a second resistance change layer and a second rectification layer. A composition of the first resistance change layer is different from a composition of the second resistance change layer.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: June 9, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Satoshi Konagai
  • Patent number: 9040370
    Abstract: A device includes a substrate, isolation regions at a surface of the substrate, and a semiconductor region over a top surface of the isolation regions. A conductive feature is disposed over the top surface of the isolation regions, wherein the conductive feature is adjacent to the semiconductor region. A dielectric material is disposed between the conductive feature and the semiconductor region. The dielectric material, the conductive feature, and the semiconductor region form an anti-fuse.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsiao-Lan Yang
  • Patent number: 9029170
    Abstract: A magnetic tunnel junction (MTJ) device is formed by a process that includes forming a trench in a substrate and depositing an MTJ structure within the trench. The MTJ structure includes a bottom electrode, a fixed layer, a tunnel barrier layer, a free layer, and a top electrode. The process includes applying reverse photo etching to remove material that is not directly over the trench. The process also includes plagiarizing the MTJ structure without performing a photo-etch process on the MTJ structure.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: May 12, 2015
    Assignee: QUALCOMM Incorporated
    Inventor: Xia Li
  • Patent number: 9018047
    Abstract: A memory device includes an array of NAND strings of memory cells. The device includes a plurality of stacks of conductive strips separated by insulating material, including at least a bottom plane of conductive strips, a plurality of intermediate planes of conductive strips, and a top plane of conductive strips. The device includes charge storage structures in interface regions at cross-points between side surfaces of the conductive strips in the plurality of intermediate planes in the stacks and inter-stack semiconductor body elements of a plurality of bit line structures. At least one reference line structure is arranged orthogonally over the stacks, including vertical conductive elements between the stacks in electrical communication with a reference conductor between the bottom plane of conductive strips and a substrate, and linking elements over the stacks connecting the vertical conductive elements. The vertical conductive elements have a higher conductivity than the semiconductor body elements.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: April 28, 2015
    Assignee: Macronix International Co., Ltd.
    Inventor: Hang-Ting Lue
  • Patent number: 8975122
    Abstract: An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: March 10, 2015
    Assignee: Macronix International Co., Ltd.
    Inventor: Hsiang-Lan Lung
  • Patent number: 8969141
    Abstract: According to one exemplary embodiment, a programmable poly fuse includes a P type resistive poly segment forming a P-N junction with an adjacent N type resistive poly segment. The programmable poly fuse further includes a P side silicided poly line contiguous with the P type resistive poly segment and coupled to a P side terminal of the poly fuse. The programmable poly fuse further includes an N side silicided poly line contiguous with the N type resistive poly segment and coupled to an N side terminal of the poly fuse. During a normal operating mode, a voltage less than or equal to approximately 2.5 volts is applied to the N side terminal of the programmable poly fuse. A voltage higher than approximately 3.5 volts is required at the N side terminal of the poly fuse to break down the P-N junction.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 3, 2015
    Assignee: Broadcom Corporation
    Inventor: Laurentiu Vasiliu
  • Patent number: 8946000
    Abstract: A back-end-of-line thin ion beam deposited fuse (204) is deposited without etching to connect first and second last metal interconnect structures (110, 120) formed with last metal layers (LM) in a planar multi-layer interconnect stack to programmably connect separate first and second circuit connected to the first and second last metal interconnect structures.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: February 3, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Douglas M. Reber, Mehul D. Shroff, Edward O. Travis
  • Patent number: 8937357
    Abstract: According to one embodiment, a one-time programmable (OTP) semiconductor device includes a programming dielectric under a patterned electrode and over an implant region, where the programming dielectric forms a programming region of the OTP semiconductor device. The OTP semiconductor device further includes an isolation region laterally separating the programming dielectric from a coupled semiconductor structure, where the isolation region can be used in conjunction with the patterned electrode and the implant region to protect the coupled semiconductor structure. In one embodiment, the programming dielectric comprises a gate dielectric. In another embodiment, the electrode and implant regions are doped to be electrochemically similar.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: January 20, 2015
    Assignee: Broadcom Corporation
    Inventors: Frank Hui, Xiangdong Chen
  • Patent number: 8932912
    Abstract: According to one embodiment, a one-time programmable (OTP) device having a lateral diffused metal-oxide-semiconductor (LDMOS) structure comprises a pass gate including a pass gate electrode and a pass gate dielectric, and a programming gate including a programming gate electrode and a programming gate dielectric. The programming gate is spaced from the pass gate by a drain extension region of the LDMOS structure. The LDMOS structure provides protection for the pass gate when a programming voltage for rupturing the programming gate dielectric is applied to the programming gate electrode. A method for producing such an OTP device comprises forming a drain extension region, fabricating a pass gate over a first portion of the drain extension region, and fabricating a programming gate over a second portion of the drain extension region.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: January 13, 2015
    Assignee: Broadcom Corporation
    Inventors: Akira Ito, Xiangdong Chen
  • Patent number: 8916938
    Abstract: The present invention discloses a three-dimensional writable printed memory (3D-wP). It comprises at least a printed memory array and a writable memory array. The printed memory array stores contents data, which are recorded with a printing means; the writable memory array stores custom data, which are recorded with a writing means. The writing means is preferably direct-write lithography. To maintain manufacturing throughput, the total amount of custom data should be less than 1% of the total amount of content data.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: December 23, 2014
    Assignees: ChengDu HaiCun IP Technology LLC
    Inventor: Guobiao Zhang
  • Publication number: 20140346603
    Abstract: Transistor devices having an anti-fuse configuration and methods of forming the transistor devices are provided. An exemplary transistor device includes a semiconductor substrate including a first fin. A first insulator layer overlies the semiconductor substrate and has a thickness less than a height of the first fin. The first fin extends through and protrudes beyond the first insulator layer to provide a buried fin portion and an exposed fin portion. A gate electrode structure overlies the exposed fin portion. A gate insulating structure is disposed between the first fin and the gate electrode structure. The gate insulating structure includes a first dielectric layer overlying a first surface of the first fin. The gate insulating structure further includes a second dielectric layer overlying a second surface of the first fin. A potential breakdown path is defined between the first fin and the gate electrode structure through the first dielectric layer.
    Type: Application
    Filed: May 21, 2013
    Publication date: November 27, 2014
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Eng Huat Toh, Shyue Seng Tan, Elgin Quek
  • Patent number: 8890107
    Abstract: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: November 18, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Naoki Yamamoto, Hideyuki Matsuoka, Tomio Iwasaki
  • Patent number: 8889490
    Abstract: As for a memory element implemented in a semiconductor device typified by an RFID, it is an object of the present invention to reduce manufacturing steps and to provide a memory element and a memory circuit having the element with reduced cost. It is a feature of the present invention that a memory element sandwiched between electrodes has an organic compound, and an electrode connected to a semiconductor element controlling the memory element functions as an electrode of the memory element. In addition, an extremely thin semiconductor film formed on an insulated surface is used for the memory element; therefore cost can be reduced.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: November 18, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshinobu Asami
  • Patent number: 8883570
    Abstract: A method includes oxidizing a semiconductor fin to form an oxide layer on opposite sidewalls of the semiconductor fin. The semiconductor fin is over a top surface of an isolation region. After the oxidizing, a tilt implantation is performed to implant an impurity into the semiconductor fin. The oxide layer is removed after the tilt implantation.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Wen-Tai Lu
  • Patent number: 8884398
    Abstract: A method of programming an anti-fuse includes steps as follows. First, an insulating layer is provided. An anti-fuse region is defined on the insulating layer. An anti-fuse is embedded within the anti-fuse region of the insulating layer. The anti-fuse includes at least a first conductor and a second conductor. Then, part of the insulating layer is removed by a laser to form an anti-fuse opening in the insulating layer. Part of the first conductor and part of the second conductor are exposed through the anti-fuse opening. After that, a under bump metallurgy layer is formed in the anti-fuse opening to connect the first conductor and the second conductor electrically.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: November 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chu-Fu Lin, Chien-Li Kuo, Ching-Li Yang
  • Patent number: 8866120
    Abstract: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: October 21, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Naoki Yamamoto, Hideyuki Matsuoka, Tomio Iwasaki
  • Patent number: 8866256
    Abstract: In one general aspect, an apparatus can include a semiconductor substrate, and a first conductive fuse bus having a triangular-shaped portion with a bottom surface aligned along a plane substantially parallel to a surface of the semiconductor substrate. The apparatus can include a second conductive fuse bus having a bottom surface aligned along the plane, and a plurality of fuse links coupled between the triangular-shaped portion of the first conductive fuse bus and the second conductive fuse bus.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: October 21, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventor: William R. Newberry
  • Patent number: 8859344
    Abstract: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: October 14, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Naoki Yamamoto, Hideyuki Matsuoka, Tomio Iwasaki
  • Patent number: 8860176
    Abstract: The present disclosure relates to an antifuse for preventing a flow of electrical current in an integrated circuit. One such antifuse includes a reactive material and a silicon region thermally coupled to the reactive material, where an electrical current to the reactive material causes the reactive material to release heat which transitions the silicon region from a high resistance state to a low resistance state. Another such antifuse includes a reactive material, at least one metal and a silicon region adjacent to the at least one metal and thermally coupled to the reactive material, where an electrical current to the reactive material causes the reactive material to release heat which transitions the silicon region from a high resistance state to a low resistance state.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Gregory M. Fritz, Bahman Hekmatshoartabari, Ali Khakifirooz, Dirk Pfeiffer, Kenneth P. Rodbell, Davood Shahrjerdi
  • Patent number: 8853818
    Abstract: A memory device includes an array of NAND strings of memory cells. The device includes a plurality of stacks of conductive strips separated by insulating material, including at least a bottom plane of conductive strips, a plurality of intermediate planes of conductive strips, and a top plane of conductive strips. The device includes charge storage structures in interface regions at cross-points between side surfaces of the conductive strips in the plurality of intermediate planes in the stacks and inter-stack semiconductor body elements of a plurality of bit line structures. At least one reference line structure is arranged orthogonally over the stacks, including vertical conductive elements between the stacks in electrical communication with a reference conductor between the bottom plane of conductive strips and a substrate, and linking elements over the stacks connecting the vertical conductive elements. The vertical conductive elements have a higher conductivity than the semiconductor body elements.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: October 7, 2014
    Assignee: Macronix International Co., Ltd.
    Inventor: Hang-Ting Lue
  • Patent number: 8853547
    Abstract: A flexible printed circuit board, in particular for the spatial connection of electronic components, includes a carrier foil (1), several bonding surfaces (10) arranged on a solder side (4) of the carrier foil (1), and several soldering surfaces (2) arranged on a bonding side (12) of the carrier foil (1) opposite the solder side. The soldering surfaces (2) are connected to the bonding surfaces (10) via electrical strip conductors, and a stiffening plate (3) is inseparably connected to the carrier foil (1) on the solder side thereof.
    Type: Grant
    Filed: October 9, 2009
    Date of Patent: October 7, 2014
    Assignees: Conti Temic microelectronic GmbH, Carl Freudenberg KG
    Inventors: Andreas Voegerl, Tilo Liebl, Gerhard Bauer, Marion Gebhardt, Alexander Wenk, Matthias Wieczorek, Juergen Henniger, Karl-Heinz Baumann
  • Patent number: 8809734
    Abstract: A method and system for locally processing a predetermined microstructure formed on a substrate without causing undesirable changes in electrical or physical characteristics of the substrate or other structures formed on the substrate are provided. The method includes providing information based on a model of laser pulse interactions with the predetermined microstructure, the substrate and the other structures. At least one characteristic of at least one pulse is determined based on the information. A pulsed laser beam is generated including the at least one pulse. The method further includes irradiating the at least one pulse having the at least one determined characteristic into a spot on the predetermined microstructure. The at least one determined characteristic and other characteristics of the at least one pulse are sufficient to locally process the predetermined microstructure without causing the undesirable changes.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: August 19, 2014
    Assignee: Electron Scientific Industries, Inc.
    Inventors: James J. Cordingley, Jonathan S. Ehrmann, David M. Filgas, Shepard D. Johnson, Joohan Lee, Donald V. Smart, Donald J. Svetkoff
  • Patent number: 8809829
    Abstract: A memory device having a phase change material element with a modified stoichiometry in the active region does not exhibit drift in set state resistance. A method for manufacturing the memory device includes first manufacturing an integrated circuit including an array of phase change memory cells with bodies of phase change material having a bulk stoichiometry; and then applying forming current to the phase change memory cells in the array to change the bulk stoichiometry in active regions of the bodies of phase change material to the modified stoichiometry, without disturbing the bulk stoichiometry outside the active regions. The bulk stoichiometry is characterized by stability under the thermodynamic conditions outside the active region, while the modified stoichiometry is characterized by stability under the thermodynamic conditions inside the active region.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: August 19, 2014
    Assignee: Macronix International Co., Ltd.
    Inventor: Ming-Hsiu Lee
  • Patent number: 8802494
    Abstract: The method of fabricating a semiconductor device may include forming a semiconductor die on a substrate, forming an interposer including at least one integrated circuit connected to the semiconductor die on the substrate or on the semiconductor die, and performing encapsulation to surround the semiconductor die and the interposer.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: August 12, 2014
    Assignee: Amkor Technology Korea, Inc.
    Inventors: Choon Heung Lee, Ki Cheol Bae, Do Hyun Na
  • Patent number: 8785300
    Abstract: An approach is provided for semiconductor devices including an anti-fuse structure. The semiconductor device includes a first metallization layer including a first portion of a first electrode and a second electrode, the second electrode being formed in a substantially axial plane surrounding the first portion of the first electrode, with a dielectric material in between the two electrodes. An ILD is formed over the first metallization layer, a second metallization layer including a second portion of the first electrode is formed over the ILD, and at least one via is formed through the ILD, electrically connecting the first and second portions of the first electrode. Breakdown of the dielectric material is configured to enable an operating current to flow between the second electrode and the first electrode in a programmed state of the anti-fuse structure.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: July 22, 2014
    Assignee: GlobalFoundries Inc.
    Inventors: Andreas Kurz, Jens Poppe
  • Patent number: 8759143
    Abstract: Some embodiments include methods of forming semiconductor constructions. Carbon-containing material is formed over oxygen-sensitive material. The carbon-containing material and oxygen-sensitive material together form a structure having a sidewall that extends along both the carbon-containing material and the oxygen-sensitive material. First protective material is formed along the sidewall. The first protective material extends across an interface of the carbon-containing material and the oxygen-sensitive material, and does not extend to a top region of the carbon-containing material. Second protective material is formed across the top of the carbon-containing material, with the second protective material having a common composition to the first protective material. The second protective material is etched to expose an upper surface of the carbon-containing material. Some embodiments include semiconductor constructions, memory arrays and methods of forming memory arrays.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: June 24, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pelizzer, Cinzia Perrone
  • Patent number: 8753927
    Abstract: An anti-fuse structure is provided in which an anti-fuse material liner is embedded within one of the openings provided within an interconnect dielectric material. The anti-fuse material liner is located between a first conductive metal and a second conductive metal which are also present within the opening. A diffusion barrier liner separates the first conductive metal from any portion of the interconnect dielectric material. The anti-fuse structure is laterally adjacent an interconnect structure that is formed within the same interconnect dielectric material as the anti-fuse structure.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Stephen M. Gates
  • Patent number: 8748235
    Abstract: In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: June 10, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Allan T. Mitchell, Mark A. Eskew, Keith Jarreau
  • Patent number: 8741697
    Abstract: An electronic device can include a nonvolatile memory cell, wherein the nonvolatile memory cell can include a substrate, an access transistor, a read transistor, and an antifuse component. Each of the access and read transistors can include source/drain regions at least partly within the substrate, a gate dielectric layer overlying the substrate, and a gate electrode overlying the gate dielectric layer. An antifuse component can include a first electrode lying at least partly within the substrate, an antifuse dielectric layer overlying the substrate, and a second electrode overlying the antifuse dielectric layer. The second electrode of the antifuse component can be coupled to one of the source/drain regions of the access transistor and to the gate electrode of the read transistor. In an embodiment, the antifuse component can be in the form of a transistor structure. The electronic device can be formed using a single polysilicon process.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: June 3, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Moshe Agam, Thierry Coffi Herve Yao, Shizen Skip Liu
  • Patent number: 8742457
    Abstract: A device includes a substrate, isolation regions at a surface of the substrate, and a semiconductor region over a top surface of the isolation regions. A conductive feature is disposed over the top surface of the isolation regions, wherein the conductive feature is adjacent to the semiconductor region. A dielectric material is disposed between the conductive feature and the semiconductor region. The dielectric material, the conductive feature, and the semiconductor region form an anti-fuse.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: June 3, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsiao-Lan Yang
  • Patent number: 8736020
    Abstract: An electronic anti-fuse structure, the structure including an Mx level comprising a first Mx metal and a second Mx metal, a dielectric layer located above the Mx level, an Mx+1 level located above the dielectric layer; and a metallic element in the dielectric layer and positioned between the first Mx metal and the second Mx metal, wherein the metallic element is insulated from both the first Mx metal and the second Mx metal.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: May 27, 2014
    Assignee: International Business Machines Corporation
    Inventors: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Naftali Eliahu Lustig, Andrew H. Simon
  • Patent number: 8722518
    Abstract: A method is provided for forming a monolithic three dimensional memory array. The method includes forming a first memory level above a substrate, and monolithically forming a second memory level above the first memory level. The first memory level is formed by forming first substantially parallel conductors extending in a first direction, forming first pillars above the first conductors, each first pillar including a first conductive layer or layerstack above a vertically oriented diode, the first pillars formed in a single photolithography step, depositing a first dielectric layer above the first pillars, etching first trenches in the first dielectric layer, the first trenches extending in a second direction. After etching, a lowest point in the trenches is above a lowest point of the first conductive layer or layerstack, and the first conductive layer or layerstack does not include a resistivity-switching metal oxide or nitride. Numerous other aspects are provided.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: May 13, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Steven J. Radigan, Usha Raghuram, Samuel V. Dunton, Michael W. Konevecki
  • Publication number: 20140120665
    Abstract: An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics.
    Type: Application
    Filed: January 6, 2014
    Publication date: May 1, 2014
    Inventor: HSIANG-LAN LUNG
  • Patent number: 8710591
    Abstract: Provided are a semiconductor chip including a TSV passing through a transistor, and a stack module and a memory card using such a semiconductor chip. The semiconductor chip may include a semiconductor layer that has a first surface and a second surface opposite to each other. A conductive layer may be disposed on the first surface of the semiconductor layer. A TSV may pass through the semiconductor layer and the conductive layer. A side wall insulating layer may surround a side wall of the TSV in order to electrically insulate the semiconductor layer and the conductive layer from the TSV.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: April 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyong-ryol Hwang, Ho-cheol Lee, Byong-wook Na
  • Patent number: 8686394
    Abstract: Some embodiments include methods of forming semiconductor constructions. Carbon-containing material is formed over oxygen-sensitive material. The carbon-containing material and oxygen-sensitive material together form a structure having a sidewall that extends along both the carbon-containing material and the oxygen-sensitive material. First protective material is formed along the sidewall. The first protective material extends across an interface of the carbon-containing material and the oxygen-sensitive material, and does not extend to a top region of the carbon-containing material. Second protective material is formed across the top of the carbon-containing material, with the second protective material having a common composition to the first protective material. The second protective material is etched to expose an upper surface of the carbon-containing material. Some embodiments include semiconductor constructions, memory arrays and methods of forming memory arrays.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: April 1, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Cinzia Perrone
  • Patent number: 8674476
    Abstract: Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Toshiharu Furukawa, William R. Tonti
  • Patent number: RE45840
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. A through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in an interior of the through-hole. The charge storage film is provided between the electrode film and the semiconductor pillar. The drive circuit supplies a potential to the electrode film. The diameter of the through-hole differs by a position in the stacking direction. The drive circuit supplies a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: January 12, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ryota Katsumata, Hideaki Aochi, Hiroyasu Tanaka, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota