Making Device Array And Selectively Interconnecting Patents (Class 438/128)
  • Patent number: 11621267
    Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: April 4, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Kuan Lin, Chang-Ta Yang, Ping-Wei Wang, Kuo-Yi Chao, Mei-Yun Wang
  • Patent number: 11461521
    Abstract: An integrated circuit including a standard cell includes: a plurality of first wells extending in a first horizontal direction with a first width and of a first conductivity type; and a plurality of second wells extending in the first horizontal direction with a second width and having a second conductivity type, wherein the plurality of first wells and the plurality of second wells are alternately arranged in a second horizontal direction that is orthogonal to the first horizontal direction, and when m and n are integers greater than or equal to 3, the standard cell has a length in the second horizontal direction, the length being equal to a sum of m times a half of the first width and n times a half of the second width.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: October 4, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Raheel Azmat, Sidharth Rastogi, Chul-Hong Park, Jae-Seok Yang, Kwan-Young Chun
  • Patent number: 11437317
    Abstract: Integrated chips and methods of forming lines in the same include forming first lines on a underlying substrate. Conformal dielectric spacers are formed on sidewalls of the first lines. Second lines are formed on the underlying substrate, in open areas between the dielectric spacers.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: September 6, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent Alan Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo, Robert Robison
  • Patent number: 11315916
    Abstract: A method of assembling a microelectronic package includes the step of: stacking a processing device vertically with at least one memory device and electrically connecting the processing device to a plurality of conductive interconnects of one of the at least one memory device, wherein each of the at least one memory device includes: a substrate, presenting a front surface and a back surface; and a plurality of memory units formed on the front surface, each of which comprises a plurality of memory cells and the conductive interconnects electrically connected to the memory cells; and arranging the conductive interconnects to contribute to a plurality of signal channels each of which dedicated to transmit signals from the processing device to one of the memory units and vice versa.
    Type: Grant
    Filed: September 13, 2020
    Date of Patent: April 26, 2022
    Assignee: AP Memory Technology Corp.
    Inventors: Wenliang Chen, Lin Ma, Alessandro Minzoni
  • Patent number: 11302679
    Abstract: A micro-LED display panel including a substrate, an anisotropic conductive film, and a plurality of micro-LEDs is provided. The anisotropic conductive film is disposed on the substrate. The micro-LEDs and the anisotropic conductive film are disposed at the same side of the substrate, and the micro-LEDs are electrically connected to the substrate through the anisotropic conductive film. Each of the micro-LEDs includes an epitaxial layer and an electrode layer electrically connected to the epitaxial layer, and the electrode layers comprises a first electrode and a second electrode which are located between the substrate and the corresponding epitaxial layer. A ratio of a thickness of each of the electrode layers to a thickness of the corresponding epitaxial layer ranges from 0.1 to 0.5, and a gap between the first electrode and the second electrode of each of the micro-LEDs is in a range of 1 ?m to 30 ?m.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: April 12, 2022
    Assignee: PlayNitride Inc.
    Inventors: Ying-Tsang Liu, Yu-Chu Li, Pei-Hsin Chen, Yi-Ching Chen
  • Patent number: 11276787
    Abstract: A semiconductor device for light detection comprises: a photodiode comprising an optical active region; and a resistor connected to said photodiode and overlapping at least a part of said optical active region, wherein the resistor comprising an anti-reflective coating for reducing reflection loss.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: March 15, 2022
    Assignee: X-FAB Semiconductor Foundries GmbH
    Inventor: Daniel Gäbler
  • Patent number: 11270917
    Abstract: The present disclosure relates to a system and a method for fabricating one or more integrated circuits (ICs). The system includes a plurality of logic tiles formed on a logic wafer and separated by at least one first scribe line, a respective logic tile including a function unit including circuitry configured to perform a respective function; at least one global interconnect configured to communicatively connect the plurality of logic tiles; a plurality of memory tiles formed on a memory wafer connected with the logic wafer, the plurality of memory tiles separated by at least one second scribe line that is substantially aligned with the at least one first scribe line, wherein the logic wafer and the memory wafer are diced along the at least one first scribe line and the at least one second scribe line to obtain a plurality of ICs, a respective IC including at least one logic tile connected with at least one memory tile.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: March 8, 2022
    Assignee: ALIBABA GROUP HOLDING LIMITED
    Inventor: Wei Han
  • Patent number: 11101292
    Abstract: A semiconductor integrated circuit device including a plurality of rows of IO cells has a configuration capable of avoiding a latchup error without causing an increase in area. The device includes a first IO cell row placed closest to an edge of a chip and a second IO cell row placed adjacent to a core region side of the first IO cell row. Each of the IO cells of the first and second IO cell rows has a high power supply voltage region and a low power supply voltage region provided separately in a direction perpendicular to a direction in which the IO cells are lined up. The IO cell rows are placed so that the high power supply voltage regions of these rows are mutually opposed.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: August 24, 2021
    Assignee: SOCIONEXT INC.
    Inventor: Isaya Sobue
  • Patent number: 10957786
    Abstract: A method of manufacturing a field effect transistor includes forming a fin on a substrate, forming source and drain electrodes on opposite sides of the fin, forming a gate stack on a channel portion of the fin between the source and drain electrodes, forming gate spacers on extension portions of the fin on opposite sides of the gate stack, removing at least portions of the gate spacers to expose the extension portions of the fin, and hydrogen annealing the extension portions of the fin. Following the hydrogen annealing of the extension portions of the fin, the channel portion of the fin has a first width and the extension portions of the fin have a second width greater than the first width.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: March 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon Goo Hong, Borna J. Obradovic, Mark Stephen Rodder
  • Patent number: 10923205
    Abstract: A method of forming a memory device having magnetic tracks individually comprising a plurality of magnetic domains having domain walls, includes forming an elevationally outer substrate material of uniform chemical composition. The uniform composition material is partially etched into to form alternating regions of elevational depressions and elevational protrusions in the uniform composition material. A plurality of magnetic tracks is formed over and which angle relative to the alternating regions. Interfaces of immediately adjacent of the regions individually form a domain wall pinning site in individual of the magnetic tracks. Other methods, including memory devices independent of method, are disclosed.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: February 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Livio Baldi, Marcello Mariani
  • Patent number: 10916568
    Abstract: A manufacturing method of a display substrate, an array substrate and a display device are provided. The method includes forming a first wire, a first insulation layer, a first and second metal layer, and a photoresist layer; forming a photoresist retained pattern above the first wire; forming a second and first metal layer retained pattern under the photoresist retained pattern; forming a second insulation layer with a thickness less than or equal to a sum of thicknesses of the first and second metal layer; the second insulation layer forming a fracture region at a boundary between a part covering the first insulation layer and another part covering the second metal layer retained pattern; removing the first and second metal layer retained patterns by a wet etch process to expose the first insulation layer; and forming a contact hole exposing the first wire.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: February 9, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jun Liu, Ming Wang, Jun Wang, Bin Zhou
  • Patent number: 10887988
    Abstract: A method of manufacturing a circuit substrate including forming, in an insulating substrate and circuit patterns that are provided on a first surface and a second surface of the insulating substrate, a through-hole penetrating the insulating substrate and the circuit patterns, where the circuit patterns contain Cu as a main component. The method including filling, in the through-hole, an electrically conductive paste that is a melting-point shift electrically conductive paste including Sn—Bi solder powder, Cu powder, and resin, and forming a protrusion obtained by causing the electrically conductive paste to protrude from the through-hole. The method further including performing pressure treatment on the protrusion near the through-hole; and performing heat treatment on the insulating substrate whose protrusion is subjected to the pressure treatment and causing the circuit patterns and the electrically conductive paste to be electrically connected with each other.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: January 5, 2021
    Assignee: NICHIA CORPORATION
    Inventors: Masaaki Katsumata, Koji Taguchi, Norifumi Sasaoka, Yosuke Noda
  • Patent number: 10847620
    Abstract: A semiconductor device comprises a semiconductor chip and a mounting substrate. The semiconductor chip has an element structure including: a silicon carbide substrate that has a hexagonal crystal structure; a gate electrode that is disposed on a part above a first surface corresponding to a (0001) plane or a (000-1) plane of the silicon carbide substrate; an insulating film that is interposed between the silicon carbide substrate and the gate electrode; and a source and a drain that are disposed with respect to the silicon carbide substrate and the gate electrode such that at least a part of a channel through which a carrier moves extends in a <1-100> direction of crystal orientation of the silicon carbide substrate. The mounting substrate is fixed with the semiconductor chip such that compressive stress in a <11-20> direction of crystal orientation of the silicon carbide substrate is applied to the semiconductor chip at least in operation.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: November 24, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Goryu, Mitsuaki Kato, Kenji Hirohata
  • Patent number: 10832933
    Abstract: A method of placing light emitting diodes (LEDs) includes embedding an array of LEDs in a polymer layer on a substrate. The method includes detaching at least one LED in the array of LEDs from the substrate by dry-etching the polymer layer in which at least one LED is embedded. A pick-up-tool (PUT) is brought into contact with at least one surface of at least one LED facing away from the substrate, responsive to dry-etching the polymer layer. The PUT is lifted with the at least one LED attached to the PUT.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: November 10, 2020
    Assignee: Facebook Technologies, LLC
    Inventors: Daniel Brodoceanu, Oscar Torrents Abad
  • Patent number: 10755996
    Abstract: A through electrode substrate includes: a substrate; a first electrode part provided on a first surface side of the substrate; and a second electrode part provided on a second surface side of the substrate. The plurality of holes includes a plurality of first holes and a plurality of second holes. The hole electrode part of each first hole is electrically connected to the first electrode part on the first surface side of the substrate, and the hole electrode part thereof is electrically connected to the second electrode part on the second surface side of the substrate. The electrode part of each second hole is electrically insulated from the first electrode part on the first surface side of the substrate, or the hole electrode part thereof is electrically insulated from the second electrode part on the second surface side of the substrate.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: August 25, 2020
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventors: Shinji Maekawa, Hiroshi Mawatari
  • Patent number: 10746788
    Abstract: A sensing structure is presented for use in testing integrated circuits on a substrate. The sensing structure includes a probe region corresponding to a conductive region for connecting to the integrated circuit. A first sensing region at least partially surrounds the probe region. A plurality of sensing elements connects in series such that a first of the plurality of sensing elements has two terminals respectively connected to the first sensing region and the probe region. And a second of the plurality of sensing elements has two terminals respectively connected to the probe region and a first reference potential.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: August 18, 2020
    Assignee: STMicroelectronics S.r.l.
    Inventor: Alberto Pagani
  • Patent number: 10714567
    Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A sacrificial layer is epitaxially grown on a bulk semiconductor substrate, a plurality of epitaxial semiconductor layers are epitaxially grown over the sacrificial layer, and the sacrificial layer and the plurality of epitaxial semiconductor layers are patterned to form a fin. A first portion of the first sacrificial layer is removed to form a first cavity arranged between the plurality of epitaxial semiconductor layers and the bulk semiconductor substrate, and a first dielectric material is deposited in the first cavity. A second portion of the first sacrificial layer, which is located adjacent to the first dielectric material in the first cavity, is removed to form a second cavity between the first fin and the bulk semiconductor substrate. A second dielectric material is deposited in the second cavity.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: July 14, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Julien Frougier, Ruilong Xie
  • Patent number: 10638615
    Abstract: The present invention relates to an improved system and method for manufacturing flexible circuit boards (FSBs) using optical alignment and various bonding systems. The invention provides an improved process to connect together the layers of rigid-flex, flexible, and printed circuit boards while maintaining alignment of the layers prior to and possibly after a lamination step. An optical alignment system is provided, a preferred arrangement is enabled as an automated pinless bonding system (PBS), for securely gripping, aligning, transferring, and clamping, bonding and moving a bonded FSB employing a multi-axis orientation. An alternative manual optical alignment and bonding system is provided.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: April 28, 2020
    Assignee: DUETTO INTEGRATED SYSTEMS, INC.
    Inventors: Anthony Faraci, Gary N. Sortino
  • Patent number: 10504901
    Abstract: A substrate processing method includes stacking a plurality of stack structures each including an insulating layer and a sacrificial layer, on one another. The method also includes generating a stair structure by etching the stack structures and generating a separation layer on a side surface of the stair structure. The method further includes removing the sacrificial layer and generating conductive word line structures in spaces from which the sacrificial layer is removed. The separation layer is provided between the conductive word line structures.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: December 10, 2019
    Assignee: ASM IP HOLDING B.V.
    Inventors: Tae Hee Yoo, Yoon Ki Min, Yong Min Yoo
  • Patent number: 10483255
    Abstract: A semiconductor device includes a first circuit, a second circuit, a first power supply line, a second power supply line coupled to the first circuit, a third power supply line, a fourth power supply line coupled to the second circuit, a first switch circuit including a first switch transistor and a well tap, the first switch transistor including one source or drain end coupled to the first power supply line and another source or drain end coupled to the second power supply line, the well tap being electrically coupled to the second power supply line, and a second switch circuit including a second switch transistor including one source or drain end coupled to the third power supply line and another source or drain end coupled to the fourth power supply line, the second switch circuit including no well tap electrically coupled to the fourth power supply line.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: November 19, 2019
    Assignee: SOCIONEXT INC.
    Inventors: Hirotaka Takeno, Atsushi Okamoto
  • Patent number: 10439064
    Abstract: A first S/D region includes a first P-type region, a first N-type region, and a first conductive layer thereon to define a first cell node. A second S/D region includes a second P-type region, a second N-type region, and a second conductive layer thereon to define a second cell node. A PDL transistor and PGLA, PGLB transistors have bottom SD regions in the first N-type region. A PUL transistor has a bottom SD region positioned in the first P-type region. A PDR transistor and PGRA, PGRB have bottom SD regions in the second N-type region. A PUR transistor has a bottom SD region in the second P-type region. A first gate is positioned around channel regions of the PUL and PDL transistors and conductively coupled to the second node. A second gate is positioned around channel regions of the PUR and PDR transistors and conductively coupled to the first node.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: October 8, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Randy W. Mann, Bipul C. Paul
  • Patent number: 10424374
    Abstract: Methods, systems, and devices for programming enhancement in memory cells are described. An asymmetrically shaped memory cell may enhance ion crowding at or near a particular electrode, which may be leveraged for accurately reading a stored value of the memory cell. Programming the memory cell may cause elements within the cell to separate, resulting in ion migration towards a particular electrode. The migration may depend on the polarity of the cell and may create a high resistivity region and low resistivity region within the cell. The memory cell may be sensed by applying a voltage across the cell. The resulting current may then encounter the high resistivity region and low resistivity region, and the orientation of the regions may be representative of a first or a second logic state of the cell.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: September 24, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Redaelli, Agostino Pirovano, Innocenzo Tortorelli, Fabio Pellizzer
  • Patent number: 10373943
    Abstract: A semiconductor device includes a first circuit, a second circuit, a first power supply line, a second power supply line coupled to the first circuit, a third power supply line, a fourth power supply line coupled to the second circuit, a first switch circuit including a first switch transistor and a well tap, the first switch transistor including one source or drain end coupled to the first power supply line and another source or drain end coupled to the second power supply line, the well tap being electrically coupled to the second power supply line, and a second switch circuit including a second switch transistor including one source or drain end coupled to the third power supply line and another source or drain end coupled to the fourth power supply line, the second switch circuit including no well tap electrically coupled to the fourth power supply line.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: August 6, 2019
    Assignee: SOCIONEXT INC.
    Inventors: Hirotaka Takeno, Atsushi Okamoto
  • Patent number: 10340179
    Abstract: A method of forming an interconnect element includes forming a trench in a dielectric material. The trench has a width equal to twice a natural pitch of a block copolymer. The block copolymer includes a first polymer and a second polymer. The method includes filling the trench with the block copolymer.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: July 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng Chi, Kafai Lai, Chi-Chun Liu, Yongan Xu
  • Patent number: 10217729
    Abstract: Embodiments of the invention include systems and methods for transferring micro LEDs. In an embodiment, the system for transferring micro LEDs, may include a donor substrate bank that is capable of supporting a plurality of donor substrates on which a plurality of micro LEDs are formed. In an embodiment, the donor substrate bank is moveable in the X, Y, and Z directions. In an embodiment, the system may also include a host substrate table that is capable of supporting a host substrate. The host substrate may include a plurality of segments. In an embodiment, the host substrate table is moveable in the X, Y, and Z directions. Embodiments of the invention may also include an array of macro transfer heads. In an embodiment, each macro transfer head may include a plurality of micro transfer heads.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: February 26, 2019
    Assignee: Intel Corporation
    Inventors: Khaled Ahmed, Kunjal ShyamKumar Parikh, Peter Chang
  • Patent number: 10199373
    Abstract: A cascode switch structure includes a group III-V transistor structure having a first current carrying electrode, a second current carrying electrode and a first control electrode. A semiconductor MOSFET device includes a third current carrying electrode electrically connected to the first current carrying electrode, a fourth current carrying electrode electrically connected to the first control electrode, and a second control electrode. A first diode includes a first cathode electrode electrically connected to the second current carrying electrode and a first anode electrode. A second diode includes a second anode electrode electrically connected to the first anode electrode and a second cathode electrode electrically connected to the fourth current carrying electrode. In one embodiment, the group III-V transistor structure, the first diode, and the second diode are integrated within a common substrate.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: February 5, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Balaji Padmanabhan, Prasad Venkatraman, Zia Hossain, Chun-Li Liu, Jason McDonald, Ali Salih, Alexander Young
  • Patent number: 10147497
    Abstract: A method of forming a memory device having magnetic tracks individually comprising a plurality of magnetic domains having domain walls, includes forming an elevationally outer substrate material of uniform chemical composition. The uniform composition material is partially etched into to form alternating regions of elevational depressions and elevational protrusions in the uniform composition material. A plurality of magnetic tracks is formed over and which angle relative to the alternating regions. Interfaces of immediately adjacent of the regions individually form a domain wall pinning site in individual of the magnetic tracks. Other methods, including memory devices independent of method, are disclosed.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: December 4, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Livio Baldi, Marcello Mariani
  • Patent number: 9865503
    Abstract: Aspects of the disclosure provide a method for semiconductor wafer manufacturing. The method includes utilizing a subset of lower level masks in a mask set to form multiple modular units of lower level circuit structures on a semiconductor wafer. The mask set includes the subset of lower level masks and at least a first subset of upper level masks and a second subset of upper level masks. The first subset of upper level masks defines intra-unit interconnections. The second subset of upper level masks defines both intra-unit interconnections and inter-unit interconnections. The method further includes selecting one of at least the first subset of upper level masks and the second subset of upper level masks based on a composition request of a final integrated circuit (IC) product and utilizing the selected subset of upper level masks to form upper level structures on the semiconductor wafer.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: January 9, 2018
    Assignee: MARVELL ISRAEL (M.I.S.L) LTD.
    Inventors: Eran Rotem, Rami Zemach, Itay Peled
  • Patent number: 9847285
    Abstract: There may be provided a method of manufacturing a semiconductor package. The method may include disposing a first semiconductor device and through mold ball connectors (TMBCs) on a first surface of an interconnection structure layer, forming a molding layer on the first surface of the interconnection structure layer to expose a portion of each of the TMBCs, attaching outer connectors to the exposed portions of the TMBCs, mounting a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer, and attaching a heat spreader to the second surface of the interconnection structure layer to overlap with a portion of the first semiconductor device.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: December 19, 2017
    Assignee: SK hynix Inc.
    Inventors: Ki Jun Sung, Jong Hoon Kim, Han Jun Bae
  • Patent number: 9793400
    Abstract: A semiconductor device includes a semiconductor substrate having a channel region interposed between a first active region and a second active region, and a gate structure formed on the channel region. A first dual-layer source/drain region is on the first active region and a second dual-layer source/drain region is on the second active region. The first and second dual-layer source/drain regions include stacked layers formed of different semiconductor materials. A first extension region is embedded in the first active region and a second extension region is embedded in the second active region.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: October 17, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Robert H. Dennard, Zhen Zhang
  • Patent number: 9773754
    Abstract: A three-dimensional integrated circuit including a first layer and a second layer electrically coupled to the first layer and disposed in a stacked relationship relative to the first layer. Logic circuitry is embodied in the first layer and input output circuitry of an input output circuit is embodied in the second layer.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: September 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chin-Ming Fu
  • Patent number: 9754947
    Abstract: A method for fabricating a static random access memory is provided. The method includes providing a semiconductor substrate. The method also includes forming a plurality of transistors on the semiconductor substrate. Further, the method includes forming a first metal layer having a word line electrically connecting with a partial number of the transistors. Further, the method also includes forming a second metal layer having a first bit line, a second bit line, a first power source line and second power source lines electrically connect with a partial number of the transistors.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: September 5, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Gong Zhang
  • Patent number: 9698263
    Abstract: A semiconductor structure that includes crystalline surfaces and amorphous hydrophilic surfaces is provided. The hydrophilic surfaces are treated with silane that includes a hydrophobic functional group, converting the hydrophilic surfaces to hydrophobic surfaces. Chemical vapor deposition or other suitable deposition methods are used to simultaneously deposit a material on both surfaces and due to the surface treatment, the deposited material exhibits superior adherence qualities on both surfaces. In one embodiment, the structure is an opening formed in a semiconductor substrate and bounded by at least one portion of a crystalline silicon surface and at least one portion of an amorphous silicon oxide structure.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lai-Wan Chong, Wen-Chu Hsiao, Ying-Min Chou, Hsiang-Hsiang Ko
  • Patent number: 9659819
    Abstract: A method of forming a memory device includes providing a substrate having a surface region, defining a cell region and first and second peripheral regions, sequentially forming a first dielectric material, a first wiring structure for a first array of devices, and a second dielectric material over the surface region, forming an opening region in the first peripheral region, the opening region extending in a portion of at least the first and second dielectric materials to expose portions of the first wiring structure and the substrate, forming a second wiring material that is overlying the second dielectric material and fills the opening region to form a vertical interconnect structure in the first peripheral region, and forming a second wiring structure from the second wiring material for a second array of devices, the first and second wiring structures being separated from each other and electrically connected by the vertical interconnect structure.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: May 23, 2017
    Assignee: CROSSBAR, INC.
    Inventor: Scott Brad Herner
  • Patent number: 9653680
    Abstract: The present disclosure provides a system and method for forming a resistive random access memory (RRAM) device. A RRAM device consistent with the present disclosure includes a substrate and a first electrode disposed thereon. The RRAM device includes a second electrode disposed over the first electrode and a RRAM dielectric layer disposed between the first electrode and the second electrode. The RRAM dielectric layer has a recess at a top center portion at the interface between the second electrode and the RRAM dielectric layer.
    Type: Grant
    Filed: June 27, 2015
    Date of Patent: May 16, 2017
    Assignee: INTEL CORPORATION
    Inventors: Ravi Pillarisetty, Prashant Majhi, Uday Shah, Niloy Mukherjee, Elijah V. Karpov, Brian S. Doyle, Robert S. Chau
  • Patent number: 9653445
    Abstract: A method of making a semiconductor device comprises the steps of providing a first manufacturing line, providing a second manufacturing line, and forming a first redistribution interconnect structure using the first manufacturing line while simultaneously forming a second redistribution interconnect structure using the second manufacturing line. The method further includes the steps of testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU), disposing a known good semiconductor die (KGD) over the first KGU of the first redistribution interconnect structure, testing a unit of the second redistribution interconnect structure to determine a second known good unit (KGU, and disposing the second KGU of the second redistribution interconnect structure over the first KGU of the first redistribution interconnect structure and the KGD. A resolution of the second manufacturing line is greater than a resolution of the first manufacturing line.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: May 16, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Yaojian Lin
  • Patent number: 9640493
    Abstract: An integrated circuit includes a substrate with several functional blocks formed thereon. At least two identical functional blocks are respectively disposed at two or more different locations on the integrated circuit. Electrically inactive dummy modules in the neighborhoods and/or inside of the functional blocks are provided, wherein at least two different electrically inactive dummy modules are includes in the respective neighborhoods and/or inside of the at least two identical functional blocks.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: May 2, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Pascal Fornara, Christian Rivero, Guilhem Bouton
  • Patent number: 9406789
    Abstract: A nanoscale variable resistor including a metal nanowire as an active element, a dielectric, and a gate. By selective application of a gate voltage, stochastic transitions between different conducting states, and even length, of the nanowire can be induced and with a switching time as fast as picoseconds. With an appropriate choice of dielectric, the transconductance of the device, which may also be considered an “electromechanical transistor,” is shown to significantly exceed the conductance quantum G0=2e2/h.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: August 2, 2016
    Assignees: NEW YORK UNIVERSITY, THE ARIZONA BOARD OF REGENTS ON BEHALF OF THE UNIVERSITY OF ARIZONA
    Inventors: Jerome Alexandre Bürki, Charles Allen Stafford, Daniel L. Stein
  • Patent number: 9401365
    Abstract: A process of forming an integrated circuit containing a first transistor and a second transistor of the same polarity, by forming an epitaxial spacer layer over gates of both transistors, performing an epitaxial spacer anisotropic etch process to form epitaxial spacers on vertical surfaces adjacent to the first transistor gate and removing the epitaxial spacer layer from the second transistor gate, subsequently performing a source/drain etch process and a source/drain epitaxial process to form source/drain epitaxial regions in the substrate adjacent to the first and second gates, such that the first source/drain epitaxial regions are separated from the first gate by a lateral space which is at least 2 nanometers larger than a second lateral space separating the second source/drain epitaxial regions from the second gate. An integrated circuit formed by the recited process.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: July 26, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Manoj Mehrotra
  • Patent number: 9379123
    Abstract: Provided are a semiconductor memory device and a method of fabricating the same. the semiconductor memory device may include a semiconductor substrate with a first trench defining active regions in a first region and a second trench provided in a second region around the first region, a gate electrode provided on the first region to cross the active regions, a charge storing pattern disposed between the gate electrode and the active regions, a blocking insulating layer provided between the gate electrode and the charge storing pattern and extending over the first trench to define a first air gap in the first trench, and an insulating pattern provided spaced apart from a bottom surface of the second trench to define a second air gap in the second trench.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: June 28, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hwang Sim, Jinhyun Shin, Jong-Min Lee
  • Patent number: 9318486
    Abstract: A semiconductor integrated circuit device may include a standard cell region on a surface of a substrate and a first active region on the surface of the substrate in the standard cell region, wherein the first active region has a length in a first direction. A second active region may be on the surface of the substrate in the standard cell region, the second active region may have a length in the first direction, the length of the second active region may be greater than the length of the first active region, and an axis in a second direction may intersect centers of the first and second active regions so that the first and second active regions are symmetric about the axis in the second direction. A first gate electrode may extend across the first active region in the first direction, and a second gate electrode may extend across the second active region in the first direction.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: April 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-Seok Shim, Young-Chang Kim, Dong-Geon Kim
  • Patent number: 9305844
    Abstract: Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and WSiX material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. The WSiX material is adjacent to the substrate, and can be used as an etch-landing layer and a conductive contact to contact both the first poly-silicon channel and the second poly-silicon channel in the opening. Other embodiments include methods of making semiconductor devices.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: April 5, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Hongbin Zhu, Gordon Haller, Paul D. Long
  • Patent number: 9276050
    Abstract: Disclosed herein is an OLED (Organic Light Emitting Display) device. A switching thin-film transistor configured to be an oxide semiconductor thin-film transistor is disposed in a first pixel. A second pixel is adjacent to the first pixel in the direction in which data lines are extended. A switching thin-film transistor configured to be an LTPS (Low Temperature Poly-Silicon) thin-film transistor is disposed in the second pixel. The switching thin-film transistor of the first pixel and the switching thin-film transistor of the second pixel are connected to the same gate line. A pixel and another pixel adjacent to the pixel connected to a gate line in common, so that it is possible to provide an OLED device with high aperture ratio and high resolution.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: March 1, 2016
    Assignee: LG Display Co., Ltd.
    Inventors: Hoi Yong Kwon, Joon Suk Lee, Eui Tae Kim, Sung Hee Park, Ki Seob Shin
  • Patent number: 9231052
    Abstract: A transistor using a single crystal silicon nanowire and a method for fabricating the transistor is disclosed. The transistor using a single crystal silicon nanowire comprises a substrate and a single crystal silicon nanowire formed on the substrate. Here, the single crystal silicon nanowire comprises a source region and a drain region formed longitudinally with the single crystal silicon nanowire and separate from each other, and a channel region located between the source region and the drain region, wherein the perpendicular thickness of the channel region to the longitudinal direction is thinner than the thickness of the source region and the drain region.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: January 5, 2016
    Assignee: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
    Inventors: Sangsig Kim, Myeong-Won Lee, Youngin Jeon
  • Patent number: 9231197
    Abstract: A memory cell and method including a first electrode conformally formed through a first opening in a first dielectric layer, a resistive layer conformally formed on the first electrode, a spacing layer conformally formed on the resistive layer, a second electrode conformally formed on the resistive layer, and a second dielectric layer conformally formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer is formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao, Chih-Yang Chang, Hsia-Wei Chen, Chin-Chieh Yang
  • Patent number: 9183933
    Abstract: Cell layouts for a memory cell, such as for ternary content addressable memory (TCAM), are disclosed. Some cell layouts include a well strap structure. A cell layout may include a p-doped well, an n-doped well, and a p-doped well sequentially along a layout. Another cell layout may include a p-doped well, an n-doped well, a p-doped well, and an n-doped well sequentially along a layout. A well strap structure may be in a p-doped well or an n-doped well. Various metallization layers having a mesh may be used with a memory cell layout. In some disclosed examples, a first metallization layer may have one, two, or four ground traces, and a second metallization layer may have two ground traces. These various ground traces may be electrically coupled together to form a mesh.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: November 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 9117707
    Abstract: The array substrate includes a plurality of gate lines and a plurality of data lines which intersect each other to define a plurality of pixel regions, each of the pixel regions includes a thin film transistor and further includes: a base substrate; more than one protrusion disposed apart from each other on the base substrate; a first electrode layer including at least one first electrode strip disposed in a gap between adjacent protrusions; a second electrode layer including at least one second electrode strip disposed on the protrusions.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: August 25, 2015
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Seungjin Choi, Heecheol Kim, Youngsuk Song, Seongyeol Yoo
  • Patent number: 9076879
    Abstract: A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: July 7, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dongchul Yoo, Phil Ouk Nam, Junkyu Yang, Woong Lee, Woosung Lee, JinGyun Kim, Daehong Eom
  • Publication number: 20150129935
    Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures.
    Type: Application
    Filed: January 22, 2015
    Publication date: May 14, 2015
    Inventors: Sanh D. Tang, Roger W. Lindsay, Krishna K. Parat
  • Patent number: 9024374
    Abstract: A 3D memory device includes a plurality of ridges, in some embodiments ridge-shaped, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor material strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. In some embodiments, the 3D memory is made using only two critical masks for multiple layers. Some embodiments include a staircase-shaped structure positioned at ends of the semiconductor material strips.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: May 5, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Chun Hsiung Hung, Hang-Ting Lue, Shin-Jang Shen