Making Device Array And Selectively Interconnecting Patents (Class 438/128)
  • Patent number: 10340179
    Abstract: A method of forming an interconnect element includes forming a trench in a dielectric material. The trench has a width equal to twice a natural pitch of a block copolymer. The block copolymer includes a first polymer and a second polymer. The method includes filling the trench with the block copolymer.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: July 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng Chi, Kafai Lai, Chi-Chun Liu, Yongan Xu
  • Patent number: 10217729
    Abstract: Embodiments of the invention include systems and methods for transferring micro LEDs. In an embodiment, the system for transferring micro LEDs, may include a donor substrate bank that is capable of supporting a plurality of donor substrates on which a plurality of micro LEDs are formed. In an embodiment, the donor substrate bank is moveable in the X, Y, and Z directions. In an embodiment, the system may also include a host substrate table that is capable of supporting a host substrate. The host substrate may include a plurality of segments. In an embodiment, the host substrate table is moveable in the X, Y, and Z directions. Embodiments of the invention may also include an array of macro transfer heads. In an embodiment, each macro transfer head may include a plurality of micro transfer heads.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: February 26, 2019
    Assignee: Intel Corporation
    Inventors: Khaled Ahmed, Kunjal ShyamKumar Parikh, Peter Chang
  • Patent number: 10199373
    Abstract: A cascode switch structure includes a group III-V transistor structure having a first current carrying electrode, a second current carrying electrode and a first control electrode. A semiconductor MOSFET device includes a third current carrying electrode electrically connected to the first current carrying electrode, a fourth current carrying electrode electrically connected to the first control electrode, and a second control electrode. A first diode includes a first cathode electrode electrically connected to the second current carrying electrode and a first anode electrode. A second diode includes a second anode electrode electrically connected to the first anode electrode and a second cathode electrode electrically connected to the fourth current carrying electrode. In one embodiment, the group III-V transistor structure, the first diode, and the second diode are integrated within a common substrate.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: February 5, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Balaji Padmanabhan, Prasad Venkatraman, Zia Hossain, Chun-Li Liu, Jason McDonald, Ali Salih, Alexander Young
  • Patent number: 10147497
    Abstract: A method of forming a memory device having magnetic tracks individually comprising a plurality of magnetic domains having domain walls, includes forming an elevationally outer substrate material of uniform chemical composition. The uniform composition material is partially etched into to form alternating regions of elevational depressions and elevational protrusions in the uniform composition material. A plurality of magnetic tracks is formed over and which angle relative to the alternating regions. Interfaces of immediately adjacent of the regions individually form a domain wall pinning site in individual of the magnetic tracks. Other methods, including memory devices independent of method, are disclosed.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: December 4, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Livio Baldi, Marcello Mariani
  • Patent number: 9865503
    Abstract: Aspects of the disclosure provide a method for semiconductor wafer manufacturing. The method includes utilizing a subset of lower level masks in a mask set to form multiple modular units of lower level circuit structures on a semiconductor wafer. The mask set includes the subset of lower level masks and at least a first subset of upper level masks and a second subset of upper level masks. The first subset of upper level masks defines intra-unit interconnections. The second subset of upper level masks defines both intra-unit interconnections and inter-unit interconnections. The method further includes selecting one of at least the first subset of upper level masks and the second subset of upper level masks based on a composition request of a final integrated circuit (IC) product and utilizing the selected subset of upper level masks to form upper level structures on the semiconductor wafer.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: January 9, 2018
    Assignee: MARVELL ISRAEL (M.I.S.L) LTD.
    Inventors: Eran Rotem, Rami Zemach, Itay Peled
  • Patent number: 9847285
    Abstract: There may be provided a method of manufacturing a semiconductor package. The method may include disposing a first semiconductor device and through mold ball connectors (TMBCs) on a first surface of an interconnection structure layer, forming a molding layer on the first surface of the interconnection structure layer to expose a portion of each of the TMBCs, attaching outer connectors to the exposed portions of the TMBCs, mounting a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer, and attaching a heat spreader to the second surface of the interconnection structure layer to overlap with a portion of the first semiconductor device.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: December 19, 2017
    Assignee: SK hynix Inc.
    Inventors: Ki Jun Sung, Jong Hoon Kim, Han Jun Bae
  • Patent number: 9793400
    Abstract: A semiconductor device includes a semiconductor substrate having a channel region interposed between a first active region and a second active region, and a gate structure formed on the channel region. A first dual-layer source/drain region is on the first active region and a second dual-layer source/drain region is on the second active region. The first and second dual-layer source/drain regions include stacked layers formed of different semiconductor materials. A first extension region is embedded in the first active region and a second extension region is embedded in the second active region.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: October 17, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Robert H. Dennard, Zhen Zhang
  • Patent number: 9773754
    Abstract: A three-dimensional integrated circuit including a first layer and a second layer electrically coupled to the first layer and disposed in a stacked relationship relative to the first layer. Logic circuitry is embodied in the first layer and input output circuitry of an input output circuit is embodied in the second layer.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: September 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chin-Ming Fu
  • Patent number: 9754947
    Abstract: A method for fabricating a static random access memory is provided. The method includes providing a semiconductor substrate. The method also includes forming a plurality of transistors on the semiconductor substrate. Further, the method includes forming a first metal layer having a word line electrically connecting with a partial number of the transistors. Further, the method also includes forming a second metal layer having a first bit line, a second bit line, a first power source line and second power source lines electrically connect with a partial number of the transistors.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: September 5, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Gong Zhang
  • Patent number: 9698263
    Abstract: A semiconductor structure that includes crystalline surfaces and amorphous hydrophilic surfaces is provided. The hydrophilic surfaces are treated with silane that includes a hydrophobic functional group, converting the hydrophilic surfaces to hydrophobic surfaces. Chemical vapor deposition or other suitable deposition methods are used to simultaneously deposit a material on both surfaces and due to the surface treatment, the deposited material exhibits superior adherence qualities on both surfaces. In one embodiment, the structure is an opening formed in a semiconductor substrate and bounded by at least one portion of a crystalline silicon surface and at least one portion of an amorphous silicon oxide structure.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lai-Wan Chong, Wen-Chu Hsiao, Ying-Min Chou, Hsiang-Hsiang Ko
  • Patent number: 9659819
    Abstract: A method of forming a memory device includes providing a substrate having a surface region, defining a cell region and first and second peripheral regions, sequentially forming a first dielectric material, a first wiring structure for a first array of devices, and a second dielectric material over the surface region, forming an opening region in the first peripheral region, the opening region extending in a portion of at least the first and second dielectric materials to expose portions of the first wiring structure and the substrate, forming a second wiring material that is overlying the second dielectric material and fills the opening region to form a vertical interconnect structure in the first peripheral region, and forming a second wiring structure from the second wiring material for a second array of devices, the first and second wiring structures being separated from each other and electrically connected by the vertical interconnect structure.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: May 23, 2017
    Assignee: CROSSBAR, INC.
    Inventor: Scott Brad Herner
  • Patent number: 9653680
    Abstract: The present disclosure provides a system and method for forming a resistive random access memory (RRAM) device. A RRAM device consistent with the present disclosure includes a substrate and a first electrode disposed thereon. The RRAM device includes a second electrode disposed over the first electrode and a RRAM dielectric layer disposed between the first electrode and the second electrode. The RRAM dielectric layer has a recess at a top center portion at the interface between the second electrode and the RRAM dielectric layer.
    Type: Grant
    Filed: June 27, 2015
    Date of Patent: May 16, 2017
    Assignee: INTEL CORPORATION
    Inventors: Ravi Pillarisetty, Prashant Majhi, Uday Shah, Niloy Mukherjee, Elijah V. Karpov, Brian S. Doyle, Robert S. Chau
  • Patent number: 9653445
    Abstract: A method of making a semiconductor device comprises the steps of providing a first manufacturing line, providing a second manufacturing line, and forming a first redistribution interconnect structure using the first manufacturing line while simultaneously forming a second redistribution interconnect structure using the second manufacturing line. The method further includes the steps of testing a first unit of the first redistribution interconnect structure to determine a first known good unit (KGU), disposing a known good semiconductor die (KGD) over the first KGU of the first redistribution interconnect structure, testing a unit of the second redistribution interconnect structure to determine a second known good unit (KGU, and disposing the second KGU of the second redistribution interconnect structure over the first KGU of the first redistribution interconnect structure and the KGD. A resolution of the second manufacturing line is greater than a resolution of the first manufacturing line.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: May 16, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Yaojian Lin
  • Patent number: 9640493
    Abstract: An integrated circuit includes a substrate with several functional blocks formed thereon. At least two identical functional blocks are respectively disposed at two or more different locations on the integrated circuit. Electrically inactive dummy modules in the neighborhoods and/or inside of the functional blocks are provided, wherein at least two different electrically inactive dummy modules are includes in the respective neighborhoods and/or inside of the at least two identical functional blocks.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: May 2, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Pascal Fornara, Christian Rivero, Guilhem Bouton
  • Patent number: 9406789
    Abstract: A nanoscale variable resistor including a metal nanowire as an active element, a dielectric, and a gate. By selective application of a gate voltage, stochastic transitions between different conducting states, and even length, of the nanowire can be induced and with a switching time as fast as picoseconds. With an appropriate choice of dielectric, the transconductance of the device, which may also be considered an “electromechanical transistor,” is shown to significantly exceed the conductance quantum G0=2e2/h.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: August 2, 2016
    Assignees: NEW YORK UNIVERSITY, THE ARIZONA BOARD OF REGENTS ON BEHALF OF THE UNIVERSITY OF ARIZONA
    Inventors: Jerome Alexandre Bürki, Charles Allen Stafford, Daniel L. Stein
  • Patent number: 9401365
    Abstract: A process of forming an integrated circuit containing a first transistor and a second transistor of the same polarity, by forming an epitaxial spacer layer over gates of both transistors, performing an epitaxial spacer anisotropic etch process to form epitaxial spacers on vertical surfaces adjacent to the first transistor gate and removing the epitaxial spacer layer from the second transistor gate, subsequently performing a source/drain etch process and a source/drain epitaxial process to form source/drain epitaxial regions in the substrate adjacent to the first and second gates, such that the first source/drain epitaxial regions are separated from the first gate by a lateral space which is at least 2 nanometers larger than a second lateral space separating the second source/drain epitaxial regions from the second gate. An integrated circuit formed by the recited process.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: July 26, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Manoj Mehrotra
  • Patent number: 9379123
    Abstract: Provided are a semiconductor memory device and a method of fabricating the same. the semiconductor memory device may include a semiconductor substrate with a first trench defining active regions in a first region and a second trench provided in a second region around the first region, a gate electrode provided on the first region to cross the active regions, a charge storing pattern disposed between the gate electrode and the active regions, a blocking insulating layer provided between the gate electrode and the charge storing pattern and extending over the first trench to define a first air gap in the first trench, and an insulating pattern provided spaced apart from a bottom surface of the second trench to define a second air gap in the second trench.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: June 28, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hwang Sim, Jinhyun Shin, Jong-Min Lee
  • Patent number: 9318486
    Abstract: A semiconductor integrated circuit device may include a standard cell region on a surface of a substrate and a first active region on the surface of the substrate in the standard cell region, wherein the first active region has a length in a first direction. A second active region may be on the surface of the substrate in the standard cell region, the second active region may have a length in the first direction, the length of the second active region may be greater than the length of the first active region, and an axis in a second direction may intersect centers of the first and second active regions so that the first and second active regions are symmetric about the axis in the second direction. A first gate electrode may extend across the first active region in the first direction, and a second gate electrode may extend across the second active region in the first direction.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: April 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-Seok Shim, Young-Chang Kim, Dong-Geon Kim
  • Patent number: 9305844
    Abstract: Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and WSiX material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. The WSiX material is adjacent to the substrate, and can be used as an etch-landing layer and a conductive contact to contact both the first poly-silicon channel and the second poly-silicon channel in the opening. Other embodiments include methods of making semiconductor devices.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: April 5, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Hongbin Zhu, Gordon Haller, Paul D. Long
  • Patent number: 9276050
    Abstract: Disclosed herein is an OLED (Organic Light Emitting Display) device. A switching thin-film transistor configured to be an oxide semiconductor thin-film transistor is disposed in a first pixel. A second pixel is adjacent to the first pixel in the direction in which data lines are extended. A switching thin-film transistor configured to be an LTPS (Low Temperature Poly-Silicon) thin-film transistor is disposed in the second pixel. The switching thin-film transistor of the first pixel and the switching thin-film transistor of the second pixel are connected to the same gate line. A pixel and another pixel adjacent to the pixel connected to a gate line in common, so that it is possible to provide an OLED device with high aperture ratio and high resolution.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: March 1, 2016
    Assignee: LG Display Co., Ltd.
    Inventors: Hoi Yong Kwon, Joon Suk Lee, Eui Tae Kim, Sung Hee Park, Ki Seob Shin
  • Patent number: 9231197
    Abstract: A memory cell and method including a first electrode conformally formed through a first opening in a first dielectric layer, a resistive layer conformally formed on the first electrode, a spacing layer conformally formed on the resistive layer, a second electrode conformally formed on the resistive layer, and a second dielectric layer conformally formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer is formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao, Chih-Yang Chang, Hsia-Wei Chen, Chin-Chieh Yang
  • Patent number: 9231052
    Abstract: A transistor using a single crystal silicon nanowire and a method for fabricating the transistor is disclosed. The transistor using a single crystal silicon nanowire comprises a substrate and a single crystal silicon nanowire formed on the substrate. Here, the single crystal silicon nanowire comprises a source region and a drain region formed longitudinally with the single crystal silicon nanowire and separate from each other, and a channel region located between the source region and the drain region, wherein the perpendicular thickness of the channel region to the longitudinal direction is thinner than the thickness of the source region and the drain region.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: January 5, 2016
    Assignee: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
    Inventors: Sangsig Kim, Myeong-Won Lee, Youngin Jeon
  • Patent number: 9183933
    Abstract: Cell layouts for a memory cell, such as for ternary content addressable memory (TCAM), are disclosed. Some cell layouts include a well strap structure. A cell layout may include a p-doped well, an n-doped well, and a p-doped well sequentially along a layout. Another cell layout may include a p-doped well, an n-doped well, a p-doped well, and an n-doped well sequentially along a layout. A well strap structure may be in a p-doped well or an n-doped well. Various metallization layers having a mesh may be used with a memory cell layout. In some disclosed examples, a first metallization layer may have one, two, or four ground traces, and a second metallization layer may have two ground traces. These various ground traces may be electrically coupled together to form a mesh.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: November 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 9117707
    Abstract: The array substrate includes a plurality of gate lines and a plurality of data lines which intersect each other to define a plurality of pixel regions, each of the pixel regions includes a thin film transistor and further includes: a base substrate; more than one protrusion disposed apart from each other on the base substrate; a first electrode layer including at least one first electrode strip disposed in a gap between adjacent protrusions; a second electrode layer including at least one second electrode strip disposed on the protrusions.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: August 25, 2015
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Seungjin Choi, Heecheol Kim, Youngsuk Song, Seongyeol Yoo
  • Patent number: 9076879
    Abstract: A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: July 7, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dongchul Yoo, Phil Ouk Nam, Junkyu Yang, Woong Lee, Woosung Lee, JinGyun Kim, Daehong Eom
  • Publication number: 20150129935
    Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures.
    Type: Application
    Filed: January 22, 2015
    Publication date: May 14, 2015
    Inventors: Sanh D. Tang, Roger W. Lindsay, Krishna K. Parat
  • Patent number: 9024288
    Abstract: Embodiments of the present invention provide an array substrate, a manufacturing method thereof and a display device. The manufacturing method of an array substrate, comprising: forming a gate electrode on a base substrate by a first patterning process, and then depositing a gate insulating layer on the base substrate on which the gate electrode is formed; forming source and drain electrodes on the base substrate obtained after the above step, by a second patterning process; forming an active layer formed of a graphene layer, and a protective layer disposed on the active layer, on the base substrate obtained after the above steps, by a third patterning process; and forming a planarizing layer on the base substrate, obtained after the above steps, by a fourth patterning process, in which the planarizing layer is provided with a through hole through which the source or drain electrode is exposed.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: May 5, 2015
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Tuo Sun
  • Patent number: 9024374
    Abstract: A 3D memory device includes a plurality of ridges, in some embodiments ridge-shaped, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor material strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. In some embodiments, the 3D memory is made using only two critical masks for multiple layers. Some embodiments include a staircase-shaped structure positioned at ends of the semiconductor material strips.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: May 5, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Chun Hsiung Hung, Hang-Ting Lue, Shin-Jang Shen
  • Patent number: 9018694
    Abstract: Methods and systems are disclosed for gate dimension control in multi-gate structures for integrated circuit devices. Processing steps for formation of one or more subsequent gate structures are adjusted based upon dimensions determined for one or more previously formed gate structures. In this way, one or more features of the resulting multi-gate structures can be controlled with greater accuracy, and variations between a plurality of multi-gate structures can be reduced. Example multi-gate features and/or dimensions that can be controlled include overall gate length, overlap of gate structures, and/or any other desired features and/or dimensions of the multi-gate structures. Example multi-gate structures include multi-gate NVM (non-volatile memory) cells for NVM systems, such as for example, split-gate NVM cells having select gates (SGs) and control gates (CGs).
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: April 28, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sung-Taeg Kang, ShanShan Du
  • Patent number: 9018046
    Abstract: An area efficient distributed device for integrated voltage regulators comprising at least one filler cell coupled between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size portion of said device is coupled to said I/O rails for distributing portions of said device on the periphery of said chip. The device is coupled as small size portion on the lower portion of said second filler cell for distributing said device on the periphery of said chip and providing maximal area utilization.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 28, 2015
    Assignees: STMicroelectronics International N.V., STMicroelectronics S.r.l.
    Inventors: Joshipura Jwalant, Nitin Bansal, Amit Katyal, Massimiliano Picca
  • Patent number: 9012318
    Abstract: Methods and compositions for etching polysilicon including aqueous compositions containing nitric acid and ammonium fluoride, and apparatus formed thereby.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: April 21, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Jerome A. Imonigie, Prashant Raghu
  • Patent number: 9012918
    Abstract: The threshold voltage is shifted in a negative or positive direction in some cases by an unspecified factor in a manufacturing process of the thin film transistor. If the amount of shift from 0 V is large, driving voltage is increased, which results in an increase in power consumption of a semiconductor device. Thus, a resin layer having good flatness is formed as a first protective insulating film covering the oxide semiconductor layer, and then a second protective insulating film is formed by a sputtering method or a plasma CVD method under a low power condition over the resin layer. Further, in order to adjust the threshold voltage to a desired value, gate electrodes are provided over and below an oxide semiconductor layer.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: April 21, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takayuki Abe, Hideaki Shishido
  • Patent number: 9012915
    Abstract: An organic light-emitting display apparatus includes a buffer layer that is on a substrate and includes nanoparticles including nickel (Ni), a pixel electrode on the buffer layer, an organic emission layer on the pixel electrode, and an opposite electrode on the organic emission layer. A method of manufacturing the organic light-emitting display apparatus is provided.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: April 21, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jae-Hwan Oh, Yeoung-Jin Chang, Seong-Hyun Jin, Won-Kyu Lee, Jae-Beom Choi
  • Patent number: 9012270
    Abstract: Methods for forming a DSA pre-patterned semiconductor transistor layout and the resulting devices are disclosed. Embodiments may include forming a pre-patterned transistor layout by directed self-assembly (DSA), forming a metal layer over the DSA pre-patterned transistor layout, including: forming a plurality of horizontal metal lines; and forming a plurality of vertical metal segments discontinuous from and between adjacent horizontal metal lines; and forming one or more bridging dots each connecting one of the plurality of horizontal metal lines to one of the plurality of vertical metal segments, wherein locations of the bridging dots determine logic functions of resulting transistor cells.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 21, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ji Xu, Vito Dai
  • Patent number: 9012905
    Abstract: A transistor including an oxide semiconductor with favorable electric characteristics and a manufacturing method thereof are provided. A semiconductor device includes a transistor. The transistor includes an oxide semiconductor film over a base insulating film, a gate electrode overlapping with the oxide semiconductor film with a gate insulating film interposed therebetween, and a pair of electrodes in contact with the oxide semiconductor film and serving as a source electrode and a drain electrode. The base insulating film includes a first oxide insulating film partly in contact with the oxide semiconductor film and a second oxide insulating film in the periphery of the first oxide insulating film. An end portion of the oxide semiconductor film which crosses the channel width direction of the transistor is located over the second oxide insulating film.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: April 21, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8999750
    Abstract: A semiconductor device includes an oxide semiconductor layer provided over a substrate having an insulating surface; a gate insulating film covering the oxide semiconductor layer; a first conductive layer and a second conductive layer laminated in this order over the gate insulating film; an insulating film covering the oxide semiconductor layer and a gate wiring including a gate electrode (the first and second conductive layers); and a third conductive layer and a fourth conductive layer laminated in this order over the insulating film and electrically connected to the oxide semiconductor layer. The gate electrode is formed using the first conductive layer. The gate wiring is formed using the first conductive layer and the second conductive layer. A source electrode is formed using the third conductive layer. A source wiring is formed using the third conductive layer and the fourth conductive layer.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: April 7, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 8993377
    Abstract: A semiconductor wafer has first and second opposing surfaces. A plurality of conductive vias is formed partially through the first surface of the semiconductor wafer. The semiconductor wafer is singulated into a plurality of first semiconductor die. The first semiconductor die are mounted to a carrier. A second semiconductor die is mounted to the first semiconductor die. A footprint of the second semiconductor die is larger than a footprint of the first semiconductor die. An encapsulant is deposited over the first and second semiconductor die and carrier. The carrier is removed. A portion of the second surface is removed to expose the conductive vias. An interconnect structure is formed over a surface of the first semiconductor die opposite the second semiconductor die. Alternatively, a first encapsulant is deposited over the first semiconductor die and carrier, and a second encapsulant is deposited over the second semiconductor die.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: March 31, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Jun Mo Koo, Pandi C. Marimuthu, Seung Wook Yoon, Il Kwon Shim
  • Patent number: 8993430
    Abstract: According to one embodiment, a first core pattern is formed in a wiring portion on a process target film and a second core pattern, which is led out from the first core pattern and includes an opening, is formed in a leading portion on the process target film, a sidewall pattern is formed along an outer periphery of the first core pattern and the second core pattern and a sidewall dummy pattern is formed along an inner periphery of the opening of the second core pattern, the first core pattern and the second core pattern are removed, and the process target film is processed to transfer the sidewall pattern and the sidewall dummy pattern.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yuya Matsuda
  • Publication number: 20150085568
    Abstract: An integrated circuit includes one or more bit cells, a word line coupled to the one or more bit cells, and a dummy word line arranged with the word line to have a capacitance therebetween. The capacitance provides a voltage boost or reduction of the word line to assist read and write operations.
    Type: Application
    Filed: September 26, 2013
    Publication date: March 26, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Chirag GULATI, Rakesh SINHA, Ritu CHABA, Sei Seung YOON
  • Patent number: 8987027
    Abstract: A method is provided for fabricating thin-film transistors (TFTs) for an LCD having an array of pixels. The method includes depositing a first photoresist layer over a portion of a TFT stack that includes a conductive gate layer, and a semiconductor layer. The method also includes doping the exposed semiconductor layer with a first doping dose. The method further includes etching a portion of the conductive gate layer to expose a portion of the semiconductor layer, and doping the exposed portion of the semiconductor layer with a second doping dose. The method also includes depositing a second photoresist layer over a first portion of the doped semiconductor layer in an active area of the pixels to expose a second portion of the doped semiconductor layer in an area surrounding the active area, and doping the second portion of the doped semiconductor layer with a third doping dose.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: March 24, 2015
    Assignee: Apple Inc.
    Inventors: Cheng-Ho Yu, Young Bae Park, Shih Chang Chang
  • Patent number: 8987696
    Abstract: According to one embodiment, a resistance change memory includes a first interconnect line extending in a first direction, a second interconnect line extending in a second direction intersecting with the first direction, a cell unit which is provided at the intersection of the first interconnect line and the second interconnect line and which includes a memory element and a non-ohmic element that are connected in series. The non-ohmic element has a first semiconductor layer which includes at least one diffusion buffering region and a conductive layer adjacent to the first semiconductor layer. The diffusion buffering region is different in crystal structure from a semiconductor region except for the diffusion buffering region in the first semiconductor layer.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Sonehara, Nobuaki Yasutake
  • Patent number: 8987066
    Abstract: A processing unit comprises a plurality of individual integrated circuits (ICs) electrically connected to one another via a common configuration of electrical interconnects (e.g., through-silicon vias). At least two of the ICs may be configured for a different function. In some examples, the processing unit is formed by selecting the ICs from stored groups of ICs. The stored ICs can be, for example, modular ICs in that the ICs can be mixed and matched in any suitable number or type in order to meet a particular set of functional requirements for the processing unit, which may depend on the application for the processing unit. Electrical coupling of these individual ICs via the electrical interconnects of the ICs results in a single processing unit that is configured to perform functions specifically suited for a particular application or set of applications.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: March 24, 2015
    Assignee: Honeywell International Inc.
    Inventors: Eric Grobelny, David Paul Campagna, David J. Kessler
  • Publication number: 20150076575
    Abstract: An integrated circuit includes a plurality of metal layers of bit cells of a memory cell array disposed in a first metal layer and extending in a first direction, a plurality of word lines of the memory cell array disposed in a second metal layer and extending in a second direction that is different from the first direction, and at least two conductive traces disposed in a third metal layer substantially adjacent to each other and extending at least partially across the memory cell array, a first one of the at least two conductive traces coupled to a driving source node of a write assist circuit, and a second conductive trace of the at least two conductive traces coupled to an enable input of the write-assist circuit, where the at least two conductive traces form at least one embedded capacitor having a capacitive coupling to the bit line.
    Type: Application
    Filed: September 19, 2013
    Publication date: March 19, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Wei WU, Wei-Shuo KAO, Chia-Cheng CHEN, Kuang Ting CHEN
  • Patent number: 8980731
    Abstract: Methods of forming a semiconductor device are provided. The methods may include forming first and second layers that are alternately and repeatedly stacked on a substrate, and forming an opening penetrating the first and second layers. The methods may also include forming a first semiconductor pattern in the opening. The methods may additionally include forming an insulation pattern on the first semiconductor pattern. The methods may further include forming a second semiconductor pattern on the insulation pattern. The methods may also include providing dopants in the first semiconductor pattern. Moreover, the methods may include thermally treating a portion of the first semiconductor pattern to form a third semiconductor pattern.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung Ho Kim, Sunghae Lee, Hanvit Yang, Dongwoo Kim, Chaeho Kim, Daehyun Jang, Ju-Eun Kim, Yong-Hoon Son, Sangryol Yang, Myoungbum Lee, Kihyun Hwang
  • Patent number: 8980654
    Abstract: The ion implantation method includes setting an ion beam scanning speed and a mechanical scanning speed of an object during ion implantation using hybrid scan in advance and implanting ions based on the set ion beam scanning speed and the set mechanical scanning speed of the object. In the setting in advance, each of the ion beam scanning speeds is set based on each of ion beam scanning amplitudes changing severally according to a surface outline of an object which is irradiated with the ions so that an ion beam scanning frequency is maintained constant for any of ion beam scanning amplitudes, and the mechanical scanning speed of the object corresponding to the ion beam scanning speed is set so that an ion implantation dose per unit area to be implanted into the surface of the object is maintained constant.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: March 17, 2015
    Assignee: SEN Corporation
    Inventors: Shiro Ninomiya, Akihiro Ochi
  • Publication number: 20150069470
    Abstract: An integrated circuit device includes a plurality of basic cells that each have a first transistor pair including two p-channel transistors of a first-type and a second transistor pair including two p-channel transistors of a second-type. The second-type transistors are configured to consume less power and operate more slowly than the first-type transistors. The basic cell further includes a third transistor pair of two n-channel transistors of a third-type. The third transistor pair is disposed between the first and second transistor pairs. Gate electrodes are separately provided for each transistor in the first, second, and third transistor pairs. The basic cell thus formed can be used to fabricate various circuit elements by making wiring connections between various transistor pairs and/or basic cells.
    Type: Application
    Filed: February 28, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Atsushi KANEKO
  • Patent number: 8969152
    Abstract: A field-effect transistor (FET) and methods for fabricating such. The FET includes a substrate having a crystalline orientation, a source region in the substrate, and a drain region in the substrate. Gate spacers are positioned over the source region and the drain region. The gate spacers include a gate spacer height. A source contact physically and electrically contacts the source region and extends beyond the gate spacer height. A drain contact physically and electrically contacts the drain region and extends beyond the gate spacer height. The source and drain contacts have the same crystalline orientation as the substrate.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Wilfried E. Haensch, Effendi Leobandung, Min Yang
  • Patent number: 8963210
    Abstract: An integrated circuit (IC) cell may include first and second semiconductor regions, and parallel electrically conductive lines extending above the first and second semiconductor regions. The IC cell may further include electrically conductive line contacts electrically connected to the parallel electrically conductive lines, and may include at least one first line contact between the first semiconductor region and a corresponding end of the IC cell, and at least one second line contact between the first semiconductor region and the second semiconductor region. Adjacent ones of the electrically conductive lines may be respectively coupled to one of the at least one first line contact and to one of the at least one second line contact.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: February 24, 2015
    Assignees: STMicroelectronics SA, STMicroelectronics, Inc.
    Inventors: Rwik Sengupta, Rohit Kumar Gupta, Mitesh Goyal, Olivier Menut
  • Patent number: 8962475
    Abstract: An integrated circuit substrate is designed and fabricated with a selectively applied transmission line reference plane metal layer to achieve signal path shielding and isolation, while avoiding drops in impedance due to capacitance between large diameter vias and the transmission line reference plane metal layer. The transmission line reference plane defines voids above (or below) the signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. For voltage-plane bearing PTHs, no voids are introduced, so that signal path conductors can be routed above or adjacent to the voltage-plane bearing PTHs, with the transmission line reference plane preventing shunt capacitance between the signal path conductors and the PTHs.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Sungjun Chun, Anand Haridass, Roger D. Weekly
  • Patent number: RE45481
    Abstract: An interconnector line of thin film comprising 0.001 to 30 at % of at least one kind of a first element capable of constituting an intermetallic compound of aluminum and/or having a higher standard electrode potential than aluminum, for example, at least one kind of the first element selected from Y, Sc, La, Ce, Nd, Sm, Gd, Tb, Dy, Er, Th, Sr, Ti, Zr, V, Nb, Ta, Cr, Mo, W, Mn, Tc, Re, Fe, Co, Ni, Pd, Ir, Pt, Cu, Ag, Au, Cd, Si, Pb and B; and one kind of a second element selected from C, O, N and H in a proportion of 0.01 at ppm to 50 at % of the first element, with the balance comprising substantially Al. In addition to having low resistance, such an Al interconnector line of thin film can prevent the occurrence of hillocks and the electrochemical reaction with an ITO electrode. The interconnector line of thin film can be obtained by sputtering in a dust-free manner by using a sputter target having a similar composition.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Ishigami, Koichi Watanabe, Akihisa Nitta, Toshihiro Maki, Noriaki Yagi