Abstract: The present invention provides a semiconductor protection device in a substrate having a first type of conductivity. The semiconductor protection device includes two vertical bipolar transistors. A well region is located within the substrate having a second type of conductivity with a base region within the well region having a first type of conductivity. A first doped region having the second type of conductivity and a second doped region having a first type of conductivity are located within the well region. A third doped region having the second type of conductivity and a fourth doped region having the first type of conductivity are located within the base region. A doped region having a first type of conductivity is located within the substrate. This doped region is connected to the fourth doped region.

Abstract: A method for preventing the snap down effect in a power rectifier with higher breakdown voltage comprises the step of forming an isolation layer between the semiconductor substrate and the epitaxy layer. The isolation layer can prevent the dislocation occurred upon the semiconductor substrate from influencing the p-n junction atop. Therefore, the power rectifier manufactured by the method of the present invention can work under a higher breakdown voltage exceeding 450 V with reduced cost.

Abstract: A method of fabricating a MOS controlled thyristor (MCT) semiconductor power device which reduces process time, reduces cell size, and increases the density of turn-off channels. The method uses a single, dopant-opaque mask to form MCT structure above the bottom N and P layers, including the upper portions of PNP and NPN transistors which form the MCT and On-FETs and Off-FETs which operate the MCT. The single mask may also be used to fabricate floating field rings for the device. The method may also be used on both sides of the device to provide a Fast Turn Off (FTO) device with both On- and Off-FETs on one side and at least an Off-FET on the other side.

Abstract: A manufacturing method for rectifying diodes, wherein, a plurality of upper and lower pins are combined with a plurality of electronic chips to form a coarse blank. And then they are processed to form shaped insulating layers by molding. Each insulating layer is processed to have superficial coarseness having micro-protuberances thereon; the areas on both the lateral sides of the insulating layer are applied with electric conductive layer. The electric conductive layer is combined with the insulating layer; they are equidistantly cut with a knife into shaped rectifying diodes. The shaped rectifying diodes each is further electrically plated with a further layer of electric conductive material on both sides of the electric conductive layer to form a harder protection layer, and then finished rectifying diodes are obtained. The upper and lower pins are in the form of thin sheets, plus the small chips, the shaped rectifying diodes have small volumes.

Abstract: Component structures of, for example, IGBTs are manufactured on the respective top sides of two substrates, the substrates are thinned proceeding from their respective back sides, and, after polishing, the back sides of the thinned substrates are durably electrically conductively connected to one another by wafer bonding.

Abstract: A monolithic assembly includes vertical power semiconductor components formed throughout the thickness of a low doped semiconductive wafer of a first conductivity type, whose bottom surface is uniformly coated with a metallization. At least some of these components, so-called autonomous components, are formed in insulated sections of the substrate, whose lateral insulation is provided by a diffused wall of the second conductivity type and whose bottom is insulated through a dielectric layer interposed between the bottom surface of the substrate and the metallization.

Abstract: A structure for the protection of a high-voltage pad includes a lateral bipolar transistor, an N-type diffusion of which, connected to the pad to be protected, is made in an N-type tub with a zone that extends laterally outside the tub in the base. A P-type implantation is made on the entire substrate outside the N-type tub except in the region in which the zone extends.

Abstract: A parasitic transistor of an insulated gate semiconductor device does not easily turn on, so that an SOA of the insulated gate semiconductor device is improved. P.sup.+ semiconductor layers (45) having a higher impurity concentration than that N.sup.+ emitter layers (44) are disposed so that the P.sup.+ semiconductor layers (45) overlap adjacent edges of the N.sup.+ emitter layers (44) of a U-type IGBT and so that bottom portions of the P.sup.+ semiconductor layers (45) contact P base layers (43). An emitter electrode (51) contacts the P base layers (43) through the P.sup.+ semiconductor layers (45). A trench pitch is small, and therefore, a parasitic transistor which is formed by an N.sup.+ emitter region (4), a P base layer (3) and an N.sup.- layer (2) does not easily turn on.

Abstract: In a surface of a silicon substrate of one conductivity type, there are formed a plurality of depressions or recesses, gate regions of opposite conductivity type are formed at bottoms of respective recesses, gate electrodes are provided on respective gate regions, and an electrically conductive block is joined to the surface of the semiconductor substrate. Between the surface of the semiconductor substrate and the electrically conductive block a contact region having a high impurity concentration and/or an electrically conductive material layer may be provided in order to improve electrical and mechanical properties of the contact between the semiconductor substrate and the electrically conductive block. The gate region can have a high impurity concentration and a distance between a channel region and the electrically conductive block can be very small.

Abstract: A method of fabricating a UMOS semiconductor device includes a blanket implant of an N type dopant into a surface of a substrate (for forming source regions), a high energy implant of a P type dopant into the substrate (for forming body regions), an etch through a hard mask to form trenches and mesas (each of the mesas having a source region at its top and a body region below), and concurrently (i) providing a gate dielectric on the sidewalls of the trenches and (ii) redistributing the dopants so that the body regions extend deeper into the substrate beneath the centers of the mesas than adjacent the walls of the trenches. Contact windows are etched in the mesas to allow electrical contact with the source regions and the body regions. The initial implant of P type dopant may be a blanket implant or an implant through a mask which concentrates the P type dopant in the centers of the mesas.

Abstract: A trench power switching transistor (10) is fabricated having sub-micron features on a body layer (26) without using sub-micron lithography. An opening in a field oxide layer (28) defines an area for implanting a source region (30) in the body layer (26) that is self-aligned to a first edge (28A) and a second edge (28B) of the field oxide layer (28). Sidewall spacers (32) are formed in accordance with the first and second edges (28A and 28B) of the field oxide layer (28). A trench is aligned to the sidewall spacers (32) and formed centered within the source region (30). An implant layer (42) formed between sections of the power switching transistor (10) is aligned to the sidewall spacers (32) at the first and second edges (28A and 28B).

Abstract: Methods of forming power semiconductor devices include the steps of forming a relatively highly doped latch-up inhibiting region to suppress the likelihood of parasitic thyristor latch-up in a power semiconductor device such as an insulated-gate bipolar transistor (IGBT). In particular, an insulated-gate bipolar transistor is formed by patterning an insulated gate electrode on a surface of a drift region and then implanting first dopants of second conductivity type (e.g., P-type) at a first depth into the drift region, using the gate electrode as an implant mask. The implanted first dopants are then diffused using a thermal treatment to form a base region (e.g., P- well region). Second dopants of second conductivity type are then implanted into the base region at a second depth, less than the first depth, using the insulated gate electrode as a mask. Third dopants of first conductivity type (e.g.

Abstract: A green-blue to ultraviolet light emitting semiconductor laser having a top contact, a Bragg reflector, cladding layer, active layer, cladding layer, buffer, substrate, bottom contact and a passivation layer. The key aspect is a Ga*N material on a base structure comprising a SiC substrate selected from a group consisting of 2H-SiC, 4H-SiC and a-axis oriented 6H-SiC. Furthermore, the cladding layers have larger band gaps than the active layer and are complimentarily doped.

Abstract: A MOS-technology power device including a semiconductor material layer of a first conductivity type having a body region disposed therein. The body region includes a heavily doped region of a second conductivity type, a lightly doped region of the second conductivity type and a heavily doped region of the first conductivity type and a process of making same. A method of making the semiconductor device includes forming an insulated gate layer on portions of the surface of the semiconductor material layer to leave selected portions of the semiconductor material layer exposed. Ions of the second conductivity type are implanted into the selected regions of the semiconductor material layer. The implanted ions are thermally diffused to form body regions, each body region including a heavily doped region substantially aligned with the edges of the insulated gate layer, and a lightly doped region formed by lateral diffusion of the first dopant under the insulated gate layer.

Abstract: A method of manufacturing a semiconductor device and device in which a sacrificial N shelf layer is grown on a P+ semiconductor substrate to contain the out-diffusion of dopant from the substrate. An N+ buffer layer is grown on the N shelf layer and an N- epitaxial layer is grown on the N+ buffer layer. The presence of the N shelf layer, which is consumed by the substrate dopant during further device fabrication, allows the integrated dopant level of the N+ buffer layer to be accurately controlled in the finished device.

Abstract: A two-stage method is proposed for producing a highly transparent anode emitter (2) in a GTO (1). In a first step, an anode emitter (2) is indiffused whose thickness is greater than 0.5 .mu.m and whose doping concentration is greater than 10.sup.17 cm.sup.-3. In a second step, the emitter efficiency of the anode emitter (2) is subsequently reduced to a desired degree by local carrier life setting.

Abstract: A dipole component with a controlled breakover sensitivity includes a main thyristor having its gate connected to its anode through a pilot thyristor, and a triggering transistor disposed in parallel with the pilot thyristor, the base of the triggering transistor being connected to the gate of the pilot thyristor.

Abstract: An epitaxial growth method for a compound semiconductor thin film, capable of forming a p-n junction with an atomic-scale ultra-micro structure is disclosed. The method involves loading the compound semiconductor substrate in a reaction chamber, injecting Group V and III metal organic source gases not processed by a thermal pre-decomposition process into the reaction chamber, and growing a p- or n-type compound semiconductor on the compound semiconductor substrate while adjusting the growth temperature of the p- or n-type compound semiconductor.

Abstract: The method in accordance with the present invention is compatible with conventional CMOS fabrication processes to form a zener diode and a lateral silicon controlled rectifier constituting an on-chip ESD protection circuit in a semiconductor substrate. The zener diode is composed of a p-type doped region and an n-type doped region, wherein one of the doped regions, formed by deep diffusing impurities from a doped polysilicon layer, is arranged between two adjacent well regions. During an ESD event, the zener diode incurs breakdown to lower the trigger voltage of the lateral SCR device to within a range of about 5-7 Volts to thereby discharge the ESD current prior to damage of an internal circuit being protected.

Abstract: VLSI I/O structures to reduce the effects of simultaneous switching noise (SSN) on output driver circuits and enhance electrostatic discharge immunity, while reducing chip area, in both input receiver circuits and output driver circuits include improved transistors having deep-junction drain and a multi-cascaded, resistive deep-junction source structure.

Abstract: A power MOS chip and package assembly is provided for packaging a power MOS chip that has high heat dissipation. The assembly maintains a low contact resistance to the chip using compression without damaging the chip. The package assembly includes a thermally conductive body, a chip, an electrically conductive contact washer and an external electrical terminal. The chip includes a semiconductor substrate layer, an insulating layer, a conductive material gate layer and a metal layer. The layers form a plurality of first regions that are functionally inactive and a plurality of second regions. The insulating layer is formed to be thicker in the first regions than in the second regions so that the metal layer is elevated with respect to the substrate layer by a greater amount in the first regions than in the second regions. The contact washer is placed in mechanical contact with the chip so that it exerts pressure against the metal layer in the first regions to create an electrical connection.

Abstract: One embodiment of a metal oxide semiconductor controlled thyristor in accordance with the present invention has a semiconductor wafer with opposing first and second surfaces. The wafer includes first through sixth sequential regions which are disposed one above the other. The first region includes the second surface of the wafer and each of the second through sixth regions has at least a portion which extends up to the first surface. The first, third, and sixth regions have a first type of conductivity and the second, fourth, and fifth regions have a second type of conductivity. A trench with a bottom and sidewalls extends from the first surface and passes through the fourth, fifth, and sixth regions and into the third region. A dielectric material coats the bottom and sidewalls of the trench and a conductive material fills the remainder of the trench.

Abstract: A process for manufacturing a vertical gate-enhanced bipolar transistor is described. The process does not require the presence of an insulating substrate to electrically isolate devices and is suitable for both NPN as well as PNP bipolar transistors. The process begins with the formation of a buried layer. This layer is accessed from the surface through a suitable well region. Then a trench, shaped as a hollow square is formed, lined with a layer of gate oxide and then filled with low resistivity polysilicon to form the gate. A polysilicon emitter layer is formed in the interior of the square, following implantation of arsenic ions with thermal drive-in to form an emitter junction just below the surface. After formation of the emitter junction, isolation layers, including self-aligned spacers, are constructed to cover the polysilicon emitter layer. Another layer of polysilicon is then laid down and then boron ions are implanted. This is followed by a thermal drive-in to form a base contact.

Abstract: A method and resulting structure is disclosed for extending or enlarging the effective volumes of one or more source, drain, and/or emitter regions of integrated circuit structures such as an SCR structure and/or an MOS structure designed to protect an integrated circuit structure from damage due to electrostatic discharge (ESD). The additional effective volume allows the SCR and/or MOS protection devices to handle additional energy from an electrostatic discharge applied, for example, to I/O contacts electrically connected to the SCR protection structure. The additional effective volume is obtained, without additional doping or masking steps, by forming individual deep doped regions or wells, beneath one or more heavily doped source, drain, and emitter regions, at the same time and to the same depth and doping concentration as conventional main P wells and/or N wells which are simultaneously formed in the substrate, whereby no additional masks and implanting steps are needed.