Vertical Channel Patents (Class 438/138)
  • Patent number: 11329147
    Abstract: In one aspect, a method of fabricating a transistor includes implanting ions into a first portion of a second epitaxial layer to form a recombination region, depositing a second portion of the second epitaxial layer having an n-type dopant on the recombination region, and forming trenches in the second portion of the second epitaxial layer.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: May 10, 2022
    Assignee: Polar Semiconductor, LLC
    Inventor: Noel Hoilien
  • Patent number: 11329126
    Abstract: In an embodiment, a method of fabricating a superjunction semiconductor device includes implanting first ions into a first region of a first epitaxial layer using a first implanting apparatus and nominal implant conditions to produce a first region in the first epitaxial layer comprising the first ions and a first implant characteristic and implanting second ions into a second region of the first epitaxial layer, the second region being laterally spaced apart from the first region, using second nominal implanting conditions estimated to produce a second region in the first epitaxial layer having the second ions and a second implant characteristic that lies within an acceptable maximum difference of the first implant characteristic.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: May 10, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Tilke, Hans Weber, Christian Fachmann, Roman Knoefler, Gabor Mezoesi, Manfred Pippan, Thomas Rupp, Michael Treu, Armin Willmeroth
  • Patent number: 11239188
    Abstract: A power semiconductor device includes a semiconductor body configured to conduct a load current. A load terminal electrically connected with the semiconductor body is configured to couple the load current into and/or out of the semiconductor body. The load terminal includes a metallization having a frontside and a backside. The backside interfaces with a surface of the semiconductor body. The frontside is configured to interface with a wire structure having at least one wire configured to conduct at least a part of the load current. The frontside has a lateral structure formed at least by at least one local elevation of the metallization. The local elevation has a height in an extension direction defined by a distance between the base and top of the local elevation and, in a first lateral direction perpendicular to the extension direction, a base width at the base and a top width at the top.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: February 1, 2022
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Rainer Pelzer, Manfred Schneegans
  • Patent number: 11204327
    Abstract: A layer of amorphous Ge is formed on a substrate using electron-beam evaporation. The evaporation is performed at room temperature. The layer of amorphous Ge has a thickness of at least 50 nm and a purity of at least 90% Ge. The substrate is complementary metal-oxide-semiconductor (CMOS) compatible and is transparent at Long-Wave Infrared (LWIR) wavelengths. The layer of amorphous Ge can be used as a waveguide in chemical sensing and data communication applications. The amorphous Ge waveguide has a transmission loss in the LWIR of 11 dB/cm or less at 8 ?m.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: December 21, 2021
    Assignee: Massachusetts Institute of Technology
    Inventors: Eveline Postelnicu, Samarth Aggarwal, Kazumi Wada, Jurgen Michel, Lionel C. Kimerling, Michelle L. Clark, Anuradha M. Agarwal
  • Patent number: 11145721
    Abstract: A semiconductor device fabrication method includes forming first and second spaced apart base regions and source regions in a substrate with a portion of a drift region therebetween. The method further includes forming at least a first trench extending laterally through the base region, the drift region and the source region, the first trench extending vertically partially through the source region. The method also includes forming a first oxide layer over the trenched upper surface, and forming a polysilicon layer over the first oxide layer. The polysilicon layer is patterned to form the gate conductor, and a drain contact is formed on a bottom surface of the semiconductor substrate.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: October 12, 2021
    Assignee: Purdue Research Foundation
    Inventor: James A. Cooper
  • Patent number: 11127831
    Abstract: Embodiments of the disclosure provide a transistor structure and methods to form the same. The transistor structure may include an active semiconductor region with a channel region between a first source/drain (S/D) region and a second S/D region. A polysilicon gate structure is above the channel region of the active semiconductor region. An overlying gate is positioned on the polysilicon gate structure. A horizontal width of the overlying gate is greater than a horizontal width of the polysilicon gate structure. The transistor structure includes a gate contact to the overlying gate.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: September 21, 2021
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Qizhi Liu, Vibhor Jain, John J. Pekarik, Judson R. Holt
  • Patent number: 11075285
    Abstract: An insulated gate power semiconductor device includes an (n-) doped drift layer between an emitter side and a collector side. A p doped protection pillow covers a trench bottom of a trench gate electrode. An n doped enhancement layer having a maximum enhancement layer doping concentration in an enhancement layer depth separates the base layer from the drift layer. An n doped plasma enhancement layer having a maximum plasma enhancement layer doping concentration covers an edge region between the protection pillow and the trench gate electrode. The N doping concentration decreases from the maximum enhancement layer doping concentration towards the plasma enhancement layer and the N doping concentration decreases from the maximum plasma enhancement layer doping concentration towards the enhancement layer such that the N doping concentration has a local doping concentration minimum between the enhancement layer and the plasma enhancement layer.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: July 27, 2021
    Assignee: ABB POWER GRIDS SWITZERLAND AG
    Inventors: Luca De-Michielis, Chiara Corvasce
  • Patent number: 11069772
    Abstract: Aspects of the present disclosure are directed toward designs and methods of manufacturing semiconductor devices, such as semiconductor charge balanced (CB) devices or semiconductor super-junction (SJ) devices. The disclosed designs and methods are useful in the manufacture of CB devices, such as planar CB metal-oxide semiconductor field-effect transistor (MOSFET) devices, as well as other devices.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: July 20, 2021
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Stephen Daley Arthur, Reza Ghandi, Alexander Viktorovich Bolotnikov, David Alan Lilienfeld, Peter Almern Losee
  • Patent number: 10957791
    Abstract: A device includes a cell, wherein each cell includes a body having a main top surface and a main bottom surface, a gate on the main surface on the device having a first length, a gate isolation layer over the gate having a second length at least twice as long as the first length, a source contact in the device body adjacent to the gate, a source metal layer over the gate isolation layer, and a drain on the main bottom surface of the cell.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: March 23, 2021
    Assignee: INFINEON TECHNOLOGIES AMERICAS CORP.
    Inventor: Yang Gao
  • Patent number: 10818784
    Abstract: A semiconductor device according to the present invention includes a channel region of a first conductivity type, disposed at a front surface portion of a semiconductor layer, an emitter region of a second conductivity type, disposed at a front surface portion of the channel region, a drift region of the second conductivity type, disposed in the semiconductor layer at a rear surface side of the channel region, a collector region of the first conductivity type, disposed in the semiconductor layer at a rear surface side of the drift region, a gate trench, formed in the semiconductor layer, a gate electrode, embedded in the gate trench, and a convex region of the second conductivity type, projecting selectively from the drift region to the channel region side at a position separated from a side surface of the gate trench.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: October 27, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Akihiro Hikasa
  • Patent number: 10784358
    Abstract: An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: September 22, 2020
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Rishabh Mehandru, Aaron D. Lilak, Kimin Jun
  • Patent number: 10529809
    Abstract: A method of manufacturing a power semiconductor device includes: creating a doped contact region on top of a surface of a carrier; creating, on top of the contact region, a doped transition region having a maximum dopant concentration of at least 0.5*1015 cm?3 for at least 70% of a total extension of the doped transition region in an extension direction and a maximal dopant concentration gradient of at most 3*1022 cm?4, wherein a lower subregion of the doped transition region is in contact with the contact region and has a maximum dopant concentration at least 100 times higher than a maximum dopant concentration of an upper subregion of the doped transition region; and creating a doped drift region on top of the upper subregion of the doped transition region, the doped drift region having a lower dopant concentration than the upper subregion of the doped transition region.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: January 7, 2020
    Assignee: Infineon Technologies AG
    Inventors: Matthias Kuenle, Daniel Schloegl, Hans-Joachim Schulze, Christoph Weiss
  • Patent number: 10403720
    Abstract: A semiconductor device fabrication method includes forming first and second spaced apart base regions and source regions in a substrate with a portion of a drift region therebetween. The method further includes forming at least a first trench extending laterally through the base region, the drift region and the source region, the first trench extending vertically partially through the source region. The method also includes forming a first oxide layer over the trenched upper surface, and forming a polysilicon layer over the first oxide layer. The polysilicon layer is patterned to form the gate conductor, and a drain contact is formed on a bottom surface of the semiconductor substrate.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: September 3, 2019
    Assignee: Purdue Research Foundation
    Inventor: James A. Cooper
  • Patent number: 10367057
    Abstract: A power semiconductor device is disclosed. The device includes a semiconductor body coupled to a first load terminal structure and a second load terminal structure, a first cell and a second cell. A first mesa is included in the first cell, the first mesa including: a first port region and a first channel region. A second mesa included in the second cell, the second mesa including a second port region. A third cell is electrically connected to the second load terminal structure and electrically connected to a drift region. The third cell includes a third mesa comprising: a third port region, a third channel region, and a third control electrode.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: July 30, 2019
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Franz-Josef Niedernostheide, Frank Dieter Pfirsch, Christian Philipp Sandow
  • Patent number: 10361082
    Abstract: A method of manufacturing a semiconductor device is provided with: (a) providing a wide bandgap substrate product, (b) for forming two channel layers applying a first mask and applying a p first dopant, for forming two source regions forming a second mask by applying a further layer on the lateral sides of the first mask and applying an n second dopant, for forming two well layers forming a third mask by removing such part of the second mask between the source regions and applying a p third dopant, wherein a well layer depth is at least as large as a channel layer depth, (c) after step (b) for forming a plug applying a fourth mask, which covers the source regions and the channel layers and applying a p fourth dopant to a greater depth than the well layer depth and with a higher doping concentration than the well layers; wherein the well layers surround the plug in the lateral direction and separate it from the two source regions.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: July 23, 2019
    Assignee: ABB Schweiz AG
    Inventors: Holger Bartolf, Munaf Rahimo, Lars Knoll, Andrei Mihaila, Renato Minamisawa
  • Patent number: 10332994
    Abstract: A semiconductor integrated circuit device may include an isolating layer, a buried gate, source and drain regions, a dielectric layer having a high dielectric constant and an insulating interlayer. The isolating layer may be formed on a semiconductor substrate to define an active region. The buried gate may be formed in the active region of the semiconductor substrate. The source and drain regions may be formed in the active region at both sides of the buried gate. The dielectric layer may be configured to surround the source and drain regions. The insulating interlayer may be formed on the dielectric layer.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: June 25, 2019
    Assignee: SK hynix Inc.
    Inventors: Dong Yean Oh, Sang Yong Kim
  • Patent number: 10256313
    Abstract: A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, and a surface insulating film disposed in a manner extending across the cell portion and the outer peripheral portion, and in the cell portion, formed to be thinner than a part in the outer peripheral portion.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: April 9, 2019
    Assignee: ROHM CO., LTD.
    Inventors: Yuki Nakano, Ryota Nakamura
  • Patent number: 10134835
    Abstract: A power semiconductor device is disclosed. The device includes a semiconductor body coupled to a first load terminal structure and a second load terminal structure, a first cell and a second cell. A first mesa is included in the first cell, the first mesa including: a first port region and a first channel region. A second mesa included in the second cell, the second mesa including a second port region. A third cell is electrically connected to the second load terminal structure and electrically connected to a drift region. The third cell includes a third mesa comprising: a third port region, a third channel region, and a third control electrode.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: November 20, 2018
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Franz-Josef Niedernostheide, Frank Dieter Pfirsch, Christian Philipp Sandow
  • Patent number: 10074648
    Abstract: A method of manufacturing a semiconductor device includes: implanting charged particles into a first range and a second range in a semiconductor substrate from at least one of a first surface of the semiconductor substrate and a second surface of the semiconductor substrate located on an opposite side of the first surface so as to increase crystal defect densities in the first range and the second range; implanting n-type impurities into the first range from the first surface so as to make a region amorphous, the region being in the first range and disposed at the first surface; irradiating the first surface with first laser after the implantation of the charged particles and the implantation of the n-type impurities so as to heat the first range and the second range; and crystallizing the region which has been made amorphous in or after the irradiation of the first laser.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: September 11, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hiroshi Hosokawa, Shinya Iwasaki, Tsuyoshi Nishiwaki, Atsushi Imai, Shuhei Oki
  • Patent number: 10020285
    Abstract: A method of producing a semiconductor device is provided. The method includes: providing a semiconductor wafer, the wafer including an upper layer of a semiconductor material, an inner etch stop layer and a lower layer; forming a plurality of functional areas in the upper layer; performing a selective first etch process on the upper layer so as to separate the plurality of functional areas from each other by trenches etched through the upper layer, the first etch process being substantially stopped by the inner etch stop layer; and removing the lower layer by a second etch process, the second etch process being substantially stopped by the inner etch stop layer.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: July 10, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Edward Fuergut, Manfred Engelhardt, Hannes Eder, Bernd Roemer
  • Patent number: 9905684
    Abstract: A semiconductor device includes a semiconductor substrate that is made of a semiconductor material with a wider band gap than silicon, a field effect transistor, including a front surface element structure, provided on a front surface of the substrate, and a drain electrode having surface contact with the substrate so as to form a Schottky junction between the semiconductor substrate and the drain electrode.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: February 27, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Haruo Nakazawa, Masaaki Ogino, Tsunehiro Nakajima
  • Patent number: 9859384
    Abstract: Semiconductor devices having vertical FET (field effect transistor) devices with metallic source/drain regions are provided, as well as methods for fabricating such vertical FET devices. For example, a semiconductor device includes a first source/drain region formed on a semiconductor substrate, a vertical semiconductor fin formed on the first source/drain region, a second source/drain region formed on an upper surface of the vertical semiconductor fin, a gate structure formed on a sidewall surface of the vertical semiconductor fin, and an insulating material that encapsulates the vertical semiconductor fin and the gate structure. The first source/drain region comprises a metallic layer and at least a first epitaxial semiconductor layer. For example, the metallic layer of the first source/drain region comprises a metal-semiconductor alloy such as silicide.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Hari V. Mallela, Robert R. Robison, Reinaldo Vega, Rajasekhar Venigalla
  • Patent number: 9748374
    Abstract: A semiconductor device includes a silicon semiconductor body having a main surface and a nitrogen concentration which is lower than about 2*1014 cm?3 at least in a first portion of the silicon semiconductor body, the first portion extending from the main surface to a depth of about 50 ?m. The nitrogen concentration increases with a distance from the main surface at least in the first portion. The semiconductor device further includes a field-effect structure arranged next to the main surface.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: August 29, 2017
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Peter Irsigler
  • Patent number: 9450085
    Abstract: A semiconductor device includes a semiconductor substrate having first regions of a first conductivity type and body regions of the first conductivity type, which are arranged in a manner adjoining the first region and overlap the latter in each case on a side of the first region which faces a first surface of the semiconductor substrate, and having a multiplicity of drift zone regions arranged between the first regions and composed of a semiconductor material of a second conductivity type, which is different than the first conductivity type. The first regions and the drift zone regions are arranged alternately and form a superjunction structure. The semiconductor device further includes a gate electrode formed in a trench in the semiconductor substrate.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: September 20, 2016
    Assignee: Infineon Technologies AG
    Inventors: Till Schloesser, Andreas Meiser
  • Patent number: 9356107
    Abstract: A semiconductor device includes a plurality of trench gates extending in a first direction and arranged with a space between one another in a second direction which is orthogonal to the first direction. Each of the plurality of trench gates includes: a first portion opened on a front surface of the semiconductor substrate; a second portion extending from the first portion in a direction inclined relative to a depth direction of the semiconductor substrate toward a positive direction of the second direction; and a third portion extending from the first portion in a direction inclined relative to the depth direction of the semiconductor substrate toward a negative direction of the second direction.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: May 31, 2016
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Yuto Kurokawa
  • Patent number: 9269769
    Abstract: A semiconductor component including a short-circuit structure. One embodiment provides a semiconductor component having a semiconductor body composed of doped semiconductor material. The semiconductor body includes a first zone of a first conduction type and a second zone of a second conduction type, complementary to the first conduction type, the second zone adjoining the first zone. The first zone and the second zone are coupled to an electrically highly conductive layer. A connection zone of the second conduction type is arranged between the second zone and the electrically highly conductive layer.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: February 23, 2016
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide, Uwe Kellner-Werdehausen, Reiner Barthelmess
  • Patent number: 9252221
    Abstract: A semiconductor device having a gate stack on a substrate is disclosed. The gate stack may include a mask layer disposed over a first gate conductor layer. The first gate conductor layer may be laterally etched beneath the mask layer to create an overhanging portion of the mask layer. A sidewall dielectric can be formed on the sidewall of the first gate conductor layer beneath the overhanging portion of the mask layer. A sidewall structure layer can be formed adjacent to the sidewall dielectric and beneath the overhanging portion of the mask layer. The mask layer can be removed. The first gate conductor layer can be used to form a memory gate and the sidewall structure layer can be used to form a select gate.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: February 2, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Rinji Sugino, Scott Bell, Chun Chen, Shenging Fang
  • Patent number: 9245984
    Abstract: A reverse blocking semiconductor device includes a base region of a first conductivity type and a body region of a second, complementary conductivity type, wherein the base and body regions form a pn junction. Between the base region and a collector electrode an emitter layer is arranged that includes emitter zones of the second conductivity type and at least one channel of the first conductivity type. The channels extend through the emitter layer between the base region and the collector electrode and reduce the leakage current in a forward blocking state.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: January 26, 2016
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Roman Baburske, Christian Jaeger, Hans-Joachim Schulze
  • Patent number: 9184280
    Abstract: A semiconductor device may include a substrate having a drift region doped to a first conduction type. A trench may be etched into an upper surface of the substrate. A gate may be arranged along side walls of the trench. A gate oxide layer may be between the side walls of the trench and gate and between a bottom surface of the trench and gate. A first source region of the first conduction type may be on the upper surface of the substrate. A second source region of the first conduction type may be on the bottom surface of the trench. A first well region may be between the first source region and drift region, and a second well region may be between the second source region and drift region, the first and second well regions being doped to a second conduction type (electrically opposite to the first conduction type).
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: November 10, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-yong Um, Jai-kwang Shin
  • Patent number: 9153676
    Abstract: An IGBT has layers between emitter and collector sides, including a drift layer, a base layer electrically contacting an emitter electrode and completely separated from the drift layer, first and second source regions arranged on the base layer towards the emitter side and electrically contacting the emitter electrode, and first and second trench gate electrodes. The first trench gate electrodes are separated from the base layer, the first source region and the drift layer by a first insulating layer. A channel is formable between the emitter electrode, the first source region, the base layer and the drift layer. A second insulating layer is arranged on top of the first trench gate electrodes. An enhancement layer separates the base layer from the drift layer. The second trench gate electrode is separated from the base layer, the enhancement layer and the drift layer by a third insulating layer.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: October 6, 2015
    Assignee: ABB TECHNOLOGY AG
    Inventors: Munaf Rahimo, Maxi Andenna, Chiara Corvasce, Arnost Kopta
  • Patent number: 9105487
    Abstract: A super junction semiconductor device includes a substrate layer of a first conductivity type and an epitaxial layer adjoining the substrate layer and including first columns of the first conductivity type and second columns of a second conductivity type. The first and second columns extend along a main crystal direction into the epitaxial layer and have vertical dopant profiles perpendicular to the first surface. The vertical dopant profile of at least one of the first and second columns includes first portions separated by second portions. In each of the first portions a dopant concentration varies by at most 30% of a maximum value within the respective first portion. In the second portions the dopant concentration is lower than in the adjoining first portions. A ratio of a total length of the first portions to a total length of the first and second portions is at least 50%.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: August 11, 2015
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Johannes Laven, Dieter Fuchs, Werner Schustereder, Roman Knoefler
  • Patent number: 9087733
    Abstract: A method is provided for forming SRAM cells with low energy implants. Embodiments include forming deep trenches in a silicon substrate; forming a deep n-well or deep p-well around a bottom of each deep trench; filling the deep trenches with oxide; forming a first or second shallow trench between each pair of adjacent deep trenches; forming a first p-well or first n-well, respectively, above each deep n-well or p-well; forming a second n-well at a bottom of each first shallow trench; forming a p+ region above each second n-well on each side of each first shallow trench; filling the first shallow trenches with oxide; forming a second p-well at a bottom of each second shallow trench; filling the second shallow trenches with oxide; forming a n+ region above each second p-well on each side of each second shallow trench.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: July 21, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Werner Juengling
  • Patent number: 9070790
    Abstract: A vertical semiconductor device has a semiconductor body with a first surface and a second surface substantially parallel to the first surface. A first metallization is arranged on the first surface. A second metallization is arranged on the second surface. In a sectional plane perpendicular to the first surface, the semiconductor body includes an n-doped first semiconductor region in ohmic contact with the second metallization, a plurality of p-doped second semiconductor regions in ohmic contact with the first metallization, and a plurality of p-doped embedded semiconductor regions. The p-doped second semiconductor regions substantially extend to the first surface, are spaced apart from one another and form respective first pn-junctions with the first semiconductor region.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: June 30, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ralf Siemieniec, Jens Peter Konrath
  • Patent number: 9040362
    Abstract: A method of manufacturing a MOS type semiconductor device, includes, before forming a semiconductor functional structure including a necessary MOS gate structure on one principal surface of a silicon semiconductor substrate, in the order recited, a first step of heating the silicon semiconductor substrate in an oxygen-containing atmosphere under heat treatment conditions including a heat treatment temperature of higher than 1,280° C. and a heat treatment time necessary for introducing oxygen up to a solid solution limit concentration in the silicon semiconductor substrate as a whole body; and a second step of holding the silicon semiconductor substrate at a specified temperature in a range from 1,000° C. to 1,200° C. The method achieves small turn-off loss and little variation of ON voltages without controlling a collector layer to a lower concentration than the conventional technology.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: May 26, 2015
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Mitsuhiro Kakefu
  • Patent number: 9041050
    Abstract: In a method of further enhancing the performance of a narrow active cell IE type trench gate IGBT having the width of active cells narrower than that of inactive cells, it is effective to shrink the cells so that the IE effects are enhanced. However, when the cells are shrunk simply, the switching speed is reduced due to increased gate capacitance. A cell formation area of the IE type trench gate IGBT is basically composed of first linear unit cell areas having linear active cell areas, second linear unit cell areas having linear hole collector areas and linear inactive cell areas disposed therebetween.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: May 26, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Hitoshi Matsuura
  • Publication number: 20150137175
    Abstract: An IGBT device includes one or more trench gates disposed over a semiconductor substrate and a floating body region of the first conductivity type disposed between two neighboring trench gates and between a semiconductor substrate and a heavily doped top region of the second conductivity type. A body region of the first conductivity type disposed over the top region has a doping concentration higher than that of the floating body region of the first conductivity type. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Application
    Filed: November 18, 2013
    Publication date: May 21, 2015
    Applicant: Alpha and Omega Semiconductor Incorporated
    Inventor: Jun Hu
  • Publication number: 20150132895
    Abstract: A method for manufacturing a semiconductor device is provided. The semiconductor device includes a cathode region of the diode, a first buffer region adjacent to the cathode region at a rear surface side of a semiconductor substrate, a collector region of the IGBT, and a second buffer region adjacent to the collector region at the rear surface side. The method includes forming the step portion on the front surface so that the thin portion and the thick portion are formed in the semiconductor substrate, and injecting n-type impurities to a range on the front surface extending across the thin and thick portions so that the first buffer region and the second buffer region are formed.
    Type: Application
    Filed: November 10, 2014
    Publication date: May 14, 2015
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Takuma KAMIJO
  • Publication number: 20150123164
    Abstract: A power semiconductor device may include a first conductivity type first semiconductor region; a second conductivity type second semiconductor region formed on an upper portion of the first semiconductor region; a first conductivity type third semiconductor region formed in an upper inner side of the second semiconductor region; a trench gate formed to penetrate through a portion of the first semiconductor region from the third semiconductor region; and a first conductivity type fourth semiconductor region formed below the second semiconductor region while being spaced apart from the trench gate.
    Type: Application
    Filed: May 8, 2014
    Publication date: May 7, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jae Hoon PARK, Jae Kyu SUNG, In Hyuk SONG, Ji Yeon OH, Dong Soo SEO
  • Publication number: 20150123165
    Abstract: A high-voltage insulated gate type power semiconductor device includes a low-concentration first conductivity type base layer; a plurality of trenches selectively formed with large intervals and narrow intervals provided alternately, in a front surface of the low-concentration first conductivity type base layer; a gate insulating film formed on a surface of each of the plurality of trenches; a gate electrode formed inside the gate insulating film; and a second conductivity type base layer selectively formed between the adjacent trenches sharing the narrow interval. The high-voltage insulated gate type power semiconductor device includes a high-concentration first conductivity type source layer selectively formed on a front surface of the second conductivity type base layer.
    Type: Application
    Filed: May 29, 2013
    Publication date: May 7, 2015
    Applicant: KYUSHU INSTITUTE OF TECHNOLOGY
    Inventors: Ichiro Omura, Masahiro Tanaka, Masanori Tsukuda, Yamato Miki
  • Publication number: 20150126000
    Abstract: A method of manufacturing a MOS type semiconductor device, includes, before forming a semiconductor functional structure including a necessary MOS gate structure on one principal surface of a silicon semiconductor substrate, in the order recited, a first step of heating the silicon semiconductor substrate in an oxygen-containing atmosphere under heat treatment conditions including a heat treatment temperature of higher than 1,280° C. and a heat treatment time necessary for introducing oxygen up to a solid solution limit concentration in the silicon semiconductor substrate as a whole body; and a second step of holding the silicon semiconductor substrate at a specified temperature in a range from 1,000° C. to 1,200° C. The method achieves small turn-off loss and little variation of ON voltages without controlling a collector layer to a lower concentration than the conventional technology.
    Type: Application
    Filed: October 10, 2014
    Publication date: May 7, 2015
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Mitsuhiro KAKEFU
  • Patent number: 9024413
    Abstract: A semiconductor device includes an IGBT cell including a second-type doped drift zone, and a desaturation semiconductor structure for desaturating a charge carrier concentration in the IGBT cell. The desaturation structure includes a first-type doped region forming a pn-junction with the drift zone, and two portions of a trench or two trenches arranged in the first-type doped region and beside the IGBT cell in a lateral direction. Each of the two trench portions or each of the two trenches has a wide part below a narrow part. The wide parts confine a first-type doped desaturation channel region of the first-type doped region at least in the lateral direction. The narrow parts confine a first-type doped mesa region of the first-type doped region at least in the lateral direction. The desaturation channel region has a width smaller than the mesa region in the lateral direction, and adjoins the mesa region.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: May 5, 2015
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Hans-Joachim Schulze
  • Publication number: 20150115314
    Abstract: In a semiconductor device, a trench includes a first trench that has an opening portion on a surface of a base layer, and a second trench that is communicated with the first trench and in which a distance between opposed side walls is greater than opposed side walls of the first trench and a bottom portion is located in a drift layer. A wall surface of a connecting portion of the second trench connecting to the first trench is rounded. Therefore, an occurrence of a large electrical field concentration in the vicinity of the connecting portion between the first trench and the second trench can be suppressed. Also, when electrons are supplied from a channel region to the drift layer, it is less likely that a flow direction of the electrons will be sharply changed in the vicinity of the connecting portion. Therefore, an on-state resistance can be reduced.
    Type: Application
    Filed: March 4, 2013
    Publication date: April 30, 2015
    Inventors: Kazuki Arakawa, Masakiyo Sumitomo, Masaki Matsui, Yasushi Higuchi, Kazuhiro Oyama
  • Patent number: 9012954
    Abstract: An Adjustable Field Effect Rectifier uses aspects of MOSFET structure together with an adjustment pocket or region to result in a device that functions reliably and efficiently at high voltages without significant negative resistance, while also permitting fast recovery and operation at high frequency without large electromagnetic interference.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics International B.V.
    Inventors: Alexei Ankoudinov, Vladimir Rodov
  • Patent number: 9006041
    Abstract: A method for manufacturing a bipolar punch-through semiconductor device is disclosed, which includes providing a wafer having a first and a second side, wherein on the first side a high-doped layer of the first conductivity type having constant high doping concentration is arranged; epitaxially growing a low-doped layer of the first conductivity type on the first side; performing a diffusion step by which a diffused inter-space region is created at the inter-space of the layers; creating at least one layer of the second conductivity type on the first side; and reducing the wafer thickness within the high-doped layer on the second side so that a buffer layer is created, which can include the inter-space region and the remaining part of the high-doped layer, wherein the doping profile of the buffer layer decreases steadily from the doping concentration of the high-doped region to the doping concentration of the drift layer.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: April 14, 2015
    Assignee: ABB Technology AG
    Inventors: Munaf Rahimo, Arnost Kopta, Thomas Clausen, Maxi Andenna
  • Patent number: 9000478
    Abstract: A semiconductor apparatus includes a substrate having a device region and a peripheral region located around the device region. A first semiconductor region is formed within the device region, is of a first conductivity type, and is exposed at an upper surface of the substrate. Second-fourth semiconductor regions are formed within the peripheral region. The second semiconductor region is of the first conductivity type, has a lower concentration of the first conductivity type of impurities, is exposed at the upper surface, and is consecutive with the first semiconductor region directly or indirectly. The third semiconductor region is of a second conductivity type, is in contact with the second semiconductor region from an underside, and is an epitaxial layer. The fourth semiconductor region is of the second conductivity type, has a lower concentration of the second conductivity type of impurities, and is in contact with the third semiconductor region from an underside.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: April 7, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Masaru Senoo
  • Patent number: 8999789
    Abstract: A super-junction trench MOSFET with a short termination area is disclosed, wherein the short termination area comprising a charge balance region and a channel stop region formed near a top surface of an epitaxial layer with a trenched termination contact penetrating therethrough.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: April 7, 2015
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8994066
    Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: March 31, 2015
    Assignee: Rohm Co., Ltd.
    Inventor: Kenichi Yoshimochi
  • Patent number: 8994086
    Abstract: The invention provides a semiconductor device which is non-volatile, easily manufactured, and can be additionally written. A semiconductor device of the invention includes a plurality of transistors, a conductive layer which functions as a source wiring or a drain wiring of the transistors, and a memory element which overlaps one of the plurality of transistors, and a conductive layer which functions as an antenna. The memory element includes a first conductive layer, an organic compound layer and a phase change layer, and a second conductive layer stacked in this order. The conductive layer which functions as an antenna and a conductive layer which functions as a source wiring or a drain wiring of the plurality of transistors are provided on the same layer.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: March 31, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiroko Abe, Yukie Nemoto, Ryoji Nomura, Mikio Yukawa
  • Publication number: 20150087116
    Abstract: This invention discloses a semiconductor power device formed in a semiconductor substrate includes rows of multiple horizontal columns of thin layers of alternate conductivity types in a drift region of the semiconductor substrate where each of the thin layers having a thickness to enable a punch through the thin layers when the semiconductor power device is turned on. In a specific embodiment the thickness of the thin layers satisfying charge balance equation q*ND*WN=q*NA*WP and a punch through condition of WP<2*WD*[ND/(NA+ND)] where ND and WN represent the doping concentration and the thickness of the N type layers 160, while NA and WP represent the doping concentration and thickness of the P type layers; WD represents the depletion width; and q represents an electron charge, which cancel out. This device allows for a near ideal rectangular electric field profile at breakdown voltage with sawtooth like ridges.
    Type: Application
    Filed: September 25, 2013
    Publication date: March 26, 2015
    Inventor: Madhur Bobde
  • Publication number: 20150087117
    Abstract: Disclosed herein is a power semiconductor device including: a base substrate having one surface and the other surface and formed of a first conductive type drift layer; a first conductive type diffusion layer formed on one surface of the base substrate and having a concentration higher than that of the first conductive type drift layer; and a trench formed so as to penetrate through the second conductive type well layer and the first conductive type diffusion layer from one surface of the base substrate including the second conductive type well layer in a thickness direction.
    Type: Application
    Filed: December 3, 2014
    Publication date: March 26, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: In Hyuk SONG, Jae Hoon Park, Dong Soo Seo