Having Field Effect Structure Patents (Class 438/135)
  • Patent number: 11367785
    Abstract: A lateral insulated gate bipolar transistor (IGBT) with a low turn-on overshoot current is provided to reduce a peak value of a current flowing through a device during turn-on of a second gate pulse while preventing a current capability and a withstand voltage capability from being degraded. The lateral IGBT includes: a buried oxygen arranged on a P-type substrate, an N-type drift region arranged on the buried oxygen, on which a P-type body region and an N-type buffer region are arranged, a P-type collector region arranged in the N-type buffer region, a field oxide layer arranged above the N-type drift region, a P-type well region arranged in the P-type body region, and a P-type emitter region and an emitter region arranged in the P-type well region, where inner boundaries of the foregoing 4 regions are synchronously recessed to form a pinch-off region. A gate oxide layer is arranged on a surface of the P-type body region, and a polysilicon gate is arranged on the gate oxide layer.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: June 21, 2022
    Assignee: SOUTHEAST UNIVERSITY
    Inventors: Jing Zhu, Ankang Li, Long Zhang, Weifeng Sun, Shengli Lu, Longxing Shi
  • Patent number: 11282840
    Abstract: Isolation between vertical thyristor memory cells in an array is improved with isolation regions between the vertical thyristor memory cells. The isolation regions are formed by electrically isolating cores surrounded by insulating material, such as silicon dioxide, in trenches between the memory cells. The electrically isolating cores may be tubes of air or conducting rods. Methods of constructing the isolation regions in a processes for manufacturing vertical thyristor memory cell arrays are also disclosed.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: March 22, 2022
    Assignee: Kilopass Technology, Inc.
    Inventors: Harry Luan, Valery Axelrad
  • Patent number: 11222961
    Abstract: A semiconductor device is disclosed, a substrate structure; a raised source region; a raised drain region; a separation region disposed laterally between the raised source region and the raised drain region; a gate structure, disposed between the raised source region and the raised drain region and above a part of the separation region, the gate structure being spaced apart from the drain region and defining a drain extension region therebetween; a dummy gate structure in the drain extension region; an epitaxial layer, disposed above and in contact with the substrate structure and forming the raised source region, the raised drain region, and a raised region between the gate structure and the dummy gate structure, wherein the raised region between the gate structure and the dummy gate structure is relatively lightly doped to a conductivity of a second conductivity type which is opposite the first conductivity type.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: January 11, 2022
    Assignee: NXP B.V.
    Inventors: Viet Dinh, Guido Sasse, Paul Grudowski
  • Patent number: 10629441
    Abstract: A photoresist is applied to a front surface of a semiconductor wafer rotating at a predetermined rotational speed and a photoresist film having a predetermined thickness is formed and dried. Next, a chemical is dripped while the semiconductor wafer is rotated at the predetermined rotational speed or less, whereby an edge part of the photoresist film is dissolved and removed by the chemical while the predetermined thickness of the photoresist film is maintained. A predetermined pattern is transferred to the photoresist film by exposure and development. After the development, without performing UV curing or post-bake, the photoresist film is used as a mask and helium irradiation having a range of 8 ?m or greater from the front surface of the semiconductor wafer is performed. Thus, a predetermined impurity may be implanted with good positioning accuracy in a predetermined region, using the photoresist film as a mask and cost may be reduced.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: April 21, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Naoko Kodama
  • Patent number: 10037895
    Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: July 31, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michel J. Abou-Khalil, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam, Robert R. Robison
  • Patent number: 10006942
    Abstract: A board may include a first set of board contact pads arranged on a first side of the board, the pads configured to connect to circuit pads of a circuit under test, the positions of the pads matching to the positions of the circuit pads; a fan-out region on the first side of the board including fan-out contact pads configured to at least one of receive a test signal and provide a measurement signal; at least one contact pad connecting to at least one pad of the first set of board pads; and a second set of board contact pads on a second side of the board, the second set of board pads configured to connect to test board pads of a test board; positions of the pads matching to the positions of the test board pads; a pad connecting to a pad of the first set of board pads.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: June 26, 2018
    Assignee: INTEL IP CORPORATION
    Inventors: Benjamin Orr, Harald Gossner
  • Patent number: 9899370
    Abstract: This document discusses, among other things, an auxiliary self-protecting transistor circuit, system, and method configured to protect a complementary metal-oxide semiconductor (CMOS) transistor. The auxiliary self-protecting transistor circuit can include an ESD device including a gate terminal, a drain terminal, and a source terminal. The ESD device is configured to be coupled to an isolation region of a complementary metal-oxide semiconductor (CMOS) transistor, and can provide a discharge path between the isolation region of the CMOS transistor and the source terminal of the ESD device. The isolation region of the CMOS transistor can include a blocking junction, such as an n-doped isolation well (niso), a p-type well (pwell), or one or more other blocking junctions.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: February 20, 2018
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Kenneth P. Snowdon, Taeghyun Kang, Alister Young
  • Patent number: 9741554
    Abstract: A method of manufacturing a semiconductor device includes a semiconductor region forming process, a cleaning process, a surface roughness uniformizing process, and an electrode forming process. As the semiconductor region forming process, semiconductor regions are formed such that a plurality of semiconductor regions with different ion injection amounts are exposed on one principal surface of a semiconductor substrate. As the cleaning process, after the semiconductor region forming process, a cleaning using hydrofluoric acid is performed on the one principal surface of the semiconductor substrate. As the surface roughness uniformizing process, after the cleaning process, the surface roughness of the one principal surface of the semiconductor substrate is uniformized. As the electrode forming process, after the surface roughness uniformizing process, electrodes are formed on the one principal surface of the semiconductor substrate.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: August 22, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Satoru Kameyama, Masaki Ajioka, Shuhei Oki
  • Patent number: 9716174
    Abstract: A semiconductor stack of a FinFET in fabrication includes a bulk silicon substrate, a selectively oxidizable sacrificial layer over the bulk substrate and an active silicon layer over the sacrificial layer. Fins are etched out of the stack of active layer, sacrificial layer and bulk silicon. A conformal oxide deposition is made to encapsulate the fins, for example, using a HARP deposition. Relying on the sacrificial layer having a comparatively much higher oxidation rate than the active layer or substrate, selective oxidization of the sacrificial layer is performed, for example, by annealing. The presence of the conformal oxide provides structural stability to the fins, and prevents fin tilting, during oxidation. Selective oxidation of the sacrificial layer provides electrical isolation of the top active silicon layer from the bulk silicon portion of the fin, resulting in an SOI-like structure. Further fabrication may then proceed to convert the active layer to the source, drain and channel of the FinFET.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: July 25, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Murat Kerem Akarvardar, Jody A. Fronheiser, Ajey Poovannummoottil Jacob
  • Patent number: 9385211
    Abstract: A p+ collector layer is provided in a rear surface of a semiconductor substrate which will be an n? drift layer and an n+ field stop layer is provided in a region which is deeper than the p+ collector layer formed on the rear surface side. A front surface element structure is formed on the front surface of the semiconductor substrate and then protons are radiated to the rear surface of the semiconductor substrate at an acceleration voltage corresponding to the depth at which the n+ field stop layer is formed. A first annealing process is performed at an annealing temperature corresponding to the proton irradiation to change the protons into donors, thereby forming a field stop layer. Then, annealing is performed using annealing conditions suitable for the conditions of a plurality of proton irradiation processes to recover each crystal defect formed by each proton irradiation process.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: July 5, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Masayuki Miyazaki, Takashi Yoshimura, Hiroshi Takishita, Hidenao Kuribayashi
  • Patent number: 9240456
    Abstract: A method includes forming on a first main surface of a semiconductor wafer of a first conduction type, a gate electrode of a semiconductor element, an edge termination region for forming a breakdown voltage of the semiconductor element, and a first semiconductor region of a second conduction type which surrounds the semiconductor element and the edge termination region. A groove may be formed to reach the first semiconductor region from a second main surface of the semiconductor wafer. The groove is formed so that a portion of the semiconductor wafer, that forms an outer circumferential end of the semiconductor wafer, remains and the groove is further towards a center of the semiconductor wafer than the outer circumferential end. A third semiconductor region of the second conduction type is on a side wall of the groove and electrically connects the first semiconductor region and a second semiconductor region.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: January 19, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroki Wakimoto, Masaaki Ogino
  • Patent number: 9166017
    Abstract: Techniques capable of improving the yield of IGBTs capable of reducing steady loss, turn-off time, and turn-off loss are provided. Upon formation of openings in an interlayer insulting film formed on a main surface of a substrate, etching of a laminated insulating film of a PSG film and an SOG film and a silicon oxide film is once stopped at a silicon nitride film. Then, the silicon nitride film and the silicon oxide film are sequentially etched to form the openings. As a result, the openings are prevented from penetrating through an n-type source layer and a p+-type emitter layer having a thickness of 20 to 100 nm and reaching the substrate.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: October 20, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Daisuke Arai, Yoshito Nakazawa, Ikuo Hara, Tsuyoshi Kachi, Yoshinori Hoshino, Tsuyoshi Tabata
  • Patent number: 9166015
    Abstract: A 3D semiconductor integrated circuit having a gate pick-up line and a method of manufacturing the same, wherein the semiconductor integrated circuit includes a plurality of active pillars formed in a gate pick-up region, buffer layers formed on the respective active pillars in the gate pick-up region, gates each surrounding an outer circumference of the corresponding active pillar and the corresponding buffer layer, and a gate pick-up line electrically coupled to the gates.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: October 20, 2015
    Assignee: SK Hynix Inc.
    Inventors: Isaac Chung, Jin Ha Kim
  • Patent number: 9153675
    Abstract: A power semiconductor includes a semiconductor substrate, a metal oxide semiconductor layer, a N-type buffer layer and a P-type injection layer. The semiconductor substrate has a first surface and a second surface. The metal oxide semiconductor layer is formed on the first surface for defining a N-type drift layer of the semiconductor substrate. The N-type buffer layer is formed on the second surface through ion implanting, and the P-type injection layer is formed on the N-type buffer layer through ion implanting. By utilizing the semiconductor substrate having drift layer and forming the N-type buffer layer and the P-type injection layer on the second surface of the semiconductor substrate through ion implanting, the ion concentration is adjustable. As a result, the electron hole injection efficiency and the width of depletion region are easily adjusted, the fabricating processes are simplified, and the fabricating time and cost are reduced.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: October 6, 2015
    Assignee: MOSEL VITALEC INC.
    Inventors: Chien-Ping Chang, Chien-Chung Chu, I-Hsien Tang, Chon-Shin Jou, Mao-Song Tseng, Shin-Chi Lai
  • Patent number: 9123805
    Abstract: Aspects of the present disclosure describe a trench MOSFET with a channel length that may be controlled by counterdoping the body-drain junction to form a straggle region adjacent to the trenches. The channel length is defined between the straggle region at the bottom and a source region at the top. Both of the straggle region and the source region are of the same conductivity type though they may be different ion species.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: September 1, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Sik Lui
  • Publication number: 20150144989
    Abstract: A power semiconductor device may include: a first semiconductor region having a first conductivity type; a second semiconductor region having a second conductivity type and formed on the first semiconductor region; a third semiconductor region having the first conductivity type and formed in an upper portion of the second semiconductor region; a trench gate formed to penetrate from the third semiconductor region to the first semiconductor region, having a gate insulating layer formed on a surface thereof, and filled with a conductive material; and a fourth semiconductor region having the second conductivity type and formed to penetrate through the second semiconductor region.
    Type: Application
    Filed: April 30, 2014
    Publication date: May 28, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Dong Soo SEO, In Hyuk SONG, Jae Hoon PARK, Kee Ju UM, Chang Su JANG
  • Publication number: 20150140742
    Abstract: Some embodiments include methods of forming gated devices. An upper region of a semiconductor material is patterned into a plurality of walls that extend primarily along a first direction. The walls are spaced from one another by trenches that extend primarily along the first direction. Steps are formed along bottoms of the trenches. Gatelines are formed on the steps and along lower regions of the walls. After the gatelines are formed, the walls are patterned into spaced-apart pillars that have bottom regions below the gatelines. In some embodiments the gated devices may be transistors or thyristors.
    Type: Application
    Filed: January 21, 2015
    Publication date: May 21, 2015
    Inventors: Carlo Pozzi, Marcello Mariani, Gianpietro Carnevale
  • Publication number: 20150137145
    Abstract: The invention provides an ultra-low-on-resistance, excellent-reliability semiconductor device that can finely be processed using SiC and a semiconductor device producing method.
    Type: Application
    Filed: January 28, 2015
    Publication date: May 21, 2015
    Inventors: Hiroshi Kono, Takashi Shinohe, Makoto Mizukami
  • Publication number: 20150140741
    Abstract: A device includes a dielectric layer, and a heavily doped semiconductor layer over the dielectric layer. The heavily doped semiconductor layer is of a first conductivity type. A semiconductor region is over the heavily doped semiconductor layer, wherein the semiconductor region is of a second conductivity type opposite the first conductivity type. A Lateral Insulated Gate Bipolar Transistor (LIGBT) is disposed at a surface of the semiconductor region.
    Type: Application
    Filed: December 3, 2014
    Publication date: May 21, 2015
    Inventors: Jhy-Jyi Sze, Biay-Cheng Hseih, Shou-Gwo Wuu
  • Patent number: 9034698
    Abstract: A semiconductor device manufacturing method includes exciting a processing gas containing a HBr gas and a Cl2 gas within a processing chamber that accommodates a target object including a substrate, regions made of silicon, which are protruded from the substrate and arranged to form a gap, a metal layer formed to cover the regions, a polycrystalline silicon layer formed on the metal layer, and an organic mask formed on the polycrystalline silicon layer. The Cl2 gas is supplied at a flow rate of about 5% or more to about 10% or less with respect to a flow rate of the HBr gas in the processing gas.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: May 19, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Toshihisa Ozu, Shota Yoshimura, Hiroto Ohtake, Kosuke Kariu, Takashi Tsukamoto
  • Publication number: 20150124360
    Abstract: Described is a low power clamp or driver comprising: an inverter; and a silicon controlled rectifier (SCR) embedded in the inverter such that the SCR is part of the inverter. The clamp offers improved conductance per area and lower leakage current compared to the traditional PMOS-based active rail clamps. The clamp or driver combines a trigger circuit with the inverter-embedded SCR for maximum area efficiency. The clamp or driver also results in less stringent requirements for power ramp rates.
    Type: Application
    Filed: November 1, 2013
    Publication date: May 7, 2015
    Inventors: Nathan D. Jack, Steven S. Poon
  • Patent number: 9018048
    Abstract: A process for manufacturing a semiconductor device, wherein a semiconductor layer is formed on a body of semiconductor material; a first mask is formed on the semiconductor layer; a first conductive region is implanted in the body using the first mask; a second mask is formed laterally and complementarily to the first mask, at least in a projection in a plane parallel to the surface of the body; a second conductive region is implanted in the body using the second mask, in an adjacent and complementary position to the first conductive region; spacers are formed on the sides of the second mask region, to form a third mask aligned to the second mask; and, using the third mask, portions of the semiconductor layer are removed to form a gate region.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: April 28, 2015
    Assignee: STMicroelectronics S.r.l.
    Inventor: Francesco Lizio
  • Patent number: 9018049
    Abstract: A method for manufacturing an IGBT includes: forming oxide layers on the surfaces of the front and the back of an N-type substrate; forming a buffer layer in the surface of the back of the N-type substrate; forming protection layers on the surfaces of the oxide layers; removing the protection layer and the oxide layer overlying the front of the N-type substrate while reserving the oxide layer and the protection layer on the back of the N-type substrate for protection of the back of the N-type substrate; forming a front IGBT structure and applying a protection film on the surface of the front IGBT structure for protection of the front IGBT structure; removing the protection layer and the oxide layer overlying the back of the N-type substrate; forming a back IGBT structure and a back metal layer; and removing the protection film overlying the surface of the front IGBT structure.
    Type: Grant
    Filed: November 29, 2013
    Date of Patent: April 28, 2015
    Assignees: Peking University Founder Group Co., Ltd., Founder Microelectronics International Co., Ltd.
    Inventor: Guangran Pan
  • Publication number: 20150111347
    Abstract: Electronic device structures including semiconductor ledge layers for surface passivation and methods of manufacturing the same are disclosed. In one embodiment, the electronic device includes a number of semiconductor layers of a desired semiconductor material having alternating doping types. The semiconductor layers include a base layer of a first doping type that includes a highly doped well forming a first contact region of the electronic device and one or more contact layers of a second doping type on the base layer that have been etched to form a second contact region of the electronic device. The etching of the one or more contact layers causes substantial crystalline damage, and thus interface charge, on the surface of the base layer. In order to passivate the surface of the base layer, a semiconductor ledge layer of the semiconductor material is epitaxially grown on at least the surface of the base layer.
    Type: Application
    Filed: June 20, 2014
    Publication date: April 23, 2015
    Inventors: Qingchun Zhang, Anant Kumar Agarwal
  • Patent number: 9012954
    Abstract: An Adjustable Field Effect Rectifier uses aspects of MOSFET structure together with an adjustment pocket or region to result in a device that functions reliably and efficiently at high voltages without significant negative resistance, while also permitting fast recovery and operation at high frequency without large electromagnetic interference.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics International B.V.
    Inventors: Alexei Ankoudinov, Vladimir Rodov
  • Patent number: 9012955
    Abstract: A MOS transistor protected against overvoltages formed in an SOI-type semiconductor layer arranged on an insulating layer itself arranged on a semiconductor substrate including a lateral field-effect control thyristor formed in the substrate at least partly under the MOS transistor, a field-effect turn-on region of the thyristor extending under at least a portion of a main electrode of the MOS transistor and being separated therefrom by said insulating layer, the anode and the cathode of the thyristor being respectively connected to the drain and to the source of the MOS transistor, whereby the thyristor turns on in case of a positive overvoltage between the drain and the source of the MOS transistor.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics SA
    Inventor: Pascal Fonteneau
  • Patent number: 9006781
    Abstract: Apparatus and methods for monolithic data conversion interface protection are provided herein. In certain implementations, a protection device includes a first silicon controlled rectifier (SCR) and a first diode for providing protection between a signal node and a power high supply node, a second SCR and a second diode for providing protection between the signal node and a power low supply node, and a third SCR and a third diode for providing protection between the power high supply node and the power low supply node. The SCR and diode structures are integrated in a common circuit layout, such that certain wells and active regions are shared between structures. Configuring the protection device in this manner enables in-suit input/output interface protection using a single cell. The protection device is suitable for monolithic data conversion interface protection in sub 3V operation.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: April 14, 2015
    Assignee: Analog Devices, Inc.
    Inventors: Javier Alejandro Salcedo, Srivatsan Parthasarathy
  • Patent number: 9006780
    Abstract: Between a back surface electrode and an electrode, a first thyristor is formed of fifth and seventh semiconductor regions, a substrate region, first and second semiconductor regions and a third semiconductor region, and a second thyristor is formed of the second and first semiconductor regions, the substrate region, the seventh and fifth semiconductor regions and a sixth semiconductor region. Depths from the surface of the semiconductor substrate to bottom surfaces of the third and fourth semiconductor regions are 20 ?m or more. The second semiconductor region with a high impurity concentration is enclosed by the first semiconductor region with a low impurity concentration, and a difference between a depth from the surface of the semiconductor substrate to the bottom of the second semiconductor region and a depth from the surface of the semiconductor substrate to the bottom of the first semiconductor region is less than 10 ?m.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: April 14, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Aki Moroda, Kosuke Miyazaki
  • Publication number: 20150091052
    Abstract: A semiconductor device includes an insulated gate bipolar transistor (IGBT) arrangement. The IGBT arrangement includes a first configuration region of emitter-side insulated gate bipolar transistor structures and a second configuration region of emitter-side insulated gate bipolar transistor structures. The first configuration region and the second configuration region are arranged at a main surface of a semiconductor substrate of the semiconductor device. Further, the IGBT arrangement includes a collector layer and a drift layer. The collector layer is arranged at a backside surface of the semiconductor substrate and the drift layer is arranged between the collector layer and the emitter-side IGBT structures of the first configuration region and the second configuration region. Additionally, the collector layer includes at least a first doping region laterally adjacent to a second doping region.
    Type: Application
    Filed: September 30, 2013
    Publication date: April 2, 2015
    Inventors: Johannes Georg Laven, Hans-Joachim Schulze, Roman Baburske
  • Publication number: 20150091051
    Abstract: A semiconductor device includes an insulated gate bipolar transistor (IGBT) arrangement. The IGBT arrangement includes a carrier confinement reduction region laterally arranged between a cell region and a sensitive region. The IGBT arrangement is configured or formed so that the cell region has a first average density of free charge carriers in an on-state of the IGBT arrangement, the carrier confinement reduction region has a second average density of free charge carriers in the on-state of the IGBT arrangement and the sensitive region has a third average density of free charge carriers in the on-state of the IGBT arrangement. The first average density of free charge carriers is larger than the second average density of free charge carriers and the second average density of free charge carriers is larger than the third average density of free charge carriers.
    Type: Application
    Filed: September 30, 2013
    Publication date: April 2, 2015
    Inventors: Johannes Georg Laven, Hans-Joachim Schulze, Roman Baburske
  • Patent number: 8994105
    Abstract: A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: March 31, 2015
    Assignee: Azure Silicon LLC
    Inventor: Jacek Korec
  • Publication number: 20150076555
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate; and a body region and a drift region formed in the semiconductor substrate. The semiconductor device also includes a bulk region and a source region formed in the body region. Further, the semiconductor device includes a drain region and a first shallow trench isolation structure having a ladder-like bottom formed in the drift region. Further, the semiconductor device also includes a gate structure spanning over an edge of the body region and an edge of the drift region formed on the semiconductor substrate and covering a portion of the first shallow trench isolation structure.
    Type: Application
    Filed: February 18, 2014
    Publication date: March 19, 2015
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Guangli YANG, Qianrong YU, Ming WANG, Xianyong PU
  • Patent number: 8980699
    Abstract: Semiconductor devices including a plurality of thyristor-based memory cells, each having a cell size of 4F2, and methods for forming the same are provided. The thyristor-based memory cells each include a thyristor having vertically superposed regions of alternating dopant types, and a control gate. The control gate may be electrically coupled with one or more of the thyristors and may be operably coupled to a voltage source. The thyristor-based memory cells may be formed in an array on a conductive strap, which may function as a cathode or a data line. A system may be formed by integrating the semiconductor devices with one or more memory access devices or conventional logic devices, such as a complementary metal-oxide-semiconductor (CMOS) device.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: March 17, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Sanh D. Tang
  • Publication number: 20150060936
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device comprises a plurality of trenches formed at a top portion of the semiconductor substrate extending laterally across the semiconductor substrate along a longitudinal direction each having a nonlinear portion comprising a sidewall perpendicular to a longitudinal direction of the trench and extends vertically downward from a top surface to a trench bottom surface. The semiconductor power device further includes a trench bottom dopant region disposed below the trench bottom surface and a sidewall dopant region disposed along the perpendicular sidewall wherein the sidewall dopant region extends vertically downward along the perpendicular sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.
    Type: Application
    Filed: August 27, 2013
    Publication date: March 5, 2015
    Inventors: Yongping Ding, Sik Lui, Madhur Bobde, Lei Zhang, Jongoh Kim, John Chen
  • Publication number: 20150060939
    Abstract: An electrostatic discharge protection circuit is disclosed. A method of manufacturing a semiconductor structure includes forming a semiconductor controlled rectifier including a first plurality of fingers between an n-well body contact and an anode in an n-well, and a second plurality of fingers between a p-well body contact and a cathode in a p-well.
    Type: Application
    Filed: August 28, 2013
    Publication date: March 5, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James P. DI SARRO, Robert J. GAUTHIER, JR., Tom C. LEE, Junjun LI, Souvick MITRA, Christopher S. PUTNAM
  • Patent number: 8969875
    Abstract: The present invention relates to a thin film transistor substrate and method for fabricating the same which can secure an alignment margin and reduce the number of mask steps. A thin transistor substrate according to the present invention includes a gate line and a data line crossing each other to define a pixel, a gate metal pattern under the data line, a thin film transistor having a gate electrode, a source electrode and a drain electrode in the pixel, and a pixel electrode connected to the drain electrode of the thin film transistor by a connection electrode, wherein the data line has a plurality of first slits to disconnect the gate metal pattern from the gate line.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: March 3, 2015
    Assignee: LG Display Co., Ltd.
    Inventor: Seung Hee Nam
  • Patent number: 8962397
    Abstract: At least one N-well implant having a different doping level is formed in a silicon substrate by first etching the substrate with an alignment target for aligning future process masks thereto. This alignment target is outside of any active device area. By using at least one N-well implant having a different doping level in combination with the substrate, a graded junction in the drift area of a metal oxide semiconductor (MOS) field effect transistor (FET) can be created and a pseudo Ldd structure may be realized thereby.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: February 24, 2015
    Assignee: Microchip Technology Incorporated
    Inventors: Gregory Dix, Leighton E. McKeen, Ian Livingston, Roger Melcher, Rohan Braithwaite
  • Patent number: 8963199
    Abstract: An N type well (NW) is formed over a prescribed depth from a main surface of a semiconductor substrate (SUB), and a P type well (PW) and an N type drain region (ND) are formed in the N type well (NW). An N type source region (NS), an N+ type source region (NNS), and a P+ type impurity region (BCR) are formed in the P type well (PW). The N type source region (NS) is formed on a region situated directly below the N+ type source region (NNS), and not on a region situated directly below the P+ type impurity region (BCR), and the P+ type impurity region (BCR) is in direct contact with the P type well (PW).
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: February 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Shunji Kubo
  • Patent number: 8956925
    Abstract: Device structures and design structures for a silicon controlled rectifier, as well as methods for fabricating a silicon controlled rectifier. The device structure includes first and second layers of different materials disposed on a top surface of a device region containing first and second p-n junctions of the silicon controlled rectifier. The first layer is laterally positioned on the top surface in vertical alignment with the first p-n junction. The second layer is laterally positioned on the top surface of the device region in vertical alignment with the second p-n junction. The material comprising the second layer has a higher electrical resistivity than the material comprising the first layer.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: February 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kiran V. Chatty, Robert J. Gauthier, Jr., Junjun Li, Alain Loiseau
  • Patent number: 8946001
    Abstract: An electrostatic discharge (ESD) protection circuit includes a first array of transistors, having source and drain doped with a first type of material, arranged in parallel in a first block, and a second array of transistors, having source and drain doped with the first type of material, arranged in parallel in a second block. The ESD protection circuit also includes an active region between the first and second array of transistors doped with a second type of material that is complementary to the first type of material.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: February 3, 2015
    Assignee: Altera Corporation
    Inventors: Jeffrey T. Watt, Antonio Gallerano
  • Publication number: 20150031174
    Abstract: A method for manufacturing an IGBT includes: forming oxide layers on the surfaces of the front and the back of an N-type substrate; forming a buffer layer in the surface of the back of the N-type substrate; forming protection layers on the surfaces of the oxide layers; removing the protection layer and the oxide layer overlying the front of the N-type substrate while reserving the oxide layer and the protection layer on the back of the N-type substrate for protection of the back of the N-type substrate; forming a front IGBT structure and applying a protection film on the surface of the front IGBT structure for protection of the front IGBT structure; removing the protection layer and the oxide layer overlying the back of the N-type substrate; forming a back IGBT structure and a back metal layer; and removing the protection film overlying the surface of the front IGBT structure.
    Type: Application
    Filed: November 29, 2013
    Publication date: January 29, 2015
    Applicants: Founder Microelectronics International Co., Ltd., Peking University Founder Group Co., Ltd.
    Inventor: Guangran Pan
  • Publication number: 20150028385
    Abstract: The disclosed lateral bipolar transistor is manufactured by a manufacturing process of self-alignedly implanting an impurity to a gate electrode and thermally diffusing the impurity to form a base layer and an emitter layer. The gate electrode is utilized as an independent fourth terminal in addition to base, emitter, and collector terminals, whereby hfe can be controlled and enhanced by a gate potential. Accordingly, the present invention can provide a bipolar transistor that is hardly affected by a manufacturing variation, or that can be corrected by the gate terminal, and that has a high gain.
    Type: Application
    Filed: July 29, 2014
    Publication date: January 29, 2015
    Inventors: Tomoyuki Miyoshi, Takayuki Ooshima, Youhei Yanagida
  • Publication number: 20150014742
    Abstract: Depth of a termination p base region provided in a termination portion of an active region close to an edge termination structure portion is more than depth of a p-type base region provided inside the termination p base region. An n-type high-concentration region is provided from one main surface of the semiconductor substrate in the entire surface layer of one surface of a semiconductor substrate within a depth of 20 ?m or less below the bottom of the termination p base region. Ratio of the impurity concentration n1 of the n-type high-concentration region (1c) to the impurity concentration n2 of an n? drift region satisfies 1.0<n1/n2?5.0. Reverse leakage current when operation temperature of an element is high can be reduced and trade-off between on-state voltage and switching loss can be improved. Rising peak voltage of collector voltage when a semiconductor device is off is reduced.
    Type: Application
    Filed: October 3, 2014
    Publication date: January 15, 2015
    Inventor: Hong-fei LU
  • Publication number: 20150008481
    Abstract: The invention generally relates to a lateral power semiconductor transistor for example in integrated circuits. In particular the invention relates to Lateral Insulated Gate Bipolar Transistors or other lateral bipolar devices such as PIN diodes. The invention also generally relates to a method of increasing switching speed of a lateral bipolar power semiconductor transistor. There is provided a lateral bipolar power semiconductor transistor comprising a first floating semiconductor region of the first conductivity type located laterally spaced to an anode/drain region and a second floating semiconductor region of the second conductivity type located laterally adjacent the first floating semiconductor region, and a floating electrode placed above and in direct contact to the first and second floating semiconductor regions.
    Type: Application
    Filed: July 2, 2013
    Publication date: January 8, 2015
    Inventors: Vasantha PATHIRANA, Nishad UDUGAMPOLA, Tanya TRAJKOVIC
  • Publication number: 20150008446
    Abstract: A method of manufacturing a semiconductor device is presented. The method includes providing a semiconductor layer comprising silicon carbide, wherein the semiconductor layer comprises a first region doped with a first dopant type. The method further includes implanting the semiconductor layer with a second dopant type using a single implantation mask and a substantially similar implantation dose to form a second region and a junction termination extension (JTE) in the semiconductor layer, wherein the implantation dose is in a range from about 2×1013 cm?2 to about 12×1013 cm?2. Semiconductor devices are also presented.
    Type: Application
    Filed: July 2, 2013
    Publication date: January 8, 2015
    Inventors: Peter Almern Losee, Alexander Viktorovich Bolotnikov, Stacey Joy Kennerly
  • Patent number: 8927347
    Abstract: A semiconductor device includes: an n?-type base layer; a p-type base layer formed in a part of a front surface portion of the n?-type base layer; an n+-type source layer formed in a part of a front surface portion of the p-type base layer; a gate insulating film formed on the front surface of the p-type base layer between the n+-type source layer and the n?-type base layer; a gate electrode that faces the p-type base layer through the gate insulating film; a p-type column layer formed continuously from the p-type base layer in the n?-type base layer; a p+-type collector layer formed in a part of a rear surface portion of the n?-type base layer; a source electrode electrically connected to the n+-type source layer; and a drain electrode electrically connected to the n?-type base layer and to the p+-type collector layer.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: January 6, 2015
    Assignee: Rohm Co., Ltd.
    Inventors: Toshio Nakajima, Syoji Higashida
  • Patent number: 8928032
    Abstract: A method includes growing an epitaxy semiconductor layer over a semiconductor substrate. The epitaxy semiconductor layer is of a first conductivity type. A Lateral Insulated Gate Bipolar Transistor (LIGBT) is formed at a front surface of the epitaxy semiconductor layer. After the LIGBT is formed, a backside thinning is performed to remove the semiconductor substrate. An implantation is performed from a backside of the epitaxy semiconductor layer to form a heavily doped semiconductor layer. The heavily doped semiconductor layer is of a second conductivity type opposite the first conductivity type.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jhy-Jyi Sze, Biay-Cheng Hseih, Shou-Gwo Wuu
  • Publication number: 20150004757
    Abstract: A silicon carbide substrate includes: an n type drift layer having a first surface and a second surface opposite to each other; a p type body region provided in the first surface of the n type drift layer; and an n type emitter region provided on the p type body region and separated from the n type drift layer by the p type body region. A gate insulating film is provided on the p type body region so as to connect the n type drift layer and the n type emitter region to each other. A p type Si collector layer is directly provided on the silicon carbide substrate to face the second surface of the n type drift layer.
    Type: Application
    Filed: September 18, 2014
    Publication date: January 1, 2015
    Inventors: Keiji Wada, Toru Hiyoshi
  • Patent number: 8921888
    Abstract: A method for fabricating a semiconductor device includes the following steps. First, a semiconductor substrate is provided, and a first region, a second region and a third region are defined thereon. Then, a first well having a first conductive type is formed in the semiconductor substrate of the first region and the second region, respectively. A semiconductor layer partially overlapping the first well of the second region is formed. Furthermore, a second well having a second conductive type is formed in the semiconductor substrate of the third region and the first well of the second region respectively, where the second well of the second region is disposed underneath the semiconductor layer.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: December 30, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Yuan-Hsiang Chang, Sung-Bin Lin
  • Publication number: 20140374793
    Abstract: A p+ collector layer is provided in a rear surface of a semiconductor substrate which will be an n? drift layer and an n+ field stop layer is provided in a region which is deeper than the p+ collector layer formed on the rear surface side. A front surface element structure is formed on the front surface of the semiconductor substrate and then protons are radiated to the rear surface of the semiconductor substrate at an acceleration voltage corresponding to the depth at which the n+ field stop layer is formed. A first annealing process is performed at an annealing temperature corresponding to the proton irradiation to change the protons into donors, thereby forming a field stop layer. Then, annealing is performed using annealing conditions suitable for the conditions of a plurality of proton irradiation processes to recover each crystal defect formed by each proton irradiation process.
    Type: Application
    Filed: March 29, 2013
    Publication date: December 25, 2014
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Masayuki Miyazaki, Takashi Yoshimura, Hiroshi Takishita, Hidenao Kuribayashi