Abstract: A method of arranging a multiplicity of LEDs in packaging units includes defining a desired range for at least one photometric measurement variable for each of the packaging units; selecting an LED from the multiplicity of LEDs not yet arranged in one of the packaging units; measuring the at least one photometric measurement variable for the selected LED; equipping one of the packaging units containing fewer than N?1 LEDs with the selected LED; storing a measured value and a position of the selected LED in the packaging unit in a memory; repeating until the packaging units are equipped with N?1 LEDs; repeating and calculating the average value of the photometric measurement variable, equipping a packaging unit for which the calculated average value of the variable lies in a defined range with the selected LED; and storing the measured value and the position of the selected LED.

Abstract: In a case where a semiconductor chip is mounted over a first package, 80 pads are coupled to 80 terminals of the package, and in a case where the semiconductor chip is mounted over a second package, 100 pads are coupled to 100 terminals of the second package. An internal circuit of the semiconductor chip operates as a microcomputer with 80 terminals in a case where electrodes are insulated from each other and operates as a microcomputer with 100 terminals in a case where the electrodes are shorted therebetween by an end part of a bonding wire. Therefore, a dedicated pad for setting the number of terminals of the packages is no longer required.

Abstract: A method of making redistributed electronic devices that includes providing a wafer having a plurality of electronic devices, each electronic device having a pattern of contact areas forming die pads. The method also includes forming redistribution layers on a temporary substrate having a pattern of contact areas forming wafer bonding pads matching the die pads and a pattern of contact areas forming redistributed pads different than the wafer bonding pads, the wafer bonding pads are coupled to the redistributed pads through a plurality of stacked conductive and insulating layers. The die pads are coupled to the wafer bonding pads, and the temporary substrate is removed. The wafer and redistribution layers are then divided into a plurality of redistributed electronic devices.

Abstract: A method for laser separation of a thin film structure with multi junction photovoltaic materials. The method includes providing an optically transparent substrate having a thickness, a back surface region, and a front surface region including an edge region. The method further includes forming a thin film structure including a conductive layer on the optical transparent substrate. The conductive layer immediately overlies the front surface region. Additionally, the method includes aligning a laser beam with a beam spot on a first portion of the edge region from the back surface region through the thickness of the optically transparent substrate. The method further includes subjecting at least partially the conductive layer overlying the first portion via absorbed energy from the laser beam to separate an edge portion of the thin film structure from the first portion of the edge region.

Abstract: An electronic circuit module and a method of manufacturing the electronic circuit module are disclosed. In one embodiment, the electronic circuit module includes i) a substrate on which a circuit is formed, ii) a plurality of electrical devices electrically connected to the circuit and iii) a first molding unit coated on the substrate to cover at least the electrical devices. The module further includes i) a test terminal unit comprising a plurality of test wires and configured to inspect the circuit, wherein each of the test wires comprises a first end electrically connected to the circuit and a second end exposed from the first molding unit, and wherein the second ends of the test wires form an inspection unit and are adjacent to each other on the substrate and ii) a second molding unit coated on the substrate to cover the second ends of the test wires.

Abstract: A method includes placing a plurality of bottom units onto a jig, wherein the plurality of bottom units is not sawed apart and forms an integrated component. Each of the plurality of bottom units includes a package substrate and a die bonded to the package substrate. A plurality of upper component stacks is placed onto the plurality of bottom units, wherein solder balls are located between the plurality of upper component and the plurality of bottom units. A reflow is performed to join the plurality of upper component stacks with respective ones of the plurality of bottom units through the solder balls.

Abstract: A probe includes a contact member brought into contact with an object to be tested. Contact particles having conductivity are uniformly distributed in the contact member. A part of the contact particles protrude from a surface of the contact member on the side of the object to be tested. A conductive member having elasticity is placed on a surface of the contact member on the opposite side to the object to be tested. The probe further includes an insulating sheet including a through hole and the contact member is so positioned as to penetrate the through hole. An upper part of the contact member is formed of a conductor which does not include the contact particles. An additional conductor is placed on a surface of the conductor on the side opposite to the object to be tested.

Abstract: Provided is a method of manufacturing a semiconductor device including a step of testing every one of through-electrodes. A second probe test is conducted to check an electrical coupling state between a plurality of copper post bumps formed on the side of the surface of a wafer and electrically coupled to a metal layer and a plurality of bumps formed on the side of the back surface of the wafer and electrically coupled to the metal layer (also another metal layer) via a plurality of through-electrodes by probing to each of the bumps on the side of the back surface while short-circuiting between the copper post bumps (electrodes). By this test, conduction between the bumps (electrodes) on the back surface side is checked.

Abstract: Nanospike contactors suitable for semiconductor device test, and associated systems and methods are disclosed. A representative apparatus includes a package having a wafer side positioned to face toward a device under test and an inquiry side facing away from the wafer side. A plurality of wafer side sites are carried at the wafer side of the package. The nanospikes can be attached to nanospike sites on a wafer side of the package. Because of their small size, multiple nanospikes make contact with a single pad/solderball on the semiconductor device. In some embodiments, after detecting that the device under test passes the test, the device under the test can be packaged to create a known good die in a package.

Abstract: Solar cell wafers are fabricated, tested, and sorted into solar cell wafer stacks. A solar cell wafer stack includes a solar cell wafer with a front side that faces a front side of an adjacent solar cell wafer, and another solar cell wafer with a backside that directly contacts a backside of the solar cell wafer. A front side protector may be placed between front sides of adjacent solar cell wafers. The solar cell wafer stack includes end pieces on both ends, and is wrapped to hold and bundle the solar cell wafers, front side protectors, and end pieces together as a single unit. The solar cell wafer stack is boxed along with other solar cell wafer stacks, and then transported to another location where the solar cell wafers are assembled into solar cell modules.

Abstract: A semiconductor device has an alignment mark which can be recognized by a conventional wafer prober. A redistribution layer connects electrodes of the semiconductor device to electrode pads located in predetermined positions of the redistribution layer. Metal posts configured to be provided with external connection electrodes are formed on the electrode pads of the redistribution layer. A mark member made of the same material as the metal posts is formed on the redistribution layer. The mark member serves as an alignment mark located in a predetermined positional relationship with the metal posts.

Abstract: A method of manufacturing a photoelectric composite substrate, includes: aligning and fixing an optical element having a solder terminal to an optical waveguide for forming a path of an optical signal on a printed circuit board; mounting the optical waveguide, to which the optical element is fixed, on the printed circuit board; and welding the solder terminal to an electrode of a package installed on the printed circuit board or an electrode of the printed circuit board.

Abstract: The invention relates to an arrangement of contact areas and test areas on patterned semiconductor chips. The contact areas and the test areas are electrically connected to one another via a conduction web. Whereas the contact areas are arranged in a first region, which has no components of an integrated circuit, the test areas lie in a second region of the top side of the semiconductor chip, which region has components of an integrated circuit.

Abstract: A light emitting package includes a circuit board, a light emitting chip disposed on the circuit board and electrically connected to the circuit board, a resin layer disposed on the light emitting chip, and a fluorescent layer disposed on the resin layer. The light emitting chip is disposed between the resin layer and the circuit board. The resin layer is disposed between the light emitting chip and the fluorescent layer. For a light, a refractive index of the resin layer is smaller than a refractive index of the light emitting chip and is larger than a refractive of the fluorescent layer.

Abstract: A method for mounting and embedding a thinned integrated circuit within a substrate is provided. In one embodiment, the thinned integrated circuit can receive one or more biasing substrate layers on a first surface of the thinned integrated circuit. When the thinned integrated circuit is embedded within a supporting substrate, such as a printed circuit board, the biasing substrate layers can position the thinned integrated circuit toward a centerline of the printed circuit board. Positioning the thinned integrated circuit toward the centerline can increase the resistance to breakage.

Abstract: Disclosed is a package method for electronic components by a thin substrate, including: providing a carrier; forming at least one metal layer and at least one dielectric layer on the carrier for manufacturing the thin substrate, and the thin substrate including at least one package unit for connecting at least one chip; forming at least one pad layer on a surface of the thin substrate; parting the thin substrate from the carrier; performing test to the thin substrate to weed out the package unit with defects in the at least one package unit and select the package units for connecting the chips; connecting the chips with the selected package units by flip chip bonding respectively. Accordingly, the yield of the entire package process can be improved and the pointless manufacture material cost can be reduced.

Abstract: A system and method for controlling temperature of a MEMS sensor are disclosed. In a first aspect, the system comprises a MEMS cap encapsulating the MEMS sensor and a CMOS die vertically arranged to the MEMS cap. The system includes a heater integrated into the MEMS cap. The integrated heater is activated to control the temperature of the MEMS sensor. In a second aspect, the method comprises encapsulating the MEMS sensor with a MEMS cap and coupling a CMOS die to the MEMS cap. The method includes integrating a heater into the MEMS cap. The integrated heater is activated to control the temperature of the MEMS sensor.

Abstract: The disclosure relates to a method of fabricating an integrated circuit of CMOS technology in a semiconductor wafer comprising scribe lines. According to the disclosure, a ground contact pad of the integrated circuit is made in a scribe line of the wafer and is destroyed during a step of individualizing the integrated circuit by singulation of the wafer. A ground contact of the integrated circuit is made on the back side of the integrated circuit when it is assembled in an interconnection package.

Abstract: A method of manufacturing a semiconductor module is provided. The method includes forming semiconductor chips on a bare substrate, performing a burn-in process on the bare substrate including the semiconductor chips, sorting semiconductor chips that exceed a predetermined level of operability determined by testing electrical driving in the semiconductor chips on the burned-in bare substrate, separating the semiconductor chips from one another by cutting the bare substrate, and directly mounting the module semiconductor chips on a module substrate.

Abstract: A method for fabricating a through wire interconnect for a semiconductor substrate having a substrate contact includes the steps of: forming a via through the semiconductor substrate from a first side to a second side thereof; placing a wire in the via having a first end with a bonded connection to the substrate contact and a second end proximate to the second side; forming a first contact on the wire proximate to the first side; forming a second contact on the second end of the wire; and forming a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed.

Abstract: To suppress the reduction in reliability of a resin-sealed semiconductor device. A first cap (member) and a second cap (member) with a cavity (space formation portion) are superimposed and bonded together to form a sealed space. A semiconductor including a sensor chip (semiconductor chip) and wires inside the space is manufactured in the following way. In a sealing step of sealing a joint part between the caps, a sealing member is formed of resin such that an entirety of an upper surface of the second cap and an entirety of a lower surface of the first cap are respectively exposed. Thus, in the sealing step, the pressure acting in the direction of crushing the second cap can be decreased.

Abstract: A method and system for uniquely identifying each semiconductor device die from a wafer is provided. Identifying features are associated with device die bond pads. In one embodiment, one or more tab features are patterned and associated with each of one or more device die bond pads. These features can represent a code (e.g., binary or ternary) that uniquely identifies each device die on the wafer. Each tab feature can be the same shape or different shapes, depending upon the nature of coding desired. Alternatively, portions of the one or more device die bond pads can be omitted as a mechanism for providing coded information, rather than adding portions to the device die bond pads.

Abstract: Methods relating to intermetallic compound testing of copper-based wire bonds are provided. For example, a method is generally provided for testing the integrity of wire bonds formed between copper-containing wires and the bond pads of a plurality of microelectronic devices. In one embodiment, the method includes selecting at least one wire bond sample produced in conjunction with the wire bonds formed between the copper-containing wires and the bond pads of the microelectronic devices. One or more copper-containing wires of the wire bond sample are contacted with a liquid copper etchant, which contains a sulfate-based oxidizing agent dissolved in a solvent, to cause separation of the copper-containing wires from the bond pads and exposure of the underlying wire-pad interfaces. Intermetallic compounds formed at the exposed wire-pad interfaces are then measured to assess the integrity of the wire bonds.

Abstract: A stacking apparatus that stacks chip assemblies each having a plurality of chips disposed continuously with circuit patterns and electrodes, includes: a plurality of stages each allowed to move arbitrarily, on which the chip assemblies are placed; a storage unit that stores an estimated extent of change in a position of an electrode at each chip, expected to occur as heat is applied to the chip assemblies placed on the plurality of stages during a stacking process; and a control unit that sets positions of the plurality of stages to be assumed relative to each other during the stacking process based upon the estimated extent of change in the position of the electrode at each chip provided from the storage unit and position information indicating positions of individual chips formed at the chip assemblies and controls at least one of the plurality of stages.

Abstract: There is provided a semiconductor device assembly with an interposer and method of manufacturing the same. More specifically, in one embodiment, there is provided a semiconductor device assembly comprising a semiconductor substrate, at least one semiconductor die attached to the semiconductor substrate, an interposer disposed on the semiconductor die, and a controller attached to the interposer. There is also provided a method of manufacturing comprising forming a first subassembly by coupling a substrate and a semiconductor die, and forming second subassembly by attaching a controller to an interposer, and coupling the first subassembly to the second subassembly.

Abstract: A method for manufacturing a stacked semiconductor memory device includes testing a plurality of memory chips to detect first defective addresses, programming optical fuses with first defective address information on each of the plurality of memory chips that have the first defective addresses, stacking the plurality of memory chips, testing the stacked memory chips to detect second defective addresses, and programming electrical fuses with second defective address information.

Abstract: A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths extending outwardly beyond a peripheral edge of an encapsulant. A plurality of terminals may be positioned proximate a terminal face of the encapsulant and these terminals may be electrically coupled to the same leads. This can facilitate connection of the microelectronic component to a substrate using the leads as a conventional leaded package. The terminals, however, can facilitate stacking of the leaded package with one or more additional microelectronic components, e.g., a BGA package.

Abstract: A wafer attaching method of attaching a wafer having a warp to a sheet includes a wafer warp detecting step of detecting a surface shape of the wafer, a wafer positioning step of applying a photocuring liquid resin to the sheet and positioning the wafer so that a predetermined surface of the wafer corresponding to attaching conditions preset in a resin bonding apparatus is opposed to the sheet and the liquid resin according to the preset attaching conditions and the surface shape detected above, and a wafer attaching step of pressing the wafer against the liquid resin to thereby spread the liquid resin over the entire area where the wafer and the sheet are superimposed, next removing the pressure applied to the wafer, and next applying light to the liquid resin to cure the liquid resin, thereby attaching the predetermined surface of the wafer to the sheet.

Abstract: Provided are a semiconductor device and a method of manufacturing the same. The method may, for example, comprise forming an interposer on a dummy substrate; forming a conductive pillar on the interposer; contacting the top of the interposer with at least one semiconductor die; encapsulating the conductive pillar and the at least one semiconductor die with an encapsulant; forming a redistribution layer that is electrically connected to the conductive pillar, on the semiconductor die; removing the dummy substrate from the interposer; attaching the interposer, which has the at least one semiconductor die in contact, to a substrate and testing the at least one semiconductor die; and contacting a stacked semiconductor device with the redistribution layer.

Abstract: A method for alignment of a first substrate coupled to a second substrate includes determining an inclination angle for the first substrate or the second substrate due to warpage. The method includes determining a joint height difference based on the inclination angle and configuring a size for one or more bond pads based on the joint height difference.

Abstract: A novel method for manufacturing embedded a capacitive stack and a novel capacitive stack apparatus are provided having a capacitive core that serves as a structural substrate on which alternating thin conductive foils and nanopowder-loaded dielectric layers may be added and tested for reliability. This layering and testing allows early fault detection of the thin dielectric layers of the capacitive stack. The capacitive stack may be configured to supply multiple isolated capacitive elements that provide segregated, device-specific decoupling capacitance to one or more electrical components. The capacitive stack may serve as a core substrate on which a plurality of additional signaling layers of a multilayer circuit board may be coupled.

Abstract: A lead frame for assembling a semiconductor device has a die pad surrounded by lead fingers. Each of the lead fingers has a proximal end close to but spaced from an edge of the die pad and a distal end farther from the die pad. A semiconductor die is attached to a surface of the die pad. The die has die bonding pads on its upper surface that are electrically connected to the proximal ends of the lead fingers with bond wires. An encapsulation material covers the bond wires, semiconductor die and the proximal ends of the lead fingers. Prior to assembly, hot spots of the die are determined and the lead fingers closest to the hot spots are selected to project closer to the die than the other lead fingers. These longer lead fingers assist in dissipating the heat at the die hot spot.

Abstract: A method of forming an integrated circuit (IC) package is disclosed comprising: (a) removing oxides from side surfaces of terminals of the IC package; (b) substantially covering an underside of the terminals of the IC package; and (c) forming a solder coating on the side surfaces of terminals of the IC packages while covering the underside of the terminals of the IC package. The solder coating on the side surfaces of the terminals protects the terminals from oxidation due to aging and subsequent processes. Additionally, the solder coating on the side surfaces of the terminals substantially improves the solderability of the IC package to printed circuit boards (PCBs) or other mountings. This further facilitates the inspection of the solder attachment using less expensive and complicated methods.

Abstract: A stacked type semiconductor memory device of having a structure in which a plurality of semiconductor chips is stacked and a desired semiconductor chip can be selected by assigning a plurality of chip identification numbers different from each other are individually assigned to the plurality of semiconductor chips comprising: a plurality of operation circuits which is connected in cascade in a stacking order of the plurality of semiconductor chips and outputs the plurality of identification numbers different from each other by performing a predetermined operation; and a plurality of comparison circuits which detects whether or not each the identification number and a chip selection address commonly connected to each the semiconductor chip are equal to each other by comparing them.

Abstract: Disclosed is a method for testing multi-chip stacked packages. Initially, one or more substrate-less chip cubes are provided, each consisting of a plurality of chips such as chips stacked together having vertically connected with TSV's where there is a stacked gap between two adjacent chips. Next, the substrate-less chip cubes are adhered onto an adhesive tape where the adhesive tape is attached inside an opening of a tape carrier. Then, a filling encapsulant is formed on the adhesive tape to completely fill the chip stacked gaps. Next, the tape carrier is fixed on a wafer testing carrier in a manner to allow the substrate-less chip cubes to be loaded into a wafer tester without releasing from the adhesive tape. Accordingly, the probers of the wafer tester can be utilized to probe testing electrodes of the substrate-less chip cubes so that it is easy to integrate this testing method in TSV fabrication processes.

Abstract: A chip on film (COF) package and a method for manufacturing same are provided. The COF package comprises a base film, a semiconductor chip mounted on the base film, a signal-inputting portion mounted on the base film, a first passive element mounted on the base film and comprising first and second terminals and a first signal line formed on the base film and connecting the first passive element to the semiconductor chip, wherein the first signal line comprises a connection pad connected to the first terminal of the first passive element and a first test line connected to the signal-inputting portion.

Abstract: Disclosed is a method for wafer-level testing a plurality of diced multi-chip stacked packages. Each package includes a plurality of chips with vertically electrical connections such as TSVs. Next, according to a die-on-wafer array arrangement, the multi-chip stacked packages are fixed on a transparent reconstructed wafer by a photo-sensitive adhesive, and the packages are located within the component-bonding area of the wafer. Then, the transparent reconstructed wafer carrying the multi-chip stacked packages can be loaded into a wafer tester for probing. Accordingly, the wafer testing probers in the wafer tester can be utilized to probe the testing electrodes of the stacked packages so that it is easy to integrate this wafer-level testing method especially into TSV packaging processes.

Abstract: A method and apparatus for depositing a phosphor using transfer molding. The method includes: forming a plurality of light-emitting devices on a wafer and rearranging the light-emitting devices on a carrier substrate according to luminance characteristics of the plurality of light-emitting devices by examining the luminance characteristics of the plurality of light-emitting devices; depositing the phosphor on the rearranged light-emitting devices using transfer molding; and separating the light-emitting devices on the carrier substrate.

Abstract: A semiconductor storage device 100 includes a controller package 110 having a BGA terminal on a bottom surface thereof; and one or a plurality of memory packages 120 each including a plurality of semiconductor storage elements and mounted on the controller package. The controller package includes a bottom substrate having the BGA terminal on a bottom surface thereof; a power supply IC, mounted on the bottom substrate, for supplying a plurality of power supplies; and a controller mounted on the bottom substrate and operable by the plurality of power supplies supplied from the power supply IC. The controller provides an interface with an external system via the BGA terminal and controls a read operation from the semiconductor storage elements and a write operation to the semiconductor storage elements.

Abstract: It has been difficult to carry out a test and an analysis with respect to combinational logic circuits mounted across plural chips, and therefore, there is provided a flip-flop (31b) by use of which either of a scan chain within a semiconductor chip (LSI_B), and a scan chain across plural semiconductor chips (LSI_A and LSI_B) can be made up.

Abstract: An align fixture for aligning an electronic component having a receptacle adapted to receive the electronic component and having a first abutting section and a second abutting section, the align fixture further having a first elastic unit and a second elastic unit, the first abutting section is flexibly mounted via the first elastic unit, and the second abutting section is flexibly mounted via the second elastic unit, and the first abutting section and the second abutting section are together adapted to floatingly engage the electronic component.

Abstract: A method of making an electronic device with a redistribution layer includes providing an electronic device having a first pattern of contact areas, and forming a redistribution layer on a temporary substrate. The temporary substrate has a second pattern of contact areas matching the first pattern of contact areas, and a third pattern of contact areas different than the second pattern of contact areas. The second pattern of contact areas is coupled to the third pattern of contact areas through a plurality of stacked conductive and insulating layers. The first pattern of contact areas is coupled to the second pattern of contact areas on the transferrable redistribution layer. The temporary substrate is then removed to thereby form a redistributed electronic device.

Abstract: A semiconductor structure less affected by stress and a method for forming the same are provided. The semiconductor structure includes a semiconductor chip. Stress-sensitive circuits are substantially excluded out of an exclusion zone to reduce the effects of the stress to the stress-sensitive circuits. The stress-sensitive circuits include analog circuits. The exclusion zone preferably includes corner regions of the semiconductor chip, wherein the corner regions preferably have a diagonal length of less than about one percent of the diagonal length of the semiconductor chip. The stress-sensitive analog circuits preferably include devices having channel lengths less than about five times the minimum channel length.

Abstract: A wafer-level bonding method for fabricating wafer level camera lenses is disclosed. The method includes: providing a lens wafer including lenses arranged in an array and a sensor wafer including sensors arranged in an array; measuring and analyzing an FFL of each lens to obtain a corresponding FFL compensation value for each lens; forming a thin transparent film (TTF) on each sensor of the sensor wafer, and the thickness of TTF is determined by the FFL compensation value of the corresponding lens; aligning and bonding the lens wafer with the sensor wafer having TTFs formed thereon. Since the focal length of each lens is adjusted to compensate the FFL of the lens by adding a TTF of transparent optical material with an index of refraction that is similar to the index of refraction of the sensor cover glass, the FFL variation of each camera lens can be reduced.

Abstract: A resin application apparatus includes: an optical property measurement unit measuring an optical property of light emitted from a light emitting diode (LED) chip which is mounted on a package body and to which transparent resin is not applied; and a resin application unit applying light conversion material-containing transparent resin to the LED chip in accordance with a resin application amount which is decided depending on the optical property measured by the optical measurement unit.

Abstract: A method is described for creating at least one recess in a semiconductor component, in particular a micromechanical or electrical semiconductor component, having the following steps: applying at least one mask to the semiconductor component, forming at least one lattice having at least one or more lattice openings in the mask over the recess to be formed, the lattice opening or lattice openings being formed as a function of the etching rate and/or the dimensioning of the recess to be formed; forming the recess below the lattice.

Abstract: A semiconductor device has a first interconnect structure formed over the carrier. A semiconductor die is disposed over the first interconnect structure after testing the first interconnect structure to be known good. The semiconductor die in a known good die. A vertical interconnect structure, such as a bump or stud bump, is formed over the first interconnect structure. A discrete semiconductor device is disposed over the first interconnect structure or the second interconnect structure. An encapsulant is deposited over the semiconductor die, first interconnect structure, and vertical interconnect structure. A portion of the encapsulant is removed to expose the vertical interconnect structure. A second interconnect structure is formed over the encapsulant and electrically connected to the vertical interconnect structure. The first interconnect structure or the second interconnect structure includes an insulating layer with an embedded glass cloth, glass cross, filler, or fiber.

Abstract: A fine pitch package-on-package (PoP), and a method of forming, are provided. The PoP may be formed by placing connections, e.g., solder balls, on a first substrate having a semiconductor die attached thereto. A first reflow process is performed to elongate the solder balls. Thereafter, a second substrate having another semiconductor die attached thereto is connected to the solder balls. A second reflow process is performed to form an hourglass connection.

Abstract: Provided are a light-emitting device package and a method of manufacturing the same. The light-emitting device package may include a plurality of light-emitting chips on one substrate (board). The plurality of light-emitting chips may produce colors around a target color. The target color may be produced by combinations of the colors of light emitted from the plurality of light-emitting chips. The colors around the target color may have the same hue as the target color and have color temperatures different from that of the target color. The plurality of light-emitting chips may have color temperatures within about ±250K of that of the target color.

Abstract: A semiconductor package device having a protruding component portion and a method of packaging the semiconductor device is disclosed. The semiconductor device has a component, such as a leadframe, and a packaging mold body. The packaging mold body is formed around a portion of the component and a recess is formed in the packaging mold body adjacent the protruding portion of the component to prevent the protruding portion of the component from damaging other adjacent and abutting semiconductor devices.